ADL5369ACPZ-R7 [ADI]
300 MHz to 1100 MHz Balanced Mixer, LO Buffer, and RF Balun;
| 型号： | ADL5369ACPZ-R7 |
| 厂家： | 
ADI |
| 描述： | 300 MHz to 1100 MHz Balanced Mixer, LO Buffer, and RF Balun |
| 文件： | 总23页 (文件大小：486K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
300 MHz to 1100 MHz Balanced Mixer,
LO Buffer, and RF Balun
Data Sheet
ADL5369
FEATURES
FUNCTIONAL BLOCK DIAGRAM
VCMI
20
IFOP
19
IFON
18
PWDN
17
COMM
16
RF frequency range of 300 MHz to 1100 MHz
IF frequency range of 30 MHz to 450 MHz
Power conversion loss: 6.2 dB
ADL5369
1
2
3
4
5
15
14
13
12
11
VPMX
RFIN
LOI2
SSB noise figure of 7.2 dB
Input IP3 of 28 dBm
Typical LO interface return loss of 0 dBm
Single-ended, 50 Ω RF and LO input ports
High isolation SPDT LO input switch
Typical single-supply operation: 3.3 V to 5 V
Exposed pad, 5 mm × 5 mm, 20-lead LFCSP
VPSW
VGS1
VGS0
LOI1
RFCT
COMM
COMM
BIAS
GENERATOR
APPLICATIONS
Cellular base station receivers
Transmit observation receivers
Radio link downconverters
6
7
LGM3
8
9
10
VLO3
VLO2
LOSW
NIC
NIC = NOT INTERNALLY CONNECTED.
Figure 1.
GENERAL DESCRIPTION
The ADL5369 uses a highly linear, doubly balanced passive mixer
core along with integrated radio frequency (RF) and local oscillator
(LO) balancing circuitry to allow single-ended operation. The
ADL5369 incorporates an RF balun, allowing optimal performance
over a 300 MHz to 1100 MHz RF input frequency range. The
balanced passive mixer arrangement provides good LO to RF
leakage, typically better than −25 dBm, and excellent intermod-
ulation performance. The balanced mixer core also provides
extremely high input linearity, allowing the device to be used in
demanding cellular applications where in-band blocking signals
may otherwise result in the degradation of dynamic perform-
ance. The passive mixer core yields a typical power conversion loss
of 6.2 dB.
The ADL5369 provides two switched LO paths that can be
used in time division duplex (TDD) applications where it is
desirable to rapidly switch between two local oscillators. LO
current can be externally set using a resistor to minimize dc
current commensurate with the desired level of performance.
For low voltage applications, the ADL5369 is capable of operation
at voltages down to 3.3 V with substantially reduced current.
Under low voltage operation, an additional logic pin is provided
to power down (<200 μA) the circuit when desired.
The ADL5369 is fabricated using a BiCMOS high performance
IC process. The device is available in a 5 mm × 5 mm, 20-lead
LFCSP and operates over a −40°C to +85°C temperature range.
An evaluation board is also available.
Table 1. Passive Mixers
RF Frequency Single
Single Mixer
and IF Amp
Dual Mixer
and IF Amp
(MHz)
Mixer
300 to 1100
500 to 1700
1200 to 2500
2200 to 2700
ADL5369
ADL5367
ADL5365
Not applicable
ADL5357
ADL5355
Not applicable
ADL5358
ADL5356
Not
ADL5353
ADL5354
applicable
2300 to 2900
ADL5363
Not applicable
Not applicable
Rev. A
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Technical Support
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ADL5369
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
3.3 V Performance Characteristics .......................................... 14
Upconversion Characteristics................................................... 15
Spurious Performance ............................................................... 16
Circuit Description......................................................................... 17
RF Subsystem.............................................................................. 17
LO Subsystem ............................................................................. 17
Applications Information.............................................................. 19
Basic Connections...................................................................... 19
IF Port .......................................................................................... 19
Mixer VGS Control DAC.......................................................... 19
Evaluation Board ............................................................................ 20
Outline Dimensions....................................................................... 23
Ordering Guide .......................................................................... 23
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
5 V Performance........................................................................... 4
3.3 V Performance........................................................................ 4
Absolute Maximum Ratings............................................................ 5
Thermal Resistance ...................................................................... 5
ESD Caution.................................................................................. 5
Pin Configuration and Function Descriptions............................. 6
Typical Performance Characteristics ............................................. 7
5 V Performance Characteristics................................................ 7
REVISION HISTORY
5/16—Rev. 0 to Rev. A
Changes to Conversion Loss Distribution, Input IP3 Distribution,
and Return Loss Section.................................................................. 11
Changes to Isolation, Leakage, Power Conversion Loss, Input
IP3, and SSB Noise Figure Section............................................... 12
Changes to 3.3 V Performance Characteristics Section............ 14
Changes to Upconversion Characteristics Section .................... 15
Changes to 5 V Performance Section .......................................... 16
Change to Figure 45 ....................................................................... 19
Change to Figure 46 ....................................................................... 20
Changes to Table 8.......................................................................... 21
Changes to Specifications Section .......................................................3
Changes to 5 V Performance Section and 3.3 V Performance
Section .........................................................................................................4
Changes to Table 5.....................................................................................5
Added Thermal Resistance Section, Table 6, and Junction to Board
Thermal Impedance Section; Renumbered Sequentially ..................5
Changes to RF Frequency Section.................................................. 7
Changes to Temperature Section.................................................... 8
Changes to IF Frequency Section................................................... 9
Changes to LO Power and Spurious Performance Section....... 10
1/16—Revision 0: Initial Version
Rev. A | Page 2 of 23
Data Sheet
ADL5369
SPECIFICATIONS
Supply voltage (VS) = 5 V, supply current (IS) = 84 mA, TA = 25°C, fRF = 450 MHz, fLO = 543 MHz, LO power = 0 dBm, ZO = 50 Ω,
R9 = 1.7 kꢀ, unless otherwise noted.
Table 2.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
RF INPUT INTERFACE
Return Loss
Tunable to >20 dB over a limited bandwidth
10
50
dB
Ω
MHz
Input Impedance
RF Frequency Range
OUTPUT INTERFACE
Output Impedance
IF Frequency Range
DC Bias Voltage1
LO INTERFACE
300
1100
Differential impedance, f = 93 MHz
Externally generated
35.2||11.9
5.0
Ω||pF
MHz
V
30
3.3
450
5.5
LO Power
−6
0
+10
1550
0.4
dBm
dB
Ω
Return Loss
16.5
50
Input Impedance
LO Frequency Range
POWER-DOWN (PWDN) INTERFACE2
PWDN Threshold
Logic 0 Level
330
MHz
1.0
V
V
Logic 1 Level
1.4
V
PWDN Response Time
Device enabled, IF output to 90% of its final level
Device disabled, supply current < 5 mA
Device enabled
160
220
0.0
70
ns
ns
μA
μA
PWDN Input Bias Current
Device disabled
1 Apply the supply voltage from the external circuit through the choke inductors.
2 PWDN function is intended for use with VS ≤ 3.6 V only.
Rev. A | Page 3 of 23
ADL5369
Data Sheet
5 V PERFORMANCE
VS = 5 V, IS = 84 mA, TA = 25°C, fRF = 450 MHz, fLO = 543 MHz, LO power = 0 dBm, VGS0 = VGS1 = 0 V, and ZO = 50 Ω, R9 = 1.7 kꢀ, unless
otherwise noted.
Table 3.
Parameter
Test Conditions/Comments
Min Typ Max Unit
DYNAMIC PERFORMANCE
Power Conversion Loss
Voltage Conversion Loss
Single Sideband (SSB) Noise Figure
Input Third-Order Intercept (IIP3)
Including 1:1 IF port transformer and printed circuit board (PCB) loss
ZSOURCE = 50 Ω, differential ZLOAD = 50 Ω differential
6.2
1.4
7.2
28
dB
dB
dB
dBm
fRF1 = 449.5 MHz, fRF2 = 451.5 MHz, fLO = 543 MHz, each RF tone
at 0 dBm
Input Second-Order Intercept (IIP2)
fRF1 = 500 MHz, fRF2 = 450 MHz, fLO = 543 MHz, each RF tone
at −10 dBm
56
dBm
Input 1 dB Compression Point (IP1dB)1 Exceeding 20 dBm RF power results in damage to the device
20
dBm
dBm
dBm
dBc
dBc
dBc
LO to IF Leakage
LO to RF Leakage
RF to IF Isolation
IF/2 Spurious
Unfiltered IF output
−16
−27
−42
−57
−60
0 dBm input power
0 dBm input power
IF/3 Spurious
POWER SUPPLY
Positive Supply Voltage
Total Quiescent Current
4.5
5
84
5.5
V
mA
VS = 5 V
1 Exceeding 20 dBm RF power results in damage to the device.
3.3 V PERFORMANCE
VS = 3.3 V, IS = 55 mA, TA = 25°C, fRF = 450 MHz, fLO = 543 MHz, LO power = 0 dBm, R9 = 226 Ω, VGS0 = VGS1 = 0 V, and ZO = 50 Ω,
unless otherwise noted.
Table 4.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
DYNAMIC PERFORMANCE
Power Conversion Loss
SSB Noise Figure
IIP3
Including 1:1 IF port transformer and PCB loss
6.5
7.4
24
dB
dB
dBm
fRF1 = 449.5 MHz, fRF2 = 451.5 MHz, fLO = 543 MHz, each RF
tone at −10 dBm
IIP2
fRF1 = 500 MHz, fRF2 = 450 MHz, fLO = 543 MHz, each RF tone
at −10 dBm
53
dBm
POWER INTERFACE
Supply Voltage
Quiescent Current
Power-Down Current
3.0
3.3
55
150
3.6
V
mA
μA
Resistor programmable
Device disabled
Rev. A | Page 4 of 23
Data Sheet
ADL5369
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 5.
θJA is the junction to ambient thermal resistance (°C/W), θJB is
the junction to board thermal resistance (°C/W), and θJC is the
junction to case thermal resistance (°C/W). θJC is determined by
the mechanical design of the ADL5369 and is optimized to the
lowest possible value. θJA and θJB are functions of the design of
the PCB, and are under the control of the user. The data shown
in Table 6 is based on a JEDEC standard design and is provided
for comparison purposes.
Parameter
Rating
VS
5.5 V
RF Input Level
LO Input Level
20 dBm
13 dBm
6.0 V
5.5 V
0.6 W
IFOP, IFON Bias Voltage
VGS0, VGS1, LOSW, PWDN
Internal Power Dissipation
Maximum Junction Temperature
Operating Temperature Range
Storage Temperature Range
Lead Temperature (Soldering, 60 sec)
150°C
−40°C to +85°C
−65°C to +150°C
260°C
Table 6. Thermal Resistance
1
1
1
Package Type
θJA
θJB
14.74
θJC
1.08
Unit
20-Lead LFCSP
25
°C/W
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
1 See JEDEC Standard JESD51-2 for information on optimizing thermal
impedance (PCB with 3 × 3 vias).
Junction to Board Thermal Impedance
The junction to board thermal impedance (θJB) is the thermal
impedance from the die to or near the component lead of the
ADL5369. For the ADL5369, θJB was determined experimentally to
be 14.74°C/W with the device mounted on a 4-layer circuit board
(two of the layers being ground planes) in a configuration
similar to that of the ADL5369-EVALZ evaluation board. Board
size and complexity (number of layers) affect θJB; more layers tend
to reduce the thermal impedance slightly.
If the board temperature is known, use the junction to board
thermal impedance to calculate die temperature (also known as
junction temperature) to ensure that it does not exceed the speci-
fied limit of 150°C. For example, if the board temperature is
85°C, the die temperature is given by the equation
TJ = TB + (PDISS × θJB)
where:
TJ is the junction temperature.
TB is the board temperature measured at or near the component
lead.
P
DISS is the power dissipated from the device.
The typical worst case power dissipation for the ADL5369 is
522 mW (5.5 V × 95 mA). Therefore, TJ is
TJ = 85°C + (0.522 W × 14.74°C/W) = 92.70°C
ESD CAUTION
Rev. A | Page 5 of 23
ADL5369
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
15 LOI2
14 VPSW
13 VGS1
12 VGS0
VPMX
RFIN
1
2
3
4
5
ADL5369
RFCT
COMM
COMM
TOP VIEW
(Not to Scale)
11
LOI1
NOTES
1. NIC = NOT INTERNALLY CONNECTED.
2. EXPOSED PAD MUST BE SOLDERED TO GROUND.
Figure 2. Pin Configuration
Table 7. Pin Function Descriptions
Pin No. Mnemonic Description
1
2
3
VPMX
RFIN
RFCT
COMM
Positive Supply Voltage for the IF Amplifier.
RF Input. This pin must be ac-coupled.
RF Balun Center Tap (AC Ground).
Device Common (DC Ground).
4, 5, 16
6, 8
7
9
10
VLO3, VLO2 Positive Supply Voltages for LO Amplifier.
LGM3
LOSW
NIC
LO Amplifier Bias Control.
LO Switch. LOI1 is selected for 0 V, or LOI2 is selected for 3 V.
Not Internally Connected.
11, 15
12, 13
14
LOI1, LOI2
LO Inputs. These pins must be ac-coupled.
VGS0, VGS1 Mixer Gate Bias Controls (3 V Logic). Ground these pins for the nominal setting.
VPSW
Positive Supply Voltage for LO Switch.
17
18, 19
20
PWDN
IFON, IFOP
VCMI
Power-Down. Connect this pin to ground for normal operation or connect this pin to 3.0 V for disable mode.
Differential IF Outputs.
No Connect. This pin can be grounded.
EPAD (EP)
Exposed Pad. The exposed pad must be soldered to ground.
Rev. A | Page 6 of 23
Data Sheet
ADL5369
TYPICAL PERFORMANCE CHARACTERISTICS
5 V PERFORMANCE CHARACTERISTICS
RF Frequency
VS = 5 V, IS = 84 mA, TA = 25°C, fRF = 450 MHz, fLO = 543 MHz, LO power = 0 dBm, VGS0 = VGS1 = 0 V, R9 = 1.7 kꢀ, and ZO = 50 Ω, unless
otherwise noted.
0.100
0.095
0.090
0.085
0.080
0.075
0.070
90
80
70
60
50
40
30
20
–40°C
+25°C
+85°C
–40°C
+25°C
+85°C
300
400
500
600
700
800
900
1000
1100
300
400
500
600
700
800
900
1000
1100
RF FREQUENCY (MHz)
RF FREQUENCY (MHz)
Figure 6. Input IP2 vs. RF Frequency
Figure 3. Supply Current vs. RF Frequency
14
12
10
8
16
–40°C
+25°C
+85°C
–40°C
+25°C
+85°C
14
12
10
8
6
6
4
4
2
2
0
300
0
300
400
500
600
700
800
900
1000
1100
400
500
600
700
800
900
1000
1100
RF FREQUENCY (MHz)
RF FREQUENCY (MHz)
Figure 4. Power Conversion Loss vs. RF Frequency
Figure 7. SSB Noise Figure vs. RF Frequency
40
–40°C
+25°C
+85°C
35
30
25
20
15
10
300
400
500
600
700
800
900
1000
1100
RF FREQUENCY (MHz)
Figure 5. Input IP3 vs. RF Frequency
Rev. A | Page 7 of 23
ADL5369
Data Sheet
Temperature
VS = 5 V, IS = 84 mA, TA = 25°C, fRF = 450 MHz, fLO = 543 MHz, LO power = 0 dBm, VGS0 = VGS1 = 0 V, R9 = 1.7 kꢀ, and ZO = 50 Ω, unless
otherwise noted.
0.100
4.75V
4.75V
5V
59
57
55
53
51
49
47
45
5V
5.25V
5.25V
0.095
0.090
0.085
0.080
0.075
0.070
0.065
–45
–25
–5
15
35
55
75
–40
–20
0
20
40
60
80
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 8. Supply Current vs. Temperature
Figure 11. Input IP2 vs. Temperature
8.0
7.0
6.5
6.0
5.5
5.0
4.5
4.0
10
4.75V
4.75V
5V
5V
5.25V
5.25V
9
8
7
6
5
4
–40
–20
0
20
40
60
80
–40
–20
0
20
40
60
80
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 9. Power Conversion Loss vs. Temperature
Figure 12. SSB Noise Figure vs. Temperature
34
4.75V
5V
33
32
31
30
29
28
27
26
25
24
5.25V
–40
–20
0
20
40
60
80
TEMPERATURE (°C)
Figure 10. Input IP3 vs. Temperature
Rev. A | Page 8 of 23
Data Sheet
ADL5369
IF Frequency
VS = 5 V, IS = 84 mA, TA = 25°C, fRF = 450 MHz, fLO = 543 MHz, LO power = 0 dBm, VGS0 = VGS1 = 0 V, R9 = 1.7 kꢀ, and ZO = 50 Ω, unless
otherwise noted.
0.100
0.095
0.090
0.085
0.080
0.075
0.070
65
60
55
50
45
40
35
–40°C
+25°C
+85°C
–40°C
+25°C
+85°C
30
80
130
180
230
280
330
380
430
30
80
130
180
230
280
330
380
430
IF FREQUENCY (MHz)
IF FREQUENCY (MHz)
Figure 16. Input IP2 vs. IF Frequency
Figure 13. Supply Current vs. IF Frequency
14
12
10
8
12
10
8
–40°C
+25°C
+85°C
6
6
4
4
2
2
0
30
0
30
80
130
180
230
280
330
380
430
80
130
180
230
280
330
380
430
IF FREQUENCY (MHz)
IF FREQUENCY (MHz)
Figure 17. SSB Noise Figure vs. IF Frequency
Figure 14. Power Conversion Loss vs. IF Frequency
26.0
25.5
25.0
24.5
24.0
23.5
23.0
22.5
22.0
21.5
21.0
–40°C
+25°C
+85°C
30
80
130
180
230
280
330
380
430
IF FREQUENCY (MHz)
Figure 15. Input IP3 vs. IF Frequency
Rev. A | Page 9 of 23
ADL5369
Data Sheet
LO Power and Spurious Performance
VS = 5 V, IS = 84 mA, TA = 25°C, fRF = 450 MHz, fLO = 543 MHz, LO power = 0 dBm, VGS0 = VGS1 = 0 V, R9 = 1.7 kꢀ, and ZO = 50 Ω, unless
otherwise noted.
8.0
7.5
7.0
6.5
6.0
5.5
5.0
4.5
4.0
–20
–30
–40
–50
–60
–70
–80
–90
–100
–40°C
+25°C
+85°C
–40°C
+25°C
+85°C
–6
–4
–2
0
2
4
6
8
10
10
10
300
400
500
600
700
800
900
1000
1100
LO POWER (dBm)
RF FREQUENCY (MHz)
Figure 18. Power Conversion Loss vs. LO Power
Figure 21. IF/2 Spurious vs. RF Frequency
35
34
33
32
31
30
29
28
27
26
25
–20
–30
–40
–50
–60
–70
–80
–90
–40°C
+25°C
+85°C
–40°C
+25°C
+85°C
–6
–4
–2
0
2
4
6
8
300
400
500
600
700
800
900
1000
1100
LO POWER (dBm)
RF FREQUENCY (MHz)
Figure 19. Input IP3 vs. LO Power
Figure 22. IF/3 Spurious vs. RF Frequency
60
59
58
57
56
55
54
53
52
51
50
–40°C
+25°C
+85°C
–6
–4
–2
0
2
4
6
8
LO POWER (dBm)
Figure 20. Input IP2 vs. LO Power
Rev. A | Page 10 of 23
Data Sheet
ADL5369
Conversion Loss Distribution, Input IP3 Distribution, and Return Loss
VS = 5 V, IS = 84 mA, TA = 25°C, fRF = 450 MHz, fLO = 543 MHz, LO power = 0 dBm, VGS0 = VGS1 = 0 V, R9 = 1.7 kꢀ, and ZO = 50 Ω, unless
otherwise noted.
0
100
80
60
40
20
0
–5
–10
–15
–20
–25
5.8
6.0
6.2
6.4
6.6
300
400
500
600
700
800
900
1000
1100
CONVERSION LOSS (dB)
RF FREQUENCY (MHz)
Figure 23. Conversion Loss Distribution
Figure 26. RF Port Return Loss, Fixed IF vs. Frequency
0
–5
100
80
60
40
20
0
–10
–15
–20
–25
–30
–35
SELECTED
UNSELECTED
24
25
26
27
28
29
30
31
32
300
400
500
600
700
800
900 1000 1100 1200
INPUT IP3 (dBm)
LO FREQUENCY (MHz)
Figure 24. Input IP3 Distribution
Figure 27. LO Return Loss vs. LO Frequency, Selected and Unselected
40
22
20
18
16
14
12
10
R11 LO1
R11 LO2
C11 (pF )LO1
C11 (pF) LO2
35
30
25
20
15
10
50
100
150
200
250
300
IF FREQUENCY (MHz)
Figure 25. IF Port Return Loss
Rev. A | Page 11 of 23
ADL5369
Data Sheet
Isolation, Leakage, Power Conversion Loss, Input IP3, and SSB Noise Figure
VS = 5 V, IS = 84 mA, TA = 25°C, fRF = 450 MHz, fLO = 543 MHz, LO power = 0 dBm, VGS0 = VGS1 = 0 V, R9 = 1.7 kꢀ, and ZO = 50 Ω, unless
otherwise noted.
70
65
60
55
50
45
40
–20
–25
–30
–35
–40
–45
–40°C
+25°C
+85°C
393
493
593
693
793
893
993
1093
1193
300
400
500
600
700
800
900
1000
1100
LO FREQUENCY (MHz)
RF FREQUENCY (MHz)
Figure 28. LO Switch Isolation vs. RF Frequency
Figure 31. LO to RF Leakage vs. LO Frequency
–30
–35
–40
–45
–50
–55
–60
–65
–70
–20
–40°C
+25°C
+85°C
–25
–30
–35
–40
–45
–50
–55
2LO TO IF
2LO TO RF
300
400
500
600
700
800
900
1000
1100
393
493
593
693
793
893
993
1093
1193
RF FREQUENCY (MHz)
LO FREQUENCY (MHz)
Figure 29. RF to IF Isolation vs. RF Frequency
Figure 32. 2LO Leakage vs. LO Frequency
0
–5
–20
–40°C
+25°C
+85°C
–25
–30
–35
–40
–45
–50
–55
–60
–10
–15
–20
–25
–30
–35
–40
–45
3LO TO RF
3LO TO IF
393
493
593
693
793
893
993
1093
1193
393
493
593
693
793
893
993
1093
1193
LO FREQUENCY (MHz)
LO FREQUENCY (MHz)
Figure 30. LO to IF Leakage vs. LO Frequency
Figure 33. 3LO Leakage vs. LO Frequency
Rev. A | Page 12 of 23
Data Sheet
ADL5369
40
35
30
25
20
15
10
5
10
9
17
15
13
11
9
8
7
CONVERSION LOSS
6
5
4
3
NOISE FIGURE
2
1
0
7
V
V
V
V
= 0, 0
= 0, 1
= 1, 0
= 1, 1
GS
GS
GS
GS
0
–30
5
1100
–25
–20
–15
–10
–5
0
5
300
400
500
600
700
800
900
1000
BLOCKER POWER (dBm)
RF FREQUENCY (MHz)
Figure 34. Power Conversion Loss and SSB Noise Figure vs. RF Frequency
Figure 36. SSB Noise Figure vs.10 MHz Offset Blocker Level
35
V
V
V
V
= 0, 0
= 0, 1
= 1, 0
= 1, 1
GS
GS
GS
GS
30
25
20
15
10
5
0
300
400
500
600
700
800
900
1000
1100
RF FREQUENCY (MHz)
Figure 35. Input IP3 vs. RF Frequency
Rev. A | Page 13 of 23
ADL5369
Data Sheet
3.3 V PERFORMANCE CHARACTERISTICS
VS = 3.3 V, IS = 56 mA, TA = 25°C, fRF = 450 MHz, fLO = 543 MHz, LO power = 0 dBm, R9 = 226 Ω, VGS0 = VGS1 = 0 V, and ZO = 50 Ω,
unless otherwise noted.
0.08
0.07
0.06
0.05
0.04
0.03
80
70
60
50
40
30
20
10
–40°C
+25°C
+85°C
–40°C
+25°C
+85°C
300
400
500
600
700
800
900
1000
1100
300
400
500
600
700
800
900
1000
1100
RF FREQUENCY (MHz)
RF FREQUENCY (MHz)
Figure 37. Supply Current vs. RF Frequency
Figure 40. Input IP2 vs. RF Frequency
18
16
14
12
10
8
14
12
10
8
–40°C
+25°C
+85°C
–40°C
+25°C
+85°C
6
6
4
4
2
2
0
300
0
300
400
500
600
700
800
900
1000
1100
400
500
600
700
800
900
1000
1100
RF FREQUENCY (MHz)
RF FREQUENCY (MHz)
Figure 38. Power Conversion Loss vs. RF Frequency
Figure 41. SSB Noise Figure vs. RF Frequency
35
–40°C
+25°C
+85°C
30
25
20
15
10
300
400
500
600
700
800
900
1000
RF FREQUENCY (MHz)
Figure 39. Input IP3 vs. RF Frequency
Rev. A | Page 14 of 23
Data Sheet
ADL5369
UPCONVERSION CHARACTERISTICS
TA = 25°C, fIF = 93 MHz, fLO = 543 MHz, LO power = 0 dBm, RF power = 0 dBm, VGS0 = VGS1 = 0 V, R9 = 1.7 kꢀ, and ZO = 50 Ω, unless
otherwise noted.
16
14
12
10
8
35
30
25
20
15
10
5
–40°C
+25°C
+85°C
–40°C
+25°C
+85°C
6
4
2
0
300
0
300
400
500
600
700
800
900
1000
1100
400
500
600
700
800
900
1000
1100
RF FREQUENCY (MHz)
RF FREQUENCY (MHz)
Figure 42. Power Conversion Loss vs. RF Frequency, VS = 5 V, Upconversion
Figure 43. Input IP3 vs. RF Frequency, VS = 5 V, Upconversion
Rev. A | Page 15 of 23
ADL5369
Data Sheet
SPURIOUS PERFORMANCE
All spur tables are (N × fRF) − (M × fLO) and were measured using the standard evaluation board. Mixer spurious products are measured
in dBc from the IF output power level. Data was measured only for frequencies less than 6 GHz. Typical noise floor of the measurement
system = −100 dBm.
5 V Performance
VS = 5 V, IS = 84 mA, TA = 25°C, fRF = 450 MHz, fLO = 543 MHz, LO power = 0 dBm, RF power = 0 dBm, VGS0 = VGS1 = 0 V, R9 = 1.7 kꢀ,
and ZO = 50 Ω, unless otherwise noted.
M
0
1
2
3
4
5
6
7
8
9
10
11
12
0
−16.885
0
−33.42
−45.535
−58.999
−79.147
−93.128
<−100
<−100
<−100
<−100
<−100
−42.57
−17.948
−60.289
−64.17
−81.092
<−100
<−100
<−100
<−100
<−100
<−100
−38.358
−54.779
−72.545
−90.573
−99.503
−95.9
−49.375
−32.507
−70.273
−70.476
−87.794
−90.504
<−100
<−100
<−100
<−100
<−100
<−100
<−100
−61.446
−47.242
−58.881
−92.162
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
−49.819
−42.403
−73.383
−81.353
−99.13
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
−51.873
−45.589
−65.824
−87.574
−98.082
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
−60.951
−45.324
−78.819
−89.786
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
−52.666
−67.094
−68.754
−82.829
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
−60.115
−47.641
−97.834
−93.849
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
−61.09
−61.494
−72.556
−86.249
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
1
−41.537
2
−71.919 −50.753
−95.982 −72.895
3
4
<−100
<−100
<−100
−78.49
<−100
<−100
<−100
5
N
6
<−100
<−100
<−100
<−100
<−100
<−100
<−100
7
8
9
10
11
12
Rev. A | Page 16 of 23
Data Sheet
ADL5369
CIRCUIT DESCRIPTION
The ADL5369 consists of two primary components: the RF
subsystem and the LO subsystem. The combination of design,
process, and packaging technology allows the functions of these
subsystems to be integrated into a single die, using mature
packaging and interconnection technologies to provide a high
performance, low cost design with excellent electrical,
mechanical, and thermal properties. In addition, the need for
external components is minimized, optimizing cost and size.
The resulting balanced RF signal is applied to a passive mixer
that commutates the RF input with the output of the LO subsystem.
The passive mixer is essentially a balanced, low loss switch that
adds minimum noise to the frequency translation. The only
noise contribution from the mixer is due to the resistive loss
of the switches, which is in the order of a few ohms.
Because the mixer is inherently broadband and bidirectional, it
is necessary to properly terminate all the idler (M × N product)
frequencies generated by the mixing process. Terminating the
mixer avoids the generation of unwanted intermodulation
products and reduces the level of unwanted signals at the IF
output. This termination is accomplished by the addition of a
sum network between the IF output and the mixer.
The RF subsystem consists of an integrated, low loss RF balun,
passive metal-oxide semiconductor field-effect transistor
(MOSFET) mixer, sum termination network, and IF amplifier.
The LO subsystem consists of a single pole, double throw (SPDT)-
terminated FET switch and a three-stage limiting LO amplifier.
The purpose of the LO subsystem is to provide a large, fixed
amplitude, balanced signal to drive the mixer independent of
the level of the LO input.
Additionally, dc current can be saved by reducing the dc supply
voltage to as low as 3.3 V, further reducing the dissipated power
of the device. Note that no performance enhancement is obtained
by reducing the value of the resistors; reducing the value of the
resistors may result in excessive dc power dissipation.
A block diagram of the device is shown in Figure 44.
VCMI
IFOP
IFON
PWDN
COMM
20
19
18
17
16
LO SUBSYSTEM
The LO amplifier provides a large signal level to the mixer to
obtain optimum intermodulation performance. The resulting
amplifier provides extremely high performance centered on an
operating frequency of 700 MHz. The best operation is achieved
with high-side LO injection for RF signals in the 300 MHz to
1100 MHz range. Operation outside these ranges is permissible,
and conversion loss is extremely wideband, easily spanning 300
MHz to 1100 MHz, but intermodulation is optimal over the
aforementioned ranges.
ADL5369
1
2
3
4
5
15
14
13
12
11
VPMX
RFIN
LOI2
VPSW
VGS1
VGS0
LOI1
RFCT
COMM
COMM
BIAS
GENERATOR
The ADL5369 has two LO inputs permitting multiple synthesizers
to be rapidly switched with extremely short switching times
(<40 ns) for frequency agile applications. The two inputs are
applied to a high isolation SPDT switch that provides a constant
input impedance, regardless of whether the port is selected, to
avoid pulling the LO sources. This multiple section switch also
ensures high isolation to the off input, minimizing any leakage
from the unwanted LO input that may result in undesired IF
responses.
6
7
LGM3
8
9
10
VLO3
VLO2
LOSW
NIC
NIC = NOT INTERNALLY CONNECTED.
Figure 44. Simplified Schematic
RF SUBSYSTEM
The single-ended LO input is converted to a fixed amplitude
differential signal using a multistage, limiting LO amplifier.
This results in consistent performance over a range of LO input
power. Optimum performance is achieved from −6 dBm to
+10 dBm, but the circuit continues to function at considerably
lower levels of LO input power.
The single-ended, 50 Ω RF input is internally transformed to a
balanced signal using a low loss (<1 dB), unbalanced to balanced
(balun) transformer. This transformer is made possible by an
extremely low loss metal stack, which provides both excellent
balance and dc isolation for the RF port. Although the port can
be dc connected, using a blocking capacitor is recommended to
avoid running excessive dc current through the device. The RF
balun can easily support an RF input frequency range of 300 MHz
to 1100 MHz.
Rev. A | Page 17 of 23
ADL5369
Data Sheet
The performance of this amplifier is critical in achieving a
high intercept passive mixer without degrading the noise floor
of the system. This is a critical requirement in an interferer rich
environment, such as cellular infrastructure, where blocking
interferers can limit mixer performance. The bandwidth of the
intermodulation performance is somewhat influenced by the
current in the LO amplifier chain. For dc current sensitive
applications, it is permissible to reduce the current in the LO
amplifier by raising the value of the external bias control resistor.
For dc current critical applications, the LO chain can operate
with a supply voltage as low as 3.3 V, resulting in substantial dc
power savings.
In addition, when operating with supply voltages below 3.6 V,
the ADL5369 has a power-down mode that permits the dc
current to drop to <200 μA.
All of the logic inputs work with any logic family that provides a
Logic 0 input level of less than 0.4 V and a Logic 1 input level that
exceeds 1.4 V. All logic inputs are high impedance up to Logic 1
levels of 3.3 V. At levels exceeding 3.3 V, protection circuitry
permits operation up to 5.5 V, although a small bias current
is drawn.
Rev. A | Page 18 of 23
Data Sheet
ADL5369
APPLICATIONS INFORMATION
BASIC CONNECTIONS
IF PORT
The ADL5369 mixer is designed to upconvert or downconvert
between radio frequencies (RF) from 300 MHz to 1100 MHz and
intermediate frequencies (IF) from 30 MHz to 450 MHz. Figure 45
depicts the basic connections of the mixer. It is recommended
to ac-couple the RF and LO input ports to prevent non-zero dc
voltages from damaging the RF balun or LO input circuit. The
RFIN capacitor value of 8 pF is recommended to provide the
optimized RF input return loss for the desired frequency band.
The real part of the output impedance is approximately 50 Ω,
as seen in Figure 25, which matches many commonly used SAW
filters without the need for a transformer. This results in a voltage
conversion loss that is approximately the same as the power
conversion loss, as shown in Table 3.
MIXER VGS CONTROL DAC
The ADL5369 features two logic control pins, Pin 12 (VGS0)
and Pin 13 (VGS1), that allow programmability for internal
gate to source voltages for optimizing mixer performance over
desired frequency bands. The evaluation board defaults both
VGS0 and VGS1 to ground. Power conversion loss, NF, and
IIP3 can be optimized, as shown in Figure 34 and Figure 35.
For upconversion, drive the IF inputs, Pin 18 (IFON) and Pin 19
(IFOP), differentially or use a 1:1 ratio transformer for single-
ended operation. An 8 pF capacitor is recommended for the RF
output, Pin 2 (RFIN).
IF1_OUT
T1
R1
0ꢀ
C25
560pF
C24
560pF
10kꢀ
910ꢀ
+5V
20
19
18
17
16
10pF
4.7µF
100pF
ADL5369
+5V
1
2
3
4
5
15
14
13
12
11
LO2_IN
+5V
100pF
RFIN
10pF
0.01µF
10pF
BIAS
GENERATOR
100pF
LO1_IN
6
7
8
9
10
R
BIAS LO
10kꢀ
+5V
10pF
10pF
Figure 45. Typical Application Circuit
Rev. A | Page 19 of 23
ADL5369
Data Sheet
EVALUATION BOARD
An evaluation board is available for the family of double balanced
mixers. The standard evaluation board schematic is shown in
Figure 46. The evaluation board is fabricated using Rogers®
RO3003 material.
Table 8 describes the various configuration options of the
evaluation board. Evaluation board layout is shown in Figure 47 to
Figure 50.
IF1_OUT
R1
0ꢀ
T1
C25
560pF
C24
560pF
PWR_UP
R21
10kꢀ
R14
910ꢀ
L3
0ꢀ
C12
100pF
LO2_IN
VPOS
VPOS
LOI2
VPMX
RFIN
C2
10µF
C21
10pF
C20
10pF
R22
10kꢀ
VPSW
RFIN
C22
R23
C1
100pF
1nF
15kꢀ
VGS1
ADL5369
RFCT
COMM
COMM
C5
0.01µF
C4
10pF
VGS1
VGS0
LOI1
VGS0
LO1_IN
C10
100pF
VPOS
LOSEL
R9
1.7kꢀ
C6
10pF
R4
10kꢀ
VPOS
C8
10pF
NIC = NOT INTERNALLY CONNECTED.
Figure 46. Evaluation Board Schematic
Rev. A | Page 20 of 23
Data Sheet
ADL5369
Table 8. Evaluation Board Configuration
Components
Description
Default Conditions
C2, C6, C8,
C20, C21
Power supply decoupling. Nominal supply decoupling consists of
a 10 μF capacitor to ground in parallel with a 10 pF capacitor to
ground positioned as close to the device as possible.
C2 = 10 μF (Size 0603),
C6, C8, C20, C21 = 10 pF (Size 0402)
C1, C4, C5
RF input interface. The input channels are ac-coupled through C1.
C4 and C5 provide bypassing for the center taps of the RF input baluns.
C1 = 100 pF (Size 0402), C4 = 10 pF (Size 0402),
C5 = 0.01 μF (Size 0402)
T1, R1, C24, C25 IF output interface. T1 is a 1:1 impedance transformer used to provide
a single-ended IF output interface. Remove R1 for balanced output
T1 = TC1-1-13M+ (Mini-Circuits),
R1 = 0 Ω (Size 0402),
operation. C24 and C25 are used to block the dc bias at the IF ports.
C24, C25 = 560 pF (Size 0402)
C10, C12, R4
LO interface. C10 and C12 provide ac coupling for the LO1_IN and
LO2_IN local oscillator inputs. LOSEL selects the appropriate LO input
for both mixer cores. R4 provides a pull-down to ensure that LO1_IN is
enabled when the LOSEL test point is logic low. LO2_IN is enabled
when LOSEL is pulled to logic high.
C10, C12 = 100 pF (Size 0402),
R4 = 10 kΩ (Size 0402)
R21
PWDN interface. R21 pulls the PWDN logic low and enables the device.
The PWR_UP test point allows the PWDN interface to be exercised
using the an external logic generator. Grounding the PWDN pin for
nominal operation is allowed. Using the PWDN pin when supply
voltages exceed 3.3 V is not allowed.
R21 = 10 kΩ (Size 0402)
C22, L3, R9, R14,
R22, R23, VGS0,
VGS1
Bias control. R22 and R23 form a voltage divider to provide 3 V for
logic control, bypassed to ground through C22. VGS0 and VGS1
jumpers provide programmability at the VGS0 and VGS1 pins. It is
recommended to pull these two pins to ground for nominal operation.
R9 sets the bias point for the internal LO buffers.
C22 = 1 nF (Size 0402), L3 = 0 Ω (Size 0603),
R9 = 1.7 kΩ (Size 0402), R14 = 910 Ω (Size 0402),
R22 = 10 kΩ (Size 0402), R23 = 15 kΩ (Size 0402),
VGS0 = VGS1 = 3-pin shunt
Rev. A | Page 21 of 23
ADL5369
Data Sheet
Figure 49. Evaluation Board Power Plane, Internal Layer 2
Figure 47. Evaluation Board Top Layer
Figure 48. Evaluation Board Ground Plane, Internal Layer 1
Figure 50. Evaluation Board Bottom Layer
Rev. A | Page 22 of 23
Data Sheet
ADL5369
OUTLINE DIMENSIONS
5.10
5.00 SQ
4.90
0.35
0.28
0.23
PIN 1
INDICATOR
PIN 1
INDICATOR
16
15
20
0.65
BSC
1
EXPOSED
PAD
3.25
3.10 SQ
2.95
5
11
6
10
0.70
0.60
0.40
0.25 MIN
TOP VIEW
BOTTOM VIEW
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.80
0.75
0.70
0.05 MAX
0.02 NOM
COPLANARITY
0.08
SECTION OF THIS DATA SHEET.
SEATING
PLANE
0.20 REF
COMPLIANT TO JEDEC STANDARDS MO-220-WHHC.
Figure 51. 20-Lead Lead Frame Chip Scale Package [LFCSP]
5 mm × 5 mm Body and 0.75 mm Package Height
(CP-20-9)
Dimensions shown in millimeters
ORDERING GUIDE
Package Ordering
Model1
Temperature Range
Package Description
Option
Quantity
1,500
1
ADL5369ACPZ-R7
ADL5369-EVALZ
−40°C to +85°C
20-Lead Lead Frame Chip Scale Package [LFCSP], 7”Tape and Reel
Evaluation Board
CP-20-9
1 Z = RoHS Compliant Part.
©2016 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D13361-0-5/16(A)
Rev. A | Page 23 of 23
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