ADL5511 [ADI]
Envelope and TruPwr RMS Detector; 信封和TruPwr RMS检波器
| 型号： | ADL5511 |
| 厂家： | 
ADI |
| 描述： | Envelope and TruPwr RMS Detector |
| 文件： | 总28页 (文件大小：2033K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DC to 6 GHz
Envelope and TruPwr RMS Detector
Data Sheet
ADL5511
FEATURES
FUNCTIONAL BLOCK DIAGRAM
VPOS
Envelope tracking RF detector with output proportional to
input voltage
15
ADL5511
Separate TruPwr rms output
20pF
400Ω
BIAS AND POWER-
ENBL
4
14 FLT4
DOWN CONTROL
No balun or external tuning required
Excellent temperature stability
Input power dynamic range of 47 dB
Input frequency range from dc to 6 GHz
130 MHz envelope bandwidth
Envelope delay: 2 ns
100Ω
11
G = 1.7
G = 1.5
VRMS
RMS
2
3
RFIN
FLT1
250Ω
10kΩ
10
9
VENV
EREF
ENVELOPE
5pF
250Ω
Single-supply operation: 4.75 V to 5.25 V
Supply current: 21.5 mA
0.8pF
VPOS
400Ω
0.4pF
VPOS
Power-down mode: 130 μW
13
6
7
8
12
16
1
5
FLT2
COMM
FLT3
NC
APPLICATIONS
Figure 1.
RMS power and envelope detection of W-CDMA, CDMA2000,
LTE, and other complex waveforms
Drain modulation based power amplifier linearization
Power amplifier linearization employing envelope-tracking
methods
CH1 HIGH
20mV
VRMS
VENV
RF INPUT
CH1 200mV Ω CH2 30.8mV Ω M 100ns
CH3 200mV CH4 234mV Ω
A CH4
1.60V
T
–68ns
Figure 2. RMS and Envelope Response to a 20 MHz QPSK-Based LTE Carrier
(Test Model E-TM1_1_20MHz)
GENERAL DESCRIPTION
The ADL5511 is an RF envelope and TruPwr™ rms detector.
The envelope output voltage is presented as a voltage that is
proportional to the envelope of the input signal. The rms
output voltage is independent of the peak-to-average ratio
of the input signal.
The ADL5511 can operate from dc to 6 GHz on signals with
envelope bandwidths up to 130 MHz.
The extracted envelope can be used for RF power amplifier
(PA) linearization and efficiency enhancements and the rms
output can be used for rms power measurement. The high rms
accuracy and fast envelope response are particularly useful for
envelope detection and power measurement of broadband, high
peak-to-average signals that are used in CDMA2000, W-CDMA,
and LTE systems.
The rms output is a linear-in-V/V voltage with a conversion
gain of 1.9 V/V rms at 900 MHz. The envelope output has a
conversion gain of 1.46 V/V at 900 MHz and is referenced to
an internal 1.1 V reference voltage, which is available on the
EREF pin.
The ADL5511 operates from −40°C to +85°C and is available in
a 16-lead, 3 mm × 3 mm LFCSP package.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2011–2012 Analog Devices, Inc. All rights reserved.
ADL5511
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Output Drive Capability and Buffering................................... 18
Applications Information .............................................................. 19
Basic Connections...................................................................... 19
Operation Below 1 GHz/Envelope Filtering........................... 19
Choosing a Value for the RMS Averaging Capacitor (CFLT4).. 20
Envelope Tracking Accuracy .................................................... 21
Time Domain Envelope Tracking Accuracy........................... 21
VRMS and VENV Output Offset............................................. 22
Device Calibration and Error Calculation.............................. 22
Error vs. Frequency.................................................................... 23
Evaluation Board ........................................................................ 24
Outline Dimensions....................................................................... 26
Ordering Guide .......................................................................... 26
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 7
ESD Caution.................................................................................. 7
Pin Configuration and Function Descriptions............................. 8
Typical Performance Characteristics ............................................. 9
Circuit Description......................................................................... 17
Envelope Propagation Delay..................................................... 17
RMS Circuit Description........................................................... 17
RMS Filtering.............................................................................. 17
REVISION HISTORY
2/12—Rev. 0 to Rev. A
Changes to Equation 4 ................................................................... 19
Updated Outline Dimensions....................................................... 26
7/11—Revision 0: Initial Version
Rev. A | Page 2 of 28
Data Sheet
ADL5511
SPECIFICATIONS
TA = 25°C, VPOS = 5 V, CFLT4 = 100 nF, 75 Ω shunt termination resistor to ground on (ac-coupled) RFIN, three-point calibration on VENV
and VRMS at +5 dBm, −15 dBm, and −26 dBm, unless otherwise noted.
Table 1.
Parameter
Conditions
Min
Typ
Max
Unit
FREQUENCY RANGE
ENVELOPE CONVERSION (100 MHz)
Input Range ( 1 dB Error)
Maximum Input Level
Minimum Input Level
Conversion Gain
Intercept
Input RFIN
DC
6
GHz
Input RFIN to output (VENV − VEREF
CW input
)
46
17
dB
dBm
dBm
V/V rms
mV
±1 dB error
−29
1.42
−5
±1 dB error
VENV = (Gain × VIN) + Intercept
Output Voltage
High Power In
Low Power In
PIN = +10 dBm, +707 mV rms
PIN = −20 dBm, +22.4 mV rms
1.00
26
V
mV
RMS Conversion
Input RFIN to output (VRMS
CW input
)
Input Range ( 1 dB Error)
Maximum Input Level
Minimum Input Level
Conversion Gain
Intercept
46
dB
17
dBm
dBm
V/V rms
mV
±1 dB error
−29
1.92
11
±1 dB error
VRMS = (Gain × VIN) + Intercept
Output Voltage
High Power In
Low Power In
PIN = +10 dBm, +707 mV rms
PIN = −20 dBm, +22.4 mV rms
Input RFIN to output (VENV − VEREF
CW input
1.38
53
V
mV
ENVELOPE CONVERSION (900 MHz)
Input Range ( 1 dB Error)
Maximum Input Level
Minimum Input Level
Conversion Gain
Intercept
)
46
17
dB
dBm
dBm
V/V rms
mV
±1 dB error
−29
1.46
−5
±1 dB error
VENV = (Gain × VIN) + Intercept
Output Voltage
High Power In
Low Power In
PIN = +10 dBm, +707 mV rms
PIN = −20 dBm, +22.4 mV rms
1.02
26
V
mV
RMS Conversion
Input RFIN to output (VRMS
CW input
)
Input Range ( 1 dB Error)
Maximum Input Level
Minimum Input Level
Conversion Gain
Intercept
46
dB
17
dBm
dBm
V/V rms
mV
±1 dB error
−29
1.9
13
±1 dB error
VRMS = (Gain × VIN) + Intercept
Output Voltage
High Power In
Low Power In
PIN = +10 dBm, +707 mV rms
PIN = −20 dBm, +22.4 mV rms
1.35
54
V
mV
Rev. A | Page 3 of 28
ADL5511
Data Sheet
Parameter
Conditions
Min
Typ
Max
Unit
ENVELOPE CONVERSION (1900 MHz)
Input Range ( 1 dB Error)
Input RFIN to output (VENV − VEREF
CW input
)
47
dB
Maximum Input Level
Minimum Input Level
Conversion Gain
Intercept
17
dBm
dBm
V/V rms
mV
±1 dB error
−30
1.5
−5
±1 dB error
VENV = (Gain × VIN) + Intercept
Output Voltage
High Power In
PIN = +10 dBm, +707 mV rms
PIN = −20 dBm, +22.4 mV rms
1.05
28
V
Low Power In
mV
RMS Conversion
Input Range ( 1 dB Error)
Maximum Input Level
Minimum Input Level
Conversion Gain
Intercept
Input RFIN to output (VRMS
CW input
)
47
dB
17
dBm
dBm
V/V rms
mV
±1 dB error
−30
1.96
14
±1 dB error
VRMS = (Gain × VIN) + Intercept
Output Voltage
High Power In
PIN = +10 dBm, +707 mV rms
PIN = −20 dBm, +22.4 mV rms
Input RFIN to output (VENV − VEREF
CW Input
1.40
56
V
Low Power In
mV
ENVELOPE CONVERSION (2140 MHz)
Input Range ( 1 dB Error)
Maximum Input Level
Minimum Input Level
Conversion Gain
Intercept
)
47
dB
17
dBm
dBm
V/V rms
mV
±1 dB error
−30
1.53
−5
±1 dB error
VENV = (Gain × VIN) + Intercept
Output Voltage
High Power In
PIN = +10 dBm, +707 mV rms
PIN = −20 dBm, +22.4 mV rms
1.07
28
V
Low Power In
mV
RMS Conversion
Input Range ( 1 dB Error)
Maximum Input Level
Minimum Input Level
Conversion Gain
Intercept
Input RFIN to output (VRMS
CW input
)
47
dB
17
dBm
dBm
V/V rms
mV
±1 dB error
−30
1.99
13
±1 dB error
VRMS = (Gain × VIN) + Intercept
Output Voltage
High Power In
PIN = +10 dBm, +707 mV rms
PIN = −20 dBm, +22.4 mV rms
1.42
56
V
Low Power In
mV
Rev. A | Page 4 of 28
Data Sheet
ADL5511
Parameter
Conditions
Min
Typ
Max
Unit
ENVELOPE CONVERSION (2600 MHz)
Input Range ( 1 dB Error)
Maximum Input Level
Minimum Input Level
Conversion Gain
Intercept
Input RFIN to output (VENV − VEREF
CW Input
)
47
17
dB
dBm
dBm
V/V rms
mV
±1 dB error
−30
1.56
−3
±1 dB error
VENV = (Gain × VIN) + Intercept
Output Voltage
High Power In
Low Power In
PIN = +10 dBm, +707 mV rms
PIN = −20 dBm, +22.4 mV rms
1.10
30
V
mV
RMS Conversion
Input RFIN to output (VRMS
CW input
)
Input Range ( 1 dB Error)
Maximum Input Level
Minimum Input Level
Conversion Gain
Intercept
47
dB
17
dBm
dBm
V/V rms
mV
±1 dB error
−30
2.04
15
±1 dB error
VRMS = (Gain × VIN) + Intercept
Output Voltage
High Power In
Low Power In
PIN = +10 dBm, +707 mV rms
PIN = −20 dBm, +22.4 mV rms
Input RFIN to output (VENV − VEREF
CW Input
1.46
58
V
mV
ENVELOPE CONVERSION (3500 MHz)
Input Range ( 1 dB Error)
Maximum Input Level
Minimum Input Level
Conversion Gain
Intercept
)
47
17
dB
dBm
dBm
V/V rms
mV
±1 dB error
−30
1.56
−5
±1 dB error
VENV = (Gain × VIN) + Intercept
Output Voltage
High Power In
Low Power In
PIN = +10 dBm, +707 mV rms
PIN = −20 dBm, +22.4 mV rms
1.10
28
V
mV
RMS Conversion
Input RFIN to output (VRMS
CW input
)
Input Range ( 1 dB Error)
Maximum Input Level
Minimum Input Level
Conversion Gain
Intercept
47
dB
17
dBm
dBm
V/V rms
mV
±1 dB error
−30
2.03
12
±1 dB error
VRMS = (Gain × VIN) + Intercept
Output Voltage
High Power In
Low Power In
PIN = +10 dBm, +707 mV rms
PIN = −20 dBm, +22.4 mV rms
1.46
57
V
mV
Rev. A | Page 5 of 28
ADL5511
Data Sheet
Parameter
Conditions
Min
Typ
Max
Unit
ENVELOPE CONVERSION (6000 MHz)
Input Range ( 1 dB Error)
Maximum Input Level
Minimum Input Level
Conversion Gain
Input RFIN to output (VENV − VEREF
CW Input
)
45
17
dB
dBm
dBm
V/V rms
mV
±1 dB error
−28
0.85
−10
±1 dB error
VENV = (Gain × VIN) + Intercept
Intercept
Output Voltage
High Power In
Low Power In
PIN = +10 dBm, +707 mV rms
PIN = −20 dBm, +22.4 mV rms
0.60
11
V
mV
RMS Conversion
Input RFIN to output (VRMS
CW input
)
Input Range ( 1 dB Error)
Maximum Input Level
Minimum Input Level
Conversion Gain
45
dB
17
dBm
dBm
V/V rms
mV
±1 dB error
−28
1.11
7
±1 dB error
VRMS = (Gain × VIN) + Intercept
Intercept
Output Voltage
High Power In
Low Power In
PIN = +10 dBm, +707 mV rms
PIN = −20 dBm, +22.4 mV rms
Pin VENV
VPOS = 5 V, RLOAD ≥ 500 Ω, CLOAD ≤ 10 pF
No signal at RFIN
3 dB
0.80
35
V
mV
ENVELOPE OUTPUT
Maximum Output Voltage
Output Offset
Envelope Bandwidth
Pulse Response Time
3.5
2
130
4
V
mV
MHz
ns
Input level = no signal to 5 dBm, 10% to
90% response time
Envelope Delay
RFIN to VENV
2
ns
Output Current Drive
RMS OUTPUT
Load = 500 Ω||10 pF
Pin VRMS
15
mA
Maximum Output Voltage
Output Offset
VPOS = 5 V, RLOAD ≥ 10 kΩ
No signal at RFIN
Load = 1.3 kΩ
3.8
23
3
V
mV
mA
Output Current Drive
ENABLE INTERFACE
Logic Level to Enable Power
Logic Level to Disable Power
POWER SUPPLIES
Pin ENBL
4.75 V ≤ VPOS ≤ 5.25 V
4.75 V ≤ VPOS ≤ 5.25 V
3.6
V
V
2.0
Operating Range
−40°C < TA < +85°C
4.75
5.25
V
Quiescent Current
RFIN < −10 dBm, ENBL high
RFIN < −10 dBm, ENBL low
RFIN = 15 dBm, ENBL high
21.5
26
43.8
mA
μA
mA
Rev. A | Page 6 of 28
Data Sheet
ADL5511
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rating
5.5 V
0 V, VPOS
5.6 V p-p
Supply Voltage, VPOS
ENBL
RFIN (RFIN AC-Coupled)
Equivalent RF Power (Peak Envelope Power or 19 dBm
CW), re: 50 Ω
Internal Power Dissipation
θJA
580 mW
68.9°C/W
17.5°C/W
125°C
−40°C to +85°C
−65°C to +150°C
1250 V
θJC
ESD CAUTION
Maximum Junction Temperature
Operating Temperature Range
Storage Temperature Range
ESD (FICDM)
ESD (HBM)
2000 V
Rev. A | Page 7 of 28
ADL5511
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PIN 1
INDICATOR
12 NC
FLT3 1
RFIN 2
FLT1 3
ENBL 4
11 VRMS
10 VENV
ADL5511
TOP VIEW
(Not to Scale)
9
EREF
NOTES
1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN.
2. THE EXPOSED PAD SHOULD BE CONNECTED
TO BOTH THERMAL AND ELECTRICAL GROUNDS.
Figure 3. Pin Configuration
Table 3. Pin Function Descriptions
Pin No.
Mnemonic Description
1, 16
FLT3, FLT2
External Envelope Filter. With the FLT3 and FLT2 pins not connected, two internal low-pass filters (operating
in series) with corner frequencies of approximately 1000 MHz and 800 MHz remove the residual RF carrier (at
two times the original input frequency) from the envelope signal. External, supply-referenced capacitors
connected to FLT3 and FLT2 can be used to reduce this corner frequency. See the Basic Connections section
for more information.
2
3
4
RFIN
FLT1
ENBL
RF Input. RFIN should be externally ac-coupled. RFIN has a nominal input impedance of 250 Ω. To achieve a
broadband 50 Ω input impedance, an external 75 Ω shunt resistor should be connected between the source
side of the ac coupling capacitor and ground.
External Envelope Filter. A capacitor to ground on this pin can be used to reduce the nominal minimum
input frequency. The capacitance on this pin helps to reduce any residual RF carrier presence on the EREF
output pin. See the Basic Connections section for more information.
Device Enable/Disable. A logic high on this pin enables the device. A logic low on this pin disables the
device.
5
COMM
NC
Device Ground. Connect to a low impedance ground plane.
Do not connect to these pins.
6, 7, 8, 12, 13
9
10
EREF
VENV
Reference Voltage for Envelope Output. The nominal value is 1.1 V.
Envelope Output. The voltage on this pin represents the envelope of the input signal and is referred to
EREF. VENV can source a current of up to 15 mA. Capacitive loading should not exceed 10 pF to achieve the
specified envelope bandwidth. Lighter loads should be chosen when possible. The nominal output voltages
on EREF and VENV with no signal present track with temperature. For dc-coupled envelope output, EREF
should be used as a reference giving the true envelope voltage of VENV − VEREF. For ac coupling of the
envelope output, the VENV pin can drive a 50 Ω load, if maximum current drive capability of 15 mA is not
exceeded. See the Output Drive Capability and Buffering section for more information.
11
VRMS
RMS Output Pin. This voltage is ground referenced and has a nominal swing of 0 V to 3.8 V. VRMS has a linear-
in-V/V transfer function with a nominal slope of 2 V/V.
14
15
0
FLT4
VPOS
EP
RMS Averaging Capacitor. Connect between FLT4 and VPOS.
Supply Voltage Pin. Operational range is 4.75 V to 5.25 V with a supply current of 21.5 mA.
Exposed Pad. The exposed pad should be connected to both thermal and electrical grounds.
Rev. A | Page 8 of 28
Data Sheet
ADL5511
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VPOS = 5 V, C FLT4 = 100 nF, 75 Ω shunt termination resistor to ground on (ac-coupled) RFIN, TA = +25°C (black), −40°C (blue),
+85°C (red), three-point calibration on VENV and VRMS at +5 dBm, −15 dBm, and −26 dBm, unless otherwise noted.
10
10
100MHz
900MHz
100MHz
900MHz
1900MHz
2140MHz
2600MHz
3500MHz
6000MHz
1900MHz
2140MHz
2600MHz
3500MHz
6000MHz
1
1
0.1
0.1
0.01
0.01
0.001
–30 –25 –20 –15 –10
–5
0
5
10
15
20
–30 –25 –20 –15 –10
–5
0
5
10
15
20
INPUT (dBm)
INPUT (dBm)
Figure 7. VRMS Output vs. Input Level, at Various Frequencies at 25°C,
Supply 5 V
Figure 4. VENV Output vs. Input Level, at Various Frequencies at 25°C,
Supply 5 V
10
10
5V, –40°C
5V, +25°C
5V, +85°C
5V, –40°C
5V, +25°C
5V, +85°C
1
0.1
1
0.1
0.01
0.01
0.001
–30 –25 –20 –15 –10
–5
0
5
10
15
20
–30 –25 –20 –15 –10
–5
0
5
10
15
20
INPUT (dBm)
INPUT (dBm)
Figure 8. VRMS Output vs. Input Level and Temperature at 1900 MHz,
Supply 5 V
Figure 5. VENV Output vs. Input Level and Temperature at 1900 MHz,
Supply 5 V
75
450
3.0
2.8
2.6
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
–40°C
+25°C
+85°C
70
65
60
55
50
45
40
35
30
25
20
15
10
5
400
350
300
250
200
150
100
50
SHUNT RESISTANCE
SHUNT CAPACITANCE
0
0
–30 –25 –20 –15 –10
–5
0
5
10
15
20
0
1
2
3
4
5
6
INPUT (dBm)
FREQUENCY (GHz)
Figure 6. Supply Current vs. Input Level and Temperature
Figure 9. Input Impedance vs. Frequency
Rev. A | Page 9 of 28
ADL5511
Data Sheet
3
3
2
2
1
1
0
0
–1
–2
–3
–1
–2
–3
–30
–25
–20
–15
–10
P
–5
0
5
10
15
–30
–25
–20
–15
–10
P
–5
0
5
10
15
(dBm)
(dBm)
IN
IN
Figure 10. VENV Output Temperature Drift from +25°C, Three-Point
Calibration for Multiple Devices at −40°C, +25°C, and +85°C at 100 MHz
Figure 13. VENV Output Delta from +25°C Output Voltage for
Multiple Devices at −40°C and +85°C at 100 MHz
3
3
2
1
0
2
1
0
–1
–2
–3
–1
–2
–3
–30
–25
–20
–15
–10
P
–5
0
5
10
15
–30
–25
–20
–15
–10
P
–5
0
5
10
15
(dBm)
(dBm)
IN
IN
Figure 11. VRMS Output Temperature Drift from +25°C, Three-Point
Calibration for Multiple Devices at −40°C, +25°C, and +85°C at 100 MHz
Figure 14. VRMS Output Delta from +25°C Output Voltage for
Multiple Devices at −40°C and +85°C at 100 MHz
3
3
2
1
0
2
1
0
–1
–2
–3
–1
–2
–3
–30
–25
–20
–15
–10
P
–5
0
5
10
15
–30 –25
–20
–15
–10
P
–5
0
5
10
15
(dBm)
(dBm)
IN
IN
Figure 12. VENV Output Temperature Drift from +25°C, Three-Point
Calibration for Multiple Devices at −40°C, +25°C, and +85°C at 900 MHz
Figure 15. VENV Output Delta from +25°C Output Voltage for
Multiple Devices at −40°C and +85°C at 900 MHz
Rev. A | Page 10 of 28
Data Sheet
ADL5511
3
2
3
2
1
1
0
0
–1
–2
–3
–1
–2
–3
–30
–25
–20
–15
–10
–5
0
5
10
15
–30
–25
–20
–15
–10
–5
0
5
10
15
P
(dBm)
IN
P
(dBm)
IN
Figure 16. VRMS Output Temperature Drift from +25°C, Three-Point
Calibration for Multiple Devices at −40°C, +25°C, and +85°C at 900 MHz
Figure 19. VRMS Output Delta from +25°C Output Voltage for
Multiple Devices at −40°C and +85°C at 900 MHz
3
3
2
2
1
1
0
0
–1
–2
–3
–1
–2
–3
–30
–25
–20
–15
–10
P
–5
0
5
10
15
–30
–25
–20
–15
–10
P
–5
0
5
10
15
(dBm)
(dBm)
IN
IN
Figure 17. VENV Output Temperature Drift from +25°C, Three-Point
Calibration for Multiple Devices at −40°C, +25°C, and +85°C at 1900 MHz
Figure 20. VENV Output Delta from +25°C Output Voltage for
Multiple Devices at −40°C and +85°C at 1900 MHz
3
2
3
2
1
1
0
0
–1
–2
–3
–1
–2
–3
–30
–25
–20
–15
–10
P
–5
0
5
10
15
–30
–25
–20
–15
–10
P
–5
0
5
10
15
(dBm)
(dBm)
IN
IN
Figure 18. VRMS Output Temperature Drift from +25°C, Three-Point
Calibration for Multiple Devices at −40°C, +25°C, and +85°C at 1900 MHz
Figure 21. VRMS Output Delta from +25°C Output Voltage for
Multiple Devices at −40°C and +85°C at 1900 MHz
Rev. A | Page 11 of 28
ADL5511
Data Sheet
3
3
2
2
1
1
0
0
–1
–2
–1
–2
–3
–3
–30
–25
–20
–15
–10
P
–5
0
5
10
15
–30
–25
–20
–15
–10
P
–5
0
5
10
15
(dBm)
(dBm)
IN
IN
Figure 22. VENV Output Temperature Drift from +25°C, Three-Point
Calibration for Multiple Devices at −40°C, +25°C, and +85°C at 2140 MHz
Figure 25. VENV Output Delta from +25°C Output Voltage for
Multiple Devices at −40°C and +85°C at 2140 MHz
3
2
3
2
1
1
0
0
–1
–2
–3
–1
–2
–3
–30
–25
–20
–15
–10
P
–5
0
5
10
15
–30
–25
–20
–15
–10
P
–5
0
5
10
15
(dBm)
(dBm)
IN
IN
Figure 23. VRMS Output Temperature Drift from +25°C, Three-Point
Calibration for Multiple Devices at −40°C, +25°C, and +85°C at 2140 MHz
Figure 26. VRMS Output Delta from +25°C Output Voltage for
Multiple Devices at −40°C and +85°C at 2140 MHz
3
2
3
2
1
1
0
0
–1
–2
–3
–1
–2
–3
–30
–25
–20
–15
–10
–5
0
5
10
15
–30
–25
–20
–15
–10
–5
0
5
10
15
P
(dBm)
IN
P
(dBm)
IN
Figure 24. VENV Output Temperature Drift from +25°C, Three-Point
Calibration for Multiple Devices at −40°C, +25°C, and +85°C at 2600 MHz
Figure 27. VENV Output Delta from +25°C Output Voltage for
Multiple Devices at −40°C and +85°C at 2600 MHz
Rev. A | Page 12 of 28
Data Sheet
ADL5511
3
2
3
2
1
1
0
0
–1
–2
–3
–1
–2
–3
–30
–25
–20
–15
–10
P
–5
0
5
10
15
–30
–25
–20
–15
–10
P
–5
0
5
10
15
(dBm)
(dBm)
IN
IN
Figure 31. VRMS Output Delta from +25°C Output Voltage for
Multiple Devices at −40°C and +85°C at 2600 MHz
Figure 28. VRMS Output Temperature Drift from +25°C Linear Reference
for Multiple Devices at −40°C, +25°C, and +85°C, 2600 MHz Frequency
3
3
2
2
1
1
0
0
–1
–2
–3
–1
–2
–3
–30
–25
–20
–15
–10
P
–5
0
5
10
15
–30
–25
–20
–15
–10
P
–5
0
5
10
15
(dBm)
(dBm)
IN
IN
Figure 32. VENV Output Delta from +25°C Output Voltage for
Multiple Devices at −40°C and +85°C at 3500 MHz
Figure 29. VENV Output Temperature Drift from +25°C Linear Reference
for Multiple Devices at −40°C, +25°C, and +85°C, 3500 MHz Frequency
3
3
2
2
1
1
0
0
–1
–2
–3
–1
–2
–3
–30
–25
–20
–15
–10
P
–5
0
5
10
15
–30
–25
–20
–15
–10
P
–5
0
5
10
15
(dBm)
(dBm)
IN
IN
Figure 33. VRMS Output Delta from +25°C Output Voltage for
Multiple Devices at −40°C and +85°C at 3500 MHz
Figure 30. VRMS Output Temperature Drift from +25°C Linear Reference
for Multiple Devices at −40°C, +25°C, and +85°C, 3500 MHz Frequency
Rev. A | Page 13 of 28
ADL5511
Data Sheet
3
3
2
2
1
1
0
0
–1
–2
–1
–2
–3
–3
–30
–25
–20
–15
–10
–5
0
5
10
15
–30
–25
–20
–15
–10
–5
0
5
10
15
P
(dBm)
IN
P
(dBm)
IN
Figure 34. VENV Output Temperature Drift from +25°C Linear Reference
for Multiple Devices at −40°C, +25°C, and +85°C, 6000 MHz Frequency
Figure 37. VENV Output Delta from +25°C Output Voltage for
Multiple Devices at −40°C and +85°C at 6000 MHz
3
2
1
0
3
2
1
0
–1
–2
–3
–1
–2
–3
–30
–25
–20
–15
–10
–5
0
5
10
15
–30
–25
–20
–15
–10
–5
0
5
10
15
P
(dBm)
IN
P
(dBm)
IN
Figure 35. VRMS Output Temperature Drift from +25°C Linear Reference
for Multiple Devices at −40°C, +25°C, and +85°C, 6000 MHz Frequency
Figure 38. VRMS Output Delta from +25°C Output Voltage for
Multiple Devices at −40°C and +85°C at 6000 MHz
20
10
2
–40°C
+25°C
0
–2
+85°C
0
–10
–20
–30
–40
–50
–4
–6
–8
–10
–12
–14
–16
–60
THD (dBc)
–70
CARRIER SUPPRESSION (dBc)
ENVELOPE GAIN (dB)
–80
–35 –30 –25 –20 –15 –10 –5
RFIN (dBm)
0
5
10
15
1
10
100
1000
ENVELOPE FREQUENCY (MHz)
Figure 39. Normalized VENV Frequency Response, VENV AC-Coupled into a
50 Ω Spectrum Analyzer Load
Figure 36. THD on VENV vs. RF Input Level; 1900 MHz RF Input, AM Modulated
by a 20 MHz Sine Wave (Modulation Index = 0.25), VENV Output AC-Coupled
into a 50 Ω Spectrum Analyzer Load
Rev. A | Page 14 of 28
Data Sheet
ADL5511
PULSED RFIN
1
V
ENBL
4
+5dBm
+1dBm
–3dBm
–10dBm
+5dBm
+1dBm
–3dBm
–10dBm
2
R1
CH1 200mV Ω
CH3 125mV Ω
REF4 125mV 10ns
M10ns
111.6ns
A CH2
1.88V
CH4 7V
REF1 250mV 1µs
M1µs
T
A CH4
3.78V
T
3.996µs
Figure 43. VENV Output Response to Enable Gating at Various RF Input Levels,
900 MHz Frequency
Figure 40. VENV Output Response to Various RF Input Pulse Levels
900 MHz Frequency
2
V
ENBL
PULSED RFIN
+5dBm
4
+1dBm
–3dBm
+5dBm
+1dBm
–3dBm
–10dBm
–10dBm
R4
R1
CH2 200mV Ω
REF4 125mV 1µs
M1µs
T
A CH4
2.2V
CH4 7V
REF1 220mV 1µs
M1µs
T
A CH4
3.78V
–824ns
4.012µs
Figure 44. VRMS Output Response to Enable Gating at Various RF Input Levels,
900 MHz Frequency, CFLT4 = Open
Figure 41. VRMS Output Response to Various RF Input Pulse Levels
900 MHz Frequency, CFLT4 = Open
V
2
ENBL
4
PULSED RFIN
+5dBm
+1dBm
+5dBm
+1dBm
–3dBm
–3dBm
–10dBm
–10dBm
R4
R4
CH4 7V
REF4 220mV 40µs
M40µs
160.4µs
A CH4
3.78V
CH2 200mV Ω M100µs
REF4 125mV 100µs
A CH4
2.2V
T
T
–100.5µs
Figure 45. VRMS Output Response to Enable Gating at Various RF Input Levels,
900 MHz Frequency, CFLT4 = 100 nF
Figure 42. VRMS Output Response to Various RF Input Pulse Levels,
900 MHz Frequency, CFLT4 = 100 nF
Rev. A | Page 15 of 28
ADL5511
Data Sheet
3
3
2
CW
QAM64
QPSK
1CWCDMA
4CWCDMA
LTE
CW
QAM64
QPSK
1CWCDMA
4CWCDMA
LTE
2
1
1
0
0
–1
–2
–3
–1
–2
–3
–25
–20
–15
–10
–5
0
5
10
15
–25
–20
–15
–10
–5
0
5
10
15
INPUT (dBm)
INPUT (dBm)
Figure 46. VRMS Error from CW Linear Reference vs. Signal Modulation,
Frequency = 900 MHz, CLPF = 0.1 µF (CW, QPSK, QAM64, 1CW-CDMA,
4CW-CDMA, LTE Test Model E-TM1_1_20MHz)
Figure 47. VRMS Error from CW Linear Reference vs. Signal Modulation,
Frequency = 2140 MHz, CLPF = 0.1 µF (CW, QPSK, QAM64, 1CW-CDMA,
4CW-CDMA, LTE Test Model E-TM1_1_20MHz)
Rev. A | Page 16 of 28
Data Sheet
ADL5511
CIRCUIT DESCRIPTION
The ADL5511 employs a proprietary rectification technique
to strip off the carrier of an input signal to reveal the true
envelope. In this first detection stage, the carrier frequency
is doubled and an on-chip two-pole passive low-pass filter
accurately preserves the envelope and filters out the carrier.
The poles of this filter, as defined by the on-chip RC filters
(0.4 pF, 400 Ω, 0.8 pF, 250 Ω) values allow some carrier
leakthrough for common RF frequencies. This is to ensure
that maximum envelope bandwidth can be maintained.
For more details, see the Basic Connections section.
RMS CIRCUIT DESCRIPTION
The rms processing is done using a proprietary translinear
technique. This method is a mathematically accurate rms
computing approach and achieves unprecedented rms
accuracies for complex modulation signals irrespective of
the crest factor of the input signal. An integrating filter
capacitor does the square-domain averaging. The VRMS
output can be expressed as
T2
VI2N ×dt
∫
VPOS
T1
VRMS = A×
15
T2 −T1
ADL5511
(1)
20pF
400Ω
BIAS AND POWER-
DOWN CONTROL
Note that A is a scaling parameter that is decided on by the on-chip
resistor ratio, and there are no other scaling parameters involved in
this computation, which means that the rms output is inherently
free from any sources of error due to temperature, supply, and
process variation.
ENBL
4
14 FLT4
100Ω
11
G = 1.7
G = 1.5
VRMS
RMS
2
3
RFIN
FLT1
250Ω
10kΩ
10
9
VENV
EREF
ENVELOPE
5pF
RMS FILTERING
250Ω
0.8pF
VPOS
400Ω
The on-chip rms filtering corner is internally set by a 400 Ω resistor
and a 20 pF capacitor, yielding a corner frequency of approximately
20 MHz. Whereas this filters out all carrier frequencies, most of the
modulation envelope is not filtered. For adequate rms filtering,
connect an external filter capacitor between FLT4 (Pin 14) and
VPOS (Pin 15). This capacitance acts on the internal 400 Ω
resistor (see Figure 48) to yield a new corner frequency for the
rms filter given by
0.4pF
VPOS
13
6
7
8
12
16
1
5
FLT2
COMM
FLT3
NC
Figure 48. Block Diagram
The extracted envelope is further processed in two parallel
channels, one computing the rms value of the envelope and
the other transferring the envelope with appropriate scaling
to the envelope output.
1
CFLT4
=
− 20 pF
(2)
(2π × fRMS × 400 Ω)
ENVELOPE PROPAGATION DELAY
For example, a supply-referenced 0.1 µF capacitor on FLT4
reduces the corner frequency of the rms averaging circuit to
approximately 4 kHz.
The delay specified in this data sheet is with no external
capacitor at the FLT2 and FLT3 pins. The delay through the
ADL5511, although very small, depends upon a number of
factors, notable of which are internal filter component values
and op amp compensation capacitors. The delay will vary from
part to part by approximately 15% due to process variations.
RMS filtering has a direct impact on rms accuracy. For most
accurate detection, the rms filter corner should be low enough
to filter out most of the modulation content. This will corre-
spond to a corner frequency that is significantly lower than the
bandwidth of the signal being measured. See the Choosing a
Value for the RMS Averaging Capacitor (CFLT4) section for more
details and filtering options.
In addition, the choice of external FLT2 and FLT3 values, as
well as load on the VNEV pin will increase the delay. In this
case, the delay variation will be dominated by the part-to-part
tolerance of the external capacitors.
Rev. A | Page 17 of 28
ADL5511
Data Sheet
The VRMS buffered output can source a maximum current of
3 mA, but is not designed to sink any appreciable amount of
current. If current sink capability is desired at this pin, a shunt
resistance to ground can be connected. The VRMS output has
an on-chip series resistance of 100 Ω, to allow a low-pass
filtering of the residual ripple using a single shunt capacitor
at this pin. Large shunt capacitors at this pin may also require
a shunt resistor to be placed to allow fast discharging of the
capacitor. The internal shunt resistance on the VRMS pin is
10 kΩ. Note that any shunt resistance placed on this pin creates
a resistive divider with the on-chip 100 Ω series resistance.
OUTPUT DRIVE CAPABILITY AND BUFFERING
The envelope output of the ADL5511 is presented on the VENV
pin as a single-ended buffered output with low output imped-
ance. To achieve high envelope bandwidth, this output is not
ground referenced, unlike the VRMS output, which is ground
referenced.
The VENV output has a no signal dc value of about 1.1 V.
This dc reference is temperature dependent and is presented
as a standalone reference voltage on the EREF pin and as a
buffered output. The true envelope at any instant of time is
simply (VENV − VEREF), but these two pins do not constitute a
differential output. EREF is a fixed dc voltage and VENV carries
all the envelope information.
The EREF output buffer also has 3 mA current sourcing
capability. The internal shunt resistance on this pin through
which any current must be sunk, is 12 kΩ. A capacitor to
ground can be placed on this pin to eliminate any RF or
envelope ripple at this pin to ensure that voltage at this pin
acts as a clean reference for the VENV output for all possible
carrier and envelope frequencies.
The VENV output is capable of supporting a parallel load of
500 Ω and 10 pF at full-scale envelope output and maximum
bandwidth. Lighter loads (higher R and lower C) are always
recommended whenever possible to minimize power
consumption and achieve maximum possible bandwidth.
The maximum source/sink current capacity of the VNEV
output is 15 mA peak and load conditions should be such
that this is not exceeded. The maximum output voltage at
this pin is approximately (VPOS − 1.5) V.
Viewing the Envelope on an Oscilloscope
When viewing the VENV output on an oscilloscope, use a low
capacitive FET probe. This reduces the capacitance presented to
the VENV output and avoids the corresponding effects of larger
capacitive loads.
For the case of ac coupling only, the VENV output can drive
a 50 Ω load, as long as the maximum signal swing does not
exceed an amplitude of approximately 1.5 V p-p. This corre-
sponds to the peak signal current of 15 mA into the 50 Ω load.
If a 50 Ω drive capability is desired, the maximum input signal
to ADL5511 should be adjusted, such that this output swing
condition is not exceeded. A 50 Ω load should never be dc
coupled to the VENV output, as it presents a current draw of
>20 mA even for no-signal condition corresponding to 1.1 V
nominal dc voltage at the VENV pin.
Rev. A | Page 18 of 28
Data Sheet
ADL5511
APPLICATIONS INFORMATION
C14
0.1µF
+5V
C13
100pF
VPOS
15
ADL5511
C17
20pF
400Ω
0.1µF
BIAS AND POWER-
DOWN CONTROL
FLT4
ENBL
4
14
11
VPOS
100Ω
VRMS
RMS
OUTPUT
C1
G = 1.7
G = 1.5
RMS
100pF
RFIN
FLT1
2
3
R5
75Ω
250Ω
10kΩ
VENV
EREF
ENVELOPE
OUTPUT
10
9
ENVELOPE
C2
100pF
5pF
250Ω
ENVELOPE
REFERENCE
0.8pF
VPOS
400Ω
0.4pF
VPOS
13
6
7
8
12
16
1
5
FLT2 FLT3
C6
COMM
NC
(SEE TEXT)
C10
(SEE TEXT)
VPOS
Figure 49. Basic Connections
ground referenced capacitor to Pin 3 (FLT1). The value of the
external capacitance is set using the following equation:
BASIC CONNECTIONS
Basic connections for operation of the ADL5511 are shown in
Figure 49. The ADL5511 requires a single supply of 5 V. The
supply is connected to the VPOS supply pin. Decouple this
pin using two capacitors with values equal or similar to those
shown in Figure 49. Place these capacitors as close as possible
to the VPOS pin.
1
CFLT1
=
− 5 pF
(3)
(2π × f3dB ×10,000 Ω)
For example, a 100 pF capacitance on FLT1 will reduce the
corner frequency to 150 kHz. As a general guideline, this
corner frequency should be set to be at least one tenth of the
minimum expected carrier frequency. This ensures a flat
frequency response around the frequency of interest.
An external 75 Ω resistor combines with the relatively high
RF input impedance of the ADL5511 to provide a broadband
50 Ω match. Place an ac coupling capacitor between this resistor
and RFIN.
The envelope detection path of the ADL5511 includes internal
carrier-suppression low-pass filtering. With the FLT2 and FLT3
pins not connected, two internal 1 GHz and 800 MHz low-pass
filters (operating in series) remove the RF carrier from the
envelope output signal.
The envelope output is available on Pin 10 (VENV) and is
referenced to the 1.1 V dc voltage on Pin 9 (EREF).
The rms output voltage is available at the VRMS pin with rms
averaging provided by the supply-referenced capacitance on
Pin 14 (FLT4).
The equations for these filters are as follows:
1
≅1GHz
(4)
OPERATION BELOW 1 GHZ/ENVELOPE FILTERING
(2π × 0.4 pF × 400 Ω)
To operate the ADL5511 at frequencies below 1 GHz, a number
of external capacitors must be added to the FLT3, FLT2, and
FLT1 pins. These changes are in addition to the choice of an
appropriate rms averaging capacitor, see the Choosing a Value
for the RMS Averaging Capacitor (CFLT4) section.
and
1
≅ 800 MHz
(5)
(2π × 0.8 pF × 250 Ω)
Because the envelope detection circuitry includes a full-wave
As part of the internal signal processing algorithm, the RF
input signal passes through a low-pass filter comprising of a
10 kΩ resistor and a 5 pF capacitor (see Figure 49). This
corresponds to a corner frequency of approximately 3.2 MHz.
If the carrier frequency is less than approximately ten times this
value (32 MHz), this corner frequency must be reduced. The
internal 5 pF capacitance can be augmented by connecting a
rectifier, this filter has to primarily suppress the signal at twice
the original input frequency.
Rev. A | Page 19 of 28
ADL5511
Data Sheet
For input frequencies in the 900 MHz range, there will still be
significant carrier content on the envelope output. With the
two filters providing a combined 6 dB roll-off at approximately
900 MHz and with the residual carrier at 1.8 GHz, carrier
filtering of approximately 18 dB can be expected (the two
single-pole filters provide a combined roll-off of 12 dB per
octave.
(Pin 14) and VPOS (Pin 15). This capacitance acts on the
internal 400 Ω resistor to yield a new corner frequency for the
rms filter given by the following equation:
1
CFLT4
=
− 20 pF
(8)
(2π × fFLT 4 × 400 Ω)
For example, a supply-referenced 0.1 µF capacitor on FLT4
reduces the corner frequency of the rms averaging circuit to
approximately 4 kHz.
The internal filtering of the carrier in the envelope detection
path can be augmented by adding additional supply-referenced
capacitance to the FLT2 and FLT3 pins. The required capaci-
tance can be calculated using the following equations:
The size of the rms filtering capacitor has a direct impact on
the rms accuracy up to a point. For most accurate detection, the
rms filter corner should be low enough to filter out most of the
modulation content. This corresponds to a corner frequency
that is significantly less than the bandwidth of the signal being
measured.
1
CFLT2
=
− 0.4 pF
(6)
(2π × fFLT2 × 400 Ω)
and
Table 4 shows recommended minimum values of CFLT4 for
popular modulation schemes. Using smaller capacitor values
than these will result in rms measurement errors; using higher
values will not further improve rms accuracy but will reduce the
output noise on VRMS at the expense of increased rise and fall
times. In Table 4, rise and fall times are also shown along with
residual output noise.
1
CFLT3
=
− 0.8 pF
(7)
(2π × fFLT3 ×250 Ω)
where fLT2 and fLT3 are the desired corner frequencies.
For example, to set the corner frequency to 200 MHz, CFLT2
and CFLT3 should be set to 1.6 pF and 2.4 pF, respectively.
The two corner frequencies should be set so that they are
approximately equal.
The recommended minimum values for CFLT4 were experimen-
tally determined by starting out with a large capacitance value
on the FLT4 pin (for example, 10 µF). The value of VRMS was
noted for a fixed input power level (for example, 0 dBm). The
value of CFLT4 was then progressively reduced (this can be done
with press-down capacitors) until the value of VRMS started to
deviate from its original value (this indicates that the accuracy
of the rms computation is degrading and that CFLT4 is becoming
too small).
Care should be taken not to set the corner frequency of this
carrier suppression filter too low as it will start to degrade
envelope bandwidth. The ADL5511 has an envelope bandwidth
of 130 MHz. Thus, if the capacitors on FLT2 and FLT3 are so
big that the carrier-suppression corner frequency approaches
130 MHz, the carrier filtering effort will directly impact the
envelope bandwidth. Thus, the corner frequency should be set
low enough so that the RF carrier is adequately removed from
the envelope output while still maintaining the desired envelope
bandwidth. An alternative option would be to filter the carrier
at the VENV output using a higher order filter.
The recommended minimum value for CFLT4 is roughly
inversely proportional to the bandwidth of the input signal, that
is, wider bandwidth signals tend to require smaller minimum
filter capacitances. As already noted, the value of CFLT4 sets up
an internal low pass corner frequency, which filters the rms
voltage. As carrier bandwidth increases, a larger proportion
of the residual noise (which has been effectively mixed down
to baseband) is filtered away. This results in smaller capaci-
tances being required as carrier bandwidths increase.
CHOOSING A VALUE FOR THE RMS AVERAGING
CAPACITOR (CFLT4
)
CFLT4 provides the averaging function for the internal rms
computation, the result of which is available at the VRMS
output. As already noted, the on-chip rms filtering corner is
internally set by a 400 Ω resistor and a 20 pF capacitor, yielding a
corner frequency of approximately 20 MHz. For adequate rms
filtering, connect an external filter capacitor between FLT4
Table 4. Recommended Minimum CFLT4 Values for Various Modulation Schemes (Pin = 0 dBm)
PEP to RMS
Ratio
Signal
Bandwidth (Min)
CFLT4
Modulation/Standard
Output Noise
98 mV p-p
140 mV p-p
Rise/Fall Time (10% to 90%)
82 µs/310 µs
40 µs/140 µs
W-CDMA, One-Carrier, TM1-64
W-CDMA Four-Carrier, TM1-64, TM1-32,
TM1-16, TM1-8
9.83 dB
12.08 dB
3.84 MHz
220 nF
100 nF
18.84 MHz
LTE Test Model E-TM1_1_4MHz
LTE Test Model E-TM1_1_10MHz
LTE Test Model E-TM1_1_20MHz
9.83 dB
11.99 dB
11.58 dB
4 MHz
10 MHz
20 MHz
220 nF
100 nF
47 nF
135 mV p-p
89 mV p-p
90 mV p-p
82 µs/310 µs
40 µs/140 µs
20 µs/70 µs
Rev. A | Page 20 of 28
Data Sheet
ADL5511
For applications that are not response time critical, a
relatively large capacitor can be placed on the FLT4.
improves until it sharply degrades at an input power level of
approximately 13 dBm. This sharp decrease is caused by the
clipping of the AM signal’s peak envelope. Figure 51 also shows
carrier leakage at VENV in dBc with respect to the input carrier
amplitude.
There is no maximum capacitance limit for CFLT4
.
Figure 50 shows how output noise, rise time and fall time
vary vs. CFLT4 when the ADL5511 is driven by an 1.9 GHz
LTE carrier with a bandwidth of 10 MHz (LTE Test Model
E-TM1_1_10MHz, peak-to-average ratio = 11.99 dB).
This measurement, when conducted over the full input power
range of the ADL5511, suffers from measurement inaccuracies
of the input modulated signal due to the spectrum analyzer’s
noise floor and therefore does not accurately reveal the ADL5511’s
limitations at the lower end of the measurement range. In
addition to this, the process of generating an AM signal for this
test (using the ADL5390 multiplier) is not perfect and resulted
in a source signal whose envelope was not harmonically pure.
800
700
600
500
400
300
200
100
0
10000000
OUTPUT NOISE (mV p-p)
10% TO 90% RISE TIME (µs)
90% TO 10% FALL TIME (µs)
1000000
100000
10000
1000
100
TIME DOMAIN ENVELOPE TRACKING ACCURACY
The envelope tracking accuracy of the ADL5511 can also be
assessed in the time domain by looking at the input peak power
levels that cause clipping.
10
1
The usable rms input power range of the ADL5511 varies
depending on the desired accuracy level and the peak-to-
average ratio of the input signal. Figure 4 shows the linear
operating range of the VENV output when the RF input is
driven by unmodulated sine waves at various frequencies.
This shows operation up to rms input levels of approximately
19 dBm. If the signal has a peak-to-average ratio that is greater
than the square root of two, the usable input range on RFIN
will decrease. In general, the maximum input power for linear
operation should be determined by the peak envelope power
(PEP) of the input signal. Figure 52 shows the time-domain
response of the VENV output to a 900 MHz LTE carrier with
a bandwidth of 20 MHz (Test Model E-TM1_2_20MHz).
The signal level of the carrier (7 dBm rms, 19 dBm PEP)
was deliberately increased until clipping was observed at
the VENV output.
0.1
1
10
100
1000
C
(nF)
FLT4
Figure 50. Output Noise, Rise and Fall Times vs. CFLT4 Capacitance, 10 MHz
BW LTE Carrier (LTE Test Model E-TM1_1_10MHz) at 1.9 GHz with PIN = 0 dBm
ENVELOPE TRACKING ACCURACY
The envelope tracking accuracy of the ADL5511 is measured in
terms of the higher order distortion of the envelope output when
the RF input signal is AM modulated using a low-harmonic
sinusoid at a given frequency. Such an input sinusoidal envelope
has been generated using the ADL5390 multiplier modulator.
This generates a double sideband AM modulated signal of a
known modulation index. In this measurement, the ADL5511
acts as free-running AM demodulator without requiring a local
oscillator to demodulate the signal.
20
Note that the peak envelope power of a signal is derived
based on the rms level of the signal during a peak cycle, that is
V p-p/√2. For example, a signal that achieves a peak voltage of
10 V (or 20 V p-p) has a PEP of 30 dBm. According to this
definition, the PEP of a sine wave is equal to its rms power
level because it has a constant envelope.
10
0
–10
–20
–30
–40
–50
–60
THD (dBc)
–70
CARRIER SUPPRESSION (dBc)
ENVELOPE GAIN (dB)
–80
–35 –30 –25 –20 –15 –10 –5
0
5
10
15
RFIN (dBm)
Figure 51. THD on VENV vs. RF Input Level; 1900 MHz RF Input, AM Modulated
by a 20 MHz Sine Wave (Modulation Index = 0.25), VENV Output AC-Coupled
into a 50 Ω Spectrum Analyzer Load
Figure 51 shows such a plot total harmonic distortion (THD)
of the VENV output vs. RF input power for the modulation
index of 0.25. As the input power level increases, the THD
Figure 52. VENV Response to a 20 MHz LTE Carrier with a PEP of 19 dBm that
has been Triggered to Capture the Envelope’s Peak Level
Rev. A | Page 21 of 28
ADL5511
Data Sheet
VRMS AND VENV OUTPUT OFFSET
DEVICE CALIBRATION AND ERROR CALCULATION
The 900 MHz RF power sweeps in Figure 53 and Figure 54
show distributions of the VRMS and VENV outputs voltages
for multiple devices at 25°C. The VRMS output response
flattens out at approximately −30 dBm while the various VENV
response traces begin to fanout unpredictably (Figure 4 and
Figure 7 show this behavior at other frequencies). While these
plots suggest that operation at input levels down to −30 dBm is
feasible, account must also be taken for variations over
temperature. Figure 10 to Figure 38 show how the linearity
error starts to increase below input levels of −20 dBm (the
size of the error varies between VENV and VRMS and with
frequency).
Because slope and intercept vary from device to device,
calibration must be performed to achieve high accuracy.
In general, calibration is performed by applying two or more
known input power levels to the ADL5511 and measuring
the corresponding output voltages. The calibration points
are generally chosen to be within the linear operating range
of the device. For a two-point calibration, the conversion gain
(or slope) and intercept are calculated for VRMS and VENV using the
following equations:
Slope = (VOUT2 − VOUT1)/(VIN2 − VIN1
Intercept = VOUT1 − (Slope × VIN1
where:
)
(9)
)
(10)
10000
V
V
IN is the rms input voltage to RFIN.
OUT is the voltage output at VRMS or VENV.
1000
100
10
Because the gain and intercept of the rms and envelope paths
will be different, both paths should be calibrated, that is, with a
measured signal applied to RFIN, VENV, and VRMS. To ensure
that the voltage at VENV and VRMS is a steady-state value, a
constant envelope signal such as a sine wave should be used as
the source during calibration.
Once slope and intercept are calculated, an equation can be
written that allows calculation of the input rms or envelope level
using the following equations:
1
–40
–30
–20
–10
0
10
V
INRMS = (VRMS − InterceptVRMS)/SlopeRMS
INENV = (VENV − InterceptVENV)/SlopeVENV
(11)
(12)
INPUT (dBm)
Figure 53. VRMS Output vs. Input Level Distribution of 50 Devices,
900 MHz Frequency
V
The law conformance error, that is, the difference between the
actual input level (VIN_IDEAL) and the measured/calculated input
level (VMEASURED), of these calculations can be calculated using
the following equation:
10000
1000
100
10
Error (dB) =
20 × log [(VMEASURED − Intercept)/(Slope × VIN_IDEAL)]
(13)
1
–40
–30
–20
–10
0
10
INPUT (dBm)
Figure 54. VENV Output vs. Input Level Distribution of 50 Devices,
900 MHz Frequency
Rev. A | Page 22 of 28
Data Sheet
ADL5511
Figure 55 is a plot of this error for VENV at 1900 MHz for a
multiple devices at +25°C, +85°C, and −40°C with calibration
performed at two points, −14 dBm and +5 dBm (notice how
the error at 25°C at the calibration points is zero). These error
plots for all temperatures are calculated using the 25°C slope
and intercept. This is consistent with calibration in a mass
production environment where calibration at temperature is
generally not practical.
ERROR VS. FREQUENCY
Figure 57 and Figure 58 show how the VRMS and VENV output
voltages and error vary with input frequency when the
ADL5511 is calibrated at a single frequency. In this example,
the ADL5511 has been calibrated at 25°C at 1.9 GHz. The
plots also show how the output voltage and error vary above
and below this frequency.
600
500
400
300
200
100
0
6
3
–40°C
+25°C
+85°C
4
2
1
2
0
0
–2
–4
–6
–1
–2
–3
V
V
V
AT –40°C
AT +25°C
AT +85°C
RMS
RMS
RMS
ERROR AT –40°C
ERROR AT +25°C
ERROR AT +85°C
0
1000
2000
3000
4000
5000
6000
–30
–25
–20
–15
–10
–5
0
5
10
15
FREQUENCY (MHz)
P
(dBm)
IN
Figure 57. VRMS Output vs. Frequency for a Fixed Input Power, PIN = 0 dBm,
Calibration at 1.9 GHz, 25°C
Figure 55. VENV Linearity Error vs. Input Level and Temperature Using a
Two-Point Calibration at 1900 MHz
400
350
300
250
200
150
100
50
8
By adding a third calibration point, the linearity of the
ADL5511 can be enhanced at lower power levels. With
a three-point calibration, calibration coefficients (slope and
intercept) are calculated for each segment (thus, there will
be two slopes and two intercepts).
6
4
2
0
Figure 56 shows the same data as Figure 55, but with a three-
point calibration (calibration points at −26 dBm, −15 dBm, and
+5 dBm. This helps to extend the usable operating range of the
ADL5511 well below −25 dBm.
–2
–4
–6
–8
V
V
V
AT –40°C
AT +25°C
AT +85°C
ENV
ENV
ENV
3
ERROR AT –40°C
ERROR AT +25°C
ERROR AT +85°C
–40°C
+25°C
+85°C
0
2
0
1000
2000
3000
4000
5000
6000
FREQUENCY (MHz)
1
0
Figure 58. VENV Output vs. Frequency for a Fixed Input Power, PIN = 0 dBm,
Calibration at 1.9 GHz, 25°C
–1
–2
–3
–30
–25
–20
–15
–10
–5
0
5
10
15
P
(dBm)
IN
Figure 56. VENV Linearity Error vs. Input Level and Temperature Using a Three-
Point Calibration at 1900 MHz
Rev. A | Page 23 of 28
ADL5511
Data Sheet
The RF input has a broadband match of 50 Ω using a single
75 Ω resistor at R5.
EVALUATION BOARD
Figure 59 shows the schematic of the ADL5511 evaluation board.
This 4-layer board is powered by a single supply in the 4.75 V
to 5.25 V range. The power supply is decoupled by 100 pF and
0.1 µF capacitors.
The VRMS output is accessible via a clip lead (a pad is also
available where an SMA connector is installed). The VENV
output is accessible via an SMA connector. For response-
time critical measurements where stray capacitance must
be minimized, R2 can be removed and a FET probe can be
attached to JP1 (JP1 must be installed).
Table 5 details the various configuration options of the evaluation
board. Figure 60 and Figure 61 show the bottom side and top
side layouts, respectively.
Figure 59. Evaluation Board Schematic
Rev. A | Page 24 of 28
Data Sheet
ADL5511
Figure 61. Layout of Evaluation Board, Top Side
Figure 60. Layout of Evaluation Board, Bottom Side
Table 5. Evaluation Board Configuration Options
Component
VPOS, GND
C13, C14
Description
Default Condition
Ground and supply vector pins.
Power supply decoupling. Nominal supply decoupling of 0.01 µF and 100 pF.
Not applicable
C13 = 100 pF (Size 0402)
C14 = 0.1 µF (Size 0402)
C17
RMS filter capacitor (FLT4). The internal rms averaging capacitor can be augmented by
placing additional capacitance in C17.
C17 = 0.1 µF (Size 0402)
R5, C1
RF input interface. The 75 Ω resistor at R5 combines with the ADL5511 internal input
impedance to give a broadband input impedance of around 50 Ω. C1 is an ac coupling
capacitor, which should be chosen according to nominal carrier frequency.
R5 = 75 Ω (Size 0402)
C1 = 100 pF (Size 0402)
R18, C9
RMS output and output filtering. The combination of C9 and the internal 100 Ω output
resistance can be used to form a low-pass filter to reduce the output noise on the VRMS
output beyond the reduction due to C17 (capacitor on FLT4). The rms output is available
on the VRMS clip-on test point. To observe VRMS using an SMA cable, an SMA connector
can be soldered on to the pad labeled VRMS1.
R18 = 0 Ω (Size 0402)
C9 = open (Size 0402)
VRMS clip-on test point =
installed
VRMS1 SMA connector =
open
R19, C8, R2,
JP1
VENV output and output filtering. The VENV output is available on the VENV SMA
connector. If post-envelope filtering is desired, R19 and C8 can be used to form a low-pass
filter at the VENV output.
R2 can be removed to isolate the JP1 jumper from the VENV SMA connector and JP1 can
be installed and used to interface to a FET probe. This helps to eliminate any excessive
trace and connector capacitance.
VENV SMA connector =
installed
R19, R2 = 0 Ω (Size 0402)
C8 = open (Size 0402)
JP1 = open
R20, C7
Envelope reference output and output filtering. The EREF output is available on the EREF
clip-on test point. The dc reference voltage at Pin EREF can be filtered by the low-pass filter
formed by the combination of R20 and C7. To observe the EREF voltage using an SMA
cable, an SMA connector can be soldered onto the pad labeled EREF1.
R20 = 0 Ω (Size 0402)
C7 = open (Size 0402)
EREF clip-on test point =
installed
EREF1 SMA connector = open
R1, SW1
Device enable. When the switch is set toward the SW1 label, the ENBL pin is connected to VPOS, R1 = 0 Ω (Size 0402)
which enables the ADL5511. In the opposite switch position, the ENBL pin is grounded which
disables the ADL5511.
SW1 = towards SW1 label
C6, C10
C2
Envelope carrier-removal filters (FLT2, FLT3). The corner frequency of the internal VENV two-pole C6, C10 = open (Size 0402)
carrier-removal filter can be reduced by placing additional capacitors in C6 and C10.
Envelope reference carrier-removal filter (FLT1). The internal filter that removes the carrier from
the envelope reference dc voltage can be augmented by placing a capacitor in C2.
C2 = 100 pF (Size 0402)
R3, R14, R15,
R16, R17
Alternate interface. The P2 edge connector provides an alternate access point to the
various ADL5511 signals.
R3, R14, R15, R16, R17 = open
(Size 0402)
Rev. A | Page 25 of 28
ADL5511
Data Sheet
OUTLINE DIMENSIONS
3.10
3.00 SQ
2.90
0.30
0.23
0.18
PIN 1
INDICATOR
PIN 1
INDICATOR
13
16
0.50
BSC
1
4
12
EXPOSED
PAD
1.75
1.60 SQ
1.45
9
8
5
0.50
0.40
0.30
0.25 MIN
TOP VIEW
BOTTOM VIEW
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.80
0.75
0.70
0.05 MAX
0.02 NOM
COPLANARITY
0.08
SECTION OF THIS DATA SHEET.
SEATING
PLANE
0.20 REF
COMPLIANT TO JEDEC STANDARDS MO-220-WEED-6.
Figure 62. 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
3 mm × 3 mm Body, Very Thin Quad
(CP-16-22)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature Range Package Description
Package Option Ordering Quantity
ADL5511ACPZ-R7 −40°C to +85°C
ADL5511-EVALZ
16-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-16-22
Evaluation Board
1500
1 Z = RoHS Compliant Part.
Rev. A | Page 26 of 28
Data Sheet
NOTES
ADL5511
Rev. A | Page 27 of 28
ADL5511
NOTES
Data Sheet
©2011–2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D09602-0-2/12(A)
Rev. A | Page 28 of 28
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