ADL5523_09 [ADI]
400 MHz to 4000 MHz Low Noise Amplifier; 400 MHz至4000 MHz的低噪声放大器
| 型号： | ADL5523_09 |
| 厂家： | 
ADI |
| 描述： | 400 MHz to 4000 MHz Low Noise Amplifier |
| 文件： | 总24页 (文件大小：591K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
400 MHz to 4000 MHz
Low Noise Amplifier
ADL5523
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Operation from 400 MHz to 4000 MHz
Noise figure of 0.8 dB at 900 MHz
Requires few external components
Integrated active bias control circuit
Integrated dc blocking capacitors
Adjustable bias for low power applications
Single-supply operation from 3 V to 5 V
Gain of 21.5 dB at 900 MHz
ACTIVE
VBIAS
RFIN
NC
1
2
3
4
8
7
6
5
VPOS
RFOUT
NC
BIAS
ADL5523
NC
NC
NC = NO CONNECT
Figure 1.
OIP3 of 34.0 dBm at 900 MHz
P1dB of 21.0 dBm at 900 MHz
Small footprint LFCSP
Pin-compatible version with 20.8 dB gain available
GENERAL DESCRIPTION
The ADL5523 is a high performance GaAs pHEMT low noise
amplifier. It provides high gain and low noise figure for single-
downconversion IF sampling receiver architectures as well as
direct-downconversion receivers.
The ADL5523 is easy to tune, requiring only a few external
components. The device can support operation from 3 V to 5 V,
and the current draw can be adjusted with the external bias
resistor for applications requiring very low power consumption.
The ADL5523 provides a high level of integration by incorporating
the active bias and the dc blocking capacitors, making it very
easy to use while not sacrificing design flexibility.
The ADL5523 comes in a compact, thermally enhanced, 3 mm ×
3 mm LFCSP and operates over the temperature range of
−40°C to +85°C.
A fully populated evaluation board is also available.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2008–2009 Analog Devices, Inc. All rights reserved.
ADL5523
TABLE OF CONTENTS
Features .............................................................................................. 1
900 MHz, VPOS = 3 V .............................................................. 11
1950 MHz, VPOS = 3 V ............................................................ 12
2600 MHz, VPOS = 3 V ............................................................ 13
3500 MHz, VPOS = 3 V ............................................................ 14
DC Characteristics..................................................................... 15
Basic Connections.......................................................................... 16
Evaluation Board ............................................................................ 17
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
AC Specifications.......................................................................... 3
DC Specifications ......................................................................... 4
De-Embedded S-Parameters, VPOS = 3 V to 5 V, RFIN =
Port 1, VPOS = Port 2, RFOUT = Port 3 .................................. 4
Soldering Information and Recommended PCB
Land Pattern................................................................................ 17
Absolute Maximum Ratings............................................................ 5
ESD Caution.................................................................................. 5
Pin Configuration And Function Descriptions............................ 6
Typical Performance Characteristics ............................................. 7
900 MHz, VPOS = 5 V................................................................. 7
1950 MHz, VPOS = 5 V .............................................................. 8
2600 MHz, VPOS = 5 V .............................................................. 9
3500 MHz, VPOS = 5 V ............................................................ 10
Tuning the ADL5523 for Optimal Noise Figure ........................ 18
Tuning S22................................................................................... 18
Tuning the LNA Input for Optimal Gain................................ 19
Tuning the LNA Input for Optimal Noise Figure.................. 19
S11 of the LNA with S22 Matched........................................... 20
Outline Dimensions....................................................................... 21
Ordering Guide .......................................................................... 21
REVISION HISTORY
9/09—Rev. 0 to Rev. A
Updated Maximum Junction Temperature Unit (Table 4) ......... 5
10/08—Revision 0: Initial Version
Rev. A | Page 2 of 24
ADL5523
SPECIFICATIONS
AC SPECIFICATIONS
TA = 25°C, R1 = 1.3 kΩ; parameters include matching circuit, matched for optimal noise, unless otherwise noted.
Table 1.
3 V
Min Typ
5 V
Max Min Typ
Parameter
Conditions
Max Unit
FREQUENCY = 900 MHz
Gain (S21)
vs. Frequency
vs. Temperature
Noise Figure1
21.0
21.5
0.3ꢀ
0.51
0.8
dB
dB
dB
dB
50 MHz
−40°C ≤ TA ≤ +85°C
0.35
0.ꢁ0
0.8
Output Third-Order Intercept (OIP3)
Output 1 dB Compression Point (P1dB)
Input Return Loss (S11)
Output Return Loss (S22)
Isolation (S12)
Δf = 1 MHz, POUT = 0 dBm per tone
28.0
1ꢀ.8
−ꢀ.5
−10.5
−24.0
34.0
21.0
−8.0
−11.0
−25.5
dBm
dBm
dB
dB
dB
FREQUENCY = 1950 MHz
Gain (S21)
vs. Frequency
vs. Temperature
Noise Figure1
1ꢁ.5
0.0ꢁ
0.50
0.9
15.8 1ꢀ.0
18.0
dB
dB
dB
dB
30 MHz
−40°C ≤ TA ≤ +85°C
0.08
0.4ꢀ
1.0
Output Third-Order Intercept (OIP3)
Output 1 dB Compression Point (P1dB)
Input Return Loss (S11)
Output Return Loss (S22)
Isolation (S12)
Δf = MHz, POUT = 0 dBm per tone
28.0
1ꢀ.ꢀ
−9.0
−1ꢀ.0
−20.5
34.0
21.2
−10.0
−20.0
−21.5
dBm
dBm
dB
dB
dB
FREQUENCY = 2ꢁ00 MHz
Gain (S21)
12.8
0.35
0.45
0.9
13.2
0.3ꢁ
0.44
0.9
dB
vs. Frequency
vs. Temperature
Noise Figure1
100 MHz
−40°C ≤ TA ≤ +85°C
dB
dB
dB
Output Third-Order Intercept (OIP3)
Output 1 dB Compression Point (P1dB)
Input Return Loss (S11)
Output Return Loss (S22)
Isolation (S12)
Δf = 1 MHz, POUT = 0 dBm per tone
30.0
1ꢀ.0
−5.0
−10.0
−21.5
35.0
21.2
−5.0
−10.0
−22.0
dBm
dBm
dB
dB
dB
FREQUENCY = 3500 MHz
Gain (S21)
vs. Frequency
vs. Temperature
Noise Figure1
10.ꢁ
0.ꢀ3
0.ꢀ8
1.0
11.0
0.ꢀ8
0.ꢀꢀ
1.0
dB
dB
dB
dB
100 MHz
−40°C ≤ TA ≤ +85°C
Output Third-Order Intercept (OIP3)
Output 1 dB Compression Point (P1dB)
Input Return Loss (S11)
Output Return Loss (S22)
Isolation (S12)
Δf = 1 MHz, POUT = 0 dBm per tone
30.0
1ꢀ.3
−11.0
−10.0
−19.0
33.5
20.1
−11.5
−10.5
−19.5
dBm
dBm
dB
dB
dB
1 Noise figure de-embedded to first matching component on input side.
Rev. A | Page 3 of 24
ADL5523
DC SPECIFICATIONS
Table 2.
3 V
Typ
5 V
Typ
Parameter
Conditions
Min
Max
Min
Max
Unit
mA
mA
Supply Current
vs. Temperature
30
4
ꢁ0
ꢀ
−40°C ≤ TA ≤ +85°C
DE-EMBEDDED S-PARAMETERS, VPOS = 3 V TO 5 V, RFIN = PORT 1, VPOS = PORT 2, RFOUT = PORT 3
Table 3.
Frequency S11
S12
(dB/Ang)
S13
(dB/Ang)
S21
(dB/Ang)
S22
(dB/Ang)
S23
(dB/Ang)
S31
(dB/Ang)
S32
(dB/Ang)
S33
(dB/Ang)
(GHz)
0.125
0.25
0.3ꢀ5
0.5
(dB/Ang)
−4.2/−12.9
−5.8/−18.8
−ꢀ.ꢁ/−20.4
−9.5/−18.4
−3ꢀ.1/−21.9 −40.ꢁ/+45.2 +19.3/+132 −ꢁ.2/+89.1 −10.ꢁ/+8.9
+15.9/−1ꢁ1
−10.5/−9.0
−13.2/−33.9 −11.0/−ꢁ.4
−8.ꢁ/−30.4
−40.0/−30.ꢁ −38.3/+40.5 +15.4/+104 −2.3/+ꢁ8.ꢁ −13.2/−33.8 +1ꢁ.ꢁ/+1ꢀ4
−42.0/−31.1 −3ꢀ.5/+38.4 +11.4/+8ꢀ.9 −1.1/+ꢁ3.5 −1ꢁ.2/−42.8 +1ꢁ.0/+158.2 −1ꢁ.2/−43.2 −11.3/+ꢁ.4
−43.9/−28.2 −3ꢁ.ꢀ/+40.2 +ꢀ.ꢁ/+ꢀꢀ.4 −0.ꢁ/+ꢁ3.3 −19.0/−45.9 +14.9/+14ꢀ
−19.0/−4ꢁ.0 −11.ꢀ/+1ꢁ.2
−21.ꢀ/−4ꢁ.ꢀ −12.1/+25.3
−24.5/−45.8 −12.5/+34.3
−2ꢀ.8/−44.5 −12.8/+43.2
−32.5/−42.4 −13.1/+52.3
−41.ꢁ/−38.ꢁ −13.4/+ꢁ0.8
−42.8/+129 −13.ꢁ/+ꢁ9.3
−33.8/+132 −13.9/+ꢀꢀ.5
−29.8/+133 −14.0/+85.3
−2ꢀ.2/+134 −14.2/+92.8
−25.5/+135 −14.4/+100
−24.2/+139 −14.5/+10ꢀ
−23.3/+143 −14.ꢁ/+114
−22.5/+148 −14.ꢀ/+121
−21.8/+154 −14.8/+12ꢀ
−21.1/+1ꢁ1 −14.8/+133
−20.5/+1ꢁ9 −14.8/+140
−19.8/+1ꢀ8 −14.8/+145
−19.1/−1ꢀ2 −14.ꢀ/+151
−18.5/−1ꢁ2 −14.ꢀ/+158
−1ꢀ.8/−152 −14.ꢀ/+1ꢁ4
−1ꢀ.3/−140 −14.5/+1ꢀ2
−1ꢁ.ꢀ/−130 −14.4/+180
−1ꢁ.2/−121 −14.0/−1ꢀ2
−15.3/−115 −13.4/−1ꢁ2
−14.1/−111 −12.4/−152
−11.9/−113 −10.8/−141
0.ꢁ25
0.ꢀ5
0.8ꢀ5
1.0
1.125
1.25
1.3ꢀ5
1.5
1.ꢁ25
1.ꢀ5
1.8ꢀ5
2.0
2.125
2.25
2.3ꢀ5
2.5
2.ꢁ25
2.ꢀ5
2.8ꢀ5
3.0
3.125
3.25
3.3ꢀ5
3.5
3.ꢁ25
3.ꢀ5
3.8ꢀ5
4.0
−11.4/−14.0 −4ꢁ.5/−2ꢀ.4 −3ꢁ.2/+42.3 +3.84/+ꢀ0.2 −0.3/+ꢁ4.8 −21.ꢀ/−4ꢁ.0 +13.8/+140
−13.2/−ꢀ.2
−15.1/+2.3
−48.8/−24.ꢁ −35.8/+44.5 +0.0/+ꢁ5.3
−51.1/−19.3 −35.4/+4ꢀ.8 −4.2/+ꢁ2.ꢁ
−0.2/+ꢁꢁ.5 −24.ꢁ/+45.ꢁ +12.8/+135
−0.1/+ꢁ8.0 −2ꢀ.8/−42.8 +11.8/+132
+0.0/+ꢁ8.5 −32.3/−40.3 +10.9/+129
−1ꢁ.8/+13.9 −5ꢁ.ꢁ/−1ꢀ.ꢁ −35.1/+51.1 −9.ꢀ/+ꢁ1.ꢀ
−18.2/+2ꢀ.3 −ꢁ4.4/−15.8 −34.ꢁ/+53.9 −19.0/+ꢀ0.9 +0.1/+ꢁꢀ.5 −41.4/−31.5 +10.1/+12ꢀ
−19.3/+42.3 −ꢁꢁ.5/−1ꢀ3 −34.5/+5ꢁ.ꢀ −22.0/−1ꢁ1 +0.2/+ꢁꢁ.0 −45.0/+118 +9.3/+12ꢁ
−19.9/+5ꢀ.4 −5ꢁ.2/+1ꢁ0 −34.1/+ꢁ0.1 −13.ꢁ/−14ꢀ +0.3/+ꢁ3.4 −34.3/+130 +8.ꢁ/+125
−20.0/+ꢀ1.1 −52.2/+153 −33.9/+ꢁ3.1 −10.2/−14ꢀ +0.4/+ꢁ1.1 −30.0/+133 +ꢀ.9/+124
−20.2/+82.ꢀ −49.0/+1ꢁ5 −33.5/+ꢁꢁ.2 −8.5/−148
−20.1/+92.5 −4ꢁ.ꢀ/+1ꢁ0 −33.3/+ꢀ0.3 −ꢀ.4/−149
−19.9/+101 −45.3/+1ꢁꢀ −32.9/+ꢀ2.5 −ꢁ.8/−148
−19.ꢀ/+10ꢀ −44.ꢁ/+1ꢀ3 −32.ꢁ/+ꢀ5.1 −ꢁ.4/−14ꢀ
−19.ꢁ/+113 −43.5/+1ꢀꢁ −32.1/+ꢀ8.2 −ꢁ.1/−144
−19.3/+11ꢁ −42.3/−180 −31.ꢀ/+80.ꢁ −ꢁ.0/−140
−19.0/+11ꢀ −41.8/−1ꢀ2 −31.5/+83.1 −5.9/−135
−18.ꢁ/+11ꢀ −41.2/−1ꢁꢁ −31.1/+84.ꢀ −5.ꢀ/−129
−18.1/+118 −40.0/−15ꢁ −30.8/+8ꢁ.ꢀ −5.ꢁ/−122
−1ꢀ.5/+11ꢀ −39.3/−14ꢁ −30.4/+89.0 −5.4/−115
−1ꢁ.8/+118 −38.ꢁ/−13ꢁ −30.3/+90.4 −5.1/−10ꢁ
−15.9/+11ꢀ −3ꢀ.ꢁ/−12ꢁ −30.0/+91.ꢀ −5.0/−9ꢀ.ꢀ
−14.9/+118 −3ꢀ.1/−115 −29.8/+92.0 −4.9/−88.5
−13.9/+120 −3ꢁ.5/−105 −29.4/+92.3 −4.9/−ꢀ9.2
−13.0/+121 −35.8/−95.4 −29.3/+92.2 −4.ꢀ/−ꢀ1.8
−12.0/+124 −35.1/−88.ꢀ −29.3/+92.3 −4.4/−ꢁꢁ.4
−11.3/+12ꢀ −33.ꢀ/−85.0 −29.ꢁ/+91.2 −3.ꢁ/−ꢁ3.ꢁ
−10.ꢀ/+131 −31.4/−8ꢁ.9 −30.5/+89.4 −1.9/−ꢁꢀ.1
−10.4/+138 −28.ꢁ/−99.9 −32.9/+95.9 +0.ꢀ/−83.0
+0.5/+ꢁ1.1 −2ꢀ.5/+134 +ꢀ.3/+125
+0.ꢁ/+ꢁ2.8 −25.9/+13ꢀ +ꢁ.8/+124
+0.ꢁ/+ꢁꢀ.4 −24.5/+139 +ꢁ.3/+124
+0.ꢁ/+ꢀ3.ꢁ −23.5/+142 +5.8/+125
+0.ꢀ/+82.ꢀ −22.ꢀ/+148 +5.4/+125
+0.ꢀ/+93.9 −22.0/+154 +5.0/+125
+0.ꢀ/+10ꢀ −21.3/+1ꢁ1 +4.ꢀ/+125
+0.ꢀ/+122 −20.ꢁ/+1ꢁ9 +4.3/+125
+0.ꢀ/+139 −20.0/+1ꢀ8 +4.0/+125
+0.ꢀ/+158 −19.3/−1ꢀ3 +3.ꢁ/+125
+0.8/+1ꢀ8 −18.ꢁ/+1ꢁ2 +3.3/+125
+0.8/−1ꢁ1 −18.0/−152 +2.9/+125
+0.ꢀ/−138 −1ꢀ.5/−141 +2.ꢁ/+124
+0.5/−11ꢁ −1ꢁ.8/−129 +2.2/+123
+0.1/−95.2 −1ꢁ.3/−121 +1.ꢀ/+122
−0.3/−ꢀꢁ.ꢀ −15.4/−115 +1.2/+120
−0.8/−ꢁ0.ꢁ −14.2/−111 +0.4/+118
−1.ꢀ/−4ꢀ.8 −12.1/−114 −0.9/+11ꢁ
−4.9/−35.8 −8.9/−129
−ꢁ.3/+42.3 −ꢀ.8/−1ꢁ4
−3.9/+124
−1.4/+155
−8.8/−129
−ꢀ.ꢀ/−1ꢁ5
−ꢀ.9/−13ꢀ
−5.8/−150
−9.3/+152
−2ꢀ.3/−13ꢁ −30.9/+132 +1.3/−120
Rev. A | Page 4 of 24
ADL5523
ABSOLUTE MAXIMUM RATINGS
Table 4.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Parameter
Rating
Supply Voltage, VPOS
RF Input Level
RF Input Level (with 8 Ω Series Resistor on VPOS)
Internal Power Dissipation
θJA (Junction to Air)
5.5 V
ꢀ dBm
20 dBm
500 mW
50°C/W
Maximum Junction Temperature
Operating Temperature Range
Storage Temperature Range
150°C
−40°C to +85°C
−ꢁ5°C to +150°C
ESD CAUTION
Rev. A | Page 5 of 24
ADL5523
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
VBIAS
RFIN
NC
1
2
3
4
8
7
6
5
VPOS
RFOUT
NC
ADL5523
TOP VIEW
(Not to Scale)
NC
NC
EXPOSED PAD
NOTES
1. NC = NO CONNECT.
2. CONNECT THE EXPOSED PAD TO A LOW
IMPEDANCE GROUND PLANE.
Figure 2. Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
Mnemonic
VBIAS
RFIN
Description
1
2
Internal DC Bias. This pin should be connected to VPOS through the R1 resistor.
RF Input. This is the input to the LNA.
3, 4, 5, ꢁ
ꢀ
8
NC
RFOUT
VPOS
No Connection. No internal connection.
RF Output.
Supply Voltage. DC bias needs to be bypassed to ground using a low inductance capacitor. This pin is
also used for output matching. See the Basic Connections section.
9 (EPAD) Exposed Pad (EPAD)
GND. Connect the exposed pad to a low impedance ground plane.
Rev. A | Page ꢁ of 24
ADL5523
TYPICAL PERFORMANCE CHARACTERISTICS
900 MHz, VPOS = 5 V
Matched for optimal noise figure, external matching circuit included.
25
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
S21
20
15
10
5
0
S11
–5
–10
–15
–20
–25
–30
–35
S22
S12
600 650 700 750 800 850 900 950 1000 1050 1100 1150 1200
800 820 840 860 880 900 920 940 960 980 1000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 3. Typical S-Parameters, Log Magnitude
Figure 6. Noise Figure vs. Frequency at 25°C, Multiple Devices
24
22
20
18
16
14
12
10
8
60
23.5
23.0
22.5
22.0
21.5
21.0
20.5
20.0
19.5
19.0
36
GAIN
+85°C
+25°C
55
34
32
30
28
26
24
22
20
18
50
45
–40°C
OIP3
40
–40°C
+25°C
OIP3
35
30
+85°C
25
P1dB
GAIN
20
15
10
P1dB
–40°C
6
4
+25°C
2
5
NOISE FIGURE
+85°C
0
0
850 860 870 880 890 900 910 920 930 940 950
850 860 870 880 890 900 910 920 930 940 950
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 4. Noise Figure, Gain, OIP3, and P1dB vs. Frequency
Figure 7. Gain, OIP3, and P1dB vs. Temperature
2.0
1.8
1.6
1.4
40
38
+25°C
36
–40°C
34
1.2
1.0
0.8
0.6
0.4
0.2
0
32
30
+85°C
+25°C
–40°C
+85°C
28
26
24
22
20
800 820 840 860 880 900 920 940 960 980 1000
–4 –2
0
2
4
6
8
10 12 14 16 18 20 22
FREQUENCY (MHz)
P
PER TONE (dBm)
OUT
Figure 5. Noise Figure vs. Temperature
Figure 8. OIP3 vs. Output Power (POUT) and Temperature
Rev. A | Page ꢀ of 24
ADL5523
1950 MHZ, VPOS = 5 V
Matched for optimal noise figure, external matching circuit included.
20
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
S21
15
10
5
0
S11
–5
–10
–15
–20
–25
–30
–35
–40
S12
S22
1800
1850
1900
1950
2000
2050
2100
2150
2200
1800 1820 1840 1860 1880 1900 1920 1940 1960 1980 2000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 9. Typical S-Parameters, Log Magnitude
Figure 12. Noise Figure vs. Frequency at 25°C, Multiple Devices
18
16
14
12
10
8
45
40
35
30
25
20
15
10
5
20.5
40
38
36
34
32
30
28
26
24
22
20
18
16
OIP3
–40°C
20.0
19.5
19.0
18.5
18.0
17.5
17.0
16.5
16.0
15.5
15.0
14.5
GAIN
OIP3
+25°C
+85°C
P1dB
–40°C
+25°C
+85°C
6
–40°C
P1dB
GAIN
4
+25°C
2
NOISE FIGURE
+85°C
1970
0
1920
0
1980
1930
1940
1950
1960
1970
1920
1930
1940
1950
1960
1980
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 10. Noise Figure, Gain, OIP3, and P1dB vs. Frequency
Figure 13. Gain, OIP3, and P1dB vs. Temperature
2.0
1.8
1.6
42
40
38
36
34
32
30
28
26
24
22
20
18
–40°C
+25°C
1.4
+85°C
1.2
+25°C
1.0
+85°C
0.8
–40°C
0.6
0.4
0.2
0
1800 1820 1840 1860 1880 1900 1920 1940 1960 1980 2000
–8 –6 –4 –2
0
2
4
6
8
10 12 14 16 18 20 22
FREQUENCY (MHz)
P
OUT
PER TONE (dBm)
Figure 11. Noise Figure vs. Temperature
Figure 14. OIP3 vs. Output Power (POUT) and Temperature
Rev. A | Page 8 of 24
ADL5523
2600 MHz, VPOS = 5 V
Matched for optimal noise figure, external matching circuit included.
20
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
S21
15
10
5
0
S11
S22
–5
–10
–15
–20
–25
–30
S12
2100
2200
2300
2400
2500
2600
2700
2800
2900
2500 2520 2540 2560 2580 2600 2620 2640 2660 2680 2700
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 15. Typical S-Parameters, Log Magnitude
Figure 18. Noise Figure vs. Frequency at 25°C, Multiple Devices
16
14
12
10
8
50
45
40
35
30
25
20
15
10
16.5
40
38
36
34
32
30
28
26
24
22
20
18
–40°C
16.0
15.5
15.0
14.5
14.0
13.5
13.0
12.5
12.0
11.5
11.0
GAIN
OIP3
+25°C
+85°C
OIP3
–40°C
+25°C
+85°C
6
P1dB
GAIN
4
P1dB
–40°C
2
+25°C
NOISE FIGURE
+85°C
0
2500 2520 2540 2560 2580 2600 2620 2640 2660 2680 2700
2500 2520 2540 2560 2580 2600 2620 2640 2660 2680 2700
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 16. Noise Figure, Gain, OIP3, and P1dB vs. Frequency
Figure 19. Gain, OIP3, and P1dB vs. Temperature
2.0
1.8
1.6
42
40
38
36
34
32
30
28
26
24
22
20
18
–40°C
+25°C
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
+85°C
+85°C
+25°C
–40°C
2500 2520 2540 2560 2580 2600 2620 2640 2660 2680 2700
–6 –4 –2
0
2
4
6
8
10 12 14 16 18 20 22
FREQUENCY (MHz)
P
PER TONE (dBm)
OUT
Figure 17. Noise Figure vs. Temperature
Figure 20. OIP3 vs. Output Power (POUT) and Temperature
Rev. A | Page 9 of 24
ADL5523
3500 MHz, VPOS = 5 V
Matched for optimal noise figure, external matching circuit included.
15
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
S21
10
5
0
S11
–5
–10
S22
–15
–20
–25
S12
2800 2900 3000 3100 3200 3300 3400 3500 3600 3700
3400 3420 3440 3460 3480 3500 3520 3540 3560 3580 3600
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 21. Typical S-Parameters, Log Magnitude
Figure 24. Noise Figure vs. Frequency at 25°C, Multiple Devices
14
12
10
8
45
19
41
39
37
35
33
31
29
27
25
23
21
19
17
15
–40°C
+25°C
18
17
16
15
14
13
12
11
10
9
40
35
30
25
20
15
10
GAIN
OIP3
+85°C
OIP3
–40°C
+25°C
+85°C
6
P1dB
P1dB
4
GAIN
–40°C
8
2
+25°C
+85°C
NOISE FIGURE
7
0
6
3400 3420 3440 3460 3480 3500 3520 3540 3560 3580 3600
3400 3420 3440 3460 3480 3500 3520 3540 3560 3580 3600
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 22. Noise Figure, Gain, OIP3, and P1dB vs. Frequency
Figure 25. Gain, OIP3, and P1dB vs. Temperature
2.0
1.8
42
–40°C
40
38
1.6
+85°C
+25°C
36
1.4
1.2
34
32
+25°C
+85°C
1.0
30
28
26
24
22
20
0.8
–40°C
0.6
0.4
0.2
0
3400 3420 3440 3460 3480 3500 3520 3540 3560 3580 3600
–14 –12 –10 –8 –6 –4 –2
0
2
4
6
8
10 12 14 16
FREQUENCY (MHz)
P
OUT
PER TONE (dBm)
Figure 23. Noise Figure vs. Temperature
Figure 26. OIP3 vs. Output Power (POUT) and Temperature
Rev. A | Page 10 of 24
ADL5523
900 MHz, VPOS = 3 V
Matched for optimal noise figure, external matching circuit included.
25
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
S21
20
15
10
5
0
–5
S11
S22
–10
–15
–20
–25
–30
–35
S12
600 650 700 750 800 850 900 950 1000 1050 1100 1150 1200
800 820 840 860 880 900 920 940 960 980 1000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 27. Typical S-Parameters, Log Magnitude
Figure 30. Noise Figure vs. Frequency at 25°C, Multiple Devices
22
20
18
16
14
12
10
8
34
23.0
32
30
28
26
24
22
20
18
16
14
–40°C
+25°C
GAIN
OIP3
32
30
28
26
24
22
20
18
16
14
12
22.5
22.0
21.5
21.0
20.5
20.0
19.5
19.0
18.5
–40°C
+85°C
+85°C
OIP3
+25°C
P1dB
P1dB
–40°C
+25°C
GAIN
6
4
2
+85°C
NOISE FIGURE
0
850 860 870 880 890 900 910 920 930 940 950
850 860 870 880 890 900 910 920 930 940 950
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 28. Noise Figure, Gain, OIP3, and P1dB vs. Frequency
Figure 31. Gain, OIP3, and P1dB vs. Temperature
2.0
1.8
1.6
1.4
32
–40°C
31
30
+25°C
29
28
27
1.2
+85°C
26
+85°C
1.0
25
24
23
22
21
20
19
18
+25°C
0.8
–40°C
0.6
0.4
0.2
0
800 820 840 860 880 900 920 940 960 980 1000
–4 –2
0
2
4
6
8
10 12 14 16 18 20
FREQUENCY (MHz)
P
PER TONE (dBm)
OUT
Figure 29. Noise Figure vs. Temperature
Figure 32. OIP3 vs. Output Power (POUT) and Temperature
Rev. A | Page 11 of 24
ADL5523
1950 MHz, VPOS = 3 V
Matched for optimal noise figure, external matching circuit included.
20
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
S21
15
10
5
0
S11
–5
–10
–15
S12
–20
–25
–30
S22
–35
1800
1850
1900
1950
2000
2050
2100
2150
2200
1800 1820 1840 1860 1880 1900 1920 1940 1960 1980 2000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 33. Typical S-Parameters, Log Magnitude
Figure 36. Noise Figure vs. Frequency at 25°C, Multiple Devices
18
16
14
12
10
8
32
30
28
26
24
22
20
18
16
14
18.5
30
28
26
24
22
20
18
16
14
GAIN
OIP3
–40°C
18.0
17.5
17.0
16.5
16.0
15.5
15.0
14.5
+25°C
+85°C
OIP3
–40°C
+25°C
+85°C
P1dB
6
GAIN
–40°C
+25°C
P1dB
4
2
+85°C
NOISE FIGURE
0
1920
1930
1940
1950
1960
1970
1980
1920
1930
1940
1950
1960
1970
1980
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 34. Noise Figure, Gain, OIP3, and P1dB vs. Frequency
Figure 37. Gain, OIP3, and P1dB vs. Temperature
2.0
1.8
1.6
30
29
28
27
26
25
24
23
22
21
20
19
18
–40°C
+25°C
1.4
+85°C
+85°C
1.2
+25°C
1.0
0.8
–40°C
0.6
0.4
0.2
0
1800 1820 1840 1860 1880 1900 1920 1940 1960 1980 2000
–8 –6 –4 –2
0
2
4
6
8
10 12 14 16 18
FREQUENCY (MHz)
P
OUT
PER TONE (dBm)
Figure 35. Noise Figure vs. Temperature
Figure 38. OIP3 vs. Output Power (POUT) and Temperature
Rev. A | Page 12 of 24
ADL5523
2600 MHz, VPOS = 3 V
Matched for optimal noise figure, external matching circuit included.
20
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
S21
15
10
5
0
S11
–5
S22
–10
–15
S12
–20
–25
–30
2100
2200
2300
2400
2500
2600
2700
2800
2900
2500 2520 2540 2560 2580 2600 2620 2640 2660 2680 2700
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 39. Typical S-Parameters, Log Magnitude
Figure 42. Noise Figure vs. Frequency at 25°C, Multiple Devices
18
16
14
12
10
8
32
30
28
26
24
22
20
18
16
14
15.5
33
31
29
27
25
23
21
19
17
15
–40°C
OIP3
15.0
14.5
14.0
13.5
13.0
12.5
12.0
11.5
11.0
+25°C
GAIN
OIP3
+85°C
–40°C
+25°C
+85°C
6
GAIN
4
P1dB
P1dB
+25°C
–40°C
+85°C
2
NOISE FIGURE
0
2500 2520 2540 2560 2580 2600 2620 2640 2660 2680 2700
2500 2520 2540 2560 2580 2600 2620 2640 2660 2680 2700
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 40. Noise Figure, Gain, OIP3, and P1dB vs. Frequency
Figure 43. Gain, OIP3, and P1dB vs. Temperature
2.0
1.8
1.6
33
–40°C
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
+25°C
+85°C
1.4
+85°C
1.2
+25°C
1.0
0.8
–40°C
0.6
0.4
0.2
0
2500 2520 2540 2560 2580 2600 2620 2640 2660 2680 2700
–6 –4 –2
0
2
4
6
8
10 12 14 16 18
FREQUENCY (MHz)
P
OUT
PER TONE (dBm)
Figure 41. Noise Figure vs. Temperature
Figure 44. OIP3 vs. Output Power (POUT) and Temperature
Rev. A | Page 13 of 24
ADL5523
3500 MHz, VPOS = 3 V
Matched for optimal noise figure, external matching circuit included.
15
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
S21
10
5
0
S11
–5
–10
–15
S22
S12
–20
–25
2800 2900 3000 3100 3200 3300 3400 3500 3600 3700
3400 3420 3440 3460 3480 3500 3520 3540 3560 3580 3600
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 45. Typical S-Parameters, Log Magnitude
Figure 48. Noise Figure vs. Frequency at 25°C, Multiple Devices
18
16
14
12
10
8
32
30
28
26
24
22
20
18
16
14
16
33
31
29
27
25
23
21
19
17
15
–40°C
+25°C
OIP3
GAIN
15
14
13
12
11
10
9
+85°C
OIP3
–40°C
+25°C
+85°C
6
GAIN
4
P1dB
P1dB
–40°C
+25°C
2
8
NOISE FIGURE
+85°C
0
7
3400 3420 3440 3460 3480 3500 3520 3540 3560 3580 3600
3400 3420 3440 3460 3480 3500 3520 3540 3560 3580 3600
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 46. Noise Figure, Gain, OIP3, and P1dB vs. Frequency
Figure 49. Gain, OIP3, and P1dB vs. Temperature
2.0
1.8
33
–40°C
32
31
+25°C
1.6
30
+85°C
1.4
29
+85°C
28
1.2
27
26
25
24
23
22
21
20
+25°C
1.0
0.8
–40°C
0.6
0.4
0.2
0
3400 3420 3440 3460 3480 3500 3520 3540 3560 3580 3600
–14 –12 –10 –8 –6 –4 –2
0
2
4
6
8
10 12 14 16
FREQUENCY (MHz)
P
OUT
PER TONE (dBm)
Figure 47. Noise Figure vs. Temperature
Figure 50. OIP3 vs. Output Power (POUT) and Temperature
Rev. A | Page 14 of 24
ADL5523
DC CHARACTERISTICS
75
70
65
60
55
50
45
40
35
30
25
20
VPOS = 5V
VPOS = 3V
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90
TEMPERATURE (°C)
Figure 51. Supply Current vs. Temperature, 3 V and 5 V
Rev. A | Page 15 of 24
ADL5523
BASIC CONNECTIONS
VPOS
GND
The basic connections for operating the ADL5523 are shown in
Figure 52. Capacitor C5 provides the power supply decoupling.
Inductor L1 (Coilcraft 0403HQ or 0402HP series) and Capacitor C1
(Murata High-Q GJM series or equivalent) provide the input
impedance matching, and the output impedance matching is
provided by either L2 or C3. Resistor R1 is used to set the supply
current, and the value of R1 is indirectly proportional to the
supply current (that is, increasing the value of R1 reduces the
supply current). The recommended external components for
selected frequencies are listed in Table 7.
W1
R2
L2
C5
100nF
TR1
TR2
C3
R1
ADL5523
1 VBIAS
VPOS
RFOUT
NC
8
7
6
5
RFIN
RFOUT
L1
C1
For 5 V applications where the input power exceeds the input
compression point of approximately 7 dBm, a series resistor
(R2) of at least 8 Ω, with a high power rating (0.2 W minimum),
should be inserted on the VPOS line to protect the device from
the input power overdrive. In this case, reduce Resistor R1 from
1.3 kΩ to 600 Ω to keep the supply current at around 60 mA.
With R2 = 8.2 Ω (Susumu RP1608S-8R2-F) and R1 = 600 Ω, the
gain and noise figure for the ADL5523 are mostly unchanged.
Table 6 lists OIP3 and P1dB at selected frequencies. For 3 V
power supply applications, a series resistor is not necessary for
the expected input overdrive powers up to 20 dBm.
2 RFIN
3 NC
NC
4 NC
Z1
Figure 52. ADL5523 Basic Connections
Table 6. ADL5523 Performance at VPOS = 5 V, 25°C with
R2 = 8.2 Ω and R1 = 600 Ω
Frequency
(MHz)
Noise
Gain P1dB
OIP3 (dBm)
Figure (dB)
(dB)
21.5
1ꢀ.0
13.5
11.3
(dBm) (POUT = 0 dBm)
900
0.8
1.0
0.9
1.0
20.3
20.ꢀ
20.5
20.1
32.5
34.0
35.0
35.0
1950
2ꢁ00
3500
Rev. A | Page 1ꢁ of 24
ADL5523
EVALUATION BOARD
Figure 53 shows the schematic of the ADL5523 evaluation board.
The board is powered by a single supply, and dc bias can be
applied to the board through clip-on leads at VPOS and GND
or through a 2-pin connector, W1.
The evaluation board comes optimized at 1950 MHz from the
factory, but it can be easily modified to work at any frequency
between 400 MHz and 4 GHz. Table 7 lists the recommended
components at various frequencies.
VPOS
GND
W1
R2
Figure 55. Evaluation Board Layout (Bottom View)
C5
100nF
L2
SOLDERING INFORMATION AND RECOMMENDED
PCB LAND PATTERN
C4
DNP
TR1
TR2
Figure 56 shows the recommended land pattern for ADL5523.
To minimize thermal impedance, the exposed pad on the
package underside is soldered down to a ground plane. If
multiple ground layers exist, they are stitched together using
vias (a minimum of five vias is recommended). Pin 3 to Pin 6
can be left unconnected or can be connected to ground. For
more information on land pattern design and layout, refer to
the AN-772 Application Note, A Design and Manufacturing
Guide for the Lead Frame Chip Scale Package (LFCSP).
C3
R1
ADL5523
1 VBIAS
VPOS
RFOUT
NC
8
7
6
5
RFIN
RFOUT
L1
C1
2 RFIN
3 NC
C2
0Ω
NC
4 NC
2.03mm
Z1
8
1
Figure 53. Evaluation Board Schematic
4
5
1.53mm
0.71mm
Figure 56. Recommended Land Pattern
Figure 54. Evaluation Board Layout (Top View)
Table 7. Recommended Components and Positions of Matching Components for Basic Connections Tuned for Optimal Noise
L22
C11
C2
C3
C4
C5
L12
R13
R24
Frequency (Size
(Size
(Size
(Size
(Size
(Size
0403)
Size
0403)
(Size
(Size
TR1
TR2
(mm)
C1
C3
(MHz)
0402)
Open
2.4 pF
2.ꢀ pF
1.ꢁ pF
1.ꢁ pF
0402) 0402) 0402) 0402)
0603) 0603) (mm)
Position Position
500
900
0 Ω
0 Ω
0 Ω
0 Ω
0 Ω
Open
Open
Open
Open
100 nF 9 nH
100 nF 8.2 nH
100 nF 3.4 nH
100 nF 1.0 nH
100 nF 1.0 nH
100 nF 1.0 nH
12 nH
3.4 nH 1.3 kΩ 0 Ω
0 Ω
0 Ω
0 Ω
0 Ω
1.3 kΩ 0 Ω
0
0
0
0
0
C1
C1
N/A
N/A
ꢁ
4
2
1300
1950
2140
2ꢁ00
3500
1.0 nF Open
1.0 nF Open
1.0 nF Open
1.0 nF Open
1.0 nF Open
1.3 kΩ 0 Ω
1.3 kΩ 0 Ω
1.3 kΩ 0 Ω
1.3 kΩ 0 Ω
1.3 kΩ 0 Ω
8.0 × 0.ꢁ C1
2.5 × 0.ꢁ 5.5 × 0.ꢁ C1
5.0 × 0.ꢁ 3.0 × 0.ꢁ C1
8.0 × 0.ꢁ
0.ꢀ5 pF 0 Ω
0.5 pF 0 Ω
0
C1
C1
C3
1
100 nF 2.4 pF5 0 Ω
ꢀ.0 × 0.ꢁ 1 × 0.ꢁ
1 The Murata GJM High-Q series capacitor is recommended for C1.
2 The Coilcraft High Q 0403HQ or 0402HP inductors are recommended for L1 and L2.
3 If R2 = 8 Ω, reduce R1 to ꢁ00 Ω.
4 If R2 = 8 Ω, use a high power resistor (0.2 W rating minimum).
5 Note that at 3500 MHz, a capacitor, not an inductor, is used at L1.
Rev. A | Page 1ꢀ of 24
ADL5523
TUNING THE ADL5523 FOR OPTIMAL NOISE FIGURE
The ADL5523 is a monolithic low noise amplifier (LNA) in a
3 mm × 3 mm LFCSP. The evaluation board, as shipped from
the factory, gives a noise figure of 0.9 dB over a bandwidth of
several hundred megahertz. The specific frequency where optimal
noise is reached depends on the tuning.
The slider is seen in the LNA PCB layout in Figure 57 as the
area near the red arrows to the right of the bias line. With a 0 Ω
resistor in place of L2, moving a 1 nF capacitor from the top to
the bottom effectively tunes S22 from 1400 MHz to 3500 MHz.
Table 8 shows the component values and placement required for
S22 tuning from 800 MHz to 3200 MHz. For lower frequencies,
higher values of L2 can be used to tune S22, and for frequencies
from 3.2 GHz to 4.0 GHz, smaller values of capacitors can be
used on the slider.
The bandwidth of the ADL5523 is 400 MHz to 4 GHz, although
noise figure degrades above 2.5 GHz as the gain begins to roll off.
This section is based on Analog Devices, Inc., lab measurements.
Although there are plots in which the Agilent Advanced Design
System (ADS) environment is used, the data in these plots come
entirely from Analog Devices lab measurements.
Table 8. Capacitor and Inductor Tuning and Placement for
LNA S22 Tuning
Frequency (MHz)
L2 (nH)
C3 (nF)
Open
1 nF
1 nF
1 nF
C3 Placement
TUNING S22
800
3.4
0 Ω
0 Ω
0 Ω
0 Ω
0 Ω
N/A
ꢁ
4
3
2
Tuning of the LNA begins with S22 (output tuning). Tuning of
the LNA output is done by placing reactive components on the
bias line, referred to in the schematic in Figure 53 as VPOS.
1400
2000
2400
2800
3200
On the LNA evaluation board, S22 tuning is achieved by either
the use of an inductor (L2) on the bias line or a shunt capacitor
(C3) on the bias line to ground. Typically, either L2 is required
or C3 but not both.
1 nF
1 nF
1
The evaluation board uses a slider on the bias line to make tuning
for S22 as easy as possible. The slider is an area of ground etch
adjacent to the bias line that is clear of solder mask. The bias
line in this area is also free of solder mask. This allows a capacitor
(C3) to be placed anywhere on the bias line to ground, which
provides easy and accurate tuning for S22.
Note that the PCB layout shows two capacitors, C3 and C4.
Typically, only one of these capacitors is needed for good
S22 tuning.
Figure 57. PCB Layout for LNA Evaluation Board (Note Slider on Bias Line
with Capacitor Placement for S22 Tuning Noted by Arrows)
Rev. A | Page 18 of 24
ADL5523
TUNING THE LNA INPUT FOR OPTIMAL GAIN
TUNING THE LNA INPUT FOR OPTIMAL NOISE
FIGURE
LNAs are generally tuned for either gain or noise optimization,
or some trade-off between the two. One figure of merit of an LNA
is how much trade-off must be made for one of these parameters to
optimize the other. With the ADL5523, an S11 of 6 dB to 8 dB
at the input to the matching network can still be achieved
typically when optimizing for noise.
The point in the Smith Chart at which matching for optimal
noise occurs is typically referred to as gamma optimal or ΓOPT
Typically, it is significantly different from the gain matching
point; finding ΓOPT is not as obvious as the gain match. ΓOPT is a
function of the semiconductor structure and characteristics of
the LNA. The fabrication facility that produces the LNA typically
has this information. ΓOPT can also be determined by doing
source pull testing in the lab.
.
For optimal gain matching, the goal is to use a matching network
that converts the input impedance of the LNA to the characteristic
impedance of the system, typically 50 Ω. Correct tuning for gain
matching results in a conjugate match. That is, the impedance of
the matching network at the LNA input, looking back toward
the generator, is always the complex conjugate of the LNA input
impedance when matched for gain.
Noise matching for the ADL5523 is actually very easy because
the area of the Smith Chart where the noise figure is optimal or
near optimal is not confined to a narrow area around ΓOPT. This
is very advantageous because it means that component variations
play a smaller part in the board-to-board variation of noise figure.
Once S11*, the complex conjugate of S11, is known, a matching
circuit must be found that transforms the 50 Ω system impedance
into the conjugate S11 impedance. To do this, the designer starts at
the origin of the Smith Chart circle and finds components that
move the 50 Ω match to S11*.
The matching area for optimal noise for the ADL5523 is shown
in Figure 60. Note that textbooks usually define noise circles as
a conjugate match. However, for the purpose of this data sheet,
the circle is a direct match. To find the correct matching circuit,
the designer must start with the S11 of the LNA and select
components that move the S11 to within this circle.
The related impedances for gain matching are shown in Figure 58.
A Smith Chart representation of the conjugate match is shown
in Figure 59.
An important aspect of the overall ADL5523 ease of tuning is
that as long as S22 is matched for a particular frequency, the
noise matching area remains very consistent in its placement for
that frequency. If S22 is matched, take the measured S11 and
move it into the red circle shown in Figure 60 for optimal noise
matching.
50Ω
S11
MATCHING
NETWORK
LNA
50Ω
S11*
Figure 58. Matching LNA Input for Gain
1
0.5
S11*
0.2
5
10
10
0.2
0.5
1
5
10
S11
0.2
5
0.5
Figure 59. Smith Chart Representation of Conjugate Match
1
Figure 60. Area of Optimal Noise Matching for ADL5523
Rev. A | Page 19 of 24
ADL5523
S11 OF THE LNA WITH S22 MATCHED
To determine the correct matching circuit for optimal noise,
look at the results of S11 for the various frequencies at which
S22 was tuned earlier in the Tuning S22 section. Once S11 is
determined for a particular frequency, find the matching
components that provided that match. Figure 62 and Figure 63
show S11 for the various frequencies. Again, these measurements
are all based on S22 being matched at that particular frequency.
Note that, for the examples shown in Figure 62 and Figure 63, S11
is either in the lower left quadrant of the Smith Chart or slightly
into the upper left. To move the impedance in the given noise
circle, a series L component at the LNA input is required. The L
values in the examples differ but a correct L value moves the match
along the constant R circle up into the upper left quadrant of the
Smith Chart.
M1
FREQUENCY 400MHz
S11 = 0.877/–44.639
IMPEDANCE = Z0 × (0.443 – j2.365)
M2
FREQUENCY 2GHz
S11 = 0.615/–170.569
IMPEDANCE = Z0 × (0.240 – j0.078)
M2
M1
FREQUENCY (400MHz TO 4GHz)
A shunt capacitor can then be added to move the match along a
constant admittance line, down and to the right, directly into
the center of the noise circle given in Figure 60.
Figure 62. S11 of ADL5523 with S22 Matched at 2 GHz
The solution for the structure of the match for the examples in
Figure 62 and Figure 63 is a series L to the input of the LNA
and a shunt capacitor at the generator end of this inductor. The
recommended components for matching at various frequencies
are shown in Table 7.
M1
FREQUENCY 400MHz
S11 = 0.864/–40.186
IMPEDANCE = Z0 × (0.594 – j2.615)
M2
FREQUENCY 3.2GHz
S11 = 0.595/163.164
M2
IMPEDANCE = Z0 × (0.259 + j0.138)
An example of the effect of the series L, shunt C match, based
on the 800 MHz example, is given in Figure 61. This example
uses the output from the Agilent ADS Smith Chart tool.
M1
FREQUENCY (400MHz TO 4GHz)
Figure 63. S11 of ADL5523 with S22 Matched at 3.2 GHz
Figure 61. Example of Series L, Shunt C Matching Network for ΓOPT
Rev. A | Page 20 of 24
ADL5523
OUTLINE DIMENSIONS
3.25
3.00 SQ
2.75
0.60 MAX
5
0.50
BSC
0.60 MAX
8
2.95
2.75 SQ
2.55
1.60
1.45
1.30
EXPOSED
PAD
TOP
VIEW
PIN 1
INDICATOR
(BOTTOM VIEW)
4
1
PIN 1
INDICATOR
0.50
0.40
0.30
1.89
1.74
1.59
12° MAX
0.70 MAX
0.65TYP
0.90 MAX
0.85 NOM
0.05 MAX
0.01 NOM
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.30
0.23
0.18
SEATING
PLANE
0.20 REF
SECTION OF THIS DATA SHEET.
Figure 64. 8-Lead Lead Frame Chip Scale Package [LFCSP_VD]
3 mm × 3 mm Body, Very Thin, Dual Lead
(CP-8-2)
Dimensions shown in millimeters
ORDERING GUIDE
Model
ADL5523ACPZ-Rꢀ1
ADL5523-EVALZ1
Temperature Range
Package Description
Package Option
Branding
Q1J
−40°C to +85°C
8-Lead LFCSP_VD, ꢀ”Tape and Reel
Evaluation Board
CP-8-2
1 Z = RoHS Compliant Part.
Rev. A | Page 21 of 24
ADL5523
NOTES
Rev. A | Page 22 of 24
ADL5523
NOTES
Rev. A | Page 23 of 24
ADL5523
NOTES
©2008–2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06829-0-9/09(A)
Rev. A | Page 24 of 24
相关型号：
ADL5530ACPZ-R2
DC to 1000 MHz IF Gain Block; Package: LFCSP (2x3x.85mm); No of Pins: 8; Temperature Range: Industrial
ADI
ADL5531ACPZ-R7
20MHz - 500MHz RF/MICROWAVE NARROW BAND MEDIUM POWER AMPLIFIER, 3 X 3 MM, LEAD FREE, LFCSP, 8 PIN
ROCHESTER
©2020 ICPDF网 联系我们和版权申明