ADL6012ACPZN-R7 [ADI]
2 GHz to 67 GHz, 500 MHz Bandwidth Envelope Detector;
| 型号： | ADL6012ACPZN-R7 |
| 厂家： | 
ADI |
| 描述： | 2 GHz to 67 GHz, 500 MHz Bandwidth Envelope Detector |
| 文件： | 总24页 (文件大小：703K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
2 GHz to 67 GHz,
500 MHz Bandwidth Envelope Detector
Data Sheet
ADL6012
FEATURES
FUNCTIONAL BLOCK DIAGRAM
ENBL
1
Over 500 MHz wide envelope bandwidth
Fast response times
0.6 ns output rise time
1.3 ns fall time from 10 dBm to no RF input
0.5 ns output propagation delay (rising edge)
1.3 ns propagation delay at 10 dBm (falling edge)
Broadband 50 Ω input impedance
ADL6012
10 DCPL
2
3
4
RFCM
RFIN
VENV+
VENV–
VOCM
9
8
7
ENVELOPE
DETECTOR
RFCM
Flat frequency response with minimal slope variation
1 dB error up to 43.5 GHz
5
6
VPOS
OCOM
Input range of −25 dBm to +15 dBm up to 43.5 GHz
Quasi differential 100 Ω output interface suitable to drive
100 Ω differential load
Figure 1.
Adjustable output common-mode voltage
Flexible supply voltage: 3.15 V to 5.25 V
3 mm × 2 mm, 10-lead LFCSP
APPLICATIONS
Envelope tracking
Microwave point to point links
Microwave instrumentation
Military radios
Pulse radar receivers
Wideband power amplifier linearization
GENERAL DESCRIPTION
The ADL6012 is a versatile, broadband envelope detector that
operates from 2 GHz to 67 GHz. The combination of a wide,
500 MHz envelope bandwidth and a fast, 0.6 ns rise time makes
the device suitable for a wide range of applications, including
wideband envelope tracking, transmitter local oscillator (LO)
leakage corrections, and high resolution pulse (radar) detection.
The quasi differential output interface formed by the VENV+
and VENV− pins has a matched, 100 Ω differential output
impedance designed to drive a 100 Ω differential load and up to
2 pF of capacitance to ground on each output. The output
interface provides the detected and amplified positive and
negative envelopes, which are level shifted using an externally
applied voltage to the VOCM interface. This configuration
simplifies interfacing to a high speed analog-to-digital
converter (ADC).
The response of the ADL6012 is stable over a wide frequency
range and features excellent temperature stability. Enabled by
propriety technology, the device independently detects the
positive and the negative envelopes of the RF input. Even order
distortion at the RF input due to nonlinear source loading is also
reduced when compared to classic diode detector architectures.
The ADL6012 is specified for operation from −55°C to +125°C,
and is available in a 10-lead, 3 mm × 2 mm LFCSP.
Rev. 0
Document Feedback
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice.
No license is granted by implication or otherwise under any patent or patent rights of Analog
Devices. Trademarks and registeredtrademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Technical Support
©2020 Analog Devices, Inc. All rights reserved.
www.analog.com
ADL6012
Data Sheet
TABLE OF CONTENTS
Features.............................................................................................. 1
Basic Connections...................................................................... 19
RF Input....................................................................................... 19
Envelope Output Interface........................................................ 20
Common-Mode Voltage Interface .......................................... 20
Enable Interface.......................................................................... 21
Decoupling Interface ................................................................. 21
PCB Layout Recommendations............................................... 21
System Calibration and Measurement Error ......................... 21
Applications Information ............................................................. 23
Evaluation Board........................................................................ 23
Outline Dimensions....................................................................... 24
Ordering Guide .......................................................................... 24
Applications ...................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications .................................................................................... 3
Absolute Maximum Ratings ........................................................... 6
Thermal Resistance...................................................................... 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions ............................ 7
Typical Performance Characteristics............................................. 8
Measurement Setups...................................................................... 17
Theory of Operation ...................................................................... 19
REVISION HISTORY
5/2020—Revision 0: Initial Version
Rev. 0 | Page 2 of 24
Data Sheet
ADL6012
SPECIFICATIONS
VPOS = 5.0 V, ENBL = 5.0 V, VOCM = 2.5 V, case temperature (TC) = 25°C, continuous wave (CW) input, 50 Ω source impedance,
input power (PIN) = 10 dBm, RF frequency (fRF) = 18 GHz, unless otherwise noted. Envelope outputs are with a differential, open load,
unless otherwise noted. See Figure 68 for the schematic.
Table 1.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
RF INPUT INTERFACE
Operating Frequency Range
Operating Input Power Range
Input Return Loss
RFIN (Pin 3)
2
−25
67
+15
GHz
dBm
dB
Reference characteristic impedance
(ZO) = 50 Ω
10
DETECTOR RESPONSE
OUTPUT DRIFT vs. TEMPERATURE1
−55°C < TC < +125°C
2 GHz
RFIN to differential VENV output
0.5
0.5
0.5
0.5
0.5
0.6
1
1
1
1
1.2
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
5.8 GHz
10 GHz
18 GHz
28 GHz
38 GHz
40 GHz
43.5 GHz
52 GHz
60 GHz
67 GHz
−40°C < TC < +105°C
2 GHz
5.8 GHz
10 GHz
18 GHz
28 GHz
38 GHz
40 GHz
43.5 GHz
52 GHz
0.4
0.4
0.4
0.4
0.4
0.5
0.9
0.9
0.8
0.8
1.0
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
60 GHz
67 GHz
DETECTOR GAIN2
2 GHz
5.8 GHz
10 GHz
18 GHz
28 GHz
38 GHz
40 GHz
43.5 GHz
52 GHz
1.967
1.82
V/VPEAK
V/VPEAK
V/VPEAK
V/VPEAK
V/VPEAK
V/VPEAK
V/VPEAK
V/VPEAK
V/VPEAK
V/VPEAK
V/VPEAK
1.776
1.677
1.868
1.554
1.718
1.799
1.095
0.505
0.294
60 GHz
67 GHz
Rev. 0 | Page 3 of 24
ADL6012
Data Sheet
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
OUTPUT INTERCEPT2
2 GHz
5.8 GHz
10 GHz
18 GHz
28 GHz
38 GHz
40 GHz
43.5 GHz
−0.266
−0.167
−0.166
−0.154
−0.161
−0.165
−0.155
−0.217
−0.177
−0.145
−0.070
V
V
V
V
V
V
V
V
V
V
V
52 GHz
60 GHz
67 GHz
DIFFERENTIAL ENVELOPE OUTPUT VOLTAGE
2 GHz
5.8 GHz
10 GHz
18 GHz
28 GHz
38 GHz
40 GHz
43.5 GHz
RFIN = 10 dBm
1.681
1.681
1.604
1.519
1.706
1.383
1.577
1.577
0.896
0.298
0.205
V
V
V
V
V
V
V
V
V
V
V
52 GHz
60 GHz
67 GHz
ENVELOPE OUTPUT INTERFACE
Output Impedance
Envelope Bandwidth (−3 dB)
Relative Gain3
100 MHz to 500 MHz
100 MHz to 700 MHz
Output Rise Time4
Output Fall Time5
10 dBm to No RF Input
0 dBm to No RF Input
−5 dBm to No RF Input
Output Propagation Delay6
Rising Edge
VENV+ (Pin 8), VENV− (Pin 9)
Differential,10 MHz
100 Ω differential load
100//0.3
500
Ω//pF
MHz
−4.3
−8.2
−3.1
−6.2
0.6
dB
dB
ns
10% to 90%,100 Ω load
90% to 10%,100 Ω load
1.3
0.5
0.4
ns
ns
ns
10 dBm
10 dBm
5 dBm
−5 dBm
0.5
1.3
1
ns
ns
ns
ns
Falling Edge
0.5
Common-Mode Voltage Range
Common-Mode Voltage7
Minimum Output Common-Mode Voltage VOCM (Pin 7) = 0.9 V
Maximum Output Common-Mode
Voltage
Operating input range, VOCM pin
VPOS = 5 V, VOCM is open
0.9
2.49
VPOS/2
2.53
V
V
V
V
2.51
0.96
2.65
VOCM = 2.625 V
Short-Circuit Output Current
Differential Output Noise Density
Output Offset
Differential load = 0 Ω, RFIN = 10 dBm
200 MHz, RFIN = 3 GHz
No signal at RFIN, differential output
(VENV+) − (VENV−)
9.7
−145
2
mA
dBm/Hz
mV
0
4.5
Rev. 0 | Page 4 of 24
Data Sheet
ADL6012
Parameter
Test Conditions/Comments
Min
0.9
Typ
10
Max
Unit
VOCM INTERFACE
VOCM Input Impedance
VOCM Input Voltage Range
Current In to Pin
VOCM
kΩ
V
µA
2.625
3.8
1.8
ENBL INPUT
ENBL (Pin 1)
Logic High Voltage, VIH
Logic Low Voltage, VIL
Input Current
1.5
V
V
µA
µs
ns
0.5
50
ENBL = 1.5 V
RFIN = 10 dBm
5
200
90
Turn On Time8
Turn Off Time9
POWER SUPPLY
VPOS (Pin 5)
Operating Supply Voltage
Active Supply Current
Shutdown Supply Current
3.15
25.6
5.0
28.6
2
5.25
31.7
26
V
mA
µA
No signal at RFIN
ENBL = 0 V
1 Output drift over temperature is relative to 25°C, calculated by Equation 4 in the Applications Information section.
2 Detector gain is the slope of the best fit straight line obtained by linear regression on the input peak voltage range from 0.2 V to 1.6 V vs. the differential envelope
output voltage. Output intercept is the calculated differential envelope output voltage when the input is 0 V, based on the best fit line from linear regression.
3 Envelope bandwidth relative gain is the delta, in dB, of the VENV differential output measured relative to 100 MHz.
4 Output rise time is the time required to change the voltage at the output pin from 10% to 90% of the final value. The input power is stepped from a no RF input to 10 dBm.
5 Output fall time is the time required to change the voltage at the output pin from 90% to 10% of the initial value. The input power is stepped from a specified power
level to a no RF input.
6 Propagation delay is the delay from a 50% change in RFIN to a 50% change in the output voltage.
7 Refer to Figure 50 and the Applications Information section to set the output common-mode voltage.
8 ENBL turn on time is from a 50% change in the voltage on the ENBL pin to 90% of the settled envelope output.
9 ENBL turn off time is from a 50% change in the voltage on the ENBL pin to a shut off condition in the supply current.
Rev. 0 | Page 5 of 24
ADL6012
Data Sheet
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 2.
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Careful attention to
PCB thermal design is required.
Parameter
Rating
Supply Voltage (VPOS to OCOM, RFCM) 5.5 V
RFIN Input Signal Power1
Average
Peak
20 dBm
23 dBm
−0.3 V to VPOS + 0.3 V
θ
JA is the junction to ambient thermal impedance, and θJC is the
junction to case (exposed pad) thermal impedance.
DC Voltage at RFIN, VOCM, ENBL
Case Operating Temperature Range
ADL6012ACPZN
Table 3. Thermal Resistance
Package Type1
2
θJA
θJC
Unit
−40°C to +105°C
−55°C to +125°C
150°C
−65°C to +150°C
300°C
ADL6012SCPZN
CP-10-12
74.69
11.64
°C/W
Junction Temperature (TJ)
Storage Temperature Range
Lead Temperature (Soldering, 60 sec)
1 Thermal impedance simulated value is based on no airflow with the exposed
pad soldered to a 4-layer JEDEC board.
2 θJC is the thermal impedance from junction to the exposed pad on the
underside of the package.
1 Guaranteed by design. Not production tested.
ESD CAUTION
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the
operational section of this specification is not implied.
Operation beyond the maximum operating conditions for
extended periods may affect product reliability.
Rev. 0 | Page 6 of 24
Data Sheet
ADL6012
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
ENBL
RFCM
RFIN
1
2
3
4
5
10 DCPL
9
8
7
6
VENV+
VENV–
VOCM
OCOM
ADL6012
TOP VIEW
(Not to Scale)
RFCM
VPOS
NOTES
1. EXPOSED PAD. THE EXPOSED PAD (EPAD) ON THE UNDERSIDE OF THE DEVICE
IS ALSO INTERNALLY CONNECTED TO GROUND AND REQUIRES GOOD THERMAL
AND ELECTRICAL CONNECTION TO THE GROUND OF THE PRINTED CIRCUIT BOARD (PCB).
CONNECT ALL GROUND PINS TO A LOW IMPEDANCE GROUND PLANE
TOGETHER WITH THE EPAD.
Figure 2. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Mnemonic Description
1
ENBL
Device Enable. Connect this pin to VPOS to enter an enabled state. Connect this pin to ground to enter a disabled
state. This pin can also be driven from a 3 V logic output.
2, 4
RFCM
RF Input Ground Pins. The RFCM pins are connected to the exposed pad (EPAD) at the bottom of the package.
Connect the RFCM pins to the system ground using a low impedance ground plane together with the EPAD.
3
5
RFIN
VPOS
Signal Input. The RFIN pin is ac-coupled and has a nominal 100 Ω RF input impedance.
Supply Voltage. The operational range of this pin is from 3.15 V to 5.25 V. Decouple the power supply using suggested
capacitor values of 100 pF and 0.1 µF and place these capacitors as close as possible to the VPOS pin.
6
7
OCOM
VOCM
Output Common. Connect this pin to a low impedance ground plane together with the EPAD.
Output Common-Mode Control Input. This pin is internally biased to VPOS/2, nominal. An acceptable range on
this pin is 0.9 V to VPOS/2.
8, 9
10
VENV−,
VENV+
Envelope Detector Pseudo Differential Outputs. VENV− and VENV+ are the negative and positive outputs, respectively,
for the envelope detector output. A 50 Ω output impedance per pin forms a 100 Ω differential output impedance.
These pins feature a 100 Ω differential load and a 2 pF to ground per pin drive capability.
Bypass Pin for an Internal Bias Node. Connect this pin through a 0.1 µF capacitor to ground for best common-
mode noise rejection.
Exposed Pad. The exposed pad (EPAD) on the underside of the device is also internally connected to ground and
requires good thermal and electrical connection to the ground of the printed circuit board (PCB). Connect all
ground pins to a low impedance ground plane together with the EPAD.
DCPL
EPAD
Rev. 0 | Page 7 of 24
ADL6012
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
10
10
1
+125°C
+125°C
+105°C
+85°C
+25°C
–40°C
–55°C
+105°C
+85°C
+25°C
–40°C
–55°C
1
0.1
0.1
0.01
0.001
0.01
0.001
–30 –25 –20 –15 –10
–5
0
5
10
15
20
–30 –25 –20 –15 –10
–5
0
5
10
15
20
P
(dBm)
P
(dBm)
IN
IN
Figure 3. Differential VENV Output Voltage vs. Input Power (PIN) for Various
Temperatures at 2 GHz
Figure 6. Differential VENV Output Voltage vs. PIN for Various Temperatures
at 18 GHz
10
10
+125°C
+125°C
+105°C
+85°C
+25°C
–40°C
+105°C
+85°C
+25°C
–40°C
–55°C
1
0.1
–55°C
1
0.1
0.01
0.001
0.01
0.001
–30 –25 –20 –15 –10
–5
0
5
10
15
20
–30 –25 –20 –15 –10
–5
0
5
10
15
20
P
(dBm)
P
(dBm)
IN
IN
Figure 7. Differential VENV Output Voltage vs. PIN for Various Temperatures
at 28 GHz
Figure 4. Differential VENV Output Voltage vs. PIN for Various Temperatures
at 5.8 GHz
10
10
+125°C
+125°C
+105°C
+85°C
+25°C
–40°C
+105°C
+85°C
+25°C
–40°C
–55°C
–55°C
1
0.1
1
0.1
0.01
0.001
0.01
0.001
–30
–25
–20
–15
–10
–5
0
5
10
15
–30 –25 –20 –15 –10
–5
0
5
10
15
20
P
(dBm)
P
(dBm)
IN
IN
Figure 8. Differential VENV Output Voltage vs. PIN for Various Temperatures
at 38 GHz
Figure 5. Differential VENV Output Voltage vs. PIN for Various Temperatures
at 10 GHz
Rev. 0 | Page 8 of 24
Data Sheet
ADL6012
10
1
+125°C
+125°C
+105°C
+85°C
+25°C
–40°C
–55°C
+105°C
+85°C
+25°C
–40°C
–55°C
1
0.1
0.1
0.01
0.01
0.001
0.001
–30
–25
–20
–15
–10
–5
0
5
10
–20
–15
–10
–5
0
5
10
P
(dBm)
P
(dBm)
IN
IN
Figure 9. Differential VENV Output Voltage vs. PIN for Various Temperatures
at 40 GHz
Figure 12. Differential VENV Output Voltage vs. PIN for Various
Temperatures at 60 GHz
10
1
+125°C
+105°C
+85°C
+25°C
–40°C
+125°C
+105°C
+85°C
+25°C
–40°C
–55°C
1
0.1
–55°C
0.1
0.01
0.01
0.001
0.001
–30
–25
–20
–15
–10
–5
0
5
10
15
–20
–15
–10
–5
0
5
10
P
(dBm)
P
(dBm)
IN
IN
Figure 10. Differential VENV Output Voltage vs. PIN for Various
Temperatures at 43.5 GHz
Figure 13. Differential VENV Output Voltage vs. PIN for Various
Temperatures at 67 GHz
10
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
3
+125°C
+105°C
+85°C
+25°C
–40°C
–55°C
2
1
0.1
1
0
–1
–2
–3
+125°C
+105°C
+85°C
+25°C
–40°C
–55°C
0.01
0.001
–30
–25
–20
–15
–10
–5
0
5
10
15
0
0.2
0.4
0.6
0.8
1.0
1.2
(V)
1.4
1.6
1.8
2.0
P
(dBm)
V
PEAK
IN
Figure 11. Differential VENV Output Voltage vs. PIN for Various
Temperatures at 52 GHz
Figure 14. Differential VENV Output Voltage and Error vs. VPEAK for Various
Temperatures at 2 GHz
Rev. 0 | Page 9 of 24
ADL6012
Data Sheet
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
3
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
3
2
1
0
2
1
0
–1
–2
–3
–1
+125°C
+105°C
+85°C
+25°C
–40°C
–55°C
+125°C
+105°C
+85°C
+25°C
–2
–40°C
–55°C
–3
0
0.2
0.4
0.6
0.8
1.0
1.2
(V)
1.4
1.6
1.8
2.0
0
0.2
0.4
0.6
0.8
1.0
1.2
(V)
1.4
1.6
1.8
2.0
V
V
PEAK
PEAK
Figure 15. Differential VENV Output Voltage and Error vs. VPEAK for Various
Temperatures at 5.8 GHz
Figure 18. Differential VENV Output Voltage and Error vs. VPEAK for Various
Temperatures at 28 GHz
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
3
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
3
2
2
1
1
0
0
–1
–2
–3
–1
–2
–3
+125°C
+105°C
+85°C
+25°C
–40°C
–55°C
+125°C
+105°C
+85°C
+25°C
–40°C
–55°C
0
0.2
0.4
0.6
0.8
1.0
1.2
(V)
1.4
1.6
1.8
2.0
0
0.2
0.4
0.6
0.8
1.0
1.2
(V)
1.4
1.6
1.8
2.0
V
V
PEAK
PEAK
Figure 16. Differential VENV Output Voltage and Error vs. VPEAK for Various
Temperatures at 10 GHz
Figure 19. Differential VENV Output Voltage and Error vs. VPEAK for Various
Temperatures at 38 GHz
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
3
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
3
2
2
1
1
0
0
–1
–2
–3
–1
–2
–3
+125°C
+105°C
+85°C
+25°C
–40°C
–55°C
+125°C
+105°C
+85°C
+25°C
–40°C
–55°C
0
0.2
0.4
0.6
0.8
1.0
1.2
(V)
1.4
1.6
1.8
2.0
0
0.2
0.4
0.6
0.8
(V)
1.0
1.2
1.4
V
V
PEAK
PEAK
Figure 17. Differential VENV Output Voltage and Error vs. VPEAK for Various
Temperatures at 18 GHz
Figure 20. Differential VENV Output Voltage and Error vs. VPEAK for Various
Temperatures at 40 GHz
Rev. 0 | Page 10 of 24
Data Sheet
ADL6012
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
3
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
3
2
2
1
1
0
0
–1
–2
–3
–1
+125°C
+105°C
+85°C
+25°C
–40°C
–55°C
+125°C
+105°C
+85°C
+25°C
–40°C
–55°C
–2
–3
1.4
0
0.2
0.4
0.6
0.8
1.0
1.2
(V)
1.4
1.6
1.8
2.0
0
0.2
0.4
0.6
0.8
(V)
1.0
1.2
V
V
PEAK
PEAK
Figure 21. Differential VENV Output Voltage and Error vs. VPEAK for Various
Temperatures at 43.5 GHz
Figure 24. Differential VENV Output Voltage and Error vs. VPEAK for Various
Temperatures at 67 GHz
2.5
2.0
1.5
1.0
0.5
0
3
3
2
1
0
2
1
0
–1
–2
–3
–1
+125°C
+105°C
+85°C
+25°C
–40°C
–55°C
+125°C
+105°C
+85°C
–40°C
–55°C
–2
–3
0
0.2
0.4
0.6
0.8
1.0
1.2
(V)
1.4
1.6
1.8
2.0
–40 –35 –30 –25 –20 –15 –10 –5
0
5
10 15 20
V
P
IN
(dBm)
PEAK
Figure 22. Differential VENV Output Voltage and Error vs. VPEAK for Various
Temperatures at 52 GHz
Figure 25. Normalized Temperature Drift Error to 25°C vs. PIN for Various
Temperatures at 2 GHz
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
3
3
2
1
2
1
+125°C
+105°C
+85°C
+25°C
–40°C
–55°C
0
0
+125°C
+105°C
+85°C
–1
–2
–3
–1
–2
–3
–40°C
–55°C
–35 –30 –25
–15 –10 –5
0
5
10 15
0
0.2
0.4
0.6
0.8
(V)
1.0
1.2
1.4
–40
–20
20
V
P
(dBm)
PEAK
IN
Figure 23. Differential VENV Output Voltage and Error vs. VPEAK for Various
Temperatures at 60 GHz
Figure 26. Normalized Temperature Drift Error to 25°C vs. PIN for Various
Temperatures at 5.8 GHz
Rev. 0 | Page 11 of 24
ADL6012
Data Sheet
3
3
2
2
1
1
0
0
–1
–2
–3
–1
–2
–3
+125°C
+105°C
+85°C
–40°C
–55°C
+125°C
+105°C
+85°C
–40°C
–55°C
–40 –35 –30 –25 –20 –15 –10 –5
0
5
10 15 20
–40 –35 –30 –25 –20 –15 –10 –5
0
5
10 15 20
P
(dBm)
P
IN
(dBm)
IN
Figure 27. Normalized Temperature Drift Error to 25°C vs. PIN for Various
Temperatures at 10 GHz
Figure 30. Normalized Temperature Drift Error to 25°C vs. PIN for Various
Temperatures at 38 GHz
3
2
1
3
+125°C
+105°C
+85°C
2
–40°C
–55°C
1
0
0
–1
–2
–3
+125°C
+105°C
+85°C
–40°C
–55°C
–1
–2
–3
–40 –35 –30 –25 –20 –15 –10 –5
0
5
10 15 20
–30 –25 –20 –15 –10
–5
0
5
10
15
20
P
(dBm)
P
(dBm)
IN
IN
Figure 28. Normalized Temperature Drift Error to 25°C vs. PIN for Various
Temperatures at 18 GHz
Figure 31. Normalized Temperature Drift Error to 25°C vs. PIN for Various
Temperatures at 40 GHz
3
3
+125°C
+105°C
+85°C
–40°C
–55°C
+125°C
+105°C
+85°C
–40°C
–55°C
2
1
2
1
0
0
–1
–2
–3
–1
–2
–3
–40 –35 –30 –25 –20 –15 –10 –5
0
5
10 15 20
–40 –35 –30 –25 –20 –15 –10 –5
0
5
10 15 20
P
(dBm)
P
IN
(dBm)
IN
Figure 29. Normalized Temperature Drift Error to 25°C vs. PIN for Various
Temperatures at 28 GHz
Figure 32. Normalized Temperature Drift Error to 25°C vs. PIN for Various
Temperatures at 43.5 GHz
Rev. 0 | Page 12 of 24
Data Sheet
ADL6012
3
10
1
VPOS = 5.0V
VPOS = 3.3V
2
1
0
0.1
–1
0.01
0.001
+125°C
+105°C
+85°C
–40°C
–55°C
–2
–3
–30 –25 –20 –15 –10
–5
0
5
10
15
20
–35
–25
–15
–5
5
15
P
(dBm)
P
(dBm)
IN
IN
Figure 33. Normalized Temperature Drift Error to 25°C vs. PIN for Various
Temperatures at 52 GHz
Figure 36. Differential VENV Output Voltage vs. PIN for Various Supply
Voltages
3
2
1
0
35
+125°C
+105°C
+85°C
30
+25°C
–40°C
–55°C
25
20
15
10
5
+125°C
+105°C
+85°C
–40°C
–55°C
–1
–2
–3
0
–30 –25 –20 –15 –10
–5
0
5
10
15
20
0
1
2
3
4
5
6
P
(dBm)
VPOS (V)
IN
Figure 37. Supply Current vs. VPOS for Various Temperatures
Figure 34. Normalized Temperature Drift Error to 25°C vs. PIN for Various
Temperatures at 60 GHz
37
3
2
1
0
+125°C
36
35
34
33
32
31
30
29
+85°C
+25°C
–40°C
–55°C
+125°C
+105°C
+85°C
–40°C
–55°C
–1
–2
–3
–40
–30
–20
–10
0
10
20
–30 –25 –20 –15 –10
–5
0
5
10
15
20
P (dBm)
IN
P
(dBm)
IN
Figure 38. Supply Current vs. PIN for Various Temperatures at18 GHz
Figure 35. Normalized Temperature Drift Error to 25°C vs. PIN for Various
Temperatures at 67 GHz
Rev. 0 | Page 13 of 24
ADL6012
Data Sheet
20
15
10
5
0
–2
+15dBm
+10dBm
+5dBm
+5dBm
0dBm
–15dBm
DISABLED
+0dBm
–5dBm
–4
–10dBm
–15dBm
–20dBm
–25dBm
–30dBm
–6
–8
0
–10
–12
–14
–16
–18
–5
–10
–15
–20
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
1
11
21
31
41
51
61
71
VPOS (V)
INPUT FREQUENCY (GHz)
Figure 39. Envelope Output Error vs. VPOS at Different RF Input Power Levels
Figure 42. Input Return Loss (S11) vs. Input Frequency with Input Connector
and PCB Trace Embedded
10
3.0
2.5
2.0
1.5
1.0
0.5
0
5
+15dBm
+10dBm
+5dBm
+0dBm
–5dBm
0
+20dBm
+15dBm
+10dBm
+0dBm
–10dBm
ENBL
1
0.1
0.01
0.001
–10dBm
2.5
–15dBm
3.0 3.5
–20dBm
–25dBm
4.5
–30dBm
5.0 5.5
–2
0
2
4
6
8
2.0
4.0
TIME (ms)
VPOS (V)
Figure 40. Differential VENV Output vs. VPOS at Different RF Input Power Levels
Figure 43. ENBL Pulse Response at Different RF Input Power Levels
0
2.0
0
1.5
1.0
0.5
0
–20
–40
–60
–80
+15dBm
+10dBm
+5dBm
0dBm
–5dBm
–10dBm
RF INPUT
–0.5
0
10
20
30
40
0
5
10 15 20 25 30 35 40 45 50 55 60 65 70
FREQUENCY (GHz)
TIME (ns)
Figure 41. RF Feedthrough Insertion Loss (S21) from RFIN to VENV
Figure 44. RF Input Pulse Response, Carrier = 4 GHz
Rev. 0 | Page 14 of 24
Data Sheet
ADL6012
5
T
CH2 SCALE: 50.0mV
CH2 POSITION: –2.48div
VENV+
RF INPUT
VENV–
0
1
3
2
–5
–10
–15
AM DEPTH
50% (0dBm)
–20
–25
10% (0dBm)
90% (0dBm)
10% (–6dBm)
CH1 50.0mV CH2 50.0mV
CH3 50.0mV
M20.0ns/div
A CH2
2.0mV
1M
10M
100M
VENV± FREQUENCY (Hz)
1G
10G
T
20.0GS/s IT 25.0ps/pt
Figure 48. AM Response on VENV Outputs, Carrier = 4 GHz, Envelope = 20 MHz
Figure 45. Envelope Bandwidth of VENV vs. VENV Frequency and
Amplitude Modulation (AM) Depth
T
CH2 SCALE: 100.0mV
CH2 POSITION: –3.08DIV
+15dBm
+10dBm
+5dBm
0dBm
–5dBm
–10dBm
–15dBm
–20dBm
–25dBm
–30dBm
3
VENV+
RF INPUT
VENV–
1
2
–2
–4
–6
CH1 100mV CH2 100mV
CH3 100mV
M2.5ns/DIV
A CH2
2.0mV
–12
–7
–2
3
8
T
20.0GS/s IT 2.5ps/pt
OUTPUT CURRENT (mA)
Figure 46. Differential VENV Output Voltage vs. Output Current for Different
RF Input Power Levels
Figure 49. Pulse Response on VENV Outputs, Carrier = 5.8 GHz
10
3.0
+15dBm
+10dBm
+5dBm
0dBm
–5dBm
–10dBm
–15dBm
–20dBm
–25dBm
–30dBm
VENV+
VENV–
(VENV+) + (VENV–)/2
2.5
2.0
1.5
1.0
0.5
0
1
0.1
0.01
0.001
1
10
70
0
0.5
1.0
1.5
2.0
2.5
3.0
INPUT FREQUENCY (GHz)
VOCM (V)
Figure 47. Differential VENV Output Voltage vs. Input Frequency at
Different RF Input Power Levels
Figure 50. VENV Output vs. VOCM, No RF Input
Rev. 0 | Page 15 of 24
ADL6012
Data Sheet
2.5
2.0
1.5
1.0
0.5
–135
–140
–145
–150
–155
–160
PIN = +15dBm
PIN = 0dBm
PIN = –15dBm
NO PIN
V
= 5V
POS
0
0
10
20
30
40
50
60
70
80
0
200
400
600
800
1000
INPUT FREQUENCY (GHz)
FREQUENCY (MHz)
Figure 53. Output Spectral Noise Density vs. Frequency, RFIN = 3 GHz
Figure 51. Detector Gain vs. Input Frequency
10
120
100
80
2GHz
40GHz
43.5GHz
52GHz
60GHz
67GHz
5.8GHz
10GHz
18GHz
28GHz
38GHz
1
0.1
60
40
0.01
20
0
0.001
0.001
0.1
1
10
100
1000
–40
–20
0
20
FREQUENCY(MHz)
INPUT POWER (dBm)
Figure 52. Power Supply Rejection Ratio (PSRR) vs. Frequency, 200 mV p-p at
the VPOS Pin (See Figure 58 for the PSRR Measurement Setup)
Figure 54. Differential Envelope Output vs. Input Power at Various
Frequencies at 25°C
Rev. 0 | Page 16 of 24
Data Sheet
ADL6012
MEASUREMENT SETUPS
E3631A
RESISTIVE
PAD
KEYSIGHT
MSOS254A
BIAS T
VPOS = 5V
MIXER
ZFBT-6GW-FT+
ZMX-8GLH
VENV+
VENV–
SIGNAL
GENERATOR
SME06
DIFFERENTIAL
PROBE
RF + DC
RF IN
AMPLIFIER
ZVA-183W-S+
SPLITTER
PD-0040
RF
IF
RF
ADL6012
CH1
CH2
CH3
1131A
DC
LO
DC
POWER
SUPPLY
MXG
AGILENT
SIGNAL
GENERATOR
Figure 55. Amplitude Modulation Envelope Bandwidth Measurement Setup
E3631A
RESISTIVE
PAD
KEYSIGHT
VPOS = 5V
VENV+
MSOS254A
MIXER
MARKI
POWER
ZMX-8GLH
DIFFERENTIAL
PROBE
PULSE
AMPLIFIER
ZVA-183W-S+
RF IN
GENERATOR
IF
RF
CH1
ADL6012
SPLITTER
1131A
HP8133A
VENV–
PD-0040
LO
TRIGGER
OUTPUT
CH2
CH3
MXG N5183B
AGILENT
SIGNAL
GENERATOR
Figure 56. Test Setup for Pulse Response
E3631A
VPOS = 5V
VENV+
RFIN
HP
34401
AGILENT
E8257D
ADL6012
VENV–
Figure 57. Setup to Measure Differential Envelope Output Voltage vs. Input Power
Rev. 0 | Page 17 of 24
ADL6012
Data Sheet
5V
POWER
SUPPLY
EVALUATION BOARD
VPOS
HP 6625A
BIAS TEE
PS 5575A
VENV+
PORT 1
PORT 2
PORTS
ADL6012
RFIN
VENV–
50Ω
COMBINER
MINI-CIRCUITS
ZFSCJ-2-2 0.01MHz TO 20MHz
SBTCJ-1W+ 1MHz TO 750MHz
ZFSCJ-2-4 50MHz TO 1GHz
NETWORK ANALYZER
HP 8753D
NOTES
1. REMOVE ALL DECOUPLING CAPACITORS FROM POWER SUPPLY NODE ON THE EVALUATION BOARD.
2. MEASURE AND ACCOUNT FOR SIGNAL ATTENUATION ON POWER SUPPLY NODE.
Figure 58. Setup for PSRR Measurement
Rev. 0 | Page 18 of 24
Data Sheet
ADL6012
THEORY OF OPERATION
The ADL6012 uses Schottky diodes in a two path detector
topology. One path responds during the positive half cycles of
the input, and the other responds during the negative half
cycles of the input, achieving full wave signal detection. This
arrangement presents a constant input impedance throughout
the full RF cycle, preventing the reflection of even order harmonic
distortion components back toward the source. This reflection
is a well known phenomenon of widely used, traditional, single-
Schottky diode detectors. Detector response time at lower RF
frequencies is also improved with symmetrical detection.
+5V
0.1µF
ADL6012
1
2
10
9
ENBL
DCPL
VENV+
VENV–
VOCM
OCOM
C1
0.1µF
RFCM
RFIN
VENV+
VENV–
RFIN
3
4
8
7
RFCM
VPOS
+5V
5
6
0.1µF
EPAD
C2
1µF
C3
100pF
Figure 59. Basic Connections
The diodes are arranged on the chip to minimize the effect of
chip stresses and temperature variations. The diodes are biased
by small, keep alive currents chosen in a trade-off between the
inherently low sensitivity of a diode detector and the need to
preserve envelope bandwidth. Therefore, the corner frequency
of the front-end, low-pass filtering is a weak function of the
input level. At low input levels, the −3 dB corner frequency is at
approximately 2 GHz.
RF INPUT
The RFIN single-ended input is internally terminated and
internally ac-coupled. No external matching is required up to
67 GHz. The simplified input stage is shown in Figure 60. The
input trace can be directly routed with CPWG with ground on
both sides of the signal trace shown in Figure 65 and Figure 66.
Broadband response is achieved with small vias on both sides of
the signal trace and microwave dielectric material. The trace
width, gap, and dielectric thickness for the CPWG is designed
to the characteristic impedance of 50 Ω to ensure the
DC voltages at the RFIN pin (Pin 3) are blocked by an on-chip
capacitor. The two RFCM ground pins, Pin 2 and Pin 4, on
either side of RFIN form part of an RF coplanar waveguide
(CPWG) launch into the detector. The RFCM pins must be
connected to the signal ground. Give careful attention to the
design of the PCB in this area.
broadband matching is achieved for the best frequency flatness.
The RFCM pins are the ground return to the RF input. It is
critical that these pins are connected to the low impedance
ground plane, and serve as ground for the CPWG.
The output stage impedance is 100 Ω differential with propagation
delay under 1 ns, and an envelope bandwidth over 500 MHz.
The differential outputs, VENV+ and VENV− (Pin 8 and Pin 9,
respectively) provide the high speed envelope information for
both the positive and negative cycles of the RF input signal.
RFCM
200Ω
200Ω
–
RFIN
ENVELOPE
+
RFCM
BASIC CONNECTIONS
The basic connections are shown in Figure 59. A dc supply of
nominally 3.3 V to 5 V is required. The bypass capacitors (C2
and C3) provide supply decoupling for the device. Place these
capacitors as close as possible to VPOS (Pin 5). The exposed
pad is internally connected to the IC ground and must be soldered
down to a low impedance ground on the PCB. OCOM (Pin 6)
is the output common. Connect OCOM to a low impedance
ground plane together with the exposed pad. DCPL (Pin 10) is
connected to an internal bias node. Place a 0.1 µF capacitor to
ground for the best common-mode noise rejection.
Figure 60. Input Stage
Rev. 0 | Page 19 of 24
ADL6012
Data Sheet
The ADL6012 envelope outputs can also be ac-coupled for pulsed
detection applications, as shown in Figure 63. AC coupling allows
different common-mode voltages to be interfaced to the ADC.
For example, the VENV+ and VENV− outputs can be used to
detect pulses in radar applications. See Figure 49 for the typical
envelope pulse response.
ENVELOPE OUTPUT INTERFACE
The differential envelope outputs, VENV+ and VENV−, provide
the envelope information of the input signal. The ADL6012 is
designed to drive 100 Ω differential or a 50 Ω load on each
VENV output when ac-coupled. It is important that the
VENV outputs are not dc-coupled to 50 Ω load referenced to
ground, which results in excessive dc current flow to the load
that may exceed the output drive capability, depending on the
output common-mode voltage level. The ADL6012 is suitable
for AM and pulse modulation detection. See Figure 48 and
Figure 49 for the typical AM and pulse output response,
respectively. The device features an extremely fast response
time of approximately 1 ns or less.
+5V
1µF
100pF
5
C1
VPOS
1µF
U3
VENV+
9
IN+
IN–
3
PULSED
RFIN
R1
100Ω
ADC
VENV–
8
For applications that require fast response to RF input levels or
pulsed RF detection, connect the envelope outputs to trans-
mission lines with a differential characteristic impedance of 100 Ω,
terminated with a 100 Ω differential load, so that the outputs are
impedance matched with no reflections from the load. Figure 61
shows the simplified ADL6012 output stage interfaced to a
100 Ω load with impedance controlled transmission lines.
C2
1µF
OCOM
6
EPAD
Figure 63. Simplified Pulsed Measurement Application
COMMON-MODE VOLTAGE INTERFACE
VOCM (Pin 7) is the input that controls the common-mode
voltage output to the VENV pins. VOCM sets the output
common-mode voltage and is internally biased to VPOS/2.
An external voltage source can be used for setting a different
output common-mode voltage to accommodate the next stage
input common-mode voltage range, as shown in Figure 64. The
reference voltage from the ADC is used as the voltage source to
accurately drive the VOCM pin. The range for VOCM is 0.9 V
to VPOS/2. In addition, this pin is used to level shift the
VENV outputs so that both the positive and negative
envelope information is accurately represented.
The output impedance of the ADL6012 drives a differential 100 Ω
load. The differential VENV output dc voltage is divided down
by the ratio of the load and output impedance. For example,
with a differential 100 Ω output load, the differential output
voltage is halved from the open load voltage. See Figure 62 for the
differential envelope output voltage vs. the input power with
various output loads.
ADL6012
50Ω
9
VENV+
Z(DIFFERENTIAL) = 100Ω
100Ω
RECEIVER
0.1µF
ADL6012
VENV–
8
1
2
10
9
ENBL
RFCM
RFIN
DCPL
VENV+
VENV–
VOCM
OCOM
U3
50Ω
IN+
ADC
IN–
R1
100Ω
3
4
8
7
VREF
RFCM
VPOS
Figure 61. Simplified ADL6012 Output Interface
5
6
0.1µF
4
3
2
1
0
EPAD
OPEN
400Ω
200Ω
100Ω
Figure 64. External Voltage Source Setting VOCM
Differential envelope outputs provide the lowest distortion and
lower noise. The advantages of differential outputs include lower
offset error, faster output response, higher common-mode noise
rejection, and less feedthrough. Place a 0.1 µF bypass capacitor
from VOCM to GND to minimize common-mode noise.
–15
–5
5
15
INPUT POWER (dBm)
Figure 62. Differential Envelope Output vs. Input Power for Different Output Loads
Rev. 0 | Page 20 of 24
Data Sheet
ADL6012
ENABLE INTERFACE
SYSTEM CALIBRATION AND MEASUREMENT
ERROR
ENBL (Pin 1) provides the ability to enable or disable the
device to conserve power. Connect ENBL to VPOS or above
1.5 V to enable the device. Connect ENBL to ground or below
0.5 V to disable the device. Do not exceed VPOS by 0.3 V or
below ground by more than 0.3 V. Leaving the ENBL pin open
turns off the device.
To achieve the highest detection accuracy, perform calibration
at the board level because output voltages vary from device to
device. Each device can be calibrated with two or more points
in the linear region of the transfer function by applying CW
input at different levels. The slope and intercept can be
calculated as described in this section. Linear regression over
the calibration range is recommended for best accuracy.
Faster turn on time can be achieved using a smaller capacitor
value on the VOCM pin. The capacitor must be large enough to
minimize the common-mode noise.
Board level calibration is a simple method to improve the
accuracy of the envelope detection. With a minimum of two
point or more calibration, the entire detection range of the
device can be calibrated to the highest accuracy possible.
DECOUPLING INTERFACE
DCPL (Pin 10) is connected to the internal bias node. DCPL
provides the stable output common-mode voltage. Connect a
0.1 µF capacitor from the DCPL pin to ground for the best
common-mode noise performance.
The measured ADL6012 transfer function at 18 GHz is shown
in Figure 67 and the envelope output and linearity conformance
error vs. the input peak voltage at various temperatures from
−40°C to +125°C. Error over temperature is relative to the
room 25°C curve.
PCB LAYOUT RECOMMENDATIONS
Parasitic elements of the PCB, such as coupling and radiation,
limit accuracy at very high frequencies. Ensure low loss power
transmission from the connector to the internal circuit of the
ADL6012. Microstrip and CPWG are popular forms of trans-
mission lines because of their ease of fabrication and low cost
(see Figure 65 and Figure 66). In the ADL6012 evaluation
board (ADL6012-EVALZ), a grounded CPWG (GCPWG)
minimizes radiation effects and provides the maximum band-
width by using two rows of grounding vias on both sides of the
signal trace.
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
3
2
1
0
–1
–2
–3
+125°C
+105°C
+85°C
+25°C
–40°C
–55°C
15mils
5mils
5mils
8mils
RO4003
0
0.2
0.4
0.6
0.8
1.0
1.2
(V)
1.4
1.6
1.8
2.0
V
PEAK
VIA
VIA
Figure 67. Differential VENV Output Voltage and Error vs. Input Peak
Voltage at 18 GHz
Figure 65. CPWG Interface Design to RFIN for RO4003 Material (Not to Scale)
Figure 66 shows the CPWG structure of the PCB layout.
Microwave material RO4003 with 8 mil thickness is used in the
ADL6012-EVALZ between the RF signal and ground layer.
VIA
RFCM
RFIN
RFCM
VIA
Figure 66. Suggested RF Input Layout
Rev. 0 | Page 21 of 24
ADL6012
Data Sheet
The following equations are used to calculate the slope and
intercept of each device, which is used in calibration to improve
the detection accuracy:
The ADL6012 offers extremely stable temperature performance
across frequencies. See Figure 25 to Figure 35 for the temperature
drift error from −55°C to +125°C. The typical temperature drift is
less than 1 dB of error over the entire detection range of the device
from 2 GHz to 67 GHz. This makes the device well suited
for applications operating over a wide temperature range.
Temperature drift error relative to 25°C is calculated as follows:
Slope = (VOUT2 − VOUT1)/(VPEAK2 − VPEAK1
Intercept = VOUT1 − (Slope × VPEAK1
)
(1)
(2)
)
The error conformance is calculated as follows:
Error = 20 × log((VOUT − Intercept)/(Slope × VPEAK))
where:
(3)
Temperature Drift Error (dB) = (VOUT (TEMPERATURE) −
V
OUT (AT 25°C))/(dVOUT/dPIN)
(4)
V
V
V
OUT2 is the output voltage with VPEAK2 input.
OUT1 is the output voltage with VPEAK1 input.
OUT is the differential envelope output voltage at different
where:
VOUT is the differential envelope output.
dVOUT/dPIN is the derivative of the transfer function of the
input levels.
PEAK1 and VPEAK2 are input peak voltages at two different input
levels.
PEAK is the peak voltage input.
differential VENV output at 25°C vs. the input power.
V
V
Rev. 0 | Page 22 of 24
Data Sheet
ADL6012
APPLICATIONS INFORMATION
labelled VENV+ and VENV−. The dc envelope output voltage
and the output common-mode voltage can be measured at the
test points labeled VENV+_TP and VENV-TP. The output
common-mode voltage can be set externally by the VOCM turret.
See the ADL6012-EVALZ user guide for additional information
on the eval board.
EVALUATION BOARD
The ADL6012-EVALZ is a fully populated, 4-layer, Rogers 4003A
and FR4-based evaluation board. For normal operation, the
board requires a 3.3 V to 5 V power supply. Connect the power
supply to the VPOS and GND test loops. Apply the RF input to
RFIN at the 1.85 mm connector. The differential envelope
output signal is ac-coupled and is available on the connectors
1892-03A-6
Figure 68. Evaluation Board Schematic (Rev. C)
Table 5. Evaluation Board Components
Component
Function/Comments
Default Value
C1
C2
Bypass capacitor for the ENBL pin
Supply bypass capacitor. Place this capacitor as close to the VPOS pin as possible. Use microwave
grade, PPI, 0402BB104KW500 material.
Supply bypass capacitor. Place this capacitor as close to the VPOS pin as possible. Use microwave
grade material.
Bypass capacitors for the output common-mode voltage. Place these capacitors as close to the IC
as possible.
0.1 µF
0.1 µF
100 pF
0.1 µF
C3
C5, C8
C6, C7
R2
R3
R4
R5
R6, R7
R9, R10
R11, R12
RFIN connector
Envelope output ac coupling capacitors.
ENBL termination resistor.
ENBL pull-up resistor.
Output load resistor.
Optional VOCM resistor.
VOCM resistor divider network.
Series resistors for measuring the dc envelope outputs.
Series VENV resistors.
1 µF
Open
20 kΩ
Open
Open
Open
1 kΩ
0 Ω
1892-03A-6
1.85 mm, edge mount. Southwest,1892-03A-6.
Rev. 0 | Page 23 of 24
ADL6012
Data Sheet
OUTLINE DIMENSIONS
DETAIL A
(JEDEC 95)
2.54
2.44
2.34
3.10
3.00
2.90
0.50 BSC
10
6
PIN 1
INDICATOR
AREA
2.10
2.00
1.90
1.00
0.90
0.80
EXPOSED
PAD
0.35
0.30
0.25
5
1
PIN 1
TOP VIEW
SIDE VIEW
BOTTOM VIEW
IONS
INDICATOR AR EA OP T
(SEE DETAIL A)
0.80
0.75
0.70
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.05 MAX
0.02 NOM
SECTION OF THIS DATA SHEET.
0.30
0.25
0.20
SEATING
PLANE
0.203 REF
COMPLIANT TO JEDEC STANDARDS MO-229-WCED-3
Figure 69. 10-Lead Lead Frame Chip Scale Package [LFCSP]
3 mm × 2 mm Body and 0.75 mm Package Height
(CP-10-12)
Dimensions shown in millimeters
ORDERING GUIDE
Ordering
Quantity
Marking
Code
Model1
Temperature Range Package Description
−40°C to +105°C 10-Lead Lead Frame Chip Scale Package [LFCSP] CP-10-12
10-Lead Lead Frame Chip Scale Package [LFCSP] CP-10-12
Package Option
ADL6012ACPZN
ADL6012ACPZN-R2 −40°C to +105°C
ADL6012ACPZN-R7 −40°C to +105°C
1
C9Y
C9Y
C9Y
CAL
CAL
100
1000
1
100
1
10-Lead Lead Frame Chip Scale Package [LFCSP] CP-10-12
10-Lead Lead Frame Chip Scale Package [LFCSP] CP-10-12
10-Lead Lead Frame Chip Scale Package [LFCSP] CP-10-12
Evaluation Board
ADL6012SCPZN
−55°C to +125°C
ADL6012SCPZN-R2 −55°C to +125°C
ADL6012-EVALZ
1 Z = RoHS Compliant Part.
©2020 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D16086-5/20(0)
Rev. 0 | Page 24 of 24
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