ADL6317 [ADI]
500 MHz to 1000 MHz Transmit VGA for Use with RF DACs and Transceivers;
| 型号： | ADL6317 |
| 厂家： | 
ADI |
| 描述： | 500 MHz to 1000 MHz Transmit VGA for Use with RF DACs and Transceivers |
| 文件： | 总38页 (文件大小：1208K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Transmit VGA for Use with
RF DACs and Transceivers
ADL6317
Data Sheet
FEATURES
GENERAL DESCRIPTION
Transmit VGA for RF DAC, transceiver, and SoC to power
amplifier interface
RF output frequency range: 1500 MHz to 3000 MHz
Internal balun with bias-tee to supply RF DAC outputs
Integrated VVA attenuation range with on-chip DAC: 20.5 dB
2-stage high linearity amplifiers
The ADL6317 is a transmit variable gain amplifier (VGA) that
provides an interface from radio frequency digital-to-analog
converters (RF DACs), transceivers, and systems on a chip (SoC)
to power amplifiers. Integrated balun and hybrid couplers allow
high performance RF capability in the frequency range of
1500 MHz to 3000 MHz.
RF DSA attenuation range: 15.5 dB with 0.5 dB step
resolution
50 Ω differential inputs and 50 Ω single-ended output
Fully programmable via a 4-wire SPI
Single 5 V supply
38-terminal, 10.5 mm × 5.5 mm LGA
To optimize performance vs. power level, the ADL6317
includes a voltage variable attenuator (VVA), high linearity
amplifiers, and a digital step attenuator (DSA). All of the
devices integrated into the ADL6317 are programmable via a
4-wire serial port interface (SPI).
The ADL6317 is manufactured on an advanced silicon
germanium (SiGe), bipolar complementary metal oxide
semiconductor (BiCMOS) process.
APPLICATIONS
2G/3G/4G/long-term evolution (LTE) in FDD/TDD broadband
communication systems
Table 1. Related Devices in Transmit VGA Family
Parameter
ADL6316
ADL6317
Frequency Range (MHz)
500 to 1000
1500 to 3000
FUNCTIONAL BLOCK DIAGRAM
GND TXEN
CS
SDI SCLK SDO
MUXOUT
GND VVA_ANALOG CS5 CS4
GND
GND
GND
GND
GND
3.3V
LDO
TEMPERATURE
SENSOR
1.8V SPI
LDO
FUSE
BLOCK
ANALOG
MUX
ADC
SERIAL PORT INTERFACE
VVA
VVA
DSA
DSA
IN_N
AMP1
AMP2
AMP2
RFOUT
GND
DAC
IN_P
AMP1
GND
GND
VDAC
ADL6317
GND
GND
GND
GND
GND
GND
GND
V50AMP1
V33FUSE
V50AMP2
Figure 1.
Rev. B
Document Feedback
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rights of third parties that may result from its use. Specifications subject to change without notice.
No license is granted by implication or otherwise under any patent or patent rights of Analog
Devices. Trademarks and registeredtrademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Technical Support
©2020 Analog Devices, Inc. All rights reserved.
www.analog.com
ADL6317
Data Sheet
TABLE OF CONTENTS
Features.............................................................................................. 1
Programmability Guide................................................................. 16
Signal Path Modes...................................................................... 16
Auxiliary Mux Control.............................................................. 16
Serial Port Interface (SPI) ......................................................... 18
Device Setup.................................................................................... 19
Applications Information ............................................................. 21
Linearity Optimization.............................................................. 21
Performance and Power Optimization................................... 21
Applications ...................................................................................... 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications .................................................................................... 3
Digital Logic Timing.................................................................... 4
Absolute Maximum Ratings ........................................................... 6
Thermal Resistance...................................................................... 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions ............................ 7
Typical Performance Characteristics............................................. 8
Theory of Operation ...................................................................... 14
RF Input Balun with DAC Interface Network....................... 14
Quadrature Hybrid .................................................................... 14
RF Signal Chain.......................................................................... 14
Basic Connections .......................................................................... 15
Adjacent and Alternate Channel Power Ratios on LTE
Operation .................................................................................... 21
Layout .......................................................................................... 22
Characterization Setups................................................................. 23
Register Summary .......................................................................... 24
Register Details ............................................................................... 25
Outline Dimensions....................................................................... 38
Ordering Guide .......................................................................... 38
REVISION HISTORY
5/2020—Revision B: Initial Version
Rev. B | Page 2 of 38
Data Sheet
ADL6317
SPECIFICATIONS
V50AMP1 = V50AMP2 = 5 V, TA = 25°C, input power (PIN) = −25 dBm (−25 dBm per tone for two tones), VVA attenuation = 0 dB, DSA
attenuation = 0 dB, source resistance (RS) = load resistance (RL) = 50 Ω, unless otherwise noted.
Table 2.
Parameter
Test Conditions/Comments
Min
Typ
Max
Units
FREQUENCY RANGE
1500
3000 MHz
1850 MHz
Power Gain
Output 1 dB Compression Point (OP1dB)
Output Second-Order Intercept (OIP2)
Output Third-Order Intercept (OIP3)
Second Harmonic (HD2)
Third Harmonic (HD3)
Noise Figure (NF)
33.7
25.7
49.2
40.9
82.1
47.2
6.0
dB
dBm
dBm
dBm
dBc
dBc
dB
2150 MHz
Power Gain
OP1dB
OIP2
OIP3
HD2
HD3
NF
33.6
24.8
51.8
38.4
76.1
48.8
6.0
dB
dBm
dBm
dBm
dBc
dBc
dB
2600 MHz
Power Gain
OP1dB
OIP2
OIP3
HD2
HD3
NF
34.0
22.8
53.8
34.5
84.6
50.7
5.5
dB
dBm
dBm
dBm
dBc
dBc
dB
RF INPUT/OUTPUT CHARACTERISTICS
Input
Impedance
Return Loss
Output
Differential
Inband, 2150 MHz
50
−18
Ω
dB
Impedance
Return Loss
Gain Flatness
Single-ended
Inband, 2150 MHz
Deviation from best linear fit at 1850 MHz, 2150 MHz,
and 2600 MHz
50
−17.4
Ω
dB
Over 100 MHz bandwidth
Over 150 MHz bandwidth
0.1
0.2
dB
dB
VOLTAGE VARIABLE ATTENUATOR
Via 12-bit integrated DAC or external analog voltage on
VVA_ANALOG pin
Range
Gain Settling Time
20.5
386.8
dB
ns
Minimum attenuation to maximum attenuation by VVA
DAC
Maximum attenuation to minimum attenuation by VVA
DAC
1.681
µs
DSA Attenuation
Range
Resolution
15.5
0.5
304.4
195.0
dB
dB
ns
ns
Gain Settling Time
Minimum attenuation to maximum attenuation
Maximum attenuation to minimum attenuation
Rev. B | Page 3 of 38
ADL6317
Data Sheet
Parameter
DIGITAL LOGIC
Input Voltage
High (VIH)
Test Conditions/Comments
Min
Typ
Max
Units
SCLK, SDI, CS, CS4, CS5, TXEN
1.07
V
V
Low (VIL)
0.68
Input Current
High (IIH)
−100 μA
Low (IIL)
100
μA
Output Voltage
At 1.8 V
SDO
Register 0x121, Bit 4 = 0x0
High (VOH
)
Output high current (IOH) = −100 μA or −1 mA static
load
Output low current (IOL) = 100 μA or 1 mA static load
Register 0x121, Bit 4 = 0x1
IOH = −100 μA or −1 mA static load
IOL = 100 μA or 1 mA static load
1.5
V
V
Low (VOL
At 3.3 V
High (VOH
)
0.2
)
2.7
V
V
Low (VOL
POWER SUPPLY
Voltage
)
0.2
4.75
5.0
435
310
6
5.25
V
Supply Current
High performance mode
Low power mode
mA
mA
mA
Power Down Current
DIGITAL LOGIC TIMING
Table 3.
Parameter Description
Min Typ Max Unit
fSCLK
tPWH
tPWL
tDS
Maximum serial clock rate, 1/tSCLK
Minimum period that SCLK is in logic high state
Minimum period that SCLK is in logic low state
Setup time between data and rising edge of SCLK
Hold time between data and rising edge of SCLK
25
10
10
5
MHz
ns
ns
ns
ns
tDH
5
CS
Setup time between falling edge of and rising edge of SCLK
tDCS
tDV
10
5
ns
Maximum time delay between falling edge of SCLK and output data valid for a read operation
ns
Timing Diagrams
DATA TRANSFER CYCLE
INSTRUCTION CYCLE
CHIP ID
ADDRESS
CS
SCLK
SDI
R/W CS5 CS4
0
0
0
0
A8 A7 A6 A5 A4 A3 A2 A1 A0
D7 D6 D5
D3 D2 D1 D0
0 0 0 0
N
0
0
Figure 2. Serial Port Interface Register Timing, MSB First
Rev. B | Page 4 of 38
Data Sheet
ADL6317
tSCLK
tPWH
t
PWL
SCLK
tDCS
CS
tDH
tDS
SDI
0
0
0
R/W
CS5
CS4
0
A_MSB
A7
A2
A1
A_LSB D_MSB
D6
D5
D1
D_LSB
Figure 3. Timing Diagram for the Serial Port Interface Register Write
SCLK
CS
DON’T
CARE
DON’T
CARE
DON’T
CARE
DON’T
CARE
DON’T
CARE
SDI
0
0
0
R/W
CS5
CS4
0
A_MSB
A7
A2
A1
A_LSB
tDV
D5
SDO
D_MSB
D6
D1
D_LSB
Figure 4. Timing Diagram for Serial Port Interface Register Read
Rev. B | Page 5 of 38
ADL6317
Data Sheet
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 4.
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Careful attention to
PCB thermal design is required.
Parameter
Rating
V50AMP1, V50AMP2
V33FUSE
VDAC
VVA_ANALOG
CS, SCLK, SDI, SDO, CS4, CS5, TXEN
RF Input Power (IN_N, IN_P) at 50 Ω
Operating Temperature Range
(Measured at Exposed Pad)
Junction Temperature Range
Storage Temperature Range
−0.3 V to +5.5V
−0.3 V to +3.6 V
−0.3 V to +3.6 V
−0.3 V to +3.6 V
−0.3 V to +3.6 V
10 dBm
θJA is the natural convection junction to ambient thermal
resistance measured in a one cubic foot sealed enclosure. θJC is
the conduction thermal resistance from junction to case where
the case temperature is measured at the bottom of the package.
−40°C to +105°C
The thermal resistance values specified in Table 5 are simulated
based on JEDEC specifications (unless specified otherwise) and
should be used in compliance with JESD51-12.
−40°C to +125°C
−65°C to +150°C
Table 5. Thermal Resistance1, 2
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the
operational section of this specification is not implied.
Operation beyond the maximum operating conditions for
extended periods may affect product reliability.
Package Type
θJA
θJC BOTTOM
Unit
CC-38-1
21.4
7.6
°C/W
1 For θJC BOTTOM, the case bottom is controlled at105°C and the case top is
controlled at 100°C.
2 Using enhanced heat removal (for example, PCB, heat sink, and airflow)
techniques to improve thermal resistance values.
ESD CAUTION
Rev. B | Page 6 of 38
Data Sheet
ADL6317
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
38 37 36 35 34 33 32 31 30 29 28 27 26
25
24
23
22
21
20
1
GND
GND
RFOUT
GND
GND
GND
GND
2
GND
3
4
5
6
IN_N
IN_P
ADL6317
TOP VIEW
(Not to Scale)
VDAC
GND
EPAD1
EPAD2
7
8
9 10 11 12 13 14 15 16 17 18 19
NOTES
1. NIC = NOT INTERNALLY CONNECTED. THIS PIN HAS NO PHYSICAL CONNECTION WITHIN THE CHIP.
2. EXPOSED PAD 1. EPAD1 IS INTERNALLY CONNECTED TO EPAD2. THE EXPOSED PAD MUST BE
CONNECTED TO GROUND FOR ELECTRICAL AND THERMAL PURPOSES.
3. EXPOSED PAD 2. EPAD2 IS INTERNALLY CONNECTED TO EPAD1. THE EXPOSED PAD MUST BE
CONNECTED TO GROUND FOR ELECTRICAL AND THERMAL PURPOSES.
Figure 5. Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
Mnemonic
Description
1, 2, 6, 7, 8, 9, 12, 14, 19, 20, 21, 22, 24,
25, 26, 31, 38
GND
Ground.
3
4
5
IN_N
IN_P
VDAC
RF Input, Negative.
RF Input, Positive.
Supply Voltage for External RF DAC. This pin can be left open during operation
without the RF DAC.
10, 11, 16, 18, 27
13
15
NIC
V50AMP1
V33FUSE
No Internal Connection. These pins have no physical connection within the chip.
Amplifier 1 Analog Power Supply (5.0 V).
VCO Low Dropout (LDO) Regulator Bypass. This pin is optionally 3.3 V when the
3.3 V LDO regulator is off.
17
23
V50AMP2
RFOUT
Amplifier 2 Analog Power Supply (5.0 V).
RF Output.
28, 29
CS4, CS5
Chip Select. Connect these pins to ground. Refer to the Multiple Chip
Operation to Share SPI Bus section for information about the connections in a
multiple chip operation.
30
32
33
34
35
36
37
VVA_ANALOG Analog Voltage Control for VVA.
MUXOUT
SDO
Test Mux Output.
Serial Port Data Output.
SCLK
SDI
Serial Port Clock Input.
Serial Port Data Input.
CS
Serial Port Latch Enable Input.
Amplifier Enable, DSA Attenuation, and Trim Value Selection.
Exposed Pad 1. EPAD1 is internally connected to EPAD2. The exposed pad must
be connected to ground for electrical and thermal purposes.
TXEN
EPAD1
EPAD2
Exposed Pad 2. EPAD2 is internally connected to EPAD1. The exposed pad must
be connected to ground for electrical and thermal purposes.
Rev. B | Page 7 of 38
ADL6317
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
V50AMP1 = V50AMP2 = 5 V, TA = 25°C, input power= −25 dBm (−25 dBm per tone for two tones), VVA attenuation = 0 dB, DSA attenuation
= 0 dB, RS = RL = 50 Ω, unless otherwise noted.
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
DSA_ATTEN_x[4:0] = 0 (Decimal)
T
T
T
= –20°C
= +40°C
= +105°C
C
C
C
DSA_ATTEN_x[4:0] = 31 (Decimal)
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 6. Gain vs. Frequency, 0.5 dB DSA Steps
Figure 9. Gain vs. Frequency for Various Temperatures
35
33
31
29
27
25
23
21
19
17
15
13
11
9
0
–1
–2
–3
–4
–5
–6
–7
–8
VVA_ATTEN[11:0] = 4000 (Decimal)
FREQUENCY = 1850MHz
FREQUENCY = 2140MHz
FREQUENCY = 2600MHz
–9
–10
–11
–12
–13
–14
–15
–16
–17
–18
–19
–20
VVA_ATTEN[11:0] = 0 (Decimal)
7
5
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28 30 32
DSA_ATTEN_x[4:0] (Decimal Code)
FREQUENCY (MHz)
Figure 10. Attenuation vs. DSA_ATTEN_x[4:0] at 1850 MHz, 2150 MHz, and
2600 MHz, VVA Attenuation = 0 dB
Figure 7. Gain vs. Frequency, 100 VVA_ATTEN[11:0] Steps
35.00
34.75
34.50
34.25
34.00
33.75
33.50
33.25
33.00
32.75
32.50
32.25
32.00
31.75
31.50
31.25
31.00
30.75
30.50
30.25
30.00
0
–1
2.5
2.4
2.3
2.2
2.1
2.0
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
–2
–3
–4
–5
–6
–7
–8
–9
–10
–11
–12
–13
–14
–15
–16
–17
–18
–19
–20
–21
–22
–23
–24
–25
SUPPLY VOLTAGE = 4.75V
SUPPLY VOLTAGE = 5.00V
SUPPLY VOLTAGE = 5.25V
FREQUENCY = 1850MHz
FREQUENCY = 2140MHz
FREQUENCY = 2600MHz
0
500
1000
1500
2000
2500
3000
3500
VVA_ATTEN[11:0] (Decimal Code)
FREQUENCY (MHz)
Figure 11. Attenuation and VVA Voltage vs. VVA_ATTEN[11:0] at 1850 MHz,
2150 MHz, and 2600 MHz, DSA Attenuation = 0 dB)
Figure 8. Gain vs. Frequency for Various Supplies
Rev. B | Page 8 of 38
Data Sheet
ADL6317
30.0
29.5
29.0
28.5
28.0
27.5
27.0
26.5
26.0
25.5
25.0
24.5
24.0
23.5
23.0
22.5
22.0
21.5
21.0
20.5
20.0
65
63
61
59
57
55
53
51
49
47
45
43
41
39
37
35
33
31
29
27
25
SUPPLY VOLTAGE = 4.75V
SUPPLY VOLTAGE = 5.00V
SUPPLY VOLTAGE = 5.25V
OIP3 (dBm)
OIP2 (dBm)
DSA ATTENUATION = 0dB
DSA ATTENUATION = 8dB
DSA ATTENUATION = 15.5dB
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 12. OP1dB vs. Frequency for Various Supplies
Figure 15. OIP3/OIP2 vs. Frequency at Various DSA Values,
VVA Attenuation = 0 dB
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
60
T
T
T
= –20°C
= +40°C
= +105°C
C
C
58
56
54
52
50
48
46
44
42
40
38
36
34
32
30
C
OIP3 (dBm)
OIP2 (dBm)
T
T
T
= +105°C
= +40°C
= –20°C
C
C
C
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 13. OP1dB vs. Frequency for Various Temperatures
Figure 16. OIP3/OIP2 vs. Frequency for Various Temperatures
50
60
58
56
54
52
50
48
46
44
42
40
38
36
34
32
30
48
46
44
42
40
38
36
34
32
30
28
26
24
22
20
OIP3 (dBm)
OIP2 (dBm)
VVA ATTENUATION = 0dB
VVA ATTENUATION = 10dB
VVA ATTENUATION = 20.5dB
FREQUENCY = 1850MHz
FREQUENCY = 2150MHz
FREQUENCY = 2600MHz
T
T
T
= +105°C
= +40°C
= –20°C
C
C
C
INPUT POWER (dBm)
FREQUENCY (MHz)
Figure 14. OIP3/OIP2 vs. Frequency at Various VVA Attenuation Values,
DSA Attenuation = 0 dB
Figure 17. OIP3 vs. Input Power for Various Temperatures at 1850 MHz,
2150 MHz, and 2600 MHz
Rev. B | Page 9 of 38
ADL6317
Data Sheet
60
58
56
54
52
50
48
46
44
42
40
38
36
34
32
30
60
55
50
45
40
35
30
25
20
15
10
OIP2 (dBm)
OIP3 (dBm)
GAIN (dB)
OP1dB (dBm)
FREQUENCY = 1850MHz
FREQUENCY = 2150MHz
FREQUENCY = 2600MHz
T
T
T
= +105°C
= +40°C
= –20°C
C
C
C
NOISE FIGURE (dB)
5
0
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20
INPUT POWER (dBm)
VVA ATTENUATION (dB)
Figure 18. OIP2 vs. Input Power for Various Temperatures at 1850 MHz,
2150 MHz, and 2600 MHz
Figure 21. Gain, OP1dB, OIP3, OIP2, Noise Figure vs. VVA Attenuation,
DSA Attenuation = 0 dB, Frequency = 1850 MHz
60
30
28
26
24
22
20
18
16
14
55
OIP2 (dBm)
50
45
OIP3 (dBm)
40
GAIN (dB)
35
30
25
20
15
10
T
T
T
= +105°C
= +40°C
= –20°C
VVA ATTENUATION = 0dB
VVA ATTENUATION = 10dB
VVA ATTENUATION = 20.5dB
C
C
C
12
10
8
OP1dB (dBm)
6
4
NOISE FIGURE (dB)
2
5
0
0
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
DSA ATTENUATION (dB)
FREQUENCY (MHz)
Figure 22. Gain, OP1dB, OIP3, OIP2, Noise Figure vs. DSA Attenuation,
VVA Attenuation = 0 dB, Frequency = 1850 MHz
Figure 19. Noise Figure vs. Frequency for Various Temperatures at Various
VVA Values, DSA Attenuation = 0 dB
60
15
14
OIP2 (dBm)
55
50
45
40
35
30
25
20
15
10
T
T
T
= +105°C
= +40°C
= –20°C
DSA ATTENUATION = 0dB
DSA ATTENUATION = 8dB
DSA ATTENUATION = 15.5dB
C
C
C
13
12
11
10
9
OIP3 (dBm)
GAIN (dB)
8
7
6
OP1dB (dBm)
5
4
3
2
NOISE FIGURE (dB)
5
0
1
0
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21
VVA ATTENUATION (dB)
FREQUENCY (MHz)
Figure 20. Noise Figure vs. Frequency for Various Temperatures at Various
DSA Values, VVA Attenuation = 0 dB
Figure 23. Gain, OP1dB, OIP3, OIP2, Noise Figure vs. VVA Attenuation,
DSA Attenuation = 0 dB, Frequency = 2150 MHz
Rev. B | Page 10 of 38
Data Sheet
ADL6317
60
250
230
210
190
170
150
130
110
90
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
OIP2 (dBm)
55
50
45
40
35
30
25
20
15
10
OIP3 (dBm)
GAIN (dB)
OP1dB (dBm)
NOISE FIGURE (dB)
70
5
0
50
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
DSA ATTENUATION (dB)
JUNCTION TEMPERATURE (°C)
Figure 24. Gain, OP1dB, OIP3, OIP2, Noise Figure vs. DSA Attenuation,
VVA Attenuation = 0 dB, Frequency = 2150 MHz
Figure 27. Proportional to Absolute Temperature (PTAT) ADC Code and PTAT
Voltage vs. Junction Temperature
60
START TIME STOP TIME
386.81ns
OIP2 (dBm)
55
50
45
40
1
2
OIP3 (dBm)
35
30
GAIN (dB)
25
OP1dB (dBm)
20
15
10
NOISE FIGURE (dB)
5
0
CH1 800mV 1MΩ –741mV
CH2 980mV 50Ω 1.36V
M200ns
10.3004000µs
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21
T
VVA ATTENUATION (dB)
Figure 25. Gain, OP1dB, OIP3, OIP2, Noise Figure vs. VVA Attenuation,
DSA Attenuation = 0 dB, Frequency = 2600 MHz
Figure 28. VVA Gain Settling Time, Minimum to Maximum VVA Attenuation
START TIME
1.6813µs
STOP TIME
60
OIP2 (dBm)
55
50
45
1
2
40
OIP3 (dBm)
35
GAIN (dB)
30
OP1dB (dBm)
25
20
15
10
NOISE FIGURE (dB)
5
0
CH1 800mV 1MΩ –741mV
CH2 980mV 50Ω 1.36V
M500ns
11.6497800
T
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
DSA ATTENUATION (dB)
Figure 26. Gain, OP1dB, OIP3, OIP2, Noise Figure vs. DSA Attenuation,
VVA Attenuation = 0 dB, Frequency = 2600 MHz
Figure 29. VVA Gain Settling Time, Maximum to Minimum VVA Attenuation
Rev. B | Page 11 of 38
ADL6317
Data Sheet
START TIME
STOP TIME
START TIME
STOP TIME
54.5ns
304.40ns
1
1
2
2
CH1 700mV 1MΩ –585mV
CH2 980mV 50Ω 1.58V
M100ns
10.1981000µs
CH1 700mV 1MΩ –689mV
CH2 980mV 50Ω 1.45V
M20.0ns
10.0359600µs
T
T
Figure 30. DSA Gain Settling Time, Minimum to Maximum DSA Attenuation
Figure 33. TXEN Response Time Measured from Amplifier 1 and Amplifier 2
Enabled (DSA = 0 dB) to Amplifier 1 and Amplifier 2 Disabled (DSA = 15.5 dB)
0.5
START TIME
STOP TIME
195.05ns
0.4
0.3
0.2
1
2
0.1
DNL
0
–0.1
–0.2
–0.3
–0.4
INL
–0.5
CH1 700mV 1MΩ –585mV
CH2 980mV 50Ω 1.58V
M50.0ns
10.1197170µs
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28 30 32
T
DSA_ATTEN_x[4:0] (Decimal Code)
Figure 31. DSA Gain Settling Time, Maximum to Minimum DSA Attenuation
Figure 34. DSA Gain Step Error, Frequency = 1850 MHz
0
–5
START TIME
STOP TIME
WITHOUT TUNING, OPTIMUM ABOVE 2.1GHz
WITH TUNING TO OPTIMIZE FOR 1.8GHz TO 2.1GHz
WITH TUNING TO OPTIMIZE BELOW 1.8GHz
182.97ns
–10
–15
–20
–25
–30
–35
–40
–45
1
2
CH1 700mV 1MΩ –585mV
CH2 980mV 50Ω 1.58V
M50.0ns
10.1197170µs
1.4
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
T
FREQUENCY (GHz)
Figure 32. TXEN Response Time, Measured from Amplifier 1 and Amplifier 2
Disabled (DSA Attenuation = 15.5 dB) to Amplifier 1 and Amplifier 2 Enabled,
(DSA Attenuation = 0 dB)
Figure 35. Return Loss of Differential RF Input S11 from 1.5 GHz to 3 GHz
Rev. B | Page 12 of 38
Data Sheet
ADL6317
0
250
245
240
235
230
225
220
215
210
205
200
195
190
185
180
175
170
165
160
155
150
–5
–10
–15
–20
–25
–30
AMPLIFIER 2 CURRENT
AMPLIFIER 1 CURRENT
T
T
T
= +105°C
= +40°C
= –20°C
C
C
C
1.4
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
FREQUENCY (GHz)
FREQUENCY (MHz)
Figure 36. Return Loss of Single-Ended RF Output S22 from 1.5 GHz to 3 GHz
Figure 37. Amplifier 1 and Amplifier 2 Supply Current vs. Frequency for
Various Temperatures
Rev. B | Page 13 of 38
ADL6317
Data Sheet
THEORY OF OPERATION
The ADL6317 is a highly integrated transmit VGA used to
interface an RF DAC to the power amplifier in a transmitter.
The ADL6317 targets high dynamic range multicarrier
transmitter designs.
RF SIGNAL CHAIN
The RF path includes a 20.5 dB VVA, the first stage of the fixed
gain amplifier, a 15.5 dB DSA, and the second stage of the fixed
gain amplifier (see Figure 38). The ADL6317 has two modes of
control of the VVA attenuation: internal analog control using an
integrated 12-bit DAC and external analog control. For internal
control, use Register 0x104, Bits[3:0] and Register 0x103, Bits[7:0]
to set the attenuation. The digital bits are double buffered to
avoid major carrier glitch. For this reason, Register 0x104 must
be written before Register 0x103. For external analog control of
the VVA, a control voltage is applied to the VVA_ANALOG pin
(Pin 30). Sample register writes for VVA control are shown in
Figure 38.
The ADL6317 offers multiple gain control options with an
integrated 20.5 dB VVA, on-chip DAC control or external
voltage control, a high linearity amplifier, an RF DSA with a
15.5 dB attenuation range in 0.5 dB steps, followed by the
second stage high linearity amplifier.
Putting all the building blocks of the ADL6317 together, the
signal path through the device starts with differential inputs
converted to singled-ended by the integrated balun and this
single-ended signal is then quadrature coupled by the internal
quadrature hybrid.
Table 7. Register Writes for the Control of VVA
Next, the integrated VVA, Amplifier 1, DSA, and Amplifier 2
optimize the RF signal amplitude for performance before the
RF signal passes through the output quadrature hybrid. All the
integrated building blocks of the ADL6317 are programmable via
the SPI.
Addres
s
Bits
Settings
Description
0x105
[1:0]
00
10
DAC to VVA
VVA_ANALOG (Pin 30) to VVA
0x104
0x103
[3:0]
[7:0]
User
defined
12-bit DAC code to set VVA
attenuation; first, write to
Register 0x104, Bits[3:0], and
then to Register 0x103, Bits[7:0]
RF INPUT BALUN WITH DAC INTERFACE
NETWORK
User
defined
The ADL6317 converts a single-channel, 50 Ω, input differen-
tial signal to a single-ended signal via the integrated balun.
Wideband matching allows the DAC to operate over a
frequency range from 1500 MHz to 3000 MHz, and a bias tee is
included to provide dc bias for the RF DAC.
Next, the fixed gain amplifier is used in a quadrature balanced
configuration. The DSA provides a 15.5 dB range with 0.5 dB
step resolution. The digital 5-bit DSA attenuation control is found
in Bits[4:0] of Register 0x102 and Register 0x112. Finally, the
second stage fixed gain amplifier is used in a quadrature
balanced configuration.
QUADRATURE HYBRID
Integrated quadrature hybrids at the RF input and RF output
allow wideband performance gain and match with a low input
and output reflection coefficient to the RF DAC and PA.
REGISTER 0x102, BITS[4:0] (TXEN = 0)
REGISTER 0x112, BITS[4:0] (TXEN = 1)
AMP
DSA
VVA
AMP
QUADRATURE
HYBRID
VVA_ATTEN, BITS[11:0] =
REGISTER 0x104, BITS[3:0]
AND
QUADRATURE
HYBRID
BALUN
REGISTER 0x103, BITS[7:0]
POWER UP
DEFAULT
IN GRAY
VVA CONTROL
DAC
0
2
30
VVA_ANALOG
VVA_SRC
REGISTER 0x105, BITS[1:0]
Figure 38. RF Signal Chain
Rev. B | Page 14 of 38
Data Sheet
ADL6317
BASIC CONNECTIONS
V50AMP1
V50AMP2
C9
0.1µF
C12
10PF
AGND
AGND
C8
C11
0.1µF
10pF
AGND
AGND
VDAC
R11
1
VVA_ANALOG
560Ω
C5
270PF
V33FUSE
C14
0.1µF
AGND
C6
1µF
C13
0.1µF
AGND
5
13
17
AGND
AGND
RFOUT
30
15
VDAC
V50AMP1
V50AMP2
VVA_ANALOG
V33FUSE
IN_N
23
RFOUT
3
4
32
IN_N
IN_P
MUXOUT
SDO
SCLK
MUXOUT
IN_P
33
34
35
36
U1
SDO
SCLK
SDI
CS
TXEN
28
ADL6317
CS4
SDI
CS
TXEN
AGND
37
29
CS5
AGND
AGND
Figure 39. Basic Connections
Table 8. Basic Connections
Functional Blocks Pin No.
Mnemonic
Description
Basic Connection
5 V
13, 17
V50AMP1,
V50AMP2
Amplifier analog supply voltage,
5 V
Decouple these pins via 10 pF and 0.1 µF
capacitors to ground. Ensure that the decoupling
capacitors are located close to the pins.
Decoupling
RF Inputs
15
V33FUSE
3.3 V LDO regulator decoupling
Decouple this pin via 0.1 µF and 1 µF capacitors
to ground. Ensure that the decoupling capacitors
are located close to the pin.
5
VDAC
Supply voltage for external RF DAC VDAC can be left open during operation without
the RF DAC.
3, 4
IN_N, IN_P
Differential RF inputs
Connect the IN_N and IN_P pins to an RF DAC or
transceiver output in differential configuration.
VVA
30
23
VVA_ANALOG External VVA control voltage input
Voltage input pin to control VVA attenuation.
RF Output
RFOUT
Single-ended RF output
Connect RF output to power meter, network
analyzer, noise figure meter, or spectrum analyzer.
Serial Port
33
34
35
36
SDO
SCLK
SDI
SPI data output
SPI clock
SPI data input
Chip select active low
1.8 V to 3.3 V tolerant logic levels.
1.8 V to 3.3 V tolerant logic levels.
1.8 V to 3.3 V tolerant logic levels.
1.8 V to 3.3 V tolerant logic levels.
CS
Auxiliary Mux
32
MUXOUT
Mux output
Connect mux output to multimeter, oscilloscope,
or spectrum analyzer.
Chip Selection
Mode Control
28, 29
37
CS4, CS5
TXEN
Chip selection
Connect these pins to ground.
1.8 V to 3.3 V tolerant logic levels.
Amplifier enable, DSA attenuation,
and trim value selection
Ground
1, 2, 6 to 9, 12,
14, 19 to 22, 24
to 26, 31, 38
GND
Ground
Connect these pins to the ground of the PCB.
Exposed Pad
Not applicable
EPAD1, EPAD2 Exposed pads
The exposed thermal pads are on the bottom of
the package. Solder the exposed pads to the PCB
ground. EPAD1 and EPAD2 are internally
connected to each other.
Rev. B | Page 15 of 38
ADL6317
Data Sheet
PROGRAMMABILITY GUIDE
Viewing the register map at the highest level, the registers are
subdivided into the major functional blocks, as shown in Table 9.
See the Register Summary section for a complete list of all the
registers on the ADL6317.
The controls of each mode of operation reside in a designated
subsection of the register map. Each operational mode includes
individual control of the enables of the amplifier blocks, DSA
attenuation, and power mode. Control of these functions reside
in Register 0x102 and Register 0x107 to Register 0x10A for
TXEN = 0 mode, or Register 0x112 and Register 0x117 to
Register 0x11A for TXEN = 1 mode. The specific mode selected
by the logic level on the TXEN pin (Pin 37) determines the state
of the registers (see Table 11).
Table 9. Memory Map Functional Groups
Register Address
Functional Blocks
0x000 to 0x011
Analog Devices, Inc., SPI configuration
0x100 to 0x101, 0x106 Signal path enable
0x103 to 0x105
0x10B, 0x11B
VVA source, VVA attenuation
Amplifier 2 optimization
Table 11. Control Registers for the Modes
0x102, 0x107 to 0x10A DSA attenuation, amplifier enable,
amplifier trim, TXEN = 0 mode
0x112, 0x117 to 0x11A DSA attenuation, amplifier enable,
amplifier trim, TXEN = 1 mode
Register Address
Mode
Function Block
0x102
0x112
TXEN = 0
TXEN = 1
TXEN = 0
TXEN = 1
TXEN = 0
TXEN = 1
TXEN = 0
TXEN = 1
TXEN = 0
TXEN = 1
DSA attenuation
DSA attenuation
0x107
0x117
Amplifier 1 optimization
Amplifier 1 optimization
Amplifier 1 enable
Amplifier 1 enable
Amplifier 2 optimization
Amplifier 2 optimization
Amplifier 2 enable
Amplifier 2 enable
0x120 to 0x121
Auxiliary mux selection, SPI supply
control
0x108
0x118
0x127 to 0x129
0x146 to 0x148
ADC clock, temperature readback
VVA and DSA attenuation readback
0x109
0x119
SIGNAL PATH MODES
The ADL6317 has two signal path modes. This feature allows two
predefined modes of operation to be controlled by TXEN, a real-
time external pin with no SPI latency. Table 10 shows the
hardware configuration to select the desired mode.
0x10A
0x11A
Signal Path Enable
The signal path enable bits are located in Register 0x100,
Register 0x108, Register 0x118, Register 0x10A, and
Register 0x11A. Figure 40 shows a breakdown of the individual
blocks that the particular enable bit controls.
Table 10. Mode Selection and Setup Registers
TXEN (Pin 37)
Mode
Enable, Setup Register
0
1
TXEN = 0 0x102, 0x107 to 0x10A
TXEN = 1 0x112, 0x117 to 0x11A
AUXILIARY MUX CONTROL
The ADL6317 has multiple auxiliary mux control blocks that
allow various modes of operation and monitoring points (see
Figure 41 and Table 12).
GND TXEN
CS
SDI SCLK SDO
MUXOUT
GND VVA_ANALOG CS5 CS4
GND
3
2
GND
GND
GND
GND
3.3V
LDO
TEMPERATURE
SENSOR
1.8V SPI
LDO
FUSE
BLOCK
ANALOG
MUX
ADC
SERIAL PORT INTERFACE
5
6
4
7
VVA
VVA
DSA
DSA
IN_N
AMP1
AMP2
AMP2
1
RFOUT
GND
DAC
IN_P
AMP1
GND
GND
VDAC
GND
GND
GND
GND
GND
GND
V50AMP1
V33FUSE
V50AMP2
1: DAC_EN
2: AMUX_BG_EN 6: AMP1_EN_x
3: ADC_EN
4: DSA_EN
5: VVA_EN
1
1
7: AMP2_EN_x
1
x = 0 (LOGIC LEVEL = 0) , 1 (LOGIC LEVEL = 1) ON TXEN PIN (PIN 37)
Figure 40. Signal Path Enable Block Diagram
Rev. B | Page 16 of 38
Data Sheet
ADL6317
(REGISTER 0x104, BITS[ 3:0], REGISTER 0x103, BITS[7:0]) = VVA_ATTEN, BITS[11:0]
DAC
00
10
VVA_CTRL
VVA_ANALOG
PIN 30
AMUX_2_SEL = REGISTER 0x120, BIT 3
PTAT
VVA_SRC = REGISTER 0x105, BITS[1:0]
0
1
AD_COUT, BITS[7:0]
ADC
000
001
002
ADC INPUT
ADC CLOCK
ADC INPUT
0
1
MUXOUT
AMUX_3_SEL = REGISTER 0x120, BITS[6:4]
PIN 32
2
3
1.8V LDO OUTPUT
3.3V LDO OUTPUT
POWER-UP DEFAULTS IN GRAY
AMUX_1_SEL = REGISTER 0x120, BITS[2:0]
Figure 41. Auxiliary Mux Block Diagram
Table 12. Auxiliary Mux Programming Guide
Bit Name
Register Address
Setting
Description
AMUX_3_SEL
Register 0x120, Bits[6:4]
ADC input, VVA_CTRL, and ADC clock selection on mux. VVA_CTRL is the
internal control voltage signal to control VVA attenuation.
000
001
010
011
100
101
110
111
VVA_CTRL.
ADC input.
ADC clock.
Not used.
Not used.
Not used.
Not used.
Not used.
AMUX_2_SEL
AMUX_1_SEL
Register 0x120, Bit 3
ADC input selection.
PTAT to ADC input.
VVA_CTRL to ADC input.
Select mux output.
PTAT.
Output of AMUX_3_SEL.
1.8 V LDO output.
3.3 V LDO output.
GND.
0
1
Register 0x120, Bits[2:0]
000
001
010
011
100
101
110
111
GND.
Not used.
Not used.
Rev. B | Page 17 of 38
ADL6317
Data Sheet
Register 0x000 to Register 0x00B. The ADL6317 always accepts
writes for these registers regardless of the six MSBs of the
address.
SERIAL PORT INTERFACE (SPI)
The SPI of the ADL6317 allows the user to configure the device
for specific functions or operations via a 4-wire SPI port. This
interface provides users with added flexibility and customization.
The serial port interface consists of four control lines: SCLK, SDI,
The ADL6317 only accepts reads for addresses where the six
MSBs are equal to the chip ID, including Register 0x000 to
Register 0x00B.
CS
SDO, and . The timing requirements for the SPI port are
shown in Table 3.
Figure 42 shows how to configure the chip ID and the CS5 and
CS4 pins to share a 4-wire SPI. The CS5 and CS4 settings are
shown in gray in Figure 42.
The ADL6317 protocol consists of a read/write bit, six chip select
ID bits, and nine register address bits, followed by eight data bits.
Both the address and data fields are organized with the MSB
first and end with the LSB by default.
4-WIRE SPI
CS, SDI, SDO, SCLK
The ADL6317 input logic level for the write cycle is with a 1.8 V
logic level (see the digital logic parameter in Table 2).
ADL6317
DEVICE 2
CHIP ID = 100000
ADL6317
DEVICE 0
CHIP ID = 000000
CS5 PIN
CS4 PIN
CS5 PIN
CS4 PIN
On a read cycle, the SDO is configurable for 1.8 V (default) or
3.3 V output levels by setting SPI_1P8_3P3_CTRL bit
(Register 0x121, Bit 4).
1.8V
ADL6317
DEVICE 3
CHIP ID = 110000
ADL6317
DEVICE 1
CHIP ID = 010000
Multiple Chip Operation to Share SPI Bus
Multiple ADL6317 devices, up to four, can be addressed using
1.8V
CS5 PIN
CS4 PIN
CS5 PIN
1.8V
CS4 PIN
CS
1.8V
the same 4-wire SPI, which means no extra
line for each
device. For this capability, the chip ID bits of the ADL6317 are
reserved as the chip ID (see the SPI interface port as shown in
Figure 2).
Figure 42. Multiple Chip Configuration to Share SPI Bus
The ADL6317 ignores any writes to addresses where the six
MSBs are not equal to the chip ID, with the exception of
Rev. B | Page 18 of 38
Data Sheet
ADL6317
DEVICE SETUP
The recommended sequence of steps to set up the ADL6317 is
as follows:
3. Set up the operating mode. See Table 16 to Table 19.
a. Set the attenuation on the DSA.
b. Enable or disable the amplifiers.
c. Set the amplifier reference currents.
d. Set the amplifier for linearity optimization.
e. Measure the internal temperature.
1. Set up the SPI interface. See Table 13.
2. Set up the common parameters, including auxiliary mux
control. See Table 14 and Table 15.
Table 13. SPI Interface Setup
Address
Setting
Notes
0x000
0x99
Soft reset, MSB first, SDO active (4-wire SPI)
0x001
0x00A
0x00
0x00
Single instruction, master/slave readback, soft reset, and master/slave transfer
Scratch pad
Table 14. Signal Path Trim
Addres
s
Setting Description
0x100
0x101
0x106
0x105
0x104
0x103
0xFF
0x01
0x00
0x00
0x0F
0xFF
Enable the DAC, auxiliary mux band gap, ADC, bias generator, DSA, and VVA
Enable IP3 optimization and 3.3 V LDO regulator
Disable the bias current, IBIAS, via the EN_IBIASGEN_RESISTOR bit (default setting)
VVA control source from DAC
Attenuation of VVA at minimum attenuation, highest four bits of 12-bit word
Attenuation of VVA at minimum attenuation, lowest eight bits of 12-bit word
Table 15. Auxiliary Mux Control
Address
Setting
Description
0x120
0x121
0x00
0x00
PTAT to ADC input, PTAT on mux output
Set SPI SDO voltage to 1.8 V
Table 16. Power-Down Mode Setup, TXEN = Logic Level 0
Address
0x102
0x107
0x108
0x109
0x10A
Setting
Description
0x1F
0x80
0x80
0x80
15.5 dB attenuation on DSA
Set Amplifier 1 reference current, IREF (TRM_AMP1_IREF_0), for low power mode
Disable Amplifier 1
Set Amplifier 2 IREF (TRM_AMP2_IREF_0) for low power mode
Disable Amplifier 2
0x80
Table 17. Normal Operating Mode Setup, TXEN = Logic Level 1
Address
0x112
0x117
0x118
0x119
0x11A
Setting
Description
0x00
0x82
0x81
0x82
0 dB attenuation on DSA
Set Amplifier 1 IREF (TRM_AMP1_IREF_1)
Enable Amplifier 1
Set Amplifier 2 IREF (TRM_AMP2_IREF_1)
Enable Amplifier 2
0x81
Table 18. Linearity Optimization
Address
Setting
Description
0x10B
0x11B
0x02
0x02
Set the TRM_AMP2_CB bit
Set the TRM_AMP2_IP3 bit
Rev. B | Page 19 of 38
ADL6317
Data Sheet
Table 19. Internal Temperature Measurement from ADC Conversion
Address Setting
Description
0x000
0x100
0x127
0x120
0x00A
0x00A
0x00A
0x00A
0x00A
0x129
0x18
0xFF
0x20
0x00
0xCC
0xCC
0xCC
0xCC
0xCC
Make SDO active
Enable ADC
Enable ADC clock divider and set ADC clock frequency
PTAT to ADC input, PTAT on mux output
Register dummy write
Register dummy write
Register dummy write
Register dummy write
Register dummy write
Not applicable Read temperature from ADC
Rev. B | Page 20 of 38
Data Sheet
ADL6317
APPLICATIONS INFORMATION
LINEARITY OPTIMIZATION
PERFORMANCE AND POWER OPTIMIZATION
The linearity in the ADL6317 can be optimized through
the TRM_AMP2_IP3 (Register 0x11B, Bits[1:0]) and
TRM_AMP2_CB (Register 0x10B, Bits[1:0]) settings. Set the
IP3_OFF bit (Register 0x101, Bit 1) 0x00 for OIP3
optimization. The TRM_AMP2_IP3 bits control the switches in
the second amplifier that enables optimal third-order distortion
cancellation and optimal OIP3. The TRM_AMP2_CB bits
control the common base bias current on the transistor and
allows additional linearity optimization.
The ADL6317 provides another level of control to optimize
power or performance. In applications where performance is
critical, the ADL6317 offers performance optimization at the
expense of power consumption. However, if low power is the
priority, the ADL6317 offers tuning options in the amplifier
blocks of the chip to further reduce power consumption.
Table 20 shows that the potential power optimization vs.
performance can fine tune the reference current on RF
amplifier settings.
45
ADJACENT AND ALTERNATE CHANNEL POWER
RATIOS ON LTE OPERATION
TRM_AMP2_IP3 = 0
TRM_AMP2_IP3 = 1
TRM_AMP2_IP3 = 2
TRM_AMP2_IP3 = 3
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
Figure 44 shows the adjacent and alternate channel power
ratios (CPR) for the ADL6317 using 5 MHz single-carrier LTE.
The adjacent CPR is −70.4 dB and the alternative CPR is
−72.9 dB at an RF of 1850 MHz. The adjacent and alternate CPR
performance varies over output power. On the ADL6317, the
output power can be varied by adjusting the input power, the
VVA attenuation, or the DSA attenuation. Figure 45 to Figure 47
show the adjacent and alternate CPR performance vs. output
power for the different methods of controlling the ADL6317.
As shown in Figure 45, the optimum adjacent and alternate
CPR can be achievable at an output power of +8 dBm, which
corresponds to an input power of −24.6 dBm driving the ADL6317
where the internal VVA is set to 0 dB, and the DSA is set to
0 dB attenuation. Figure 46 and Figure 47 show adjacent and
alternate CPR performance vs. output power that is adjusted by
VVA attenuation and by DSA attenuation, respectively, with
−17.2 dBm of input power. Figure 45 to Figure 47 show below
−65 dB adjacent and alternate CPR performance at below
+10 dBm output power, and there is gradual degradation above
+10 dBm from the contribution to the adjacent and alternate
CPR performance of the second stage RF amplifier. When
fixing the VVA attenuation and sweeping the DSA, the
adjacent and alternate CPR performance remains constant
below 6 dBm output power (see Figure 47).
FREQUENCY (MHz)
Figure 43. OIP3 vs. RF Frequency for Various TRM_AMP2_IP3 Settings,
TRM_AMP2_CB = 0x02, TRM_AMP1_IREF_x and TRM_AMP2_IREF_x = 0x02
Figure 43 shows that the OIP3 is optimizable across the
TRM_AMP2_IP3 settings.
Figure 43 shows better than 1.5 dB OIP3 improvement that
correlates to 3 dB improvement on IMD3 performance at
below 1.9 GHz through linearity optimization.
Table 20. Power Optimization vs. Performance at 1850 MHz, VVA Attenuation= 0 dB, DSA Attenuation = 0 dB, TRM_AMP2_IP3 = 0x02
TRM_AMPx_IREF_1 Setting (Decimal),
Register 0x117 and Register 0x119, Bits[3:0]
DC Power (W)
Gain (dB)
33.1
33.1
33.1
32.8
OP1dB (dBm)
25.8
25.6
25.1
24.3
OIP3 (dBm)
40.3
40.3
39.2
36.9
NF (dB)
6.6
5.9
5.8
5.8
3
2
1
0
2.36
2.10
1.84
1.55
Rev. B | Page 21 of 38
ADL6317
Data Sheet
–30
–40
–50
–60
–70
–80
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
ADJACENT CPR
ALTERNATE CPR
–90
–2
CENTER 1.85GHz
#RES BW 30kHz
VBW 30kHz
SPAN 24.52MHz
SWEEP 103.9ms
0
2
4
6
8
10
12
14
16
18
OUTPUT POWER (dBm)
Figure 44. LTE Carrier, Adjacent and Alternate CPR at 1850 MHz,
VVA Attenuation = 0 dB, DSA Attenuation = 11 dB, PIN = −17.2 dBm
Figure 47. Adjacent and Alternate Channel Power Ratio vs. Output Power
(POUT) by DSA Attenuation at 1850 MHz, LTE TM1.1, PIN = −17.2 dBm,
VVA Attenuation = 0 dB
–30
ADJACENT CPR
ALTERNATE CPR
LAYOUT
–40
–50
–60
–70
–80
Solder the exposed pad on the underside of the ADL6317 to a
low thermal and electrical impedance ground plane. This pad is
typically soldered to an exposed opening in the solder mask on
the evaluation board. Notice the use of 19 via holes on the exposed
pad of the ADL6317-EVALZ evaluation board. Connect these
ground vias to all other ground layers on the evaluation board to
maximize heat dissipation from the device package. For more
information on the ADL6317-EVALZ evaluation board,
contact Analog Devices, Inc.
–90
–6 –4 –2
Ensure that the decoupling capacitors are located close to the
supply voltage pins.
0
2
4
6
8
10 12 14 16 18
OUTPUT POWER (dBm)
Figure 45. Adjacent and Alternate Channel Power Ratio vs. Output Power
(POUT) by PIN at 1850 MHz, LTE Test Model 1.1 (TM1.1), VVA Attenuation = 0 dB,
DSA Attenuation = 0 dB
–30
ADJACENT CPR
ALTERNATE CPR
–40
–50
–60
–70
–80
Figure 48. Evaluation Board Layout for the ADL6317-EVALZ
–90
–6 –4 –2
0
2
4
6
8
10 12 14 16 18
OUTPUT POWER (dBm)
Figure 46. Adjacent and Alternate Channel Power Ratio vs. Output Power
(POUT) by VVA Attenuation at 1850 MHz, LTE TM1.1, PIN = −17.2 dBm, DSA
Attenuation = 0 dB
Rev. B | Page 22 of 38
Data Sheet
ADL6317
CHARACTERIZATION SETUPS
The primary setup used to characterize the ADL6317 is shown in
Figure 49. The setup measures gain, HD2, HD3, OIP2, and OIP3.
ROHDE & SCHWARZ
ROHDE & SCHWARZ
SMA100A SIGNAL GENERATOR
SMA100A SIGNAL GENERATOR
COMBINER
KEITHLEY S46
SWITCH SYSTEM
PC CONTROLLER
RFIN
3dB
4-WIRE SPI PROGRAMMING
BOARD SUPPLY
ADL6317
EVALUATION BOARD
AUXILIARY
MUX
3dB
RFOUT
AGILENT PXA N9030B
SPECTRUM ANALYZER
Figure 49. General Characterization Setup
Rev. B | Page 23 of 38
ADL6317
Data Sheet
REGISTER SUMMARY
Table 21. Register Summary
Reg
Name
Bits
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
RW
0x000
ADI_SPI_
CONFIG
[7:0]
SOFTRESET_
LSB_
FIRST_
ENDIAN_
SDOACTIVE_
SDOACTIVE
ENDIAN
LSB_
FIRST
SOFTRESET
0x00
R/W
0x001
REG_0X0001
[7:0]
SINGLE_
INSTRUCTION
CSB_
STALL
MASTER_
SLAVE_RB
RESERVED
SOFT_RESET
MASTER_
SLAVE_
0x00
R/W
TRANSFER
0x003
0x004
CHIPTYPE
[7:0]
[7:0]
CHIPTYPE
0x00
0x00
R
R
PRODUCT_
ID_L
PRODUCT_ID[7:0]
0x005
PRODUCT_
ID_H
[7:0]
PRODUCT_ID[15:8]
0x00
R
0x00A
0x00B
0x010
SCRATCHPAD
SPI_REV
[7:0]
[7:0]
[7:0]
SCRATCHPAD
SPI_REV
0x00
0x00
0x00
R/W
R
VARIANT_
FEOL
FEOL
SIF
VARIANT
BEOL
R
0x011
0x012
0x013
0x100
BEOL_SIF
[7:0]
[7:0]
[7:0]
[7:0]
0x01
0x00
0x00
0x40
R
SPARE_012
SPARE_013
SIG_PATH0_0
SPARE_012
SPARE_013
R
R
DAC_EN
AMUX_
BG_EN
ADC_EN
EN_IBIASGEN
DSA_EN
VVA_EN
RESERVED
LDO33_EN
R/W
0x101
0x102
0x103
0x104
0x105
0x106
SIG_PATH1_0
SIG_PATH2_0
SIG_PATH3_0
SIG_PATH4_0
SIG_PATH5_0
SIG_PATH6_0
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
RESERVED
IP3_OFF
0x01
0x3F
0x00
0x00
0x00
0x00
R/W
R/W
R/W
R/W
R/W
R/W
RESERVED
DSA_ATTEN_0
VVA_ATTEN[7:0]
RESERVED
VVA_ATTEN[11:8]
RESERVED
VVA_SRC
RESERVED
EN_IBIASGEN_
RESISTOR
0x107
0x108
0x109
0x10A
SIG_PATH7_0
SIG_PATH8_0
SIG_PATH9_0
SIG_PATHA_0
[7:0]
[7:0]
[7:0]
[7:0]
BYPASS_TRM_
AMP1_IREF_0
RESERVED
RESERVED
TRM_AMP1_
IREF_SEL_0
TRM_AMP1_IREF_0
TRM_AMP2_IREF_0
0x00
0x00
0x00
0x00
R/W
R/W
R/W
R/W
BYPASS_TRM_
AMP1_EN_0
RESERVED
AMP1_EN_0
BYPASS_TRM_
AMP2_IREF_0
TRM_AMP2_
IREF_SEL_0
BYPASS_TRM_
AMP2_EN_0
RESERVED
AMP2_EN_0
0x10B
0x112
0x117
SIG_PATHB_0
SIG_PATH2_1
SIG_PATH7_1
[7:0]
[7:0]
[7:0]
SPARE_10B
TRM_AMP2_CB
0x00
0x20
0x00
R/W
R/W
R/W
RESERVED
DSA_ATTEN_1
BYPASS_TRM_
AMP1_IREF_1
RESERVED
TRM_AMP1_
IREF_SEL_1
TRM_AMP1_IREF_1
0x118
0x119
0x11A
SIG_PATH8_1
SIG_PATH9_1
SIG_PATHA_1
[7:0]
[7:0]
[7:0]
BYPASS_TRM_
AMP1_EN_1
RESERVED
AMP1_EN_1
AMP2_EN_1
0x00
0x00
0x00
R/W
R/W
R/W
BYPASS_TRM_
AMP2_IREF_1
RESERVED
TRM_AMP2_
IREF_SEL_1
TRM_AMP2_IREF_1
BYPASS_TRM_
AMP2_EN_1
RESERVED
0x11B
0x120
SIG_PATHB_1
AMUX_SEL
[7:0]
[7:0]
SPARE_11B
AMUX_3_SEL
TRM_AMP2_IP3
AMUX_1_SEL
0x00
0x20
R/W
R/W
RESERVED
AMUX_2_
SEL
0x121
0x127
MULTI_FUNC_
CTRL_0111
[7:0]
[7:0]
RESERVED
RESERVED
SPI_1P8_
3P3_CTRL
AMUX_EX
0x00
0x00
R/W
R/W
ADC_
CONTROL_
ADC_CLOCK_
DIV_EN
ADC_MUX_
SEL
RESERVED
ADC_CLK_FREQ
ADC_EOC
0x128
0x129
0x146
ADC_EOC
ADC_OUT
[7:0]
[7:0]
[7:0]
RESERVED
0x00
0x00
0x00
R
R
R
TEMP_ADC_OUT
VVA_ATTEN_RDBK[7:0]
GENERIC_
READBACK_2
0x147
0x148
GENERIC_
READBACK_3
[7:0]
[7:0]
RESERVED
VVA_ATTEN_RDBK[11:8]
0x00
0x00
R
R
GENERIC_
RESERVED
DSA_ATTEN_RDBK
READBACK_4
Rev. B | Page 24 of 38
Data Sheet
ADL6317
REGISTER DETAILS
Address: 0x000, Reset: 0x00, Name: ADI_SPI_CONFIG
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7] SOFTRESET_ (R/W)
Soft Reset
[0] SOFTRESET (R/W)
Soft Reset
[6] LSB_FIRST_ (R/W)
LSB First
[1] LSB_FIRST (R/W)
LSB First
[5] ENDIAN_ (R/W)
Endian
[2] ENDIAN (R/W)
Endian
[4] SDOACTIVE_ (R/W)
SDO Active
[3] SDOACTIVE (R/W)
SDO Active
Table 22. Bit Descriptions for ADI_SPI_CONFIG
Bits
Bit Name
Description
Reset
Access
7
SOFTRESET_
Soft Reset.
0x0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0: Reset not asserted.
1: Reset asserted.
LSB First.
0: MSB first.
1: LSB first.
6
5
4
3
2
1
0
LSB_FIRST_
ENDIAN_
0x0
0x0
0x0
0x0
0x0
0x0
0x0
Endian.
0: Little endian.
1: Big endian.
SDO Active.
0: SDO inactive.
1: SDO active.
SDO Active.
0: SDO inactive.
1: SDO active.
Endian.
0: Little endian.
1: Big endian.
LSB First.
SDOACTIVE_
SDOACTIVE
ENDIAN
LSB_FIRST
SOFTRESET
0: MSB first.
1: LSB first.
Soft Reset.
0: Reset not asserted.
1: Reset asserted.
Rev. B | Page 25 of 38
ADL6317
Data Sheet
Address: 0x001, Reset: 0x00, Name: REG_0X0001
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7] SINGLE_INSTRUCTION (R/W)
Single Instruction
[0] MASTER_SLAVE_TRANSFER (R/W)
Master Slave Transfer
[6] CSB_STALL (R/W)
CSB Stall
[2:1] SOFT_RESET (R/W)
Soft Reset
[5] MASTER_SLAVE_RB (R/W)
[4:3] RESERVED
Master Slave Readback
Table 23. Bit Descriptions for REG_0X0001
Bits
7
6
Bit Name
SINGLE_INSTRUCTION
CSB_STALL
Description
Single Instruction
CS Stall
Reset
0x0
0x0
0x0
0x0
0x0
0x0
Access
R/W
R/W
R/W
R
5
MASTER_SLAVE_RB
RESERVED
Master Slave Readback
Reserved
[4:3]
[2:1]
0
SOFT_RESET
MASTER_SLAVE_TRANSFER
Soft Reset
Master Slave Transfer
R/W
R/W
Address: 0x003, Reset: 0x00, Name: CHIPTYPE
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:0] CHIPTYPE (R)
Chip Type, Read Only
Table 24. Bit Descriptions for CHIPTYPE
Bits
[7:0]
Bit Name
CHIPTYPE
Description
Chip Type, Read Only
Reset
0x0
Access
R
Address: 0x004, Reset: 0x00, Name: PRODUCT_ID_L
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:0] PRODUCT_ID[7:0] (R)
Product ID Low, Lower 8 Bits
Table 25. Bit Descriptions for PRODUCT_ID_L
Bits
[7:0]
Bit Name
PRODUCT_ID[7:0]
Description
Product ID Low, Lower 8 Bits
Reset
0x0
Access
R
Address: 0x005, Reset: 0x00, Name: PRODUCT_ID_H
7
6
5
4
3
2
1
0
0
0
0
0
0
0 0 0
[7:0] PRODUCT_ID[15:8] (R)
Product ID High, Higher 8 Bits
Table 26. Bit Descriptions for PRODUCT_ID_H
Bits Bit Name Description
[7:0] PRODUCT_ID[15:8] Product ID High, Higher 8 Bits
Reset
0x0
Access
R
Rev. B | Page 26 of 38
Data Sheet
ADL6317
Address: 0x00A, Reset: 0x00, Name: SCRATCHPAD
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:0] SCRATCHPAD (R/W)
Scratchpad. Used by Software to test read
and write
Table 27. Bit Descriptions for SCRATCHPAD
Bits
Bit Name
Description
Reset
Access
[7:0]
SCRATCHPAD
Scratchpad. Used by Software to test read and write.
0x0
R/W
Address: 0x00B, Reset: 0x00, Name: SPI_REV
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:0] SPI_REV (R)
SPI Register Map Revision
Table 28. Bit Descriptions for SPI_REV
Bits
[7:0]
Bit Name
SPI_REV
Description
SPI Register Map Revision
Reset
0x0
Access
R
Address: 0x010, Reset: 0x00, Name: VARIANT_FEOL
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:4] FEOL (R)
Front end of line (FEOL)
[3:0] VARIANT (R)
Variant
Table 29. Bit Descriptions for VARIANT_FEOL
Bits
[7:4]
[3:0]
Bit Name
FEOL
Description
Front end of line (FEOL)
Variant
Reset
0x0
Access
R
R
VARIANT
0x0
Address: 0x011, Reset: 0x01, Name: BEOL_SIF
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
1
[7:4] SIF (R)
Serial Interface Version
[3:0] BEOL (R)
Back end of line (BEOL) Version
Table 30. Bit Descriptions for BEOL_SIF
Bits
[7:4]
[3:0]
Bit Name
SIF
BEOL
Description
Serial Interface Version
Back end of line (BEOL) Version
Reset
0x0
0x1
Access
R
R
Address: 0x012, Reset: 0x00, Name: SPARE_0012
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:0] SPARE_012 (R)
Spare Register 0x012
Table 31. Bit Descriptions for SPARE_0012
Bits
[7:0]
Bit Name
SPARE_012
Description
Spare Register 0x012
Reset
0x0
Access
R
Rev. B | Page 27 of 38
ADL6317
Data Sheet
Address: 0x013, Reset: 0x00, Name: SPARE_013
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:0] SPARE_013 (R)
Spare Register 0x013
Table 32. Bit Descriptions for SPARE_013
Bits
Bit Name
Description
Reset
Access
[7:0]
SPARE_013
Spare Register 0x013
0x0
R
Address: 0x100, Reset: 0x40, Name: SIG_PATH0_0
7
6
5
4
3
2
1
0
0
1
0
0
0
0
0
0
[7] DAC_EN (R/W)
DAC Enable
[1:0] RESERVED
[2] VVA_EN (R/W)
[6] AMUX_BG_EN (R/W)
VVA Enable
Auxiliary Mux Bandgap Enable
[3] DSA_EN (R/W)
[5] ADC_EN (R/W)
DSA Enable
ADC Enable
[4] EN_IBIASGEN (R/W)
Enable Bias Generator
Table 33. Bit Descriptions for SIG_PATH0_0
Bits
7
Bit Name
DAC_EN
Description
DAC Enable.
Reset
0x0
Access
R/W
0: Disable DAC.
1: Enable DAC.
6
AMUX_BG_EN
ADC_EN
Auxiliary Mux Band Gap Enable.
0x1
0x0
0x0
0x0
0x0
0x0
R/W
R/W
R/W
R/W
R/W
R
0: Disable auxiliary mux band gap.
1: Enable auxiliary mux band gap.
ADC Enable.
0: Disable ADC.
1: Enable ADC.
Enable Bias Generator.
0: Disable bias generator.
1: Enable bias generator.
DSA Enable.
0: Disable DSA.
1: Enable DSA.
5
4
EN_IBIASGEN
DSA_EN
3
2
VVA_EN
VVA Enable.
0: Disable VVA.
1: Enable VVA.
Reserved.
[1:0]
RESERVED
Rev. B | Page 28 of 38
Data Sheet
ADL6317
Address: 0x101, Reset: 0x01, Name: SIG_PATH1_0
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
1
[7:2] RESERVED
[1] IP3_OFF (R/W)
[0] LDO33_EN (R/W)
3.3V LDO Enable
Turn off linearization optimization
functionality for IP3 optimization
Table 34. Bit Descriptions for SIG_PATH1_0
Bits
[7:2]
1
Bit Name
RESERVED
IP3_OFF
Description
Reserved.
Reset
0x0
0x0
Access
R
R/W
Turn off linearization optimization functionality for
IP3 optimization.
0: Turn on linearization optimization functionality.
1: Turn off linearization optimization functionality.
3.3 V LDO Enable.
0
LDO33_EN
0x1
R/W
0: Disable 3.3 V LDO.
1: Enable 3.3 V LDO.
Address: 0x102, Reset: 0x3F, Name: SIG_PATH2_0
7
6
5
4
3
2
1
0
0
0
1
1
1
1
1
1
[7:5] RESERVED
[4:0] DSA_ATTEN_0 (R/W)
DSA Attenuator Setting 0
Table 35. Bit Descriptions for SIG_PATH2_0
Bits
[7:5]
[4:0]
Bit Name
RESERVED
DSA_ATTEN_0
Description
Reserved.
DSA Attenuator Setting 0.
0: 0 dB.
Reset
0x1
0x1F
Access
R
R/W
1: 0.5 dB.
10: 1 dB.
11: 1.5 dB.
100: 2 dB.
101: 2.5 dB.
110: 3 dB.
111: 3.5 dB.
1000: 4 dB.
1001: 4.5 dB.
1010: 5 dB.
1011: 5.5 dB.
1100: 6 dB.
1101: 6.5 dB.
1110: 7 dB.
1111: 7.5 dB.
10000: 8 dB.
10001: 8.5 dB.
10010: 9 dB.
10011: 9.5 dB.
10100: 10 dB.
10101: 10.5 dB.
10110: 11 dB.
10111: 11.5 dB.
Rev. B | Page 29 of 38
ADL6317
Data Sheet
Bits
Bit Name
Description
Reset
Access
11000: 12 dB.
11001: 12.5 dB.
11010: 13 dB.
11011: 13.5 dB.
11100: 14 dB.
11101: 14.5 dB.
11110: 15 dB.
11111: 15.5 dB.
Address: 0x103, Reset: 0x00, Name: SIG_PATH3_0
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:0] VVA_ATTEN[7:0] (R/W)
VVA Attenuation DAC Setting
Table 36. Bit Descriptions for SIG_PATH3_0
Bits
Bit Name
Description
Reset
Access
[7:0]
VVA_ATTEN[7:0]
VVA Attenuation DAC Setting
0x0
R/W
Address: 0x104, Reset: 0x00, Name: SIG_PATH4_0
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:4] RESERVED
[3:0] VVA_ATTEN[11:8] (R/W)
VVA Attenuation DAC Setting
Table 37. Bit Descriptions for SIG_PATH4_0
Bits
[7:4]
[3:0]
Bit Name
RESERVED
VVA_ATTEN[11:8]
Description
Reserved
VVA Attenuation DAC Setting
Reset
0x0
0x0
Access
R
R/W
Address: 0x105, Reset: 0x00, Name: SIG_PATH5_0
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:2] RESERVED
[1:0] VVA_SRC (R/W)
VVA Voltage Source
Table 38. Bit Descriptions for SIG_PATH5_0
Bits
[7:2]
[1:0]
Bit Name
RESERVED
VVA_SRC
Description
Reserved
VVA Voltage Source
00: DAC to VVA
Reset
0x0
0x0
Access
R
R/W
10: Pin 30 to VVA
Rev. B | Page 30 of 38
Data Sheet
ADL6317
Address: 0x106, Reset: 0x00, Name: SIG_PATH6_0
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:1] RESERVED
[0] EN_IBIASGEN_RESISTOR (R/W)
Set Bias Generator to Use Resistor
Reference
Table 39. Bit Descriptions for SIG_PATH6_0
Bits
[7:1]
0
Bit Name
RESERVED
EN_IBIASGEN_RESISTOR
Description
Reserved
Set Bias Generator to Use Resistor Reference
0: Disable IBIAS
Reset
0x0
0x0
Access
R
R/W
1: Enable IBIAS
Address: 0x107, Reset: 0x00, Name: SIG_PATH7_0
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7] BYPASS_TRM_AMP1_IREF_0 (R/W)
Bypass Fused Value of TRM_AMP1_IREF_0
[3:0] TRM_AMP1_IREF_0 (R/W)
Amplifier 1 IREF Trim 0
[6:5] RESERVED
[4] TRM_AMP1_IREF_SEL_0 (R/W)
Amplifier 1 IREF Trim Select 0
Table 40. Bit Descriptions for SIG_PATH7_0
Bits
7
[6:5]
4
[3:0]
Bit Name
BYPASS_TRM_AMP1_IREF_0
RESERVED
Description
Bypass Fused Value of TRM_AMP1_IREF_0
Reserved
Reset
0x0
0x0
Access
R/W
R
TRM_AMP1_IREF_SEL_0
TRM_AMP1_IREF_0
Amplifier 1 IREF Trim Select 0
Amplifier 1 IREF Trim 0
0x0
0x0
R/W
R/W
Address: 0x108, Reset: 0x00, Name: SIG_PATH8_0
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7] BYPASS_TRM_AMP1_EN_0 (R/W)
[0] AMP1_EN_0 (R/W)
Bypass Fused Value of AMP1_EN_0
Internal Trim Data
Enable Amplifier 1 (TXEN=0)
[6:1] RESERVED
Table 41. Bit Descriptions for SIG_PATH8_0
Bits
7
[6:1]
0
Bit Name
BYPASS_TRM_AMP1_EN_0
RESERVED
Description
Reset
0x0
0x0
0x0
Access
R/W
R
Bypass Fused Value of AMP1_EN_0 Internal Trim Data
Reserved
Enable Amplifier 1 (TXEN = 0)
AMP1_EN_0
R/W
Rev. B | Page 31 of 38
ADL6317
Data Sheet
Address: 0x109, Reset: 0x00, Name: SIG_PATH9_0
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7] BYPASS_TRM_AMP2_IREF_0 (R/W)
Bypass Fused Value of TRM_AMP2_IREF_0
[3:0] TRM_AMP2_IREF_0 (R/W)
Amplifier 2 IREF Trim 0
[6:5] RESERVED
[4] TRM_AMP2_IREF_SEL_0 (R/W)
Amplifier 2 IREF Trim Select 0
Table 42. Bit Descriptions for SIG_PATH9_0
Bits
7
Bit Name
BYPASS_TRM_AMP2_IREF_0
RESERVED
TRM_AMP2_IREF_SEL_0
TRM_AMP2_IREF_0
Description
Bypass Fused Value of TRM_AMP2_IREF_0
Reserved
Amplifier 2 IREF Trim Select 0
Amplifier 2 IREF Trim 0
Reset
0x0
Access
R/W
R
R/W
R/W
[6:5]
4
[3:0]
0x0
0x0
0x0
Address: 0x10A, Reset: 0x00, Name: SIG_PATHA_0
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7] BYPASS_TRM_AMP2_EN_0 (R/W)
Bypass Fused Value of AMP2_EN_0
Internal Trim Data
[0] AMP2_EN_0 (R/W)
Enable Amplifier 2 (TXEN=0)
[6:1] RESERVED
Table 43. Bit Descriptions for SIG_PATHA_0
Bits
7
[6:1]
0
Bit Name
BYPASS_TRM_AMP2_EN_0
RESERVED
Description
Reset
Access
R/W
R
Bypass Fused Value of AMP2_EN_0 Internal Trim Data
Reserved
Enable Amplifier 2 (TXEN = 0)
0x0
0x0
0x0
AMP2_EN_0
R/W
Address: 0x10B, Reset: 0x00, Name: SIG_PATHB_0
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:2] SPARE_10B (R/W)
[1:0] TRM_AMP2_CB (R/W)
Spare Register 0x10B
Amplifier 2 Common Base Trim
Table 44. Bit Descriptions for SIG_PATHB_0
Bits
[7:2]
[1:0]
Bit Name
SPARE_10B
TRM_AMP2_CB
Description
Spare Register 0x10B
Amplifier 2 Common Base Trim
Reset
0x0
0x0
Access
R/W
R/W
Rev. B | Page 32 of 38
Data Sheet
ADL6317
Address: 0x112, Reset: 0x20, Name: SIG_PATH2_1
7
6
5
4
3
2
1
0
0
0
1
0
0
0
0
0
[7:5] RESERVED
[4:0] DSA_ATTEN_1 (R/W)
DSA Attenuator Setting 1
Table 45. Bit Descriptions for SIG_PATH2_1
Bits
[7:5]
[4:0]
Bit Name
RESERVED
DSA_ATTEN_1
Description
Reserved.
DSA Attenuator Setting 1.
0: 0 dB.
Reset
0x1
0x0
Access
R
R/W
1: 0.5 dB.
10: 1 dB.
11: 1.5 dB.
100: 2 dB.
101: 2.5 dB.
110: 3 dB.
111: 3.5 dB.
1000: 4 dB.
1001: 4.5 dB.
1010: 5 dB.
1011: 5.5 dB.
1100: 6 dB.
1101: 6.5 dB.
1110: 7 dB.
1111: 7.5 dB.
10000: 8 dB.
10001: 8.5 dB.
10010: 9 dB.
10011: 9.5 dB.
10100: 10 dB.
10101: 10.5 dB.
10110: 11 dB.
10111: 11.5 dB.
11000: 12 dB.
11001: 12.5 dB.
11010: 13 dB.
11011: 13.5 dB.
11100: 14 dB.
11101: 14.5 dB.
11110: 15 dB.
11111: 15.5 dB.
Rev. B | Page 33 of 38
ADL6317
Data Sheet
Address: 0x117, Reset: 0x00, Name: SIG_PATH7_1
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7] BYPASS_TRM_AMP1_IREF_1 (R/W)
Bypass Fused Value of TRM_AMP1_IREF_1
[3:0] TRM_AMP1_IREF_1 (R/W)
Amplifier 1 IREF Trim 1
[6:5] RESERVED
[4] TRM_AMP1_IREF_SEL_1 (R/W)
Amplifier 1 IREF Trim Select 1
Table 46. Bit Descriptions for SIG_PATH7_1
Bits
7
Bit Name
BYPASS_TRM_AMP1_IREF_1
RESERVED
TRM_AMP1_IREF_SEL_1
TRM_AMP1_IREF_1
Description
Bypass Fused Value of TRM_AMP1_IREF_1
Reserved
Amplifier 1 IREF Trim Select 1
Amplifier 1 IREF Trim 1
Reset
0x0
Access
R/W
R
R/W
R/W
[6:5]
4
[3:0]
0x0
0x0
0x0
Address: 0x118, Reset: 0x00, Name: SIG_PATH8_1
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7] BYPASS_TRM_AMP1_EN_1 (R/W)
[0] AMP1_EN_1 (R/W)
Bypass Fused Value of AMP1_EN_1
Internal Trim Data
Enable Amplifier 1 (TXEN=1)
[6:1] RESERVED
Table 47. Bit Descriptions for SIG_PATH8_1
Bits
7
[6:1]
0
Bit Name
BYPASS_TRM_AMP1_EN_1
RESERVED
Description
Reset
0x0
0x0
Access
R/W
R
Bypass Fused Value of AMP1_EN_1 Internal Trim Data
Reserved
Enable Amplifier 1 (TXEN = 1)
AMP1_EN_1
0x0
R/W
Address: 0x119, Reset: 0x00, Name: SIG_PATH9_1
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7] BYPASS_TRM_AMP2_IREF_1 (R/W)
Bypass Fused Value of TRM_AMP2_IREF_1
[3:0] TRM_AMP2_IREF_1 (R/W)
Amplifier 2 IREF Trim 1
[6:5] RESERVED
[4] TRM_AMP2_IREF_SEL_1 (R/W)
Amplifier 2 IREF Trim Select 1
Table 48. Bit Descriptions for SIG_PATH9_1
Bits
7
Bit Name
BYPASS_TRM_AMP2_IREF_1
RESERVED
TRM_AMP2_IREF_SEL_1
TRM_AMP2_IREF_1
Description
Bypass Fused Value of TRM_AMP2_IREF_1
Reserved
Amplifier 2 IREF Trim Select 1
Amplifier 2 IREF Trim 1
Reset
0x0
Access
R/W
R
R/W
R/W
[6:5]
4
[3:0]
0x0
0x0
0x0
Address: 0x11A, Reset: 0x00, Name: SIG_PATHA_1
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7] BYPASS_TRM_AMP2_EN_1 (R/W)
Bypass Fused Value of AMP2_EN_1
Internal Trim Data
[0] AMP2_EN_1 (R/W)
Enable Amplifier 2 (TXEN=1)
[6:1] RESERVED
Table 49. Bit Descriptions for SIG_PATHA_1
Bits
7
[6:1]
0
Bit Name
BYPASS_TRM_AMP2_EN_1
RESERVED
Description
Reset
0x0
0x0
Access
R/W
R
Bypass Fused Value of AMP2_EN_1 Internal Trim Data
Reserved
AMP2_EN_1
Enable Amplifier 2 (TXEN = 1)
Rev. B | Page 34 of 38
0x0
R/W
Data Sheet
ADL6317
Address: 0x11B, Reset: 0x00, Name: SIG_PATHB_1
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:2] SPARE_11B (R/W)
Spare Register 0x11B
[1:0] TRM_AMP2_IP3 (R/W)
Amplifier 2 IP3 Trim
Table 50. Bit Descriptions for SIG_PATHB_1
Bits
[7:2]
[1:0]
Bit Name
SPARE_11B
TRM_AMP2_IP3
Description
Reset
0x0
0x0
Access
R/W
R/W
Spare Register 0x11B
Amplifier 2 IP3 Trim
00: Trim Mode 0
01: Trim Mode 1
10: Trim Mode 2
11: Trim Mode 3
Address: 0x120, Reset: 0x20, Name: AMUX_SEL
7
6
5
4
3
2
1
0
0
0
1
0
0
0
0
0
[7] RESERVED
[2:0] AMUX_1_SEL (R/W)
Select Mux Output
[6:4] AMUX_3_SEL (R/W)
ADC Input, VVA_CTRL, ADC Clock Selection
on MUX
[3] AMUX_2_SEL (R/W)
ADC Input Selection
Table 51. Bit Descriptions for AMUX_SEL
Bits
7
[6:4]
Bit Name
RESERVED
AMUX_3_SEL
Description
Reserved.
Reset
0x0
0x2
Access
R/W
R/W
ADC Input, VVA_CTRL, ADC Clock Selection on Mux.
000: VVA_CTRL.
001: ADC input.
010: ADC clock.
011 to 111: Not used.
ADC Input Selection.
0: PTAT to ADC input.
1: VVA_CTRL to ADC input.
Select Mux Output.
000: PTAT.
3
AMUX_2_SEL
AMUX_1_SEL
0x0
0x0
R/W
R/W
[2:0]
001: Output of AMUX_3_SEL.
010: 1.8 V LDO output.
011: 3.3 V LDO output.
100: GND.
101: GND.
110: Not used.
111: Not used.
Address: 0x121, Reset: 0x00, Name: MULTI_FUNC_CTRL_0111
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:5] RESERVED
[3:0] AMUX_EX (R/W)
Auxiliary Mux External
[4] SPI_1P8_3P3_CTRL (R/W)
SPI Supply Control
Table 52. Bit Descriptions for MULTI_FUNC_CTRL_0111
Bits
[7:5]
4
Bit Name
RESERVED
SPI_1P8_3P3_CTRL
Description
Reserved
SPI Supply Control
0: 1.8 V readback
1: 3.3 V readback
Reset
0x0
0x0
Access
R
R/W
[3:0]
AMUX_EX
Auxiliary Mux External
0x0
R/W
Rev. B | Page 35 of 38
ADL6317
Data Sheet
Address: 0x127, Reset: 0x00, Name: ADC_CONTROL
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:6] RESERVED
[2:0] ADC_CLK_FREQ (R/W)
ADC Clock Frequency Division Ratio. Divided
Down Gated Clock
[5] ADC_CLOCK_DIV_EN (R/W)
ADC Clock Divider Enable
[3] RESERVED
[4] ADC_MUX_SEL (R/W)
ADC Clock Source Selection
Table 53. Bit Descriptions for ADC_CONTROL
Bits
[7:6]
5
Bit Name
RESERVED
ADC_CLOCK_DIV_EN
Description
Reserved.
ADC Clock Divider Enable.
Reset
0x0
0x0
Access
R
R/W
0: Disable ADC clock divider.
1: Enable ADC clock divider.
ADC Clock Source Selection.
0: ADC clock from SCLK.
1: Not used.
4
ADC_MUX_SEL
0x0
R/W
3
[2:0]
RESERVED
ADC_CLK_FREQ
Reserved.
0x0
0x0
R
R/W
ADC Clock Frequency Division Ratio. Divided Down Gated Clock.
000: ADC clock at SCLK/2.
001: ADC clock at SCLK/1.
010: ADC clock at SCLK/2.
011: ADC clock at SCLK/4.
Address: 0x128, Reset: 0x00, Name: ADC_EOC
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:1] RESERVED
[0] ADC_EOC (R)
ADC End of Conversion (EOC)
Table 54. Bit Descriptions for ADC_EOC
Bits
[7:1]
0
Bit Name
RESERVED
ADC_EOC
Description
Reserved
ADC End of Conversion (EOC)
Reset
0x0
0x0
Access
R
R
Address: 0x129, Reset: 0x00, Name: ADC_OUT
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:0] TEMP_ADC_OUT (R)
Temperature Sensor Output of Auxiliary MUX
ADC
Table 55. Bit Descriptions for ADC_OUT
Bits
[7:0]
Bit Name
TEMP_ADC_OUT
Description
Temperature Sensor Output of Auxiliary Mux ADC
Reset
0x0
Access
R
Address: 0x146, Reset: 0x00, Name: GENERIC_READBACK_2
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:0] VVA_ATTEN_RDBK[7:0] (R)
VVA Attenuation Setting Readback
Table 56. Bit Descriptions for GENERIC_READBACK_2
Bits
[7:0]
Bit Name
VVA_ATTEN_RDBK[7:0]
Description
VVA Attenuation Setting Readback
Reset
0x0
Access
R
Rev. B | Page 36 of 38
Data Sheet
ADL6317
Address: 0x147, Reset: 0x00, Name: GENERIC_READBACK_3
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:4] RESERVED
[3:0] VVA_ATTEN_RDBK[11:8] (R)
VVA Attenuation Setting Readback
Table 57. Bit Descriptions for GENERIC_READBACK_3
Bits
[7:4]
[3:0]
Bit Name
RESERVED
VVA_ATTEN_RDBK[11:8]
Description
Reserved
VVA Attenuation Setting Readback
Reset
0x0
0x0
Access
R
R
Address: 0x148, Reset: 0x00, Name: GENERIC_READBACK_4
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:6] RESERVED
[5:0] DSA_ATTEN_RDBK (R)
DSA Attenuator Readback
Table 58. Bit Descriptions for GENERIC_READBACK_4
Bits
[7:6]
[5:0]
Bit Name
RESERVED
DSA_ATTEN_RDBK
Description
Reserved
DSA Attenuator Readback
Reset
0x0
0x0
Access
R
R
Rev. B | Page 37 of 38
ADL6317
Data Sheet
OUTLINE DIMENSIONS
10.60
10.50
10.40
8.40 REF
0.20
BSC
0.70
BSC
PIN 1
PIN 1
CORNER AREA
INDICATOR
C0.30 ×0.45°
26
38
25
1
5.60
5.50
5.40
3.50 REF
3.50 BSC
20
6
0.45
0.40
0.35
0.70
BSC
19
7
BOTTOM VIEW
TOP VIEW
SIDE VIEW
0.10
REF
4.15 BSC
0.50
0.45
0.40
8.50 BSC
1.08
0.98
0.88
0.530 REF
0.498
0.448
0.398
FOR PROPER CONNECTION OF
THE EXPOSED PADS, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SEATING
PLANE
SECTION OF THIS DATA SHEET.
Figure 50. 38-Terminal Land Grid Array [LGA]
(CC-38-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature Range2
−40°C to +105°C
Package Description
Package Option
CC-38-1
CC-38-1
ADL6317ACCZ
ADL6317ACCZ-R7
ADL6317-EVALZ
38-Terminal Land Grid Array [LGA]
38-Terminal Land Grid Array [LGA]
Evaluation Board
−40°C to +105°C
1 Z = RoHS Compliant Part
2 Measured at the exposed pad.
©2020 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D20829-5/20(B)
Rev. B | Page 38 of 38
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