ADL9005ACPZN [ADI]
Wideband, Low Noise Amplifier, Single Positive Supply, 0.01 GHz to 26.5 GHz;
| 型号： | ADL9005ACPZN |
| 厂家： | 
ADI |
| 描述： | Wideband, Low Noise Amplifier, Single Positive Supply, 0.01 GHz to 26.5 GHz |
| 文件： | 总24页 (文件大小：616K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Wideband, Low Noise Amplifier, Single
Positive Supply, 0.01 GHz to 26.5 GHz
ADL9005
Data Sheet
FEATURES
FUNCTIONAL BLOCK DIAGRAM
ADL9005
Single positive supply
Low noise figure: 2.5 dB typical from 0.01 GHz to 14 GHz
High gain: 17.5 dB typical from 0.01 GHz to 14 GHz
OP1dB: 13.5 dBm typical from 0.01 GHz to 20 GHz
High OIP3: 26 dBm typical from 0.01 GHz to 14 GHz
RoHS-compliant, 4 mm × 4 mm, 24-lead LFCSP
18
17
1
2
3
R
NC
BIAS
NC
GND
APPLICATIONS
16 RF
/V
GND
OUT DD
Test instrumentation
Military
Communications
15 GND
14
RF
IN
4
5
6
GND
NC
NC
13 NC
Figure 1.
GENERAL DESCRIPTION
The ADL9005 is a gallium arsenide (GaAs), monolithic
balanced, inphase/quadrature (I/Q) or image rejection mixers.
The ADL9005 also features inputs and outputs (I/Os) that are
internally matched to 50 Ω, making it ideal for surface-mounted
technology (SMT)-based, high capacity microwave radio
applications.
microwave integrated circuit (MMIC), pseudomorphic high
electron mobility transistor (pHEMT), wideband, LNA that
operates from 0.01 to 26.5 GHz. The ADL9005 provides a typical
gain of 17.5 dB from 0.01 GHz to 14 GHz with a positive gain
slope from 14 GHz to 20 GHz, a 13.5 dBm typical output power
at 1 dB compression (OP1dB) from 0.01 GHz to 20 GHz, a 2.5 dB
typical noise figure from 0.01 GHz to 14 GHz, and a typical output
third-order intercept (OIP3) of 26 dBm from 0.01 GHz to 14 GHz,
requiring only 80 mA from a 5 V supply voltage. The saturated
output power (PSAT) of up to 16 dBm enables the LNA to function
as a local oscillator (LO) driver for many of Analog Devices, Inc.,
The ADL9005 is housed in a RoHS-compliant, 4 mm × 4 mm,
LFCSP.
Multifunction pin names may be referenced by their relevant
function only.
Rev. 0
Document Feedback
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice.
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Devices. Trademarks and registeredtrademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Technical Support
©2021 Analog Devices, Inc. All rights reserved.
www.analog.com
ADL9005
Data Sheet
TABLE OF CONTENTS
Features.............................................................................................. 1
Pin Configuration and Function Descriptions .............................6
Interface Schematics .....................................................................7
Typical Performance Characteristics .............................................8
Biasing Through the ACG4/VDD2 Pin...................................... 18
Theory of Operation ...................................................................... 19
Applications Information ............................................................. 20
Basic Connections...................................................................... 20
Biasing the ADL9005 by Using the LTM8020 ....................... 21
Providing Drain Bias ................................................................. 22
Providing Drain Bias Through the ACG4/VDD2 Pin ............. 23
Power-Up and Power-Down Sequencing............................... 23
Outline Dimensions....................................................................... 24
Ordering Guide .......................................................................... 24
Applications ...................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications .................................................................................... 3
0.01 GHz to 14 GHz..................................................................... 3
14 GHz to 20 GHz........................................................................ 3
20 GHz to 26.5 GHz..................................................................... 4
DC Specifications ......................................................................... 4
Absolute Maximum Ratings ........................................................... 5
Thermal Resistance...................................................................... 5
Electrostatic Discharge (ESD) Ratings...................................... 5
ESD Caution.................................................................................. 5
REVISION HISTORY
2/2021—Revision 0: Initial Version
Rev. 0 | Page 2 of 24
Data Sheet
ADL9005
SPECIFICATIONS
0.01 GHz TO 14 GHz
Drain voltage (VDD) = 5 V, bias voltage (VBIAS) = 5 V, total current (IDQ) = 80 mA, RBIAS = 300 Ω, and TA = 25°C, unless otherwise noted.
Table 1.
Parameter
FREQUENCY RANGE
Min Typ
0.01
Max Unit
Test Conditions/Comments
14
GHz
dB
GAIN
15.5 17.5
Gain Variation Over Temperature
0.0077
dB/°C
RETURN LOSS
Input
15
14
dB
dB
Output
OUTPUT
OP1dB
PSAT
11.5 13.5
dBm
dBm
dBm
dB
16
26
2.5
OIP3
Measurement taken at output power (POUT) per tone = 0 dBm
NOISE FIGURE
14 GHz TO 20 GHz
VDD = 5 V, VBIAS = 5 V, IDQ = 80 mA, RBIAS = 300 Ω, and TA = 25°C, unless otherwise noted.
Table 2.
Parameter
FREQUENCY RANGE
Min Typ
14
Max Unit
Test Conditions/Comments
20
GHz
dB
GAIN
16.5 18.5
Gain Variation Over Temperature
0.0127
dB/°C
RETURN LOSS
Input
15
14
dB
dB
Output
OUTPUT
OP1dB
PSAT
11
13.5
15
25
3
dBm
dBm
dBm
dB
OIP3
Measurement taken at POUT per tone = 0 dBm
NOISE FIGURE
Rev. 0 | Page 3 of 24
ADL9005
Data Sheet
20 GHz TO 26.5 GHz
VDD = 5 V, VBIAS = 5 V, IDQ = 80 mA, RBIAS = 300 Ω, and TA = 25°C, unless otherwise noted.
Table 3.
Parameter
FREQUENCY RANGE
Min
20
Typ
Max
26.5
Unit
GHz
dB
Test Conditions/Comments
GAIN
17
19
Gain Variation Over Temperature
0.0214
dB/°C
RETURN LOSS
Input
15
14
dB
dB
Output
OUTPUT
OP1dB
PSAT
8.5
11.5
14
22
4
dBm
dBm
dBm
dB
OIP3
Measurement taken at POUT per tone = 0 dBm
NOISE FIGURE
DC SPECIFICATIONS
Table 4.
Parameter
VDD
Min
3
Typ
5
Max
6
Unit
V
CURRENT
IDQ
80
mA
mA
mA
Amplifier (IDQ_AMP
RBIAS (IDQ_BIAS
)
73.6
6.4
)
Rev. 0 | Page 4 of 24
Data Sheet
ADL9005
ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter
VDD
RFIN Power
Continuous Power Dissipation (PDISS),
TA = 85°C (Derate 12.5 mW/°C Above 85°C)
THERMAL RESISTANCE
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Careful attention to
PCB thermal design is required.
Rating
7 V
22 dBm
1.125 W
θJC is the junction to case thermal resistance.
Table 6. Thermal Resistance
Package
Temperature
Peak Reflow, Moisture Sensitivity Level (MSL)1 260°C
θJC
Unit
CP-24-15
80
°C/W
Junction to Maintain 1,000,000 Hour
Meant Time to Failure (MTTF)
175°C
Nominal Junction (TA = 85°C, VDD = 5 V,
IDQ = 80 mA)
Storage Range
117°C
ELECTROSTATIC DISCHARGE (ESD) RATINGS
The following ESD information is provided for handling of
ESD sensitive devices in an ESD protected area only.
−65°C to +150°C
−40°C to +85°C
Operating Range
Human body model (HBM) per ANSI/ESDA/JEDEC JS-001.
1 See the Ordering Guide for more information.
ESD Ratings for ADL9005
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Table 7. ADL9005, 24-Lead LFCSP
ESD Model
Withstand Threshold (V)
Class
1A
HBM
250
ESD CAUTION
Rev. 0 | Page 5 of 24
ADL9005
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
18
17
1
2
3
R
NC
BIAS
NC
GND
ADL9005
16 RF
/V
OUT DD
GND
TOP VIEW
15 GND
14
RF
IN
4
5
6
(Not to Scale)
GND
NC
NC
13 NC
NOTES
1. NC = NO INTERNAL CONNECTION. NOTE THE DATA
SHOWN HEREIN WAS MEASURED WITH THESE PINS
EXTERNALLY CONNECTED TO THE RF AND DC GROUND.
2. EXPOSED PAD. THE EXPOSED PAD MUST BE CONNECTED
TO RF AND DC GROUND.
Figure 2. Pin Configuration
Table 8. Pin Function Descriptions
Pin No.
Mnemonic Description
1
RBIAS
Current Mirror Bias Resistor Pin. Use the RBIAS pin to set the IDQ by connecting an external bias
resistor as defined in Table 9. Refer to Figure 74 for the bias resistor connection. See Figure 3 for
the interface schematic.
2, 6 to 10, 13, 14, 18 to 22 NC
No Internal Connection. Note the data shown herein was measured with these pins externally
connected to the RF and dc ground.
3, 5, 15, 17
GND
Ground. The GND pins must be connected to RF and dc ground. See Figure 4 for the interface
schematic.
4
RFIN
RF Input. The RFIN pin is dc-coupled and matched to 50 Ω. See Figure 5 for the interface
schematic.
11
12
16
23
24
ACG1
AC Grounding 1. A capacitor is required on the ACG1 pin to provide low frequency decoupling.
Refer to Figure 74 for the capacitor value. See Figure 5 for the interface schematic.
AC Grounding 2. A capacitor is required on the ACG2 pin to provide low frequency decoupling.
Refer to Figure 74 for the capacitor value. See Figure 5 for the interface schematic.
RF Output (RFOUT)/Drain Voltage for Amplifier (VDD). The RFOUT/VDD pin is dc-coupled and matched
to 50 Ω. See Figure 6 for the interface schematic.
AC Grounding 3. A capacitor is required on the ACG3 pin to provide low frequency decoupling.
Refer to Figure 74 for the capacitor value. See Figure 6 for the interface schematic.
ACG2
RFOUT/VDD
ACG3
ACG4/VDD2
AC Grounding 4 (ACG4). A capacitor is required on the ACG4 pin to provide low frequency
decoupling. Refer to Figure 74 for the capacitor value. See Figure 6 for the interface schematic.
Optional Drain Voltage for the Amplifier that Requires a Higher Voltage (VDD2). Do not use the
VDD2 pin simultaneously with RFOUT/VDD. See Figure 6 for the interface schematic.
EPAD
Exposed Pad. The exposed pad must be connected to RF and dc ground.
Rev. 0 | Page 6 of 24
Data Sheet
ADL9005
INTERFACE SCHEMATICS
R
BIAS
RF
IN
ACG2
ACG1
Figure 5. RFIN, ACG1, and ACG2 Interface Schematic
Figure 3. RBIAS Interface Schematic
RF
/V
OUT DD
ACG4/V
ACG3
DD2
GND
Figure 4. GND Interface Schematic
Figure 6. RFOUT/VDD, ACG3, and ACG4/VDD2 Interface Schematic
Rev. 0 | Page 7 of 24
ADL9005
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
25
20
25
20
15
15
10
S11
10
S21
5
S11
S21
S22
S22
5
0
–5
0
–5
–10
–15
–20
–25
–30
–10
–15
–20
0
20
40
60
80
100 120 140 160 180 200
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28
FREQUENCY (GHz)
FREQUENCY (MHz)
Figure 7. Gain and Return Loss vs. Frequency, 0.01 GHz to 28 GHz, VDD = 5 V,
Figure 10. Gain and Return Loss vs. Frequency, 10 MHz to 200 MHz, VDD = 5 V,
BIAS = 5 V, IDQ = 80 mA, RBIAS = 300 Ω
V
BIAS = 5 V, IDQ = 80 mA, RBIAS = 300 Ω (S22 Is the Output Return Loss, S11 Is the
Input Return Loss, and S21 Is the Gain)
V
24
22
20
18
16
14
12
10
8
24
22
20
18
16
14
12
10
8
6
6
–40°C
+25°C
+85°C
4
2
0
4
–40°C
+25°C
+85°C
2
0
0
20
40
60
80
100 120 140 160 180 200
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28
FREQUENCY (GHz)
FREQUENCY (MHz)
Figure 8. Gain vs. Frequency for Various Temperatures, 10 MHz to 200 MHz,
VDD = 5 V, VBIAS = 5 V, IDQ = 80 mA, RBIAS = 300 Ω
Figure 11. Gain vs. Frequency for Various Temperatures, 0.2 GHz to 28 GHz,
VDD = 5 V, VBIAS = 5 V, IDQ = 80 mA, RBIAS = 300 Ω
22
20
18
16
14
12
22
20
18
16
14
12
1.5kΩ, I
= 40mA
DQ
1kΩ, I
= 50mA
DQ
3V
4V
5V
6V
10
8
10
8
650Ω, I
450Ω, I
300Ω, I
180Ω, I
= 60mA
= 70mA
= 80mA
= 90mA
DQ
DQ
DQ
DQ
6
6
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28
FREQUENCY (GHz)
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28
FREQUENCY (GHz)
Figure 9. Gain vs. Frequency for Various VDD, IDQ = 80 mA, 0.01 GHz to 28 GHz
Figure 12. Gain vs. Frequency for Various Bias Resistor Values and IDQ
,
10 MHz to 28 GHz, VDD = 5 V
Rev. 0 | Page 8 of 24
Data Sheet
ADL9005
0
–5
0
–40°C
+25°C
+85°C
–40°C
+25°C
+85°C
–5
–10
–15
–20
–25
–30
–10
–15
–20
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28
FREQUENCY (GHz)
0
20
40
60
80
100 120 140 160 180 200
FREQUENCY (MHz)
Figure 16. Input Return Loss vs. Frequency for Various Temperatures,
0.2 GHz to 28 GHz, VDD = 5 V, VBIAS = 5 V, IDQ = 80 mA, RBIAS = 300 Ω
Figure 13. Input Return Loss vs. Frequency for Various Temperatures,
10 MHz to 200 MHz, VDD = 5 V, VBIAS = 5 V, IDQ = 80 mA, RBIAS = 300 Ω
0
0
3V
4V
5V
1.5kΩ, I
= 40mA
= 50mA
= 60mA
= 70mA
= 80mA
= 90mA
DQ
1kΩ, I
DQ
650Ω, I
450Ω, I
300Ω, I
180Ω, I
DQ
DQ
DQ
DQ
6V
–5
–5
–10
–15
–20
–10
–15
–20
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28
FREQUENCY (GHz)
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28
FREQUENCY (GHz)
Figure 17. Input Return Loss vs. Frequency for Various Bias Resistor Values
and IDQ, 0.01 GHz to 28 GHz, VDD = 5 V
Figure 14. Input Return Loss vs Frequency for Various VDD
IDQ = 80 mA, 0.01 GHz to 28 GHz
,
0
0
–5
–40°C
+25°C
+85°C
–40°C
+25°C
+85°C
–5
–10
–15
–20
–10
–15
–20
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28
FREQUENCY (GHz)
0
20
40
60
80
100 120 140 160 180 200
FREQUENCY (MHz)
Figure 18. Output Return Loss vs. Frequency for Various Temperatures,
0.2 GHz to 28 GHz, VDD = 5 V, VBIAS = 5 V, IDQ = 80 mA, RBIAS = 300 Ω
Figure 15. Output Return Loss vs. Frequency for Various Temperatures,
10 MHz to 200 MHz, VDD = 5 V, VBIAS = 5 V, IDQ = 80 mA, RBIAS = 300 Ω
Rev. 0 | Page 9 of 24
ADL9005
Data Sheet
0
0
–5
1.5kΩ, I
= 40mA
DQ
3V
4V
5V
6V
1kΩ, I
= 50mA
DQ
650Ω, I
450Ω, I
300Ω, I
180Ω, I
= 60mA
= 70mA
= 80mA
= 90mA
DQ
DQ
DQ
DQ
–5
–10
–15
–20
–10
–15
–20
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28
FREQUENCY (GHz)
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28
FREQUENCY (GHz)
Figure 19. Output Return Loss vs. Frequency at Various VDD
DQ = 80mA, 0.01 GHz to 28 GHz
,
Figure 22. Output Return Loss vs. Frequency for Various Bias Resistor Values
and IDQ, 0.01 GHz to 28 GHz, VDD = 5 V
I
0
0
–40°C
+25°C
+85°C
–40°C
–5
–5
+25°C
+85°C
–10
–10
–15
–20
–25
–30
–35
–40
–15
–20
–25
–30
–35
–40
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28
FREQUENCY (GHz)
0
20
40
60
80
100 120 140 160 180 200
FREQUENCY (MHz)
Figure 20. Reverse Isolation (S12) vs. Frequency for Various Temperatures,
10 MHz to 200 MHz, VDD = 5 V, VBIAS = 5 V, IDQ = 80 mA, RBIAS = 300 Ω
Figure 23. Reverse Isolation vs. Frequency for Various Temperatures,
0.2 GHz to 28 GHz, VDD = 5 V, VBIAS = 5 V, IDQ = 80 mA, RBIAS = 300 Ω
0
0
3V
–5
1.5kΩ, I
= 40mA
= 50mA
= 60mA
= 70mA
= 80mA
= 90mA
DQ
–5
–10
–15
–20
–25
–30
–35
–40
4V
5V
1kΩ, I
DQ
650Ω, I
450Ω, I
300Ω, I
180Ω, I
DQ
DQ
DQ
DQ
–10
6V
–15
–20
–25
–30
–35
–40
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28
FREQUENCY (GHz)
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28
FREQUENCY (GHz)
Figure 21. Reverse Isolation vs. Frequency for Various VDD
DQ = 80 mA, 0.01 GHz to 28 GHz
,
Figure 24. Reverse Isolation vs. Frequency for Various Bias Resistor Values
and IDQ, 0.01 GHz to 28 GHz, VDD = 5 V
I
Rev. 0 | Page 10 of 24
Data Sheet
ADL9005
12
10
8
12
10
8
–40°C
+25°C
+85°C
–40°C
+25°C
+85°C
6
6
4
4
2
2
0
0
0
20
40
60
80
100 120 140 160 180 200
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 25. Noise Figure vs. Frequency for Various Temperatures,
10 MHz to 200 MHz, VDD = 5 V, VBIAS = 5 V, IDQ = 80 mA, RBIAS = 300 Ω
Figure 28. Noise Figure vs. Frequency for Various Temperatures,
0.2 GHz to 28 GHz, VDD = 5 V, VBIAS = 5 V IDQ = 80 mA, RBIAS = 300 Ω
12
12
3V
4V
5V
6V
3V
4V
5V
10
10
6V
8
8
6
4
2
0
6
4
2
0
0
20
40
60
80
100 120 140 160 180 200
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 26. Noise Figure vs. Frequency for Various VDD, IDQ = 80 mA,
10 MHz to 200 MHz
Figure 29. Noise Figure vs. Frequency for Various VDD, IDQ = 80 mA,
0.2 GHz to 28 GHz
12
12
1.5kΩ, I
1.0kΩ, I
650Ω, I
450Ω, I
300Ω, I
180Ω, I
= 40mA
= 50mA
= 60mA
= 70mA
= 80mA
= 90mA
DQ
DQ
DQ
DQ
DQ
DQ
1.5kΩ, I
1.0kΩ, I
650Ω, I
450Ω, I
300Ω, I
180Ω, I
= 40mA
= 50mA
= 60mA
= 70mA
= 80mA
= 90mA
DQ
DQ
DQ
DQ
DQ
DQ
10
8
10
8
6
6
4
4
2
2
0
0
0
20
40
60
80
100 120 140 160 180 200
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 27. Noise Figure vs. Frequency for Various Bias Resistor Values and IDQ
10 MHz to 200 MHz, VDD = 5 V, VBIAS = 5 V
,
Figure 30. Noise Figure vs. Frequency for Various Bias Resistor Values and IDQ
0.2 GHz to 28 GHz, VDD = 5 V, VBIAS = 5 V
,
Rev. 0 | Page 11 of 24
ADL9005
Data Sheet
18
16
14
12
10
8
18
16
14
12
10
8
6
6
–40°C
+25°C
+85°C
–40°C
+25°C
+85°C
4
4
2
2
0
0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 31. OP1dB vs. Frequency for Various Temperatures, 0.01 GHz to 1 GHz,
Figure 34. OP1dB vs. Frequency for Various Temperatures, 1 GHz to 28 GHz,
V
DD = 5 V, VBIAS = 5 V, IDQ = 80 mA, RBIAS = 300 Ω
V
DD = 5 V, VBIAS = 5 V, IDQ = 80 mA, RBIAS = 300 Ω
18
16
14
12
10
8
18
16
14
12
10
8
6
6
3V
4V
5V
6V
3V
4V
5V
6V
4
4
2
2
0
0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 32. OP1dB vs. Frequency for Various Supply Voltages, IDQ = 80 mA,
0.01 GHz to 1 GHz
Figure 35. OP1dB vs. Frequency for Various Supply Voltages, IDQ = 80 mA,
1 GHz to 28 GHz
18
16
14
12
10
8
18
16
14
12
10
8
1.5kΩ, I
1.0kΩ, I
650Ω, I
450Ω, I
300Ω, I
180Ω, I
= 40mA
= 50mA
= 60mA
= 70mA
= 80mA
= 90mA
DQ
DQ
DQ
DQ
DQ
DQ
1.5kΩ, I
1.0kΩ, I
650Ω, I
450Ω, I
300Ω, I
180Ω, I
= 40mA
= 50mA
= 60mA
= 70mA
= 80mA
= 90mA
6
4
2
0
6
4
2
0
DQ
DQ
DQ
DQ
DQ
DQ
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 33. OP1dB vs. Frequency for Various Bias Resistor Values and IDQ
0.01 GHz to 1 GHz, VDD = 5 V, VBIAS = 5 V
,
Figure 36. OP1dB vs. Frequency for Various Bias Resistor Values and IDQ
1 GHz to 28 GHz, VDD = 5 V, VBIAS = 5 V
,
Rev. 0 | Page 12 of 24
Data Sheet
ADL9005
20
18
16
14
12
10
8
20
18
16
14
12
10
8
6
6
–40°C
+25°C
+85°C
–40°C
+25°C
+85°C
4
4
2
2
0
0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 37. PSAT vs. Frequency for Various Temperatures, 0.01 GHz to 1 GHz,
VDD = 5 V, VBIAS = 5 V, IDQ = 80 mA, RBIAS = 300 Ω
Figure 40. PSAT vs. Frequency for Various Temperatures, 1 GHz to 28 GHz,
VDD = 5 V, VBIAS = 5 V, IDQ = 80 mA, RBIAS = 300 Ω
20
18
16
14
12
10
8
20
18
16
14
12
10
8
3V
4V
3V
4V
6
6
5V
6V
5V
6V
4
2
0
4
2
0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 38. PSAT vs. Frequency for Various VDD, IDQ = 80 mA, 0.01 GHz to 1 GHz
Figure 41. PSAT vs. Frequency for Various VDD, IDQ = 80 mA, 1 GHz to 28 GHz
20
18
16
14
12
10
8
20
18
16
14
12
10
8
1.5kΩ, I
1.0kΩ, I
650Ω, I
450Ω, I
300Ω, I
180Ω, I
= 40mA
= 50mA
= 60mA
= 70mA
= 80mA
= 90mA
1.5kΩ, I
1.0kΩ, I
650Ω, I
450Ω, I
300Ω, I
180Ω, I
= 40mA
= 50mA
= 60mA
= 70mA
= 80mA
= 90mA
DQ
DQ
DQ
DQ
6
4
2
0
6
4
2
0
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 39. PSAT vs. Frequency for Various Bias Resistor Values and IDQ
0.01 GHz to 1 GHz, VDD = 5 V, VBIAS = 5 V
,
Figure 42. PSAT vs. Frequency for Various Bias Resistor Values and IDQ
1 GHz to 28 GHz, VDD = 5 V, VBIAS = 5 V
,
Rev. 0 | Page 13 of 24
ADL9005
Data Sheet
25
20
15
10
5
25
20
15
10
5
–40°C
+25°C
+85°C
–40°C
+25°C
+85°C
0
0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 43. Power Added Efficiency (PAE) vs. Frequency for Various Temperatures,
0.01 GHz to 1 GHz, VDD = 5 V, VBIAS = 5 V, IDQ = 80 mA, RBIAS = 300 Ω
Figure 46. PAE vs. Frequency for Various Temperatures, 1 GHz to 28 GHz,
DD = 5 V, VBIAS = 5 V, IDQ = 80 mA, RBIAS = 300 Ω
V
25
20
15
10
5
105
95
85
75
65
55
25
20
15
10
5
105
95
85
75
65
55
P
GAIN
PAE
OUT
P
GAIN
PAE
OUT
I
DD
I
DD
0
–20
0
–20
–17
–14
–11
–8
–5
–2
1
4
7
–16
–12
–8
–4
0
4
8
INPUT POWER (dBm)
INPUT POWER (dBm)
Figure 44. POUT, PAE, Gain, and Drain Current (IDD) vs. Input Power,
Power Compression at 1 GHz, VDD = 5 V, VBIAS = 5 V, RBIAS = 300 Ω
Figure 47. POUT, PAE, Gain, and IDD vs. Input Power,
Power Compression at 10 GHz, VDD = 5 V, VBIAS = 5 V, RBIAS = 300 Ω
25
105
95
85
75
65
55
25
20
15
10
5
105
P
GAIN
PAE
P
GAIN
PAE
OUT
OUT
95
20
15
10
5
I
I
DD
DD
85
75
65
55
0
–20
0
–16
–12
–8
–4
0
4
8
–20 –18 –16 –14 –12 –10 –8 –6 –4 –2
0
2
4
6
INPUT POWER (dBm)
INPUT POWER (dBm)
Figure 45. POUT, PAE, Gain, and IDD vs. Input Power,
Power Compression at 8 GHz, VDD = 5 V, VBIAS = 5 V, RBIAS = 300 Ω
Figure 48. POUT, PAE, Gain, and IDD vs. Input Power,
Power Compression at 14 GHz, VDD = 5 V, VBIAS = 5 V, RBIAS = 300 Ω
Rev. 0 | Page 14 of 24
Data Sheet
ADL9005
25
20
15
10
5
105
95
85
75
65
55
25
20
15
10
5
105
P
GAIN
PAE
P
GAIN
PAE
OUT
OUT
95
85
75
65
55
I
I
DD
DD
0
–20
0
–20
–16
–12
–8
–4
0
4
–16
–12
–8
–4
0
INPUT POWER (dBm)
INPUT POWER (dBm)
Figure 49. POUT, PAE, Gain, and IDD vs. Input Power,
Figure 52. POUT, PAE, Gain, and IDD vs. Input Power,
Power Compression at 20 GHz, VDD = 5 V, VBIAS = 5 V, RBIAS = 300 Ω
Power Compression at 26 GHz, VDD = 5 V, VBIAS = 5 V, RBIAS = 300 Ω
45
40
35
30
25
20
45
40
35
30
25
20
15
15
–40°C
+85°C
+25°C
+85°C
+25°C
–40°C
10
10
5
0
5
0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 50. OIP3 vs. Frequency for Various Temperatures, 0.01 GHz to 1 GHz,
VDD = 5 V, VBIAS = 5 V, IDQ = 80 mA, RBIAS = 300 Ω
Figure 53. OIP3 vs. Frequency for Various Temperatures, 1 GHz to 28 GHz,
VDD = 5 V, VBIAS = 5 V, IDQ = 80 mA, RBIAS = 300 Ω
45
40
35
30
25
20
45
40
35
30
25
20
15
15
3V
3V
4V
5V
4V
5V
10
10
6V
6V
5
5
0
0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 51. OIP3 vs. Frequency for Various VDD, IDQ = 80 mA, 0.01 GHz to 1 GHz
Figure 54. OIP3 vs. Frequency for Various VDD, IDQ = 80 mA, 1 GHz to 28 GHz
Rev. 0 | Page 15 of 24
ADL9005
Data Sheet
45
40
35
30
25
20
15
10
5
45
40
35
30
25
20
15
10
5
1.5kΩ, I
1.0kΩ, I
650Ω, I
450Ω, I
300Ω, I
180Ω, I
= 40mA
= 50mA
= 60mA
= 70mA
= 80mA
= 90mA
1.5kΩ, I
1.0kΩ, I
650Ω, I
450Ω, I
300Ω, I
180Ω, I
= 40mA
= 50mA
= 60mA
= 70mA
= 80mA
= 90mA
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
0
0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 55. OIP3 vs. Frequency for Various Bias Resistor Values and IDQ
,
Figure 58. OIP3 vs. Frequency for Various Bias Resistor Values and IDQ
,
0.01 GHz to 1 GHz, VDD = 5 V, VBIAS = 5 V
1 GHz to 28 GHz, VDD = 5 V, VBIAS = 5 V
70
60
50
40
70
60
50
40
30
30
–40°C
+25°C
+85°C
+25°C
20
20
+85°C
–40°C
10
10
0
0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
0
2
4
6
8
10 12 14 16 18 20 22 24 26
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 56. OIP2 vs. Frequency for Various Temperatures, 0.01 GHz to 1 GHz,
Figure 59. OIP2 vs. Frequency for Various Temperatures, 1 GHz to 24.5 GHz,
V
DD = 5 V, VBIAS = 5 V, IDQ = 80 mA, RBIAS = 300 Ω
V
DD = 5 V, VBIAS = 5 V, IDQ = 80 mA, RBIAS = 300 Ω
70
60
50
40
30
20
10
0
70
60
50
40
30
20
10
0
3V
4V
5V
6V
3V
4V
5V
6V
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
0
2
4
6
8
10 12 14 16 18 20 22 24 26
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 57. OIP2 vs. Frequency for Various VDD, IDQ = 80 mA, 0.01 GHz to 1 GHz
Figure 60. OIP2 vs. Frequency for Various VDD, IDQ = 80 mA, 1 GHz to 24.5 GHz
Rev. 0 | Page 16 of 24
Data Sheet
ADL9005
55
50
45
40
35
30
25
20
15
10
5
55
50
45
40
35
30
25
20
15
10
5
1.5kΩ, I
1.0kΩ, I
650Ω, I
450Ω, I
300Ω, I
180Ω, I
= 40mA
= 50mA
= 60mA
= 70mA
= 80mA
= 90mA
1.5kΩ, I
1.0kΩ, I
650Ω, I
450Ω, I
300Ω, I
180Ω, I
= 40mA
= 50mA
= 60mA
= 70mA
= 80mA
= 90mA
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
0
0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
0
2
4
6
8
10 12 14 16 18 20 22 24 26
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 61. OIP2 vs. Frequency for Various Bias Resistor Values and IDQ
,
Figure 64. OIP2 vs. Frequency for Various Bias Resistor Values and IDQ
,
0.01 GHz to 1 GHz, VDD = 5 V, VBIAS = 5 V
1 GHz to 24.5 GHz, VDD = 5 V, VBIAS = 5 V
0.40
100
90
80
70
60
50
40
30
20
10
0
1GHz
8GHz
10GHz
14GHz
20GHz
0.36
26GHz
0.32
0.28
0.24
0.20
–20
–16
–12
–8
–4
0
4
8
0
1
2
3
4
5
6
7
INPUT POWER (dBm)
V
(V)
DD
Figure 62. PDISS vs. Input Power at Various Frequencies, TA = 85°C, VDD = 5 V,
VBIAS = 5 V, IDQ = 80 mA
Figure 65. IDQ vs. VDD, VBIAS = 5 V, RBIAS = 300 Ω
100
90
80
70
60
50
40
30
20
10
0
90
80
70
60
50
40
0
1
2
3
4
5
6
7
0
0.3
0.6
0.9
1.2
1.5
V
(V)
BIAS
BIAS RESISTOR VALUE (kΩ)
Figure 63. IDQ vs. VBIAS, VDD = 5 V, RBIAS = 300 Ω
Figure 66. IDQ vs. Bias Resistor Value, VBIAS = 5 V, VDD = 5 V
Rev. 0 | Page 17 of 24
ADL9005
Data Sheet
BIASING THROUGH THE ACG4/VDD2 PIN
VDD2 = 8.5 V, VBIAS = 5 V, IDQ = 80 mA, RBIAS = 300 Ω, and frequency range = 0.01 GHz to 28 GHz.
25
12
10
8
20
–40°C
+25°C
+85°C
15
10
S21
S11
S22
S12
5
0
–5
6
–10
–15
–20
–25
–30
–35
–40
4
2
0
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28
FREQUENCY (GHz)
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28
FREQUENCY (GHz)
Figure 67. Gain, Return Loss, and Reverse Isolation vs. Frequency
Figure 70. Noise Figure vs. Frequency for Various Temperatures
18
16
14
12
10
20
18
16
14
12
10
8
–40°C
+25°C
+85°C
–40°C
+25°C
+85°C
8
6
4
2
0
6
4
2
0
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28
FREQUENCY (GHz)
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28
FREQUENCY (GHz)
Figure 68. OP1dB vs. Frequency for Various Temperatures
Figure 71. PSAT vs. Frequency for Various Temperatures
45
40
35
30
25
20
15
10
5
70
60
50
40
30
20
10
0
–40°C
+25°C
+85°C
–40°C
+25°C
+85°C
0
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28
FREQUENCY (GHz)
0
2
4
6
8
10 12 14 16 18 20 22 24 26
FREQUENCY (GHz)
Figure 69. OIP3 vs. Frequency for Various Temperatures
Figure 72. OIP2 vs. Frequency for Various Temperatures
Rev. 0 | Page 18 of 24
Data Sheet
ADL9005
THEORY OF OPERATION
ACG4/V
ACG3
DD2
The ADL9005 is a GaAs, MMIC, pHEMT, wideband LNA. A
simplified block diagram is shown in Figure 73. The RFIN and
RFOUT pins are dc-coupled and matched to 50 Ω.
R
BIAS
The ADL9005 operates from a single positive supply. IDQ is set
by connecting a resistor between the RBIAS pin and the external
supply voltage. The drain bias voltage is normally provided via
an external bias tee. However, the drain bias voltage can also be
resistively biased by connecting the ACG4/VDD2 pin to an external
supply.
RF
RF
/V
OUT DD
ADL9005
IN
ACG2
ACG1
Figure 73. Simplified Block Diagram
Rev. 0 | Page 19 of 24
ADL9005
Data Sheet
APPLICATIONS INFORMATION
BASIC CONNECTIONS
Table 9. Recommended Bias Resistor Values
The basic connections for operating the ADL9005 are shown
in Figure 74. Connect the recommended capacitor values to the
ac ground pins (ACG1, ACG2, ACG3, and ACG4) as shown
in Figure 74. The bias current is set by connecting a resistor
between RBIAS and VDD. When using 5 V VDD, a resistor value
of 300 Ω is recommended to achieve an IDQ of 80 mA. Table 9
shows the resulting IDQ for the various RBIAS values where the
resistor is tied to 5 V. Decouple the RBIAS pin with a 100 pF
capacitor as shown in Figure 74.
RBIAS (Ω)
180
300
450
650
1000
1500
IDQ (mA)
90
80
70
60
50
40
IDQ_AMP (mA)
82.3
73.6
64.8
55.8
46.8
37.4
IDQ_BIAS (mA)
7.7
6.4
5.2
4.2
3.2
2.6
Refer to ADL9005-EVALZ user guide (UG-1859) for the
recommended part numbers of the manufacturers for all
the external components required to operate the ADL9005.
V
DD
(5V)
C9
0.01µF
C6
4.7µF
R1
300Ω
R
1
2
3
18
BIAS
17
16
15
14
13
C4
RF
OUTPUT
RF
V
/
OUT
DD
100pF
RF INPUT
RF
IN
4
5
DRAIN
BIASING
NETWORK
C
IN
0.1µF
ADL9005
6
C7
4.7µF
C10
100pF
C11
0.01µF
Figure 74. Typical Application Circuit
Rev. 0 | Page 20 of 24
Data Sheet
ADL9005
The ADL9005 can be powered by using a well regulated power
source. The LTM8020 is a complete 200 mA, dc to dc, step-down
power supply that provides a single 5 V supply to VDD through a
bias tee on RBIAS. The recommended input voltage (VIN) for the
LTM8020 is from 6.5 V to 36 V to achieve a 5 V output voltage
(VOUT).
BIASING THE ADL9005 BY USING THE LTM8020
The LTM8020, µModule® regulator is suitable for the ADL9005
due to its compact size and wide input voltage range of 4 V to
36 V while maintaining high efficiency and output noise below
the maximum allowable ripple of the ADL9005 due to its high
power supply modulation ratio.
Figure 75 shows the application circuit for ADL9005 using the
LTM8020 regulator.
V
OUT
5V
200mA
V
IN
V
V
OUT
IN
6.5V TO 36V
C9
0.01µF
C6
4.7µF
2.2µF
LTM8020
SHDN
BIAS
10µF
GND ADJ
165kΩ
1%
R1
300Ω
R
BIAS
1
2
3
4
5
18
17
C4
RF
OUTPUT
RF
V
/
OUT
DD
100pF
16
15
14
13
RF INPUT
RF
IN
DRAIN
BIASING
NETWORK
C
IN
0.1µF
ADL9005
6
C7
4.7µF
C10
100pF
C11
0.01µF
Figure 75. Application Circuit for the ADL9005 Using the LTM8020 Regulator
Rev. 0 | Page 21 of 24
ADL9005
Data Sheet
20
15
PROVIDING DRAIN BIAS
S21
S11
S22
The ADL9005 was characterized using a connectorized wideband
bias tee (Marki Microwave BT2-0040). In practice, the drain bias
must be provided by a board mountable component. Drain biasing
for a wideband amplifier, such as the ADL9005, is traditionally
provided by connecting a wideband conical inductor between
RFOUT/VDD and the 5 V power supply, as shown in Figure 74.
Conical inductors are fragile and physically large. Figure 76
shows an alternative biasing circuit that uses 0402 sized, surface-
mount components. The gain, input return loss, and output
return loss over frequency are shown in Figure 77.
10
5
0
–5
–10
–15
–20
–25
–30
0
5
10
15
20
25
30
5V
FREQUENCY (GHz)
C2
R4
Figure 77. Gain and Return Loss vs. Frequency Using the Surface-Mount Bias Tee
270Ω
1pF
The circuit consists of ferrite beads (FB1 and FB2), an ac coupling
capacitor (COUT), an inductor (L3), de-Q resistors (R3 and R4),
and bypass capacitors (C1 and C2).
L3
0.11µH
C1
R3
340Ω
1pF
The R3, R4, C1, and C2 decoupling components are used to
reduce the RF coupling and to filter out power supply noise.
R3 and R4 are de-Q resistors that can reduce frequency glitches
caused by interactions between the PCB and the decoupling
capacitors.
FB1
470Ω
GND
FB2
470Ω
C
OUT
RF
/V
OUT DD
RF
OUT
FB2 is critical to achieving high frequency operation. Optimal
performance is achieved when FB2 touches down on the RF
trace directly. FB1 is also a critical component that must be
placed as close as possible to FB2 because a longer trace adds
increased inductance and capacitance. FB1 mitigates resonances
caused by the interaction between FB2 and the PCB.
100nF
Figure 76. Surface-Mounted Bias Tee Schematic
The L3 inductor is only needed if operation at below 100 MHz
is required. Otherwise, omit L3.
Table 10 lists the part numbers of the manufacturers and values
used in the surface-mounted bias tee circuit shown in Figure 76.
Further details on design of surface-mount bias tee circuits can
be found in Application Note AN-2061.
Table 10. Part Numbers of the Manufacturers and Values Used in the Surface-Mounted Bias Tee Circuit Shown in Figure 76
Component
FB1, FB2
L3
COUT
R3
Value
470 Ω
0.11 µH
100 nF
340 Ω
1 pF
Manufacturer
Murata
Coilcraft
American Technical Ceramics
Panasonic
Part Number
BLM15GG471SN1D
0805LS-111X_E_
ATC 560L
ERA-2AEB3400X
GJM1555C1H1R0CB01D
ERJ-2GEJ271X
C1, C2
R4
Murata
Panasonic
270 Ω
Rev. 0 | Page 22 of 24
Data Sheet
ADL9005
PROVIDING DRAIN BIAS THROUGH THE
ACG4/VDD2 PIN
POWER-UP AND POWER-DOWN SEQUENCING
Apply the RF input signal after the main supply voltage and
the voltage driving RBIAS (R1 in Figure 74 and Figure 78) and
remove the RF input signal before the main supply voltage and
the voltage on RBIAS are turned off. The voltage on RBIAS can either
be applied simultaneously with VDD or after VDD is applied.
An alternative way to bias the ADL9005 is through the ACG4/VDD2
pin (Pin 24), which is shown in Figure 78. Because of the voltage
drop across the internal bias resistor, a higher VDD is required.
If a 300 Ω bias resistor (R1) is used and connected to the 5 V
power supply, which results in a total current of 80 mA, a VDD
of 8.5 V is recommended. R1 can also be connected to the VDD
of 8.5 V. In this case, to set IDQ to 80 mA, use an R1 value of
850 Ω on RBIAS. The performance of this circuit is summarized
in Figure 67 to Figure 72.
V
DD
(8.5V)
C9
0.01µF
C6
4.7µF
5V
R1
300Ω
R
BIAS
1
2
3
4
5
18
17
16
15
14
13
C4
RF
OUTPUT
100pF
RF
/V
OUT DD
RF INPUT
RF
IN
C
OUT
0.1µF
C
IN
0.1µF
ADL9005
6
C7
4.7µF
C10
100pF
C11
0.01µF
Figure 78. Providing Resistive Drain Bias Through the ACG4/VDD2 Pin
Rev. 0 | Page 23 of 24
ADL9005
Data Sheet
OUTLINE DIMENSIONS
DETAIL A
(JEDEC 95)
4.10
4.00 SQ
3.90
0.30
0.25
0.18
PIN 1
INDICATOR
AREA
PIN 1
TIONS
INDICATOR AR E A OP
(SEE DETAIL A)
24
19
18
1
0.50
BSC
2.70
2.60 SQ
2.50
EXPOSED
PAD
13
12
6
7
0.50
0.40
0.30
0.20 MIN
TOP VIEW
SIDE VIEW
BOTTOM VIEW
0.80
0.75
0.70
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.05 MAX
0.02 NOM
COPLANARITY
0.08
SECTION OF THIS DATA SHEET.
SEATING
PLANE
0.20 REF
COMPLIANT TO JEDEC STANDARDS MO-220-WGGD-8
Figure 79. 24-Lead Lead Frame Chip Scale Package [LFCSP]
4 mm × 4 mm and 0.75 Package Height
(CP-24-15)
Dimensions shown in millimeters
ORDERING GUIDE
Model1, 2
ADL9005ACPZN
ADL9005ACPZN-R7
ADL9005-EVALZ
Temperature Range
−40°C to +85°C
−40°C to +85°C
MSL Rating3 Package Description4
Package Option
CP-24-15
CP-24-15
MSL3
MSL3
24-Lead Lead Frame Chip Scale Package [LFCSP]
24-Lead Lead Frame Chip Scale Package [LFCSP]
Evaluation Board
1 Z = RoHS Compliant Part.
2 When ordering the evaluation board only, reference the model number, ADL9005-EVALZ.
3 See the Absolute Maximum Ratings section for additional information.
4 The lead finish of the ADL9005ACPZN and ADL9005ACPZN-R7 is nickel palladium gold (NiPdAu).
©2021 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D25033-2/21(0)
Rev. 0 | Page 24 of 24
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