ADL9006ACGZN [ADI]
2 GHz to 28 GHz, GaAs, pHEMT, MMIC Low Noise Amplifier;
| 型号： | ADL9006ACGZN |
| 厂家： | 
ADI |
| 描述： | 2 GHz to 28 GHz, GaAs, pHEMT, MMIC Low Noise Amplifier |
| 文件： | 总14页 (文件大小：397K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
2 GHz to 28 GHz, GaAs,
pHEMT, MMIC Low Noise Amplifier
Data Sheet
ADL9006
FEATURES
FUNCTIONAL BLOCK DIAGRAM
P1dB: 20 dBm typical at 2 GHz to 6 GHz
P
SAT: 20.5 dBm typical at 2 GHz to 6 GHz
Gain: 15.5 dB typical at 6 GHz to 28 GHz
Noise figure: 2.5 dB typical at 2 GHz to 20 GHz
OIP3: 26 dBm typical at 2 GHz to 6 GHz
Supply voltage: 5 V at 53 mA
GND
1
2
3
4
5
6
7
8
24 GND
23 NIC
22 GND
V
GG
2
GND
RFIN
RFOUT
21
20
19
GND
NIC
NIC
GND
NIC
50 Ω matched input and output
ADL9006
18 NIC
GND
17
GND
APPLICATIONS
Test instrumentation
Military and space
PACKAGE
BASE
Local oscillator driver amp
Figure 1.
GENERAL DESCRIPTION
The ADL9006 is a gallium arsenide (GaAs), pseudomorphic
high electron mobility transistor (pHEMT), monolithic microwave
integrated circuit (MMIC), low noise amplifier that operates
between 2 GHz and 28 GHz. The amplifier provides 15.5 dB of
gain, 2.5 dB noise figure, 26 dBm output third-order intercept
(OIP3), and 20 dBm of output power for 1 dB compression
(P1dB) while requiring 53 mA from a 5 V supply. The ADL9006
is self biased with only a single positive supply needed to
achieve a supply current (IDD) of 53 mA.
The ADL9006 amplifier input and output are internally
matched to 50 Ω.
Rev. 0
Document Feedback
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rights of third parties that may result from its use. Specifications subject to change without notice. No
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Tel: 781.329.4700
Technical Support
©2020 Analog Devices, Inc. All rights reserved.
www.analog.com
ADL9006
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Electrostatic Discharge (ESD) Ratings.......................................5
ESD Caution...................................................................................5
Pin Configuration and Function Descriptions..............................6
Interface Schematics .....................................................................6
Typical Performance Characteristics ..............................................7
Theory of Operation ...................................................................... 12
Applications Information.............................................................. 13
Biasing Procedures..................................................................... 13
Outline Dimensions....................................................................... 14
Ordering Guide .......................................................................... 14
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
2 GHz to 6 GHz ............................................................................ 3
6 GHz to 20 GHz .......................................................................... 3
20 GHz to 28 GHz........................................................................ 3
DC Specifications ......................................................................... 4
Absolute Maximum Ratings............................................................ 5
Thermal Resistance ...................................................................... 5
REVISION HISTORY
8/2020—Revision 0: Initial Version
Rev. 0 | Page 2 of 14
Data Sheet
ADL9006
SPECIFICATIONS
2 GHz TO 6 GHz
TA = 25°C, VDD = 5 V, IDD = 53 mA, VGG2 = open, and a 50 Ω matched input and output, unless otherwise noted.
Table 1.
Parameter
Symbol
Test Conditions/Comments
Min Typ
Max Unit
FREQUENCY RANGE
GAIN
2
6
GHz
dB
13
15
Gain Variation Over Temperature
RETURN LOSS
0.007
dB/°C
Input
Output
11
12
dB
dB
OUTPUT
Output Power for 1 dB Compression
Saturated Output Power
Output Third-Order Intercept
P1dB
PSAT
OIP3
20
20.5
26
dBm
dBm
dBm
18
Measurement taken at output power (POUT) per
tone = 0 dBm
NOISE FIGURE
NF
2.5
4
dB
6 GHz TO 20 GHz
TA = 25°C, VDD = 5 V, IDD = 53 mA, VGG2 = open, and a 50 Ω matched input and output, unless otherwise noted.
Table 2.
Parameter
Symbol
Test Conditions/Comments
Min Typ
Max Unit
FREQUENCY RANGE
GAIN
6
20
GHz
dB
13
15.5
Gain Variation Over Temperature
RETURN LOSS
0.012
dB/°C
Input
Output
12
17
dB
dB
OUTPUT
Output Power for 1 dB Compression
Saturated Output Power
Output Third-Order Intercept
NOISE FIGURE
P1dB
PSAT
OIP3
NF
18
18.5
23
dBm
dBm
dBm
dB
16
Measurement taken at POUT per tone = 0 dBm
2.5
4.0
20 GHz TO 28 GHz
TA = 25°C, VDD = 5 V, IDD = 53 mA, VGG2 = open, and a 50 Ω matched input and output, unless otherwise noted.
Table 3.
Parameter
Symbol
Test Conditions/Comments
Min Typ
Max Unit
FREQUENCY RANGE
GAIN
20
13
28
GHz
dB
15.5
Gain Variation Over Temperature
RETURN LOSS
0.018
dB/°C
Input
Output
15
15
dB
dB
OUTPUT
Saturated Output Power
Output Third-Order Intercept
NOISE FIGURE
PSAT
OIP3
NF
15
17.5
19.5
4
dBm
dBm
dB
Measurement taken at POUT per tone = 0 dBm
6
Rev. 0 | Page 3 of 14
ADL9006
Data Sheet
DC SPECIFICATIONS
Table 4.
Parameter
Symbol
Test Conditions/Comments
Nominal voltage = 5 V
Min
Typ
Max
Unit
SUPPLY CURRENT
Total Supply Current
SUPPLY VOLTAGE
GATE BIAS VOLTAGE
IDD
53
5
mA
V
VDD
VGG2
4
7
Normal condition is VGG2 = open
−2.0
+2.6
V
Rev. 0 | Page 4 of 14
Data Sheet
ADL9006
ABSOLUTE MAXIMUM RATINGS
Table 5.
ELECTROSTATIC DISCHARGE (ESD) RATINGS
Parameter
Rating
The following ESD information is provided for handling of ESD
sensitive devices in an ESD protected area only.
VDD
VGG2
8 V
−2.6 V to +3.6 V
20 dBm
1.96 W
Human body model (HBM) per ANSI/ESDA/JEDEC JS-001.
RF Input Power (RFIN)
Continuous Power Dissipation (PDISS),
TA = 85°C (Derate 21.7 mW/°C Above 85°C)
Maximum Peak Reflow Temperature,
Moisture Sensitivity Level 3 (MSL3)
ESD Ratings for ADL9006
Table 7. ADL9006, 32-Lead LFCSP_CAV
260°C
ESD Model
Withstand Threshold (V)
Class
HBM
500
1B
Channel Temperature to Maintain 1,000,000 175°C
Hour Meant Time to Failure (MTTF)
ESD CAUTION
Nominal Channel Temperature (T = 85°C,
VDD = 5 V)
98°C
Storage Temperature Range
Operating Temperature Range
−65°C to +150°C
−40°C to +85°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
THERMAL RESISTANCE
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Careful attention to
PCB thermal design is required.
θJC is the junction to case thermal resistance.
Table 6. Thermal Resistance
Package
CG-32-21
θJC
Unit
46
°C/W
1 Thermal resistance (θJC) was determined by simulation under the following
conditions: the heat transfer is due solely to thermal conduction from the
channel, through the ground paddle, to the PCB, and the ground paddle is
held constant at the operating temperature of 85°C.
Rev. 0 | Page 5 of 14
ADL9006
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
GND
1
2
3
4
5
6
7
8
24 GND
23 NIC
22 GND
V
2
GG
GND
RFIN
ADL9006
TOP VIEW
(Not to Scale)
RFOUT
21
20
19
GND
NIC
NIC
GND
NIC
18 NIC
GND
17
GND
NOTES
1. NIC = NO INTERNAL CONNECTION. SOLDER THE
NIC PINS TO A LOW IMPEDANCE GROUND PLANE.
2. EXPOSED PAD. THE EXPOSED PAD MUST BE
CONNECTED TO RF AND DC GROUND.
Figure 2. Pin Configuration
Table 8. Pin Function Descriptions
Pin No.
Mnemonic Description
1, 3, 5, 8, 9, 16, 17, GND
Ground. Solder the GND pins to a low impedance ground plane.
20, 22, 24, 25,
32
2
VGG2
Gain Control. VGG2 is dc-coupled and accomplishes gain control by reducing the internal voltage and
becoming more negative. Attach bypass capacitors to VGG2, as shown in Figure 38. Under normal
operating conditions, VGG2 is left open.
4
RFIN
RF Input. RFIN is ac-coupled and matched to 50 Ω.
6, 7, 10 to 15, 18, NIC
19, 23, 26 to 30
No Internal Connection. Solder the NIC pins to a low impedance ground plane.
21
31
RFOUT
VDD
RF Output. RFOUT is ac-coupled and matched to 50 Ω.
Power Supply Voltage for the Amplifier.
EPAD
Exposed Pad. The exposed pad must be connected to RF and dc ground.
INTERFACE SCHEMATICS
RFOUT
RFIN
Figure 3. RFIN Interface Schematic
Figure 6. RFOUT Interface Schematic
GND
V
2
GG
Figure 7. GND Interface Schematic
Figure 4. VGG2 Interface Schematic
V
DD
Figure 5. VDD Interface Schematic
Rev. 0 | Page 6 of 14
Data Sheet
ADL9006
TYPICAL PERFORMANCE CHARACTERISTICS
20
20
19
18
17
16
15
14
13
12
11
10
15
+85°C
+25°C
–40°C
GAIN
10
5
INPUT RETURN LOSS
OUTPUT RETURN LOSS
0
–5
–10
–15
–20
0
5
10
15
20
25
30
2
4
6
8
10 12 14 16 18 20 22 24 26 28
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 8. Gain and Return Loss vs. Frequency
Figure 11. Gain vs. Frequency at Various Temperatures
0
–5
0
–5
+85°C
+25°C
–40°C
+85°C
+25°C
–40°C
–10
–15
–20
–10
–15
–20
2
4
6
8
10 12 14 16 18 20 22 24 26 28
FREQUENCY (GHz)
2
4
6
8
10 12 14 16 18 20 22 24 26 28
FREQUENCY (GHz)
Figure 12. Output Return Loss vs. Frequency at Various Temperatures
Figure 9. Input Return Loss vs. Frequency at Various Temperatures
10
10
9
9
4V
5V
+85°C
8
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1
0
+25°C
–40°C
6V
7V
2
4
6
8
10 12 14 16 18 20 22 24 26 28
FREQUENCY (GHz)
2
4
6
8
10 12 14 16 18 20 22 24 26 28
FREQUENCY (GHz)
Figure 10. Noise Figure vs. Frequency at Various Temperatures
Figure 13. Noise Figure vs. Frequency at Various Supply Voltages
Rev. 0 | Page 7 of 14
ADL9006
Data Sheet
20
15
20
19
18
17
16
15
14
13
12
11
10
4V
5V
6V
7V
10
5
+2.6V
+2.4V
+2.0V
+1.6V
+1.2V
+0.8V
+0.4V
0V
–0.4V
–0.8V
–1.2V
–1.6V
–2.0V
0
–5
–10
–15
–20
–25
–30
2
4
6
8
10 12 14 16 18 20 22 24 26
FREQUENCY (GHz)
2
4
6
8
10 12 14 16 18 20 22 24 26 28 30
FREQUENCY (GHz)
Figure 17. Gain vs. Frequency at Various VGG2 Voltages
Figure 14. Gain vs. Frequency at Various Supply Voltages
0
–5
0
+2.6V
+2.4V
+2.0V
+1.6V
+1.2V
+0.8V
+0.4V
0V
–0.8V
–1.2V
4V
5V
6V
7V
–0.4V
–5
–10
–15
–20
–10
–15
–20
2
4
6
8
10 12 14 16 18 20 22 24 26 28
FREQUENCY (GHz)
2
4
6
8
10 12 14 16 18 20 22 24 26 28
FREQUENCY (GHz)
Figure 15. Input Return Loss vs. Frequency at Various Supply Voltages
Figure 18. Input Return Loss vs. Frequency at Various VGG2 Voltages
0
0
+2.6V
+2.4V
+2.0V
+1.6V
+1.2V
+0.8V
+0.4V
0V
–0.4V
–0.8V
–1.2V
4V
5V
6V
7V
–5
–10
–15
–20
–5
–10
–15
–20
2
4
6
8
10 12 14 16 18 20 22 24 26 28
FREQUENCY (GHz)
2
4
6
8
10 12 14 16 18 20 22 24 26 28
FREQUENCY (GHz)
Figure 16. Output Return Loss vs. Frequency at Various Supply Voltages
Figure 19. Output Return Loss vs. Frequency at Various VGG2 Voltages
Rev. 0 | Page 8 of 14
Data Sheet
ADL9006
30
28
26
24
22
20
18
16
14
12
10
8
24
20
16
12
8
+6dBm
+4dBm
+2dBm
0dBm
–2dBm
–4dBm
–6dBm
–8dBm
–10dBm
–12dBm
–14dBm
–16dBm
5V, +85°C
5V, +25°C
5V, –40°C
4
6
0
4
2
0
–4
2
4
6
8
10 12 14 16 18 20 22 24 26 28
FREQUENCY (GHz)
0
5
10
15
20
25
30
FREQUENCY (dBm)
Figure 20. PSAT vs. Frequency at Various Temperatures
Figure 23. POUT vs. Frequency at Various Input Power Levels
20
15
10
5
150
25
20
15
10
5
140
120
100
80
125
100
75
50
25
0
60
P
GAIN
PAE
P
GAIN
PAE
0
OUT
OUT
0
40
I
I
DD
DD
–5
–5
–10
20
0
10
–10
–20
–20
–15
–10
–5
0
5
–15
–10
–5
0
5
10
INPUT POWER (dBm)
INPUT POWER (dBm)
Figure 21. POUT, Gain, PAE, and IDD vs. Input Power, 2 GHz,
VDD = 5 V
Figure 24. POUT, Gain, PAE, and IDD vs. Input Power, 20 GHz, VDD = 5 V
25
20
15
10
5
140
20
15
10
5
120
100
80
60
40
20
0
120
100
80
60
40
20
0
P
GAIN
PAE
P
GAIN
PAE
0
OUT
OUT
0
I
I
DD
DD
–5
–10
–5
–10
–20
–15
–10
–5
0
5
10
–20
–15
–10
–5
0
5
INPUT POWER (dBm)
INPUT POWER (dBm)
Figure 22. POUT, Gain, PAE, and IDD vs. Input Power, 10 GHz, VDD = 5 V
Figure 25. POUT, Gain, PAE, and IDD vs. Input Power, 26 GHz, VDD = 5 V
Rev. 0 | Page 9 of 14
ADL9006
Data Sheet
28
26
24
22
20
18
16
14
12
10
30
28
26
24
22
20
18
16
14
12
10
4V
5V
6V
7V
+85°C
+25°C
–40°C
2
4
6
8
10 12 14 16 18 20 22 24 26 28
FREQUENCY (GHz)
2
4
6
8
10 12 14 16 18 20 22 24 26 28
FREQUENCY (GHz)
Figure 26. Output IP3 vs. Frequency at Various Temperatures, POUT per Tone =
0 dBm
Figure 29. Output IP3 vs. Frequency at Various Supply Voltages
70
70
4V, 26GHz
4V, 20GHz
4V, 10GHz
4V, 6GHz
4V, 2GHz
6V, 26GHz
6V, 20GHz
6V, 10GHz
6V, 6GHz
6V, 2GHz
60
50
40
30
20
10
0
60
50
40
30
20
10
0
–4
–2
0
2
4
6
8
–4
–2
0
2
4
6
8
P
PER TONE (dBm)
P
PER TONE (dBm)
OUT
OUT
Figure 30. Output IMD3 vs. POUT per Tone for Various Frequencies, VDD = 6 V
Figure 27. Output Third-Order Intermodulation Distortion Relative to Carrier
(IMD3) vs. POUT per Tone for Various Frequencies, VDD = 4 V
70
70
5V, 26GHz
5V, 20GHz
5V, 10GHz
5V, 6GHz
5V, 2GHz
7V, 26GHz
7V, 20GHz
7V, 10GHz
7V, 6GHz
7V, 2GHz
60
50
40
30
20
10
0
60
50
40
30
20
10
0
–4
–2
0
2
4
6
8
–4
–2
0
2
4
6
8
P
PER TONE (dBm)
P
PER TONE (dBm)
OUT
OUT
Figure 28. Output IMD3 vs. POUT per Tone for Various Frequencies, VDD = 5 V
Figure 31. Output IMD3 vs. POUT per Tone for Various Frequencies, VDD = 7 V
Rev. 0 | Page 10 of 14
Data Sheet
ADL9006
30
28
26
24
22
20
18
16
14
12
10
8
30
28
26
24
22
20
18
16
14
12
10
8
+2.6V
+2.4V
+2.2V
+2.0V
+1.8V
+1.6V
+1.4V
+1.2V
+1.0V
+0.8V
+0.6V
+0.4V
+0.2V
0V
–0.4V
–0.6V
–0.8V
–1.0V
–1.2V
+2.6V
+2.4V
+2.2V
+2.0V
+1.8V
+1.6V
+1.4V
+1.2V
+1.0V
+0.8V
+0.6V
+0.4V
+0.2V
0V
–0.2V
–0.4V
–0.6V
–0.8V
–1.0V
–0.2V
6
6
4
4
2
2
0
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28 30
FREQUENCY (GHz)
2
4
6
8
10 12 14 16 18 20 22 24 26 28
FREQUENCY (GHz)
Figure 32. PSAT vs. Frequency at Various VGG2 Voltages
Figure 35. OIP3 vs. Frequency at Various VGG2 Voltages
55
50
45
40
35
30
25
20
15
10
5
0
–10
–20
–30
–40
–50
–60
+87°C
+25°C
–40°C
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28
FREQUENCY (GHz)
V
2 (V)
GG
Figure 33. Isolation vs. Frequency over Various Temperatures
Figure 36. IDD vs. VGG2 Voltages, VDD = 5 V
60
58
56
54
52
50
48
46
44
42
40
4.0
4.5
5.0
5.5
(V)
6.0
6.5
7.0
V
DD
Figure 34. IDD vs. VDD
Rev. 0 | Page 11 of 14
ADL9006
Data Sheet
THEORY OF OPERATION
The ADL9006 is a GaAs, pHEMT, MMIC low noise amplifier.
The basic architecture of the ADL9006 is that of a single-supply,
biased, cascode distributed amplifier with an integrated RF choke
for the drain. A simplified schematic of this architecture is
shown in Figure 37.
Though the gate bias voltages of the upper field effect transistors
(FETs) are set internally by a resistive voltage divider tapped off
of VDD, the VGG2 pin is provided to allow the user an optional
means of changing the gate bias of the upper FETs. Adjustment
of the VGG2 pin voltage across the range of −2.0 V to +2.6 V
changes the gate bias of the upper FETs, thus affecting gain
changes, depending on the frequency (see Figure 17).
V
DD
TRANSMISSION LINE
RFOUT
V
2
GG
TRANSMISSION LINE
RFIN
Figure 37. Architecture and Simplified Schematic
Rev. 0 | Page 12 of 14
Data Sheet
ADL9006
APPLICATIONS INFORMATION
Unless otherwise noted, all measurements and data shown were
taken using the typical application circuit (see Figure 38), biased
per the conditions in the Specifications section. The bias con-
ditions shown in the Specifications section are the operating
points recommended to optimize the overall performance of
the device. Operation using other bias conditions may provide
performance that differs from what is shown in this data sheet.
To obtain the optimal performance while not damaging the
device, follow the recommended biasing sequences outlined in
this section.
BIASING PROCEDURES
Capacitive bypassing is required for VDD, as shown in the typical
application circuit in Figure 38. Gain control is possible through
the application of a dc voltage to the VGG2 pin. If gain control is
used, VGG2 must be bypassed by a 100 pF capacitor, a 0.01 μF
capacitor, and a 4.7 μF capacitor. If gain control is not used, VGG2
can be either left open or capacitively bypassed, as shown in
Figure 38.
The recommended bias sequence during power-up is as follows:
1. Set VDD to 5 V (this setting results in an IDD near its
specified typical value).
V
DD
4.7µF
0.01µF
100pF
2. If the gain control function is used, apply a voltage within
the range of −2.0 V to +2.6 V to VGG2 until the desired gain is
achieved.
2
4
V
2
31
GG
4.7µF
0.01µF
100pF
21
RFOUT
3. Apply the RF input signal.
RFIN
The recommended bias sequence during power-down is as follows:
Figure 38. Typical Application Circuit
1. Turn off the RF input signal.
2. Remove the VGG2 voltage or set it to 0 V.
3. Set VDD to 0 V.
Rev. 0 | Page 13 of 14
ADL9006
Data Sheet
OUTLINE DIMENSIONS
DETAIL A
(JEDEC 95)
5.10
5.00 SQ
4.90
0.30
0.25
0.20
PIN 1
INDICATOR
PIN 1
INDICATOR AREA OPTIONS
25
24
32
(SEE DETAIL A)
1
0.50
BSC
3.20
3.10 SQ
3.00
EXPOSED
PAD
17
16
8
9
0.45
0.40
0.35
TOP VIEW
SIDE VIEW
BOTTOM VIEW
3.50 REF
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
1.35
1.25
1.15
0.60 REF
0.40
0.050 MAX
0.035 NOM
SECTION OF THIS DATA SHEET.
COPLANARITY
SEATING
PLANE
0.08
0.203 REF
Figure 39. 32-Lead Lead Frame Chip Scale Package, Premolded Cavity [LFCSP_CAV]
5 mm × 5 mm Body and 1.25 mm Package Height
(CG-32-2)
Dimensions shown in millimeters
ORDERING GUIDE
Temperature
Range
MSL
Package
Option
Model1
Rating2
Package Description3
ADL9006ACGZN
ADL9006ACGZN-R7
ADL9006-EVALZ
−40°C to +85°C
−40°C to +85°C
MSL3
MSL3
32-Lead Lead Frame Chip Scale Package, Premolded Cavity [LFCSP_CAV] CG-32-2
32-Lead Lead Frame Chip Scale Package, Premolded Cavity [LFCSP_CAV] CG-32-2
Evaluation Board
1 Z = RoHS Compliant Part.
2 See the Absolute Maximum Ratings section for additional information.
3 The lead finish of the ADL9006ACGZN and the ADL9006ACGZN-R7 is nickel palladium gold (NiPdAu).
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