ADM1060 [ADI]
Communications System Supervisory/Sequencing Circuit; 通信系统监控/排序电路
| 型号： | ADM1060 |
| 厂家： | 
ADI |
| 描述： | Communications System Supervisory/Sequencing Circuit |
| 文件： | 总45页 (文件大小：295K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY TECHNICAL DATA
CommunicationsSystem
a
PreliminaryTechnicalData
Supervisory/SequencingCircuit
ADM1060
AD M1060 TABLE O F CO NTENTS
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
ADM1060 Functional Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
ADM1060 Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Powering the ADM1060 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Programmable Supply Fault Detectors (SFD’s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
SFD Comparator Hysteresis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Bipolar SFD’s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
SFD Fault T ypes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Glitch Filtering on the SFD’s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Programming the SFD’s on the SMBus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
SFD Register Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
SFD Register Bitmaps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Bipolar Supply Fail Detect (BSnSFD) Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
High Voltage Supply Fault Detect (HVSFD) Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Positive Voltage Supply Fault Detect (PSnSFD) Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Watchdog Fault Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
General Purpose Inputs (GPI’s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Logic State of the GPI’s (and other Logic Inputs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Programmable Logic Block Array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
PLBA Register Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
PLBA Register Bitmaps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Programmable Delay Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Programmable Driver Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Fault/Status Reporting on the ADM1060 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Fault Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Mask Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Configuuration Download at Power- Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Updating the Configuration of the ADM1060 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Internal Registers of the ADM1060 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
EEP RO M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Serial Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
General SMBus T iming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
SMBus Protocols for RAM and EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
ADM1060 Write Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
ADM1060 Read Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Error Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Applications Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Register Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Outline Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
REV. PrJ 11/02
Inform ation furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assum ed by Analog Devices for its
use, nor for any infringem ents of patents or other rights of third parties
which m ay result from its use. No license is granted by im plication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106,
U.S.A. Tel:781/ 329-4700 World Wide Web Site:http:/ / w w w .analog.com
Fax: 781/ 326-8703
© Analog Devices, Inc., 2002
PRELIMINARY TECHNICAL DATA
ADM1060
Other inputs to the ADM1060 include a Watchdog Detec-
FEATURES
tor (WDI) and 4 General Purpose Inputs (GPIn). T he
Watchdog Detector can be used to monitor a processor
clock. If the clock does not toggle (transition from low to
high or from high to low) within a programmable timeout
period (up to 18 sec.), a fail flag will assert. T he 4 Gen-
eral Purpose inputs can be configured as logic buffers or
to detect positive/negative edges and to generate a logic
pulse or level from those edges. T hus, the user can input
control signals from other parts of their system (eg RE-
SET or POWER_GOOD) to gate the sequencing of the
supplies supervised by the ADM1060.
Fa u lt s d e t e c t e d o n 7 in d e p e n d e n t s u p p lie s
•
•
•
1 Hig h Vo lt a g e s u p p ly (u p t o 1 4 .4 V)
4 P o s it ive Vo lt a g e On ly S u p p lie s (u p t o 6 V)
2 P o s it ive /Ne g a t ive Vo lt a g e s u p p lie s (u p t o +6 V OR
d o w n t o -6 V)
Wa t c h d o g De t e c t o r In p u t - Tim e o u t d e la y p ro g ra m m a b le
fro m 2 0 0 m s t o 1 2 .8 s e c
4 Ge n e ra l P u rp o s e Lo g ic In p u t s
P ro g ra m m a b le Lo g ic Blo c k - c o m b in a t o ria l a n d s e q u e n c -
in g lo g ic c o n t ro l o f a ll in p u t s a n d o u t p u t s
9 P ro g ra m m a b le Ou t p u t Drive rs
•
•
•
•
•
•
Op e n Co lle c t o r (e xt e rn a l re s is t o r re q u ire d )
Op e n Co lle c t o r w it h in t e rn a l p u ll-u p t o VDD
Fa s t In t e rn a l p u ll-u p t o VDD
Op e n Co lle c t o r w it h in t e rn a l p u ll-u p t o VP n
Fa s t In t e rn a l p u ll-u p t o VP n
In t e rn a lly c h a rg e p u m p e d h ig h d rive (fo r u s e w it h
e xt e rn a l N- c h a n n e l FETS - P DO’s 1 t o 4 o n ly)
EEP ROM- 5 1 2 Byt e s
T he ADM1060 features 9 Programmable Driver Outputs
(PDO’s). All 9 outputs can be configured to be logic
outputs, which can provide multiple functions for the end
user such as RESET generation, POWER_GOOD status,
enabling of LDO’s, Watchdog T imeout assertion etc.
PDO’s 1- 4 have the added feature of being able to pro-
vide an internally charge pumped high voltage for use as
the gate drive of an external N- Channel FET which
could be placed in the path of one of the supplies being
supervised.
In d u s t ry S t a n d a rd 2 - Wire Bu s In t e rfa c e (S MBu s )
Gu a ra n t e e d P DO Lo w w it h VP n , VH=1 V
All of the inputs and outputs described above are con-
trolled by the Programmable Logic Block Array. T his is
the logic core of the ADM1060. It is comprised of 9
macrocells, one for each PDO. T hese macrocells are
essentially just wide AND gates. Any/all of the inputs can
be used as an input to these macrocells. T he output of a
macrocell can also be used as an input to any macrocell
other than itself (an input to itself would result in a no-
terminating loop). T he PLBA outputs control the PDO’s
of the ADM1060 via delay blocks, where a delay of be-
tween 0 and 500ms can be programmed on the rising and/
or the falling edge of the data. T his results in a very flex-
AP P LICATIO N S
Ce n t ra l Offic e S ys t e m s
S e rve rs
Infrastructure Netw ork Boards
Hig h d e n s it y, m u lt i- vo lt a g e s ys t e m c a rd s
G E NE R AL D E S C R IP T IO N
T he AD M 1060 is a programmable supervisory/sequencing
device which offers a single chip solution for multiple
power supply fault detection and sequencing in communi-
cations systems.
ible sequencing ability.
T hus, for instance, PDO1 can be
In central office, servers and other infrastructure systems,
a common backplane dc supply is reduced to multiple
board supplies using dc/dc converters. T hese multiple
supplies are used to power different sections of the board
(eg) 3.3V Logic circuits, 5V logic circuits, DSP core and
I/O circuits etc. T here is usually a requirement that cer-
tain sections power up before others (eg) a DSP core to
power up before the DSP I/O or vice versa. T his is in
order to avoid damage, miscommunication or latch- up.
T he ADM1060 facilitates this, providing supply fault
detection and sequencing/combinatorial logic for up to 7
independent supplies. T he 7 Supply Fault Detectors con-
sist of one high voltage detector (up to +14.4V), two bi-
polar voltage detectors (up to +6V OR down to -6V) and
4 positive low voltage detectors (up to +6V). All of the
detectors can be programmed to detect undervoltage, ov-
ervoltage or out- of window (undervoltage OR overvolt-
age) conditions. T he inputs to these Supply Fault
Detectors are via the VH pin (High Voltage), VBn pins
(positive OR negative) and VPn pins (Positive only) pins
respectively. Either the VH supply or one of the VPn
supplies is used to power the ADM1060 (whichever is
highest). T his ensures that, in the event of a supply fail-
ure, the ADM1060 is kept alive for as long as possible,
thus enabling a reliable fault flag to be asserted and the
system to be powered down in an ordered fashion.
programmed so that it will not assert until, say, VP2,
VP3and VP4 supplies are in tolerance, VB1 and VH have
been in tolerance for 200mS, and PDO7 has already been
asserted. A simple sequencing operation would be to
daisy chain each PLB output into the input of the next
PLB such that PDO9 doesn’t assert until PDO8 asserts,
which in turn doesn’t assert until PDO7 asserts etc.
All of the functional capability described here is program-
mable through the industry standard 2 wire bus (SMBus)
provided. Device settings can be written to EEPROM
memory for automatic programming of the device on
power-up. T he EEPROM is organised in 512 bytes, half
of which are used to program all of the functions on the
ADM1060. T he other 256 bytes of EEPROM are for
general purpose system use (eg) date codes, system ID etc.
Read/write access to this is also via the 2 wire interface.
In addition, each output state can be directly overdriven
from the serial interface, allowing a further level of con-
trol (eg) a system controlled soft powerdown.
REV. PrJ 11/02
–2 –
PRELIMINARY TECHNICAL DATA
ADM1060
PROGRAMMABLE
DELAY BLOCKS
PROGRAMMABLE
DRIVER OUPUTS
PDB1
PROGRAMMABLE
PDO1
15
PDO1
LOGIC BLOCK
ARRAY
T
RISE
T
FALL
(PLBA)
8
VH
HIGH SUPPLY(14.4v)
FAULT DETECTOR
PDB2
PDB3
PDO2
PDO3
16 PDO2
PLB
MACROCELL 1
T
T
FALL
RISE
POSITIVE SUPPLY
FAULT DETECTOR 1
9
VP1
PLB
MACROCELL 2
17
10
11
PDO3
VP2
VP3
VP4
T
RISE
T
FALL
PLB
MACROCELL 3
PDB4
12
POSITIVE SUPPLY
FAULT DETECTOR 4
PDO4
PDO4
18
PLB
MACROCELL4
T
RISE
T
FALL
PDB5
PDB6
PDB7
VB1
VB2
13
14
BIPOLAR SUPPLY
FAULT DETECTOR 1
PLB
MACROCELL 5
PDO5
PDO6
19 PDO5
T
T
FALL
RISE
BIPOLAR SUPPLY
FAULT DETECTOR 2
PLB
MACROCELL 6
PDO6
20
PLB
MACROCELL 7
T
RISE
T
FALL
28
27
GPI1
GPI2
INPUT LOGIC
SIGNAL CONDITION
PDO7
PLB
MACROCELL 8
21
26
25
GPI3
GPI4
WDI
PDO7
T
T
FALL
RISE
WATCHDOG FAULT
DETECTOR
24
PLB
MACROCELL 9
PDB8
PDB9
22 PDO8
PDO8
PDO9
T
RISE
T
FALL
GND
6
7
VREF
23
PDO9
T
RISE
T
FALL
1
0
0
K
H
z
Internal
5.5V supply
S
M
B
U
S
VCCP
REGULATED
5.5V SUPPLY
CHARGE PUMP
Data, Address and
Write Enable Buses
to store control information
local to functions
C
L
O
C
K
D
A
T
A
V
DD
ARBITRATOR
EEPROM
DEVICE
CONTROLLER
SMBus INTERFACE
5
4
3
2
1
ADM1060 FUNCTIONALBLOCKDIAGRAM
REV. PrJ 11/02
–3 –
PRELIMINARY TECHNICAL DATA
ADM1060–SPECIFICATIONS
(VH=4.5V to 14.4V, VPn = 3.0V to 6.0V 2, T = -40oC to 85oC, unless otherwise noted.)
A
Parameter
M in
T yp
M ax
Units T est Conditions/Comments
P O WER SUP P LY ARBITRATIO N
VD D C AP
2.7
2.7
V
Any VPn>=3.0V
VH > = 4.5V
4.75
4.75
5.1
5.1
V
V
Any VPn=6.0V
VH = 14.4V
P O WER SUP P LY
Supply Current, ID D
3
m A
VD D CAP=4.75V, no PD O FET
Drivers on, no loaded PDO pullups
to VDDCAP
5
1
m A
m A
VD D C AP=4.75V, all PD O FET
Drivers on (loaded with 1A), no
PDO pullups to VDDCAP
Max. additional load that can be
drawn from PDO pullups to
VD D C AP
Additional current available from VDDCAP
SUP P LY FAULT D ETECTO RS
VH Input
Input Impedance
T hreshold Ranges
M id Range
52
k⍀
From VH to GND
2
6
V
Programming Step Size
H igh Range
Programming Step Size
VP n Inputs
15.6
37.6
52
m V
V
m V
4.8
14.4
Input Impedance
T hreshold Ranges
Ultra Low Range
Programming Step Size
Low Range
k⍀
From VPn to GND
0.6
1
1.8
3
V
m V
V
4.7
Programming Step Size
M id Range
7.8
m V
V
2
6
Programming Step Size
VBn Inputs
15.6
m V
Input Impedance
190
52
30
k⍀
k⍀
k⍀
From VBn to 2.25V (Internal Ref.)
From VBn to GND (positive mode)
From VBn to GND (negative mode)
T hreshold Ranges
N egative M ode:
M id Range
-6
-2
V
Programming Step Size
Positive M ode:
15.6
m V
Low Range
Programming Step Size
M id Range
1
2
3
V
m V
V
7.8
6
Programming Step Size
Absolute Accuracy
Absolute Accuracy-
C alibrated Voltage T hresholds4
15.6
m V
%
2.5
1.0
%
8
T A=0oC to 85oC, T hreshold
Voltage> 0.9V
Bits
T hreshold Programming Resolution
D igital G litch Filter
0
100
s
See figure 3. 8 timeout options
between 0 and 100s
NO T E S
1
2
3
4
T hese are target specifications and subject to change.
At least one VPn must be >=3.0V if used as supply. VH must be >=4.5V if used as supply.
Logic inputs will accept input high voltages up to 5.5V even when device is operating at supply voltages below 5V.
C alibrated Voltage T hresholds are set at Production.
REV.PrJ 11/02
–4 –
PRELIMINARY TECHNICAL DATA
1
ADM1060–SPECIFICATIONS
(VH=4.5V to 14.4V, VPn = 3.0V to 6.0V , T = -40oC to 85oC, unless otherwise noted.)
2
A
P a r a m eter
M in
T yp
M a x
Units Test Conditions/Com m ents
P RO GRAMMABLE D RIVER
O U T P U T S
H igh Voltage (Char ge P um p) Mode
(P D O ’s 1 to 4)
Output Impedance, ROUT
VO H
440
12.5
12
k⍀
V
V
10.5
10
14
IO H = 0
O H = 1A
I
IO U T AVG
20
A
2V< VO H < 7V
Standar d (D igital O utput) Mode
(P D O ’s 1 to 9)
VO H
2.4
V
VPU (Pullup to VDDCAP or
VPn)= 2.7V, IO H = 1mA
VPU to VPn=6.0V, IOH =0mA
VPU < = 2.7V, IO H = 1mA
IO L= 2m A
IO L= 10m A
IO L= 15m A
T otal Sink Current
Internal pullup
Current Load on any VPn pull-ups
(ie) total source current available
through any number of PDO pull-up
switches configured on to any one
4.5
V
V
V
V
V
PU -0.3
VO L
0.4
1.2
2.0
20
V
ISIN K
RP U LLU P -
ISOU RC E
m A
k⍀
m A
Weak Pull-up
20
2
(VPn)
T ristate Output Leakage Current
10
A
VP D O = 14.4V
D IGITAL INP UTS
(GP I 1-4,WD I,A0,A1)
Input H igh Voltage, VIH
Input Low Voltage, VIL
Input High Current, IIH
Input Low Current, IIL
Input Capacitance
2.0
-1
V
V
A
A
p F
A
M ax. VIN = 5.5V
M ax. VIN = 5.5V
VIN = 5.5V
0.8
1
VIN = 0
T BD
10
Programmable Pulldown C urrent, IPU LLD OWN
If known logic state required
SERIAL BUS D IGITAL INP UTS
(SD A,SC L)
Input H igh Voltage, VIH
Input Low Voltage, VIL
Output Low Voltage, VOL
2.0
V
V
V
0.8
0.4
IOUT = -3.0mA
P RO GRAMMABLE D ELAY BLO CK
T im eout
0
0
500
m s
s
16 programmable options on both
rising and falling edge
WATCH D O G TIMER INP UT
T im eout
12.8
8 programmable timeout options
SERIAL BUS TIMING
Clock Frequency, fSC LK
Glitch Immunity, tSW
400
50
K H z
ns
µs
µs
µs
µs
µs
ns
µs
See Figure 8c
See Figure 8c
See Figure 8c
See Figure 8c
See Figure 8c
See Figure 8c
See Figure 8c
See Figure 8c
See Figure 8c
See Figure 8c
See Figure 8c
Bus Free T ime, tBU F
4.7
4.7
4
4.7
4
Start Setup T ime, tSU;ST A
Start H old T ime, tH D ;ST A
SCL Low T ime, tLOW
SCL H igh T ime, tH IGH
SCL, SDA Rise T ime, tr
SCL, SDA Fall T ime, tf
Data Setup T ime, tSU;D AT
D ata H old T ime, tH D ;D AT
1000
300
250
300
ns
ns
NO T E S
1
2
3
4
T hese are target specifications and subject to change.
At least one supply connected to VH or VPn must be >=3.0V
Logic inputs will accept input high voltages up to 5.5V even when device is operating at supply voltages below 5V.
T iming specifications are tested at logic levels of VIL
=
0.8V for
a
falling edge and VIH = 2.2V for a rising edge.
REV.PrJ 11/02
–5 –
PRELIMINARY TECHNICAL DATA
ADM1060
P IN F U NC T IO N D E S C R IP T IO N
P in
1
Mn em on ic
F u n ction
A0
Logic input. Controls the 7th bit (LSB) of the 7 bit Serial Bus Address.
Logic input. Controls the 6th bit of the 7 bit Serial Bus Address.
Serial Bus data I/O pin. Open- Drain output. Requires 2.2k pullup resistor
Open- Drain Serial Bus Clock pin. Requires 2.2k pullup resistor
2
A1
3
SD A
S C L
VD D C AP
4
5
VDD bypass capacitor pin. A capacitor from this pin to GND stabilises the VDD Arbitrator.
0.1F is recommended for this function.
6
7
G N D
Ground. Connect to common of power supplies.
VC C P
Reservoir Capacitor for Central Charge Pump. T his charge pump powers all of the internal
circuits of the ADM1060 and provides the first stage in the tripler circuits used to produce
12V of gate drive on PDO’s 1- 4.
8
VH
High Voltage Supply Input. 2 input ranges. A supply of between 2V and 6V or between
4.8V and 14.4V can be applied to this pin. T he VDD arbitrator will select this supply to power
the ADM1060 if it is the highest supply supervised.
9-12
VP1-4
Positive Only Supply Inputs. 2 input ranges. A supply of between 1V and 3V or between
2V and 6V can be applied to this pin. T he VDD arbitrator will select one of these supplies to
power the ADM1060 if it is the highest supply supervised.
13-14 VB1-2
Bipolar Supply Inputs. 2 modes. 2 input ranges in positive mode. 1 input range in negative
mode. A supply of between -6V and -2V can be applied to this pin when set in negative mode.
A supply of between 1V and 3V or between 2V and 6V can be applied to this pin when set in
positive mode.
15-23 P D O _1-9
Programmable Driver Output pin. All 9 can be programmed as logic outputs with multiple
pull-up options to VDD or VPn. PDO’s 1 to 4 can also provide a charge-pump generated
gate drive for external N- Channel FET
24
W D I
Watchdog Input. Used to monitor a processor clock and asserts a fault condition if the clock
fails to transition from low-to-high or high-to-low within a programmed timeout period (up to
18sec).
25-28 G P I_4-1
Reset,
General Purpose Logic Input. T T L compatible Logic. Can be used as, say, a
a Chip Enable pin or as an input for a control logic signal which may be critical to the power
up/down sequence of the supplies under control.
M anual
AB SO LUT E M AXIM UM RAT ING S*
A0
A1
1
2
3
4
5
6
28
27
26
GPI1
GPI2
GPI3
Voltage on VH Pin . . . . . . . . . . . . . . . . . . . . . . . . . . +17 V
Voltage on VP Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . +7 V
Voltage on VB Pins . . . . . . . . . . . . . . . . . . . . . -7 V to +7V
Voltage on A0,A1 . . . . . . . . . . . . . . -0.3V to (VC C +0.3V)
Voltage on Any Other Input . . . . . . . . . . . . . . -0.3V to 6.5V
Input Current at any pin . . . . . . . . . . . . . . . . . . . . . . ± 5m A
Package Input Current . . . . . . . . . . . . . . . . . . . . . . ± 20m A
M aximum Junction T emperature (T Jmax) . . . . . . . 150 °C
Storage T emperature Range . . . . . . . . . –65°C to +150°C
Lead T emperature, Soldering
SDA
25 GPI4
24 WDI
SCL
ADM1060
VDDCAP
GND
23 PDO9
22
21
PDO8
PDO7
PDO6
PDO5
VCCP
VH
8
VP1
VP2
20
19
9
10
11
VP3
18 PDO4
17
VP4 12
PDO3
Vapor Phase 60 sec . . . . . . . . . . . . . . . . . . . . . . . + 215°C
ESD Rating all pins . . . . . . . . . . . . . . . . . . . . . . . . 2000 V
VB1
VB2
16 PDO2
15 PDO1
13
14
*Stresses above those listed under “Absolute M aximum Ratings” may
cause permanent damage to the device. T his is
a stress rating only;
ADM1060 PIN CONFIGURATION
functional operation of the device at these or any other conditions above
those indicated in the operational section of this specification is not
im plied . Exposu re to absolu te m axim u m ratin g con d ition s for ex-
tended periods may affect device reliability.
O RD ERING GUID E
Tem perature
Range
P ackage
Description
P ackage
Option
Model
T H E R M AL C H AR AC T E R IS T IC S
AD M 1060ARU -40°C to +85°C
28-PinT SSOP
RU-28
28-Pin T SSOP Package:
⍜
=
98°C/Watt
JA
REV. PrJ 11/02
–6 –
PRELIMINARY TECHNICAL DATA
ADM1060 INPUTS
ADM1060
ADM1060INP UTS
P RO GRAMMABLE SUP P LY FAULT D ETECTO RS
(SF D ’S)
P O WERING TH E AD M1060
T he ADM1060 is powered from the highest voltage input
on either the Positive Only supply inputs (VPn) or the
High Voltage supply input (VH). T he same pins are used
for supply fault detection (discussed below) . A VDD Arbi-
trator on the device chooses which supply to use. T he
arbitrator can be considered to be diode OR’ing the posi-
tive supplies together (as shown in figure 1). In addition
to this, the diodes are supplemented with switches in a
synchronous rectifier manner, to minimise voltage loss.
T his loss can be reduced to ~0.2V, resulting in the ability
to power the ADM1060 from a supply as low as 3.0V.
Note that the supply on the VBn pins cannot be used to
power the device, even if the input on these pins is posi-
tive. Also, the minimum supply of 3.0V must appear on
one of the VPn pins in order to power up the ADM1060
correctly. A supply of no less than 4.5V can be used on
VH. T his is because there is no synchronous rectifier
circuit on the VH pin, resulting in a voltage drop of ~1.5V
across the diode of the VDD Arbitrator.
T he ADM1060 has seven programmable Supply Fault
Detectors, 1 high voltage detector (2V to 14.4V), 2 bipo-
lar detectors (2V to 6V, -2V to -6V) and 4 Positive only
voltage detectors (0.6V to 6V). Inputs are applied to these
detectors via the VH (High Voltage Supply input) pin,
VBn (Bipolar Supply input) pins and VPn (Positive Only
input) pins respectively. T he SFD’s detect a fault condi-
tion on any of these input supplies. A fault is defined as
Undervoltage (where the supply drops below a
preprogrammed level), Overvoltage (where the supply
rises above a preprogrammed level) or Out-of-Window
(where the supply deviates outside either the programmed
overvoltage OR undervoltage threshold). Only one fault
type can be selected at a time.
An Undervoltage fault is detected by comparing the input
supply to a programmed reference (the undervoltage
threshold). If the input voltage drops below the
undervoltage threshold the output of the comparator goes
high, asserting a fault. T he undervoltage threshold is
programmed using an 8 bit DAC. On a given range, the
UV threshold can be set with a resolution of:-
An external cap to GND is required to decouple the on-
chip supply from noise. T his cap should be connected to
the VDDCAP pin, as shown in figure 1. T he cap has
another use during “brown outs” (momentary loss of
power). Under these conditions, where the input supply,
VPn, dips transiently below VDD , the synchronous rectifier
switch immediately turns off so that it doesn’t pull VDD
down. T he VDD cap can then act like a reservoir and keep
the chip active until the next highest supply takes over the
powering of the device. 0.1F is recommended for this
function.
Step Size = Threshold Range/255
An Overvoltage (OV) fault is detected in exactly the same
way, using a second comparator and DAC to program the
reference.
All thresholds are programmed using 8 bit registers, one
register each for the 7 UV thresholds and 1 each for the 7
OV thresholds. T he UV or OV threshold programmed by
the user is given by:-
Note that in the case where there are 2 or more supplies
within 100mV of each other, the supply which takes con-
trol of VDD first will keep control (e.g) if VP1 is con-
nected to a 3.3V supply, then VDD will power up to
approximately 3.1V through VP1. If VP2 is then con-
nected to another 3.3V supply, VP1 will still power the
device, unless VP2 goes 100mV higher than VP1.
VT= VR x N + VB
255
where:-
VT = Desired T hreshold Voltage (UV or OV)
VR= T hreshold Voltage Range
N = Decimalized version of 8 bit code
VB = Bottom of T hreshold Range
VH
T his results in the code for a given threshold being given
by:-
N=255 x (VT- VB)/VR
T hus, for example, if the user wishes to set a 5V OV
threshold on VP1, the code to be programmed in the
PS1OVT H register (discussed later) would be given by:-
Limit current
VDDCAP pin
surge to VDDI/
decoupling cap
VP1
Off -chip
decoupling
capacitor
VP2
VP3
VP4
N=255 x ( 5-2)/4
VDDI
Fig u re 1. VDD Arb itra to r Op e ra tio n
REV. PrJ 11/02
–7 –
PRELIMINARY TECHNICAL DATA
ADM1060 INPUTS
ADM1060
T hus, N=192 (11000000 or C0H )
VH = Desired H ysteresis Voltage
T he available threshold ranges, and the resolution they are
programmed to are shown in table 1. Note that the low
end of the detection range is fixed to 33.33% of the top of
the range. Note also, that for a given SFD, the ranges
overlap (eg) VH goes from 2V to 6V then from 4.8V to
14.4V. T his is to provide better threshold setting resolu-
tion as supplies decrease in value.
NT H RESH = Decimalized version of 5 bit hysteresis code
T herefore, if the low range threshold detector was selected
(ie) 1V to 3V (VR), the max hysteresis is then defined as:-
(3V-1V) x 31/255 = 242mV (25-1 =31)
T he hysteresis programming resolution is the same as the
threshold detect ranges (ie) 37.5mV on the high range,
15.6mV on the mid range, 7.8mV on the low range and
4.7mV on the ultra low range.
Input Nam e
Voltage Ranges
Resolution
BIP O LAR SFD ’S
VH
4.8V to 14.4V
2V to 6V
37.6m V
15.6m V
T he 2 bipolar SFD’s also allow the detection of faults on
negative supplies. A polarity bit in the setup register for
this SFD (bit 7- register BSnSEL- see register map
overleaf) determines if a positive or negative input should
be applied to VBn. Only 1 range (-6V to -2V) is available
when the SFD’s are in negative mode. Note that the bi-
polar SFD’s cannot be used to power the ADM1060, even
if the voltage on VBn is positive.
VBn
VPn
2V to 6V
1V to 3V
-6V to -2V
2V to 6V
15.6mV (Pos. Mode)
7.8m V
“
15.6mV (Neg. Mode)
15.6m V
1V to 3V
7.8m V
0.6V to 1.8V
4.7m V
SFD FAULT TYP ES
Ta b le 1. In p u t th re s h o ld Ra n g e s a n d Re s o lu tio n
.
3 types of faults can be asserted by the SFD- 1) An OV
fault, 2) an UV fault and 3) an out-of-window fault (where
the UV and OV faults are OR’ed together). T he type of
fault required is programmed using the Fault T ype Select
bits (bits 0,1- Register _SnSEL). If an application re-
quires separate fault conditions to be detected on one sup-
ply (eg) assert PDO1 if an UV fault occurs on a 3.3V
supply, assert PDO9 if an OV fault occurs on the same
3.3V supply, that supply will need to be applied to more
than one input pin.
Figure 2 illustrates the function of the programmable
SFD (for the case of a positive supply).
VPn
RANGE SELECT
DAC (1- BIT)
OV
Comparator
Glitch Filter
FAULT
OUTPUT
VREF
GLITCH FILTERING O N TH E SFD ’S
T he final stage of the SFD is a glitch filter. T his block
provides time domain filtering on spurious transitions of
the SFD fault output. T hese could be caused by bounce
on a supply at its initial turn- on. T he comparators of the
SFD can have hysteresis digitally programmed into them
to ensure smooth transitions but further deglitching is
provided by the glitch filter stage. A fault must be as-
serted for greater than the programmed Glitch Filter
timeout before it is seen at the output of the glitch filter.
T he max. programmable timeout period is 100s. Both
edges of the input are filtered by the same amount of time,
so if the input pulse is longer than the glitch filter timeout
and is seen at the output, the length of the output pulse is
the same as the input pulse. If the input pulse is shorter
than the programmed timeout, then nothing appears at the
output. Figure 2 shows the implementation of glitch fil-
tering.
Fault Type
select
DUAL 8-BIT DAC
FOR SETTING UV
AND OV THRESHOLDS
UV
Comparator
Figure 2. Positive Program m able Supply Fault Detector
SFD CO MP ARATO R H YSTERESIS
T he OV and UV comparators, shown in figure 1, are al-
ways looking at VPn via a potential divider. In order to
avoid chattering (multiple transitions when the input is
very close to the threshold level set), these comparators
have digitally progammable hysteresis. T he UV and OV
hysteresis can be programmed in two registers which are
similar but separate to the UV or OV threshold registers.
Only the 5 LSB’s of these registers can be set.
T he
hysteresis is added after the supply voltage goes out of
tolerance. T hus, the user can determine how much above
the UV threshold the input must rise again before a UV
fault is de-asserted.
Similarly, the user can determine
how much below the OV threshold the input must fall
again before an OV fault is de-asserted. T he hysteresis
figure is given by:-
VH =VR x NTHRESH /255
where:-
REV. PrJ 11/02
–8 –
PRELIMINARY TECHNICAL DATA
ADM1060 INPUTS
ADM1060
P RO GRAMMING TH E SFD ’S O N TH E SMBUS
T he details of using the SMBus are described later, but
the register names associated with the Supply Fault Detec-
tor blocks, the bitmap of those registers, and the function
of each of the bits is described in the following tables.
T he tables show how to set up UV threshold, UV hyster-
esis, OV threshold, OV hysteresis, glitch filtering and
fault type for each of the SFD’s on the ADM1060.
GLITCH FILTER INPUT
PROGRAMMED TIMEOUT
PROGRAMMED TIMEOUT
T
T
GF
0
T
T
0
GF
T
T
GF
0
T
T
GF
0
GLITCH FILTER OUTPUT
Fig u re 3 . Glitch Filte rin g o n th e S FD’s
SFD REGISTER NAMES
TABLE 2. LIST O F REGISTERS FO R TH E SUP P LY FAULT D ETECTO RS
H ex
T able
Nam e
D efa u lt
D escr iption
Addr ess
P ower O n Value
A0
A1
A2
A3
A4
A8
A9
A A
A B
A C
B 0
B 1
B 2
B 3
B 4
B 8
B 9
B A
B B
B C
C 0
C 1
3
4
BS1 O VT H
BS1 O VH YST
BS1 U VT H
BS1 U VH YST
BS1 SE L
F F h
00h
00h
00h
00h
F F h
00h
00h
00h
00h
F F h
00h
00h
00h
00h
F F h
00h
00h
00h
00h
F F h
00h
Overvoltage T hreshold for Bipolar Voltage SFD 1 (BS1SFD )
Digital H ysteresis on OV threshold for BS1SFD
Undervoltage T hreshold for BS1SFD
5
6
Digital H ysteresis on UV threshold for BS1SFD
Glitch filter, Range and Fault T ype select for BS1SFD
Overvoltage T hreshold for Bipolar Voltage SFD 2 (BS2SFD )
Digital H ysteresis on OV threshold for BS2SFD
Undervoltage T hreshold for BS2SFD
7
3
BS2 O VT H
BS2 O VH YST
BS2 U VT H
BS2 U VH YST
BS2 SE L
4
5
6
Digital H ysteresis on UV threshold for BS2SFD
Glitch filter, Range and Fault T ype select for BS2SFD
7
8
H SO VT H
Overvoltage T hreshold for H igh Voltage SFD
Digital H ysteresis on OV threshold for H VSFD
Undervoltage T hreshold for H VSFD
(H VSF D )
9
H SO VH YST
H SU VT H
10
11
12
13
14
15
16
17
13
14
H SU VH YST
H SSE L
Digital H ysteresis on UV threshold for H VSFD
Glitch filter, Range and Fault T ype select for HVSFD
Overvoltage T hreshold for Positive Voltage SFD 1 (PS1SFD )
Digital H ysteresis on OV threshold for PS1SFD
Undervoltage T hreshold for PS1SFD
P S1 O VT H
P S1 O VH YST
P S1 U VT H
P S1 U VH YST
P S1 SE L
Digital H ysteresis on UV threshold for PS1SFD
Glitch filter, Range and Fault T ype select for PS1SFD
Overvoltage T hreshold for Positive Voltage SFD 2 (PS2SFD )
Digital H ysteresis on OV threshold for PS2SFD
P S2 O VT H
P S2 O VH YST
REV. PrJ 11/02
–9 –
PRELIMINARY TECHNICAL DATA
ADM1060 INPUTS
ADM1060
TABLE 2. LIST O F RE GISTE RS FO R TH E SUP P LY FAULT D E TE C TO RS (C ontd.)
H ex
T able
Nam e
D efa u lt
D escr iption
Addr ess
P ower O n Value
C 2
C 3
C 4
C 8
C 9
C A
C B
C C
D 0
D 1
D 2
D 3
D 4
15
16
17
13
14
15
16
17
13
14
15
16
17
P S2 U VT H
P S2 U VH YST
P S2 SE L
00h
00h
00h
F F h
00h
00h
00h
00h
F F h
00h
00h
00h
00h
Undervoltage T hreshold for PS2SFD
Digital H ysteresis on UV threshold for PS2SFD
Glitch filter, Range and Fault T ype select for PS2SFD
Overvoltage T hreshold for Positive Voltage SFD 3 (PS3SFD )
Digital H ysteresis on OV threshold for PS3SFD
Undervoltage T hreshold for PS3SFD
P S3 O VT H
P S3 O VH YST
P S3 U VT H
P S3 U VH YST
P S3 SE L
Digital H ysteresis on UV threshold for PS3SFD
Glitch filter, Range and Fault T ype select for PS3SFD
Overvoltage T hreshold for Positive Voltage SFD 4 (PS4SFD )
Digital H ysteresis on OV threshold for PS4SFD
Undervoltage T hreshold for PS4SFD
P S4 O VT H
P S4 O VH YST
P S4 U VT H
P S4 U VH YST
P S4 SE L
Digital H ysteresis on UV threshold for PS4SFD
Glitch filter, Range and Fault T ype select for PS4SFD
REV. PrJ 11/02
–1 0 –
PRELIMINARY TECHNICAL DATA
ADM1060 INPUTS
ADM1060
SFD REGISTER BITMAPS
BIP O LAR SUP P LY FAIL D ETECT (BSnSFD ) REGISTERS
TABLE 3. RE GISTE R A0H ,A8H BSnO VTH (P O WE R- O N D E FAULT FFH )
Bit
Nam e
R/W
D escr iption
7-0
O V7 -O V0
R /W
8 bit digital value for overvoltage threshold on BSn SFD.
TABLE 4. RE GISTE R A1H ,A9H BSnO VH YST (P O WE R- O N D E FAULT 00H )
Bit
Nam e
R/W
D escr iption
7-5
4-0
Reserved
N /A
R /W
Cannot be used
H Y4-H Y0
5 bit digital value for hysteresis on OV threshold of BSn SFD
TABLE 5. RE GISTE R A2H ,AAH BSnUVTH (P O WE R- O N D E FAULT 00H )
Bit
Nam e
R/W
D escr iption
7-0
U V7-U V0
R /W
8 bit digital value for undervoltage threshold on BSn SFD
TABLE 6. RE GISTE R A3H ,ABH BSn UVH YST (P O WE R- O N D E FAULT 00H )
Bit
Nam e
R/W
D escr iption
7-5
4-0
Reserved
N /A
R /W
Cannot be used
H Y4-H Y0
5 bit digital value for hysteresis on UV threshold of BSn SFD
TABLE 7. REGISTER A4H ,ACH BSnSEL (P O WER- O N D EFAULT 00H )
Bit
Nam e
R/W
D escr iption
7
P O L
R /W
Polarity of Bipolar SFDn
P O L
Sign of D etection Range
0
Positive
1
N egative
6-4
G F 2-G F 0
R /W
GF2
GF1
GF0
Glitch Filter D elay (s)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
5
10
20
30
50
75
100
3
2
Reserved
RSE L
N /A
R /W
Cannot be used
Note: When POL is set to 1 (ie) SFD is in negative mode, then
RSEL is unused since there is only one range in this mode.
R S E L1 Bottom of
R a n ge
Top of
R a n ge
3 V
Step Size (m V)
0
1
1 V
2 V
7.8
6 V
15.6
1-0
F S1-F S0
R /W
FS1
FS0
Fault Select Type
O vervoltage
0
0
1
1
0
1
0
1
U ndervoltage
O ut-of-Window
N ot Allowed
REV. PrJ 11/02
–1 1 –
PRELIMINARY TECHNICAL DATA
ADM1060 INPUTS
ADM1060
HIGHVOLTAGE SUP P LYFAULT DETECT (HVSFD) REGISTERS
TABLE 8. RE GISTE R B0H H SO VTH (P O WE R- O N D E FAULT FFH )
Bit
Nam e
R/W
D escr iption
7-0
O V7 -O V0
R /W
8 bit digital value for overvoltage threshold on HV SFD.
TABLE 9. RE GISTE R B1H H SO VH YST (P O WE R- O N D E FAULT 00H )
Bit
Nam e
R/W
D escr iption
7-5
4-0
Reserved
N /A
R /W
Cannot be used
H Y4-H Y0
5 bit digital value for hysteresis on OV threshold of HV SFD
TABLE 10. RE GISTE R B2H H SUVTH (P O WE R- O N D E FAULT 00H )
Bit
Nam e
R/W
D escr iption
7-0
U V7-U V0
R /W
8 bit digital value for undervoltage threshold on HV SFD
TABLE 11. REGISTER B3H H SUVH YST (P O WER- O N D EFAULT 00H )
Bit
Nam e
R/W
D escr iption
7-5
4-0
Reserved
N /A
R /W
Cannot be used
H Y4-H Y0
5 bit digital value for hysteresis on UV threshold of HV SFD
TABLE 12. RE GISTE R B4H H SSE L (P O WE R- O N D E FAULT 00H )
Bit
Nam e
R/W
D escr iption
7
Reserved
N /A
R /W
Cannot be used
6-4
G F 2-G F 0
GF2
GF1
GF0
Glitch Filter D elay (s)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
5
10
20
30
50
75
100
3
2
Reserved
RSE L
N /A
W
Cannot be used
R S E L
Bottom of
Top of
R a n ge
6 V
Step Size (m V)
R a n ge
2 V
0
1
15.6
37.6
4.8V
14.4V
1-0
F S1-F S0
W
FS1
FS0
Fault Select Type
O vervoltage
0
0
1
1
0
1
0
1
U ndervoltage
O ut-of-Window
N ot Allowed
REV. PrJ 11/02
–1 2 –
PRELIMINARY TECHNICAL DATA
ADM1060 INPUTS
ADM1060
P O SITIVE VO LTAGE SUP P LY FAULT D ETECT (P SNSFD ) REGISTERS
T ABLE 13. RE GIST E R B8H ,C 0H ,C 8H ,D 0H P SNO VT H (P O WE R- O N D E F AULT F F H )
Bit
Nam e
R/W
D escr iption
7-0
O V7 -O V0
R /W
8 bit digital value for overvoltage threshold on PSn SFD.
T ABLE 14. RE GIST E R B9H ,C 1H ,C 9H ,D 1H P SnO VH YST (P O WE R- O N D E F AULT 00H )
Bit
Nam e
R/W
D escr iption
7-5
4-0
Reserved
N /A
R /W
Cannot be used
H Y4-H Y0
5 bit digital value for hysteresis on OV threshold of PSn SFD
TABLE 15. RE GISTE R BAH ,C 2H ,C AH ,D 2H P Sn UVTH (P O WE R- O N D E F AULT 00H )
Bit
Nam e
W
D escr iption
7-0
U V7-U V0
R /W
8 bit digital value for undervoltage threshold on PSn SFD
T ABLE 16. RE GIST E R BBH ,C 3H ,C BH ,D 3H P Sn UVH YST (P O WE R- O N D E F AULT 00H )
Bit
Nam e
W
D escr iption
7-5
4-0
Reserved
N /A
R /W
Cannot be used
H Y4-H Y0
5 bit digital value for hysteresis on UV threshold of PSn SFD
TABLE 17. RE GISTE R BC H ,C 4H ,C C H ,D 4H P SnSE L (P O WE R- O N D E FAULT 00H )
Bit
Nam e
R/W
D escr iption
7
Reserved
N /A
R /W
Cannot be used
6-4
G F 2-G F 0
GF2
GF1
GF0
Glitch Filter D elay (s)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
5
10
20
30
50
75
100
3-2
1-0
RSEL1-RESL0
R /W
R /W
R S E L1 R S E L0 Bottom of
R a n ge
Top of
R a n ge
6 V
Step Size (m V)
0
0
1
0
2 V
15.6
7.8
1
1 V
3 V
X
0.6V
1.8V
4.7
F S1-F S0
FS1
FS0
Fault Select Type
O vervoltage
0
0
1
1
0
1
0
1
U ndervoltage
O ut-of-Window
N ot Allowed
REV. PrJ 11/02
–1 3 –
PRELIMINARY TECHNICAL DATA
ADM1060
ADM1060 INPUTS
WAT C H D O G F AU LT D E T E C T O R
can also be inverted, if required (eg) if a high- low- high
pulse was required by a processor to reset. T hus, a fault
on the watchdog can be used to generate a pulsed or
latched output on any or all of the 9 PDO’s.
T he latched signal can be cleared low by reading LAT F1,
then LAT F2 across the SMBus interface (see Fault Regis-
ters section). T he RAM register list and the bit map for
the Watchdog Fault Detector are shown below.
T he ADM1060 has a Watchdog Fault Detector. T his can
be used to monitor a processor clock to ensure normal
operation. T he detector monitors the WDI pin, expecting
there to be a low-to-high or high to low transition within a
preprogrammed period. T he watchdog timeout period
can be programmed from 200msec to a maximum of
12.8sec.
If no transition is detected, 2 signals are asserted. One is
a latched high signal, indicating a fault has occurred. T he
other signal is a low- high- low pulse which can be used as
a RESET signal for a processor core. T he width of this
pulse can be programmed (from 10s to a maximum of
10ms). T hese two Watchdog signals can be selected as
inputs to each of the PLB’s (see PLBA section). T hey
TABLE 18. LIST O F RE GISTE RS FO R WATC H D O G FAULT D E TE C TO R
H ex
T able
Nam e
D efa u lt
D escr iption
Addr ess
P ower O n Value
9 C
19
W D C F G
00h
Program length Watchdog timeout and length of pulsed output
TABLE 19. RE GISTE R 9C H WD C FG (P O WE R- O N D E FAULT 00H )
Bit
Nam e
R/W
D escr iption
7-5
4-3
Reserved
R /W
R /W
U nused
P U LS1-P U LS0
Length of pulse outputted once the Watchdog Detector has timed out
P U L S 1 P U L S 0 P ulse Length Selected
(s)
0
0
1
1
0
1
0
1
10
100
1000
10000
2-0
P ER3-P ER0
R /W
Watchdog T imeout Period
P E R 2
P E R 1
P E R 0
Watch dog T im eou t selected (m s)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
D isabled
200
400
800
1600
3200
6400
12800
REV. PrJ 11/02
–1 4 –
PRELIMINARY TECHNICAL DATA
ADM1060 INPUTS
ADM1060
filter can be used to debounce a Manual Reset switch.
T he length of the glitch filter can also be programmed.
G E NE RAL P URP O SE INP UT S (G P I’S)
T he ADM1060 has 4 General Purpose Logic Inputs
(GPI’s). T hese are T T L/CMOS logic level compatible.
Standard logic signals can be applied to the pins (eg)
RESET from reset generators, PWRGOOD signals, Fault
flags, Manual Resets etc. T hese signals can be gated with
the other inputs supervised by the ADM1060, and used to
control the status of the PDO’s. T he inputs can be simply
buffered, or a logic transition can be detected and a pulse
output generated. T he width of this pulse is
programmable from 10s to a maximum of 10ms. T he
configuration of the GPI’s is shown in the register and
bitmaps below.
T he GPI’s also feature a glitch filter, similar to that
provided on the SFD’s. T his enables the user to ignore
spurious transitions on the GPI’s. For example, the glitch
LO GIC STATE O F TH E GP I’S (AND O TH E R LO GIC
I N P U T S )
Each of the GPI’s has a weak (10A) pull-down current
source. T he current sources can be connected to the
inputs by progamming the relevant bit in a register
(PDEN). T his enables the user to control the condition
of these inputs, pulling them to GND, even when they are
unused or left floating.
Note that the same pull- down function is provided for the
SMBus address pins, A0 and A1 and for the WDI pin.
register is used to program which of the inputs is
connected to the current sources.
A
TABLE 20. LIST O F REGISTERS FO R TH E GENERAL P URP O SE INP UTS (GP IN)
H ex
T able
Nam e
D efa u lt
D escr iption
Addr ess
P ower O n Value
98
99
G P I4C F G
G P I3C F G
G P I2C F G
G P I1C F G
00h
00h
00h
00h
Setup of the glitch filter delay, pulse width, level/edge
detection etc. configuration of GPI4
Setup of the glitch filter delay, pulse width, level/edge
detection etc. configuration of GPI3
9 A
9 B
Setup of the glitch filter delay, pulse width, level/edge
detection etc. configuration of GPI2
Setup of the glitch filter delay, pulse width, level/edge
detection etc. configuration of GPI1
TABLE 21. BIT MAP FO R GP InC FG RE GISTE RS (P O WE R- O N D E FAULT 00H )
Bit
Nam e
R/W
D escr iption
7
6
5
Reserved
IN VIN
N /A
R /W
R /W
Cannot be used
If high, invert Input
IN T YP
Determines whether a level or an edge is detected on the pin. If an edge
is detected then positive pulse of programmable length is outputted
INT YP
D e t e c t
0
1
Detect level
D etect edge
4-3
P U L S1-0
R /W
Length of pulse outputted once an edge has been detected on input
P U L S 1 P U L S 0 P ulse Length Selected s)
(
0
0
1
1
0
1
0
1
10
100
1000
10000
2-0
G F 2-G F 0
R /W
Length of time for which the input is ignored
GF2
GF1
GF0
Glitch Filter D elay (s)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
5
10
20
30
50
75
100
REV. PrJ 11/02
–1 5 –
PRELIMINARY TECHNICAL DATA
ADM1060 INPUTS
ADM1060
TABLE 22. LIST O F RE GISTE RS FO R TH E P ULL- D O WN C URRE NT SO URC E S O N LO GIC INP UTS
H ex
T able
Nam e
D efa u lt
D escr iption
Addr ess
P ower O n Value
91
P D EN
00h
Setup of the Pull- down current sources on all logic
inputs. Pulls the selected input to GND
TABLE 23. BIT MAP FO R P D EN REGISTER- 91H (P O WER- O N D EFAULT 00H )
Bit
Nam e
R/W
D escr iption
7
6
Reserved
N /A
R /W
Cannot be used
P D E N A1
If high, then address pin A1 is pulled to GND using a 10uA pull- down
current source.
5
4
3
2
1
0
P D E N A0
P D E N WD I
P D EN G P I4
P D EN G P I3
P D EN G P I2
P D EN G P I1
R /W
R /W
R /W
R /W
R /W
R /W
If high, then address pin A0 is pulled to GND using a 10uA pull- down
current source.
If high, then WDI is pulled to GND using a 10A pull- down
current source.
If high, then GPI4 is pulled to GND using a 10A pull- down
current source.
If high, then GPI3 is pulled to GND using a 10A pull- down
current source.
If high, then GPI2 is pulled to GND using a 10A pull- down
current source.
If high, then GPI1 is pulled to GND using a 10A pull- down
current source.
REV. PrJ 11/02
–1 6 –
PRELIMINARY TECHNICAL DATA
PROGRAMMING ADM1060
ADM1060
inverting gate shown is an X-OR gate, resulting in the
following truth table:-
P RO G RAM M ABLE LO G IC BLO C K ARRAY
T he ADM1060 contains a Programmable Logic Block
Array (PLBA). T his block is the logical core of the
device. T he PLBA (and the PDBs- see next section) is
what provides the sequencing function of the ADM1060.
T he assertion of the 9 Programmable Driver Outputs
(PDO) is controlled by the PLBA. T he PLBA comprises
of 9 macrocells, 1 per PDO Channel. T he main
P O L
INP UT SIGNAL
X-O R O UTP UT
0
0
1
1
0
1
0
1
0
1
1
0
Table 25. Truth Table for PLB Input Inversion
components of the macrocells are 2 Wide AND- OR
gates, as shown in Figure 4. Each AND gate represents a
function (A and B) which can be used independently to
control the assertion of the PDO pin. T here are 21 inputs
to each of these AND gates. T hese are:-
T he last 2 entries in the truth table show, that with the
INVERT bit set, the X-OR output is always the inverse of
the input.
Similarly, the ignore gate shown is an OR gate, resulting
in the following truth table:-
• T he logic outputs of all 7 of the Supply Fault Detectors
• T he 4 GPI logic inputs
IMK
INP UT SIGNAL
O R O UTP UT
0
0
1
1
0
1
0
1
0
1
1
1
• T he Watchdog fault detector (Latched and Pulsed)
• T he delayed output of any of the other macrocells (the
output of a macrocell cannot be an input to itself, since
this would result in a non- terminating loop).
Table 26 Truth Table for PLB Input Masking
It can be seen here that once the IMK bit is set the OR
output is always 1, regardless of the input, thus ignoring
it. Overleaf is a detailed diagram of the 21 inputs and the
registers required to program them. T hose shown are just
for function A of PLB1 but function B and all of the
functions in the other 8 PLB’s are programmed exactly the
same way. An Enable register allows the user to use
function A or B or both. T he output of functions A and/
or B is inputted to a Programmable Delay Block (PDB)
where a delay can be programmed on both the rising and
falling edge of an input (see next section). T he output of
this PDB block can be progammed to invert before one or
any of the PDO pins is asserted.
All 21 inputs are hardwired to both function A and
function B AND gates. T he user can then select which of
these inputs controls the output. T his is done using 2
control signals, IMK (a masking bit, setting it ignores the
relevant input) and POL (a polarity bit, setting it inverts
the input before it is applied to the AND gate). T he effect
of setting these bits can be seen in figure 4 below. T he
SIGNAL INPUTS
POL (INVERT)
T he control bits for these macrocells are stored locally in
latches which are loaded at power up. T hese latches can
also be updated via the serial interface. T he registers
containing the macrocell control bits, and the function of
each bit are defined in the tables overleaf.
ENABLE
FUNCTION A
IMK ( IGNORE)
PROGRAMMABLE
2 wide AND gates
(20 inputs)
DELAY
BLOCK
PLBOUT
INVERT
OUTPUT
ENABLE
FUNCTION B
Figure 4. Sim plified Program m able Logic Block Macrocell Schem atic
–1 7 –
REV. PrJ 11/02
PRELIMINARY TECHNICAL DATA
ADM1060 LOGIC
ADM1060
T he diagram shown highlights all 21 inputs to a given
function and the register/ bits which need to be set in
order to condition the 21 inputs correctly. T he diagram
only shows function A of Programmable Logic Block 1
(PLB1) but all functions are programmed in the same way.
(ie) Not Connected
PLB1
If, as an example, the user wishes to assert PLBOUT
200ms after all of the supplies are in spec. (PLBOUT may
be used to drive the enable pin of an LDO) then the
supply fault detectors VBn, VH and VPn are required to
control the function. T he function is programmed as
follows:-
PLB2
PLB3
PLB4
PLB5
PLB6
PLB7
INVERT 00H P1PLBPOLA.0
01H P1PLBIMKA.0
IGNORE
INVERT 00H P1PLBPOLA.1
01H P1PLBIMKA.1
IGNORE
INVERT 00H P1PLBPOLA.2
01H P1PLBIMKA.2
• T he IGNORE bit of all the other inputs (GPI’s, PDB’s
WDI) in the relevant P1xxxIMK registers is set to 1.
T hus, regardless of their status, the input to the function
AND gate for these inputs will be 1.
IGNORE
INVERT 00H P1PLBPOLA.3
01H P1PLBIMKA.3
IGNORE
• Since the SFD’s assert a 1 under a fault condition and a
0 when the supplies are in tolerance, the SFD outputs
need to be inverted before being applied to the function.
T hus the relevant bit in the P1SFDPOL register is set
(See T able Y).
INVERT 00H P1PLBPOLA.4
01H P1PLBIMKA.4
IGNORE
INVERT 00H P1PLBPOLA.5
01H P1PLBIMKA.5
PLB8 IGNORE
INVERT 00H P1PLBPOLA.6
01H P1PLBIMKA.6
• T he function is enabled (bit 1 of register P1EN- T able
IGNORE
PLB9
Z))
INVERT 00H P1PLBPOLA.7
• A rise time of 200ms is programmed (register
01H P1PLBIMKA.7
IGNORE
P1PDBT IM- see register map overleaf for details)
VB1
INVERT 02H P1SFDPOLA.0
03H P1SFDIMKA.0
IGNORE
ENABLE
FUNCTION A
VB2
VH
07H P1EN.1
RISE TIME
INVERT 02H P1SFDPOLA.1
03H P1SFDIMKA.1
IGNORE
0CH P1PDBTIM.7-4
INVERT 02H P1SFDPOLA.2
03H P1SFDIMKA.2
IGNORE
PDB
PLBOUT
VP1
VP2
VP3
VP4
INVERT 02H P1SFDPOLA.3
03H P1SFDIMKA.3
0CH P1PDBTIM.3-0
IGNORE
TO
FALL TIME
FUNCTION B
07H P1EN.2
INVERT 02H P1SFDPOLA.4
03H P1SFDIMKA.4
IGNORE
INVERT 02H P1SFDPOLA.5
03H P1SFDIMKA.5
IGNORE
INVERT 02H P1SFDPOLA.6
03H P1SFDIMKA.6
IGNORE
GPI1
GPI2
GPI3
GPI4
INVERT 04H P1GPIPOL.4
05H P1GPIIMK.4
IGNORE
INVERT 04H P1GPIPOL.5
05H P1GPIIMK.5
IGNORE
INVERT 04H P1GPIPOL.6
05H P1GPIIMK.6
IGNORE
INVERT 04H P1GPIPOL.7
05H P1GPIIMK.7
IGNORE
WDI_P
WDI_L
INVERT 06H P1WDICFG.7
06H P1WDICFG.6
IGNORE
INVERT 06H P1WDICFG.5
06H P1WDICFG.4
IGNORE
Figure 5. Detailed Diagram for function A of PLB1
REV. PrJ 11/02
–1 8 –
PRELIMINARY TECHNICAL DATA
ADM1060 LOGIC
ADM1060
PLBAREGISTER NAMES
TABLE 27. LIST O F RE GISTE RS FO R TH E P RO GRAMMABLE LO GIC BLO C K ARRAY (P LBA)
H ex
T able
Nam e
D efa u lt
D escr iption
Addr ess
P ower O n Value
00
01
02
03
04
05
06
28
29
30
31
32
33
34
P 1P L BP O L A
P 1P L BIM K A
P 1SF D P O L A
P 1SF D IM K A
P 1G P IP O L
00h
00h
00h
00h
00h
00h
00h
Polarity Sense for all 8 other PLB outputs when used as
inputs to the A function of PLB1
Ignore Mask for all 8 other PLB outputs when used as
inputs to the A function of PLB1
Polarity Sense for all 7 SFD inputs (VH, 2 VB, 4 VP’s) to
the A function of PLB1
Ignore Mask for all 7 SFD inputs (VH, 2 VB, 4 VP’s) to
the A function of PLB1
Polarity Sense and Ignore Mask bits for all 4 GPI’s when
used as inputs to the A function of PLB1
P 1G P IIM K
Polarity Sense and Ignore Mask bits for all 4 GPI’s when
used as inputs to the B function of PLB1
P 1W D IC F G
Polarity Sense and Ignore Mask bits for the pulsed and
latched outputs of the watchdog detector when used as
inputs to both A and B functions of PLB1
07
08
09
0 A
0 B
10
11
12
13
14
15
16
35
28
29
30
31
28
29
30
31
32
33
34
P S1 E N
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
Enable bits for A and B functions of PLB1, polarity bit
for PLB1 output
P 1P L BP O L B
P 1P L BIM K B
P 1SF D P O L B
P 1 SF D IM K B
P 2P L BP O L A
P 2P L BIM K A
P 2SF D P O L A
P 2SF D IM K A
P 2G P IP O L
Polarity Sense for all 8 other PLB outputs when used as
inputs to the B function of PLB1
Ignore Mask for all 8 other PLB outputs when used as
inputs to the B function of PLB1
Polarity Sense for all 7 SFD inputs (VH, 2 VB, 4 VP’s) to
the B function of PLB1
Ignore Mask for all 7 SFD inputs (VH, 2 VB, 4 VP’s) to
the B function of PLB1
Polarity Sense for all 8 other PLB outputs when used as
inputs to the A function of PLB2
Ignore Mask for all 8 other PLB outputs when used as
inputs to the A function of PLB2
Polarity Sense for all 7 SFD inputs (VH, 2 VB, 4 VP’s) to
the A function of PLB2
Ignore Mask for all 7 SFD inputs (VH, 2 VB, 4 VP’s) to
the A function of PLB2
Polarity Sense and Ignore Mask bits for all 4 GPI’s when
used as inputs to the A function of PLB2
P 2G P IIM K
Polarity Sense and Ignore Mask bits for all 4 GPI’s when
used as inputs to the B function of PLB2
P 2W D IC F G
Polarity Sense and Ignore Mask bits for the pulsed and
latched outputs of the watchdog detector when used as
inputs to both A and B functions of PLB2
17
18
35
28
P S2 E N
00h
00h
Enable bits for A and B functions of PLB2, polarity bit
for PLB2 output
P 2P L BP O L B
Polarity Sense for all 8 other PLB outputs when used as
inputs to the B function of PLB2
REV. PrJ 11/02
–1 9 –
PRELIMINARY TECHNICAL DATA
ADM1060 LOGIC
ADM1060
TABLE 27. LIST O F RE GISTE RS FO R TH E P RO GRAMMABLE LO GIC BLO C K ARRAY (P LBA) (C ontd.)
H ex
T able
Nam e
D efa u lt
D escr iption
Addr ess
P ower O n Value
19
1 A
1 B
20
21
22
23
24
25
26
29
P 2P L BIM K B
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
Ignore Mask for all 8 other PLB outputs when used as
inputs to the B function of PLB2
30
31
28
29
30
31
32
33
34
P 2SF D P O L B
P 2 SF D IM K B
P 3P L BP O L A
P 3P L BIM K A
P 3SF D P O L A
P 3SF D IM K A
P 3G P IP O L
Polarity Sense for all 7 SFD inputs (VH, 2 VB, 4 VP’s) to
the B function of PLB2
Ignore Mask for all 7 SFD inputs (VH, 2 VB, 4 VP’s) to
the B function of PLB2
Polarity Sense for all 8 other PLB outputs when used as
inputs to the A function of PLB3
Ignore Mask for all 8 other PLB outputs when used as
inputs to the A function of PLB3
Polarity Sense for all 7 SFD inputs (VH, 2 VB, 4 VP’s) to
the A function of PLB3
Ignore Mask for all 7 SFD inputs (VH, 2 VB, 4 VP’s) to
the A function of PLB3
Polarity Sense and Ignore Mask bits for all 4 GPI’s when
used as inputs to the A function of PLB3
P 3G P IIM K
Polarity Sense and Ignore Mask bits for all 4 GPI’s when
used as inputs to the B function of PLB3
P 3W D IC F G
Polarity Sense and Ignore Mask bits for the pulsed and
latched outputs of the watchdog detector when used as
inputs to both A and B functions of PLB3
27
28
29
2 A
2 B
30
31
32
33
34
35
36
35
28
29
30
31
28
29
30
31
32
33
34
P S3 E N
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
Enable bits for A and B functions of PLB3, polarity bit
for PLB3 output
P 3P L BP O L B
P 3P L BIM K B
P 3SF D P O L B
P 3 SF D IM K B
P 4P L BP O L A
P 4P L BIM K A
P 4SF D P O L A
P 4SF D IM K A
P 4G P IP O L
Polarity Sense for all 8 other PLB outputs when used as
inputs to the B function of PLB3
Ignore Mask for all 8 other PLB outputs when used as
inputs to the B function of PLB3
Polarity Sense for all 7 SFD inputs (VH, 2 VB, 4 VP’s) to
the B function of PLB3
Ignore Mask for all 7 SFD inputs (VH, 2 VB, 4 VP’s) to
the B function of PLB3
Polarity Sense for all 8 other PLB outputs when used as
inputs to the A function of PLB1
Ignore Mask for all 8 other PLB outputs when used as
inputs to the A function of PLB1
Polarity Sense for all 7 SFD inputs (VH, 2 VB, 4 VP’s) to
the A function of PLB1
Ignore Mask for all 7 SFD inputs (VH, 2 VB, 4 VP’s) to
the A function of PLB1
Polarity Sense and Ignore Mask bits for all 4 GPI’s when
used as inputs to the A function of PLB1
P 4G P IIM K
Polarity Sense and Ignore Mask bits for all 4 GPI’s when
used as inputs to the B function of PLB1
P 4W D IC F G
Polarity Sense and Ignore Mask bits for the pulsed and
latched outputs of the watchdog detector when used as
inputs to both A and B functions of PLB4
37
35
P S4 E N
00h
Enable bits for A and B functions of PLB4, polarity bit
for PLB4 output
REV. PrJ 11/02
–2 0 –
PRELIMINARY TECHNICAL DATA
ADM1060 LOGIC
ADM1060
TABLE 27. LIST O F RE GISTE RS FO R TH E P RO GRAMMABLE LO GIC BLO C K ARRAY (P LBA) (C ontd.)
H ex
Addr ess
38
T able
Nam e
D efa u lt
P ower O n Value
00h
D escr iption
28
P 4P L BP O L B
Polarity Sense for all 8 other PLB outputs when used as
inputs to the B function of PLB4
39
3 A
3 B
40
41
42
43
44
45
46
29
30
31
28
29
30
31
32
33
34
P 4P L BIM K B
P 4SF D P O L B
P 4 SF D IM K B
P 5P L BP O L A
P 5P L BIM K A
P 5SF D P O L A
P 5SF D IM K A
P 5G P IP O L
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
Ignore Mask for all 8 other PLB outputs when used as
inputs to the B function of PLB4
Polarity Sense for all 7 SFD inputs (VH, 2 VB, 4 VP’s) to
the B function of PLB4
Ignore Mask for all 7 SFD inputs (VH, 2 VB, 4 VP’s) to
the B function of PLB4
Polarity Sense for all 8 other PLB outputs when used as
inputs to the A function of PLB5
Ignore Mask for all 8 other PLB outputs when used as
inputs to the A function of PLB5
Polarity Sense for all 7 SFD inputs (VH, 2 VB, 4 VP’s) to
the A function of PLB5
Ignore Mask for all 7 SFD inputs (VH, 2 VB, 4 VP’s) to
the A function of PLB5
Polarity Sense and Ignore Mask bits for all 4 GPI’s when
used as inputs to the A function of PLB5
P 5G P IIM K
Polarity Sense and Ignore Mask bits for all 4 GPI’s when
used as inputs to the B function of PLB5
P 5W D IC F G
Polarity Sense and Ignore Mask bits for the pulsed and
latched outputs of the watchdog detector when used as
inputs to both A and B functions of PLB5
47
48
49
4 A
4 B
50
51
52
53
54
55
35
28
29
30
31
28
29
30
31
32
33
P S5 E N
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
Enable bits for A and B functions of PLB5, polarity bit
for PLB5 output
P 5P L BP O L B
P 5P L BIM K B
P 5SF D P O L B
P 5 SF D IM K B
P 6P L BP O L A
P 6P L BIM K A
P 6SF D P O L A
P 6SF D IM K A
P 6G P IP O L
Polarity Sense for all 8 other PLB outputs when used as
inputs to the B function of PLB5
Ignore Mask for all 8 other PLB outputs when used as
inputs to the B function of PLB5
Polarity Sense for all 7 SFD inputs (VH, 2 VB, 4 VP’s) to
the B function of PLB5
Ignore Mask for all 7 SFD inputs (VH, 2 VB, 4 VP’s) to
the B function of PLB5
Polarity Sense for all 8 other PLB outputs when used as
inputs to the A function of PLB6
Ignore Mask for all 8 other PLB outputs when used as
inputs to the A function of PLB6
Polarity Sense for all 7 SFD inputs (VH, 2 VB, 4 VP’s) to
the A function of PLB6
Ignore Mask for all 7 SFD inputs (VH, 2 VB, 4 VP’s) to
the A function of PLB6
Polarity Sense and Ignore Mask bits for all 4 GPI’s when
used as inputs to the A function of PLB6
P 6G P IIM K
Polarity Sense and Ignore Mask bits for all 4 GPI’s
when
used as inputs to the B function of PLB6
H ex
T able
Nam e
D efa u lt
D escr iption
Addr ess
P ower O n Value
REV. PrJ 11/02
–2 1 –
PRELIMINARY TECHNICAL DATA
ADM1060 LOGIC
ADM1060
TABLE 27. LIST O F RE GISTE RS FO R TH E P RO GRAMMABLE LO GIC BLO C K ARRAY (P LBA) (C ontd.)
H ex
Table
Nam e
D efa u lt
D escr iption
Addr ess
P ower O n Value
56
34
P 6W D IC F G
00h
Polarity Sense and Ignore Mask bits for the pulsed and
latched outputs of the watchdog detector when used as
inputs to both A and B functions of PLB6
57
58
59
5 A
5 B
60
61
62
63
64
65
66
35
28
29
30
31
28
29
30
31
32
33
34
P S6 E N
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
Enable bits for A and B functions of PLB6, polarity bit
for PLB6 output
P 6P L BP O L B
P 6P L BIM K B
P 6SF D P O L B
P 6 SF D IM K B
P 7P L BP O L A
P 7P L BIM K A
P 7SF D P O L A
P 7SF D IM K A
P 7G P IP O L
Polarity Sense for all 8 other PLB outputs when used as
inputs to the B function of PLB6
Ignore Mask for all 8 other PLB outputs when used as
inputs to the B function of PLB6
Polarity Sense for all 7 SFD inputs (VH, 2 VB, 4 VP’s) to
the B function of PLB6
Ignore Mask for all 7 SFD inputs (VH, 2 VB, 4 VP’s) to
the B function of PLB6
Polarity Sense for all 8 other PLB outputs when used as
inputs to the A function of PLB7
Ignore Mask for all 8 other PLB outputs when used as
inputs to the A function of PLB7
Polarity Sense for all 7 SFD inputs (VH, 2 VB, 4 VP’s) to
the A function of PLB7
Ignore Mask for all 7 SFD inputs (VH, 2 VB, 4 VP’s) to
the A function of PLB7
Polarity Sense and Ignore Mask bits for all 4 GPI’s when
used as inputs to the A function of PLB7
P 7G P IIM K
Polarity Sense and Ignore Mask bits for all 4 GPI’s when
used as inputs to the B function of PLB7
P 7W D IC F G
Polarity Sense and Ignore Mask bits for the pulsed and
latched outputs of the watchdog detector when used as
inputs to both A and B functions of PLB7
67
68
69
6 A
6 B
70
71
72
73
74
35
28
29
30
31
28
29
30
31
32
P S7 E N
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
Enable bits for A and B functions of PLB7, polarity bit
for PLB7 output
P 7P L BP O L B
P 7P L BIM K B
P 7SF D P O L B
P 7 SF D IM K B
P 8P L BP O L A
P 8P L BIM K A
P 8SF D P O L A
P 8SF D IM K A
P 8G P IP O L
Polarity Sense for all 8 other PLB outputs when used as
inputs to the B function of PLB7
Ignore Mask for all 8 other PLB outputs when used as
inputs to the B function of PLB7
Polarity Sense for all 7 SFD inputs (VH, 2 VB, 4 VP’s) to
the B function of PLB7
Ignore Mask for all 7 SFD inputs (VH, 2 VB, 4 VP’s) to
the B function of PLB7
Polarity Sense for all 8 other PLB outputs when used as
inputs to the A function of PLB8
Ignore Mask for all 8 other PLB outputs when used as
inputs to the A function of PLB8
Polarity Sense for all 7 SFD inputs (VH, 2 VB, 4 VP’s) to
the A function of PLB8
Ignore Mask for all 7 SFD inputs (VH, 2 VB, 4 VP’s) to
the A function of PLB8
Polarity Sense and Ignore Mask bits for all 4 GPI’s when
used as inputs to the A function of PLB8
REV. PrJ 11/02
–2 2 –
PRELIMINARY TECHNICAL DATA
ADM1060 LOGIC
ADM1060
TABLE 27. LIST O F RE GISTE RS FO R TH E P RO GRAMMABLE LO GIC BLO C K ARRAY (P LBA) (C ontd.)
H ex
T able
Nam e
D efa u lt
D escr iption
Addr ess
P ower O n Value
75
33
P 8G P IIM K
00h
Polarity Sense and Ignore Mask bits for all 4 GPI’s when
used as inputs to the B function of PLB8
76
34
P 8W D IC F G
00h
Polarity Sense and Ignore Mask bits for the pulsed and
latched outputs of the watchdog detector when used as
inputs to both A and B functions of PLB8
77
78
79
7 A
7 B
80
81
82
83
84
85
86
35
28
29
30
31
28
29
30
31
32
33
34
P S8 E N
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
Enable bits for A and B functions of PLB8, polarity bit
for PLB8 output
P 8P L BP O L B
P 8P L BIM K B
P 8SF D P O L B
P 8 SF D IM K B
P 9P L BP O L A
P 9P L BIM K A
P 9SF D P O L A
P 9SF D IM K A
P 9G P IP O L
Polarity Sense for all 8 other PLB outputs when used as
inputs to the B function of PLB8
Ignore Mask for all 8 other PLB outputs when used as
inputs to the B function of PLB8
Polarity Sense for all 7 SFD inputs (VH, 2 VB, 4 VP’s) to
the B function of PLB8
Ignore Mask for all 7 SFD inputs (VH, 2 VB, 4 VP’s) to
the B function of PLB8
Polarity Sense for all 8 other PLB outputs when used as
inputs to the A function of PLB9
Ignore Mask for all 8 other PLB outputs when used as
inputs to the A function of PLB9
Polarity Sense for all 7 SFD inputs (VH, 2 VB, 4 VP’s) to
the A function of PLB9
Ignore Mask for all 7 SFD inputs (VH, 2 VB, 4 VP’s) to
the A function of PLB9
Polarity Sense and Ignore Mask bits for all 4 GPI’s when
used as inputs to the A function of PLB9
P 9G P IIM K
Polarity Sense and Ignore Mask bits for all 4 GPI’s when
used as inputs to the B function of PLB9
P 9W D IC F G
Polarity Sense and Ignore Mask bits for the pulsed and
latched outputs of the watchdog detector when used as
inputs to both A and B functions of PLB9
87
88
35
28
29
30
31
P S9 E N
00h
00h
00h
00h
00h
Enable bits for A and B functions of PLB9, polarity bit
for PLB9 output
P 9P L BP O L B
P 9P L BIM K B
P 9SF D P O L B
P 9 SF D IM K B
Polarity Sense for all 8 other PLB outputs when used as
inputs to the B function of PLB9
89
Ignore Mask for all 8 other PLB outputs when used as
inputs to the B function of PLB9
8 A
8 B
Polarity Sense for all 7 SFD inputs (VH, 2 VB, 4 VP’s) to
the B function of PLB9
Ignore Mask for all 7 SFD inputs (VH, 2 VB, 4 VP’s) to
the B function of PLB9
REV. PrJ 11/02
–2 3 –
PRELIMINARY TECHNICAL DATA
ADM1060 LOGIC
ADM1060
P LBA REGISTER BITMAP S
TABLE 28. BIT MAP FO R P n P LBP O LA/P nP LBP O LB RE GISTE RS (P O WE R- O N D E FAULT 00H )
Bit
Nam e
R/W
D escr iption
7-0
P O L9-P O L1
R /W
P LB1
00H
If high, inver t the P LBn input before it is used in function A or B
P LB2
10H
P LB3
20H
P LB4
30H
P LB5
40H
P LB6
50H
P LB7
60H
P LB8
70H
P LB9
80H
Function A
Function B
08H
18H
28H
38H
48H
58H
68H
78H
88H
7
6
5
4
3
2
1
0
P LB9
P LB8
P LB7
P LB6
P LB5
P LB4
P LB3
P LB2
P LB9
P LB8
P LB7
P LB6
P LB5
P LB4
P LB3
P LB1
P LB9
P LB8
P LB7
P LB6
P LB5
P LB4
P LB2
P LB1
P LB9
P LB8
P LB7
P LB6
P LB5
P LB3
P LB2
P LB1
P LB9
P LB8
P LB7
P LB6
P LB4
P LB3
P LB2
P LB1
P LB9
P LB8
P LB7
P LB5
P LB4
P LB3
P LB2
P LB1
P LB9
P LB8
P LB6
P LB5
P LB4
P LB3
P LB2
P LB1
P LB9
P LB7
P LB6
P LB5
P LB4
P LB3
P LB2
P LB1
P LB8
P LB7
P LB6
P LB5
P LB4
P LB3
P LB2
P LB1
TABLE 29. BIT MAP FO R P nP LBIMKA/P nP LBIMKB RE GISTE RS (P O WE R- O N D E FAULT 00H )
Bit
Nam e
R/W
D escr iption
7-0
IG N 9-IG N 1
R /W
P LB1
01H
If high, m ask the P LBn input before it is used in function A or B
P LB2
11H
P LB3
21H
P LB4
31H
P LB5
41H
P LB6
51H
P LB7
61H
P LB8
71H
P LB9
81H
Function A
Function B
09H
19H
29H
39H
49H
59H
69H
79H
89H
7
6
5
4
3
2
1
0
P LB9
P LB8
P LB7
P LB6
P LB5
P LB4
P LB3
P LB2
P LB9
P LB8
P LB7
P LB6
P LB5
P LB4
P LB3
P LB1
P LB9
P LB8
P LB7
P LB6
P LB5
P LB4
P LB2
P LB1
P LB9
P LB8
P LB7
P LB6
P LB5
P LB3
P LB2
P LB1
P LB9
P LB8
P LB7
P LB6
P LB4
P LB3
P LB2
P LB1
P LB9
P LB8
P LB7
P LB5
P LB4
P LB3
P LB2
P LB1
P LB9
P LB8
P LB6
P LB5
P LB4
P LB3
P LB2
P LB1
P LB9
P LB7
P LB6
P LB5
P LB4
P LB3
P LB2
P LB1
P LB8
P LB7
P LB6
P LB5
P LB4
P LB3
P LB2
P LB1
TABLE 30. BIT MAP FO R P nSFD P O LA/P n SFD P O LB RE GISTE RS (P O WE R- O N D E FAULT 00H )
Bit
Nam e
R/W
D escr iption
7
Reserved N /A
P O L7-P O L1
Cannot be used
6-0
R /W
P LB1
02H
If high, inver t the SFD n input before it is used in function A or B
P LB2
12H
P LB3
22H
P LB4
32H
P LB5
42H
P LB6
52H
P LB7
62H
P LB8
72H
P LB9
82H
Function A
Function B
0AH
1AH
2AH
3AH
4AH
5AH
6AH
7AH
8AH
6
5
4
3
VP 4
VP 3
VP 2
VP 1
VP 4
VP 3
VP 2
VP 1
VP 4
VP 3
VP 2
VP 1
VP 4
VP 3
VP 2
VP 1
VP 4
VP 3
VP 2
VP 1
VP 4
VP 3
VP 2
VP 1
VP 4
VP 3
VP 2
VP 1
VP 4
VP 3
VP 2
VP 1
VP 4
VP 3
VP 2
VP 1
REV. PrJ 11/02
–2 4 –
PRELIMINARY TECHNICAL DATA
ADM1060 LOGIC
ADM1060
2
1
0
VH
VH
VH
VH
VH
VH
VH
VH
VH
VB 2
VB 1
VB 2
VB 1
VB 2
VB 1
VB 2
VB 1
VB 2
VB 1
VB 2
VB 1
VB 2
VB 1
VB 2
VB 1
VB 2
VB 1
TABLE 31. BIT MAP FO R P nSFD IMKA/P nSFD IMKB RE GISTE RS (P O WE R- O N D E FAULT 00H )
Bit
Nam e
R/W
D escr iption
7
Reserved N /A
IG N 7-IG N 1
Cannot be used
6-0
R /W
P LB1
03H
If high, m ask the SFD n input before it is used in function A or B
P LB2
13H
P LB3
23H
P LB4
33H
P LB5
43H
P LB6
53H
P LB7
63H
P LB8
73H
P LB9
83H
Function A
Function B
0BH
1BH
2BH
3BH
4BH
5BH
6BH
7BH
8BH
6
5
4
3
2
1
0
VP 4
VP 3
VP 2
VP 1
VH
VP 4
VP 3
VP 2
VP 1
VH
VP 4
VP 3
VP 2
VP 1
VH
VP 4
VP 3
VP 2
VP 1
VH
VP 4
VP 3
VP 2
VP 1
VH
VP 4
VP 3
VP 2
VP 1
VH
VP 4
VP 3
VP 2
VP 1
VH
VP 4
VP 3
VP 2
VP 1
VH
VP 4
VP 3
VP 2
VP 1
VH
VB 2
VB 1
VB 2
VB 1
VB 2
VB 1
VB 2
VB 1
VB 2
VB 1
VB 2
VB 1
VB 2
VB 1
VB 2
VB 1
VB 2
VB 1
TABLE 32. BIT MAP FO R P nGP IP O L RE GISTE RS (P O WE R- O N D E FAULT 00H )
Bit
Nam e
R/W
D escr iption
7-4
3-0
AP O L4-AP O L1
BP O L 4-BP O L 1
R /W
If high, inver t the GP In input before it is used in function A
If high, inver t the GP In input before it is used in function B
R /W
P LB1
P LB2
P LB3
P LB4
P LB5
P LB6
P LB7
P LB8
P LB9
84H
04H
14H
24H
34H
44H
54H
64H
74H
7
6
5
4
Function A
G P I1
G P I2
G P I3
G P I4
G P I1
G P I2
G P I3
G P I4
G P I1
G P I2
G P I3
G P I4
G P I1
G P I2
G P I3
G P I4
G P I1
G P I2
G P I3
G P I4
G P I1
G P I2
G P I3
G P I4
G P I1
G P I2
G P I3
G P I4
G P I1
G P I2
G P I3
G P I4
G P I1
G P I2
G P I3
G P I4
3
2
1
0
Function B
G P I1
G P I2
G P I3
G P I4
G P I1
G P I2
G P I3
G P I4
G P I1
G P I2
G P I3
G P I4
G P I1
G P I2
G P I3
G P I4
G P I1
G P I2
G P I3
G P I4
G P I1
G P I2
G P I3
G P I4
G P I1
G P I2
G P I3
G P I4
G P I1
G P I2
G P I3
G P I4
G P I1
G P I2
G P I3
G P I4
REV. PrJ 11/02
–2 5 –
PRELIMINARY TECHNICAL DATA
ADM1060 LOGIC
ADM1060
TABLE 33. BIT MAP FO R P NGP IIMK RE GISTE RS (P O WE R- O N D E FAULT 00H )
Bit
Nam e
R/W
D escr iption
7-4
3-0
AIM K 4-AIM K 1
BIM K 4-BIM K 1
R /W
R /W
If high, m ask the GP In input before it is used in function A
If high, m ask the GP In input before it is used in function B
P LB1
05H
P LB2
15H
P LB3
25H
P LB4
35H
P LB5
45H
P LB6
55H
P LB7
65H
P LB8
75H
P LB9
85H
7
6
5
4
Function A
G P I1
G P I2
G P I3
G P I4
G P I1
G P I2
G P I3
G P I4
G P I1
G P I2
G P I3
G P I4
G P I1
G P I2
G P I3
G P I4
G P I1
G P I2
G P I3
G P I4
G P I1
G P I2
G P I3
G P I4
G P I1
G P I2
G P I3
G P I4
G P I1
G P I2
G P I3
G P I4
G P I1
G P I2
G P I3
G P I4
3
2
1
0
Function B
G P I1
G P I2
G P I3
G P I4
G P I1
G P I2
G P I3
G P I4
G P I1
G P I2
G P I3
G P I4
G P I1
G P I2
G P I3
G P I4
G P I1
G P I2
G P I3
G P I4
G P I1
G P I2
G P I3
G P I4
G P I1
G P I2
G P I3
G P I4
G P I1
G P I2
G P I3
G P I4
G P I1
G P I2
G P I3
G P I4
T ABLE 34. P n WD IC F G RE GIST E RS 06H ,16H ,26H ,36H ,46H ,56H ,66H ,76H ,86H (P O WE R- O N D E F AULT 00H )
Bit
Nam e
R/W
D escr iption
7
AP O L P R /W
If high, invert the pulsed WDI input before it is used in function A
6
AI M K P R /W
If high, mask the pulsed WDI input before it is used in function A
5
4
AP O L L R /W
AI M K L R /W
If high, invert the latched WDI input before it is used in function A
If high, mask the latched WDI input before it is used in function A
3
2
BP O L P R /W
B I M K P R /W
If high, invert the pulsed WDI input before it is used in function B
If high, mask the pulsed WDI input before it is used in function B
1
0
BP O L L R /W
BI M K L R /W
If high, invert the latched WDI input before it is used in function B
If high, mask the latched WDI input before it is used in function B
T ABLE 35. P nE N RE GIST E RS 07H ,17H ,27H ,37H ,47H ,57H ,67H ,77H ,87H (P O WE R- O N D E F AULT 00H )
Bit
Nam e
R/W
D escr iption
7-3
Reserved N /A
I N VO P R /W
Cannot be used
2
1
0
If high, invert the PLB output
If high, enable function A
If high, enable function B
E N A
E N B
R /W
R /W
REV. PrJ 11/02
–2 6 –
PRELIMINARY TECHNICAL DATA
ADM1060 LOGIC
ADM1060
PDB INPUT
P RO GRAMMABLE D ELAY BLO CK
PROGRAMMED FALLTIME =0
PROGRAMMED RISETIME
Each output of the PLBA is fed into a separate Program-
mable Delay Block (PDB). T he PDB enables the user to
add a delay to the logic block output before it is applied to
either a PDO or one of the other PLB’s (the output of a
PLB can be the input to any of the other PLB’s- not it-
self). T he PDB operation is similar to that of the glitch
filter (discussed in the SFD section). T here is an impor-
tant difference between the 2 functions, however. T he
delay on the falling edge of an input to the PDB can be
programmed independently of the rising edge. T his al-
lows the user to program the length of the pulse outputted
from the PDB. T hus, for instance, the width of the pulse
from the Watchdog Fault Detector can be adjusted, or the
user can ensure that a supply supervised by one of the
SFD’s is within its UV/OV range for a programmed pe-
riod of time before asserting a PDO. A delay of between
0ms and 500ms can be programmed in the PnPDBT IM
registers. 4 bits each are used to program the rising edge
and falling edge. Once programmed, the PDB operates as
follows. If the user programs a delay on the rising edge
of, say, 200ms, the PDB looks for a rising edge on the
input. Once it sees the edge it starts a timer. If the input
remains high and the timer reaches 200ms, then the PDB
immediately outputs a rising edge. If the input falls low
before the timer has reached 200ms then no edge is out-
putted from the PDB and the timer is reset. Because there
is separate control over the falling edge, if no delay is
programmed on the falling edge, the delay defaults to 0
and a falling edge on the input will immediately appear on
the output. If a falling edge delay is programmed, then
the PDB operates exactly the opposite to the way it does
for a rising edge. Again, if a delay of, say, 200ms is pro-
grammed on the falling edge, the PDB looks for a falling
edge on the input. Once it sees the edge, it again starts a
timer. If the input remains low and the timer reaches
PROGRAMMED RISETIME
T
RISE
T
T
RISE
T
T
FALL
0
0
T
T
T
T
T
0
RISE FALL
0
RISE
PDB OUTPUT
PROGRAMMING RISE TIME ONLY
PDB INPUT
PROGRAMMED RISETIME
PROGRAMMED RISETIME
PROGRAMMED FALLTIME
PROGRAMMED FALLTIME
T
T
T
RISE
T
T
FALL
T
1
0
T
T
RISE
FALL
1
0
T
RISE
T
FALL
T
T
T
T
RISE
T
T
0
1
0
FALL
1
200ms, then the output transitions from high to low.
A
PDB OUTPUT
valid rising edge must appear at the output before a falling
edge delay can be activated. T he function of the PDB is
illustrated in figure 6 below.
PROGRAMMING RISE TIME AND FALL TIME
Aside from the extra timing flexibility offered, the pro-
grammable delay also provides a crude form of filtering.
In much the same way as the Glitch Filter operates, an
input must be high (or low) for a programmed period of
time before being seen on the output. T ransients which
are shorter that the programmed timeouts will not appear
on the output. T he bitmap for the register which controls
both the rising and falling edges is shown overleaf:-
Figure 6. Functionality of the Program m able Delay Block (PDB)
REV. PrJ 11/02
–2 7 –
PRELIMINARY TECHNICAL DATA
ADM1060 LOGIC
ADM1060
TABLE 36. LIST O F RE GISTE RS FO R P RO GRAMMABLE D E LAY BLO C K (P D B)
H ex
T able
Nam e
D efa u lt
D escr iption
Addr .
P ower O n Value
0 C
1 C
2 C
3 C
4 C
5 C
6 C
7 C
8 C
37
37
37
37
37
37
37
37
37
P 1P D BT IM
P 2P D BT IM
P 3P D BT IM
P 4P D BT IM
P 5P D BT IM
P 6P D BT IM
P 7P D BT IM
P 8P D BT IM
P 9P D BT IM
00h
00h
00h
00h
00h
00h
00h
00h
00h
Delay for PDB1. Delay for rising edge and falling edge pro
grammed separately.
Delay for PDB2. Delay for rising edge and falling edge pro
grammed separately.
Delay for PDB3. Delay for rising edge and falling edge prog
rammed separately.
Delay for PDB4. Delay for rising edge and falling edge pro
grammed separately.
Delay for PDB5. Delay for rising edge and falling edge pro
grammed separately.
Delay for PDB6. Delay for rising edge and falling edge pro
grammed separately.
Delay for PDB7. Delay for rising edge and falling edge pro
grammed separately.
Delay for PDB8. Delay for rising edge and falling edge pro
grammed separately.
Delay for PDB9. Delay for rising edge and falling edge pro
grammed separately.
TABLE 37. P n P D BTIM REGISTERS 0Ch,1CH ,2CH ,3CH ,4CH ,5CH ,6CH ,7CH ,8CH
Bit
Nam e
R/W
D escr iption
7-4
3-0
T R3-T R0
T F 3-T F 0
W
W
Programmed Rise T ime
Programmed Fall T ime
TR3
TR2
TR1
TR0
D elay(m s)
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
2
5
10
20
40
60
80
100
150
200
250
300
400
500
TF3
TF2
TF1
TF0
D elay(m s)
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
2
5
10
20
40
60
80
100
150
200
250
300
400
500
REV. PrJ 11/02
–2 8 –
PRELIMINARY TECHNICAL DATA
ADM1060 OUTPUTS
ADM1060
P R O G R AM M AB LE D R IVE R O U T P U T S
the user to directly drive the gate of an N- Channel FET
in the path of a power supply. T he required pull- up is
selected by programming bits 0 to 3 in PnPDOCFG
appropriately (see table overleaf).
T he ADM1060 has 9 Programmable Driver Outputs
(PDO’s). T hese are the logic outputs of the device. Each
PDO is normally controlled by a PDB. T hus, the PDO’s
can be set up assert when the conditions on the PDB are
met (eg) the SFD’s are in tolerance, the levels on the GPI
are correct, the Watchdog timer has not timed out etc.
T he PDO’s can be used for a number of functions (eg)
provide a POWER_GOOD signal when all the SFD’s are
in tolerance, provide a reset generator output if one of the
SFD’s goes out of spec. (which can be used as a status
signal for a DSP or other microprocessor), provide enable
signals for LDO’s on the supplies that the ADM1060 is
supervising etc.
T he data driving each of the PDO’s can come from one of
3 inputs. T hese inputs are enabled by a bit each in the
PnPDOCFG registers. T he inputs are:-
• T he (delayed) output from the associated PLB (enabled
by setting bit CFG4 to 1)
• Data which is driven directly over the SMBus interface
(enabled by setting bit CFG5 to1). When set in this
mode, the data from the PDB is disabled and the data on
the PDO is the data on CFG4. T hus the PDO can be
software controlled (eg) to initiate a software power up/
powerdown.
T here are a number of pull up options on the PDO’s to
enable the user to program the output level.
T he outputs can be programmed to be:-
• Open Drain (allows the user to connect an external
pull- up resistor)
• An On- Chip Clock (enabled by setting bit CFG6 to1).
A 100KHz clock is available to clock an external device
(eg) a LED.
• Open Drain with weak internal pull-up to VDD
• Open Drain with strong internal pull-up to VDD
• Open Drain with weak internal pull-up to VP_n
• Open Drain with strong internal pull-up to VP_n
• Internally charge-pumped high drive (+12V)
More detail of these data modes is given in the register
map overleaf.
T he default setup of each of the PDO’s is to be pulled low
by a weak (20k⍀) pulldown resistor. T his is also the setup
of the PDO’s on power- up until the registers are loaded
and the programmed conditions are latched. T he outputs
are actively pulled low once 1V or greater is seen at any of
VPn or VH. Until there is a 1V supply on the chip the
outputs are high impedance. T his provides a known
condition for the PDO’s during power- up. T he pulldown
can be overdriven if required (eg) tie an external pull- up
resistor to the PDO to ensure that the gate of a PMOS
device was not turned on.
T he last option is only available on PDO1- 4. T his allows
T he register list and the bit map for the PDO’s is shown
below.
VFET (PDO1-4 ONLY)
V
DD
VP4
VP1
SEL
PDB_OUT
PDO
CFG4
M_CLK
Figure 7. Program m able Driver Output
REV. PrJ 11/02
–2 9 –
PRELIMINARY TECHNICAL DATA
ADM1060 OUTPUTS
ADM1060
TABLE 38. LIST O F REGISTERS FO R TH E P RO GRAMMABLE D RIVER O UTP UTS
H ex
T able
Nam e
D efa u lt
D escr iption
Addr ess
P ower O n Value
0 D
1 D
2 D
3 D
4 D
39
P 1 P D O C F G
P 2 P D O C F G
P 3 P D O C F G
P 4 P D O C F G
P 5 P D O C F G
00h
00h
00h
00h
00h
Selects the format of the PDO1 output (open drain, open
drain with internal pull-up, charge pumped etc.)
39
Selects the format of the PDO2 output (open drain, open
drain with internal pull-up, charge pumped etc.)
39
Selects the format of the PDO3 output (open drain, open
drain with internal pull-up, charge pumped etc.)
39
Selects the format of the PDO4 output (open drain, open
drain with internal pull-up, charge pumped etc.)
39
Selects the format of the PDO5 output (open drain, open
drain with internal pull-up etc.). Note: C har ge P um ped
output is not available on this dr iver
5 D
6 D
7 D
8 D
39
39
39
39
P 6 P D O C F G
P 7 P D O C F G
P 8 P D O C F G
P 9 P D O C F G
00h
00h
00h
00h
Selects the format of the PDO6 output (open drain, open
drain with internal pull-up etc.). Note: C har ge P um ped
output is not available on this dr iver
Selects the format of the PDO7 output (open drain, open
drain with internal pull-up etc.). Note: C har ge P um ped
output is not available on this dr iver
Selects the format of the PDO8 output (open drain, open
drain with internal pull-up etc.). Note: C har ge P um ped
output is not available on this dr iver
Selects the format of the PDO9 output (open drain, open
drain with internal pull-up etc.). Note: C har ge P um ped
output is not available on this dr iver
T ABLE 39. RE G IST E R 0D H ,1D H ,2D H ,3D H ,4D H ,5D H ,6D H ,7D H ,8D H P n P D O C F G (P O WE R- O N D E F AULT 00H )
Bit
Nam e
R/W
D escr iption
7
Reserved
N /A
R /W
Cannot be used
6-4
C F G 6-C F G 4
Control the logical state of the PDO. T hese three bits deter
mine what effect, if any, the logical input to the PDO has on its output
CFG6
CFG5
CFG4
P D O
S t a t e
0
0
0
0
1
0
0
1
1
X
0
1
0
1
X
0
Disabled, with weak pull-down
Enabled, follows PLB Logic Output
Enable SMBus Data, Drive Low
Enable SMBus Data, Drive H igh
Enable MCLK out onto pin
P L B_O U T
0
1
M C L K
3-0
C F G 3-C F G 0
R /W
CFG3
CFG2
CFG1
CFG0
P ull-Up
Supply
P ull-Up
Str en gth
0
0
0
0
0
0
1
1
1
1
1
1
0
0
1
1
1
1
0
0
0
0
1
1
0
1
0
0
1
1
0
0
1
1
1
1
X
X
0
1
0
1
0
1
0
1
0
1
none
VC P
VP 1
VP 1
VP 2
VP 2
VP 3
VP 3
VP 4
VP 4
VD D
VD D
N /A
(1/fC )
L ow
H igh
L ow
H igh
L ow
H igh
L ow
H igh
L ow
H igh
REV. PrJ 11/02
–3 0 –
PRELIMINARY TECHNICAL DATA
ADM1060 STATUS/FAULTS
ADM1060
F AULT /ST AT US RE P O RT ING O N T H E AD M 1060
T he important exception is the MSB of the LAT F1 regis-
ter. T his is the ANYFLT bit. T his bit goes high if one
As discussed in the last section, any one, a number or all
of the PDO’s can be programmed to assert under a set of
pre- programmed conditons. T hese conditions could be a
fault on a SFD, a change in status on a GPI, a timeout on
the watchdog detector etc. Because of the flexibility and
the choice of combinations available on the ADM1060,
the assertion of the PDO will tell the user nothing about
what caused it to assert (unless it is programmed to assert
with only one input).
of the other bits in the 2 registers “faults”.
A “fault” is
defined as a change in polarity from the last time the fault
registers were read. Once ANYFLT goes high the con-
tents of the 2 registers are latched, thus preventing more
than 1 of the other bits from changing polarity before the
contents of the registers are read. T he first faulting input
can, therefore, be determined.
T he sequence in which the registers are read is determined
by ANYFLT . As long as ANYFLT remains at 0, only the
contents of LAT F1 are read. T here are 2 reasons for this.
T he first is that ANYFLT =0 implies that no fault has
occurred and, therefore, there is no need to read the con-
tents of LAT F2. Secondly, and more importantly, read-
ing register LAT F2 actually resets the ANYFLT bit to 0.
T hus, if a fault occurred on an SFD after LAT F1 had
been read but before LAT F2 had been read, ANYFLT
would change to 1, indicating that a fault had occurred,
but would be reset to 0 once LAT F2 was read, thus eras-
ing the log of the fault. In summary then, LAT F2 should
only ever be read if ANYFLT =1. Reading the registers in
this sequence ensures that the contents are never reset
before a fault has been logged over the SMBus, thus en-
suring that the supervising processor or CPLD knows
what function supervised by the ADM1060 caused the
fault. T he “faulting” function is determined by compar-
ing the contents of the fault plane (ie) the contents of the 2
registers, with the values read previously, and determining
which bit changed polarity.
T o enable the user to debug the cause of the PDO asser-
tion, a number of registers are provided on the ADM1060
which provide status and fault information on the various
individual functions supervised by the device.
ST AT U S R E G IST E R S
A number of Status Registers are provided which indicate
the logic state of all of the functions controlled by the
ADM1060. T hese logics states include the output of both
the UV and OV comparators of each of the 7 SFD’s, the
logic output of the SFD’s themselves, the logic state of
the GPI’s, the error condition on the WDI, and the logic
state of each of the 9 PDO’s. T he contents of these regis-
ters can be read at any time via the SMBus interface. T he
content of these registers is read- only. T he register and
bitmap for each of these status registers is described in the
table overleaf.
F AU LT RE G IST E RS
Fault reporting is also provided on the ADM1060. If a
fault occurs, causing, say, a PDO to change its status, the
user can determine what function actually faulted. T his is
achieved by providing a “fault plane”, consisting of 2
registers, LAT F1 and LAT F2, which the system control-
ler can read out of the ADM1060 via the SMBus. Each
bit in the 2 registers (with one important exception, see
below) is assigned to one of the inputs of the devices as
shown in the table below:-
T he functionality of the Fault Plane is best illustrated with
an example. T ake, for instance, VP1 to have an input
supply of 5.0V. A UV/OV window of 4.5V to 5.5V is set
up on VP1. T he supply is ramped in and out of this win-
dow, each time reading the contents of LAT F1 and
LAT F2. T he values recorded are as follows:-
1. VP1 at 5V- LAT F1=LAT F2=00000000. T his is ex-
pected. T he supply is in tolerance, SFD output is 0,
therefore no fault.
RE G IST E R
LAT F1
BIT
7
ASSIGNED FUNCTIO N
ANYFLT
2. VP1 at 4.2V- LAT F1=10001000, LAT F2=00000000.
SFD output has changed status to 1, therefore ANYFLT
goes high.
6
5
4
3
2
1
0
7
Logic Output of VP4’s SFD
Logic Output of VP3’s SFD
Logic Output of VP2’s SFD
Logic Output of VP1’s SFD
Logic Output of VH’s SFD
Logic Output of VB2’s SFD
Logic Output of VB1’s SFD
-
3. VP1 at 5.0V- LAT F1=10000000, LAT F2=00000000.
SFD output has changed status to 0, therefore ANYFLT
goes high again.
4. VP1 at 5.8V- LAT F1=10001000, LAT F2=00000000.
SFD output again changed status from 0 to 1, so
AN YFLT goes high.
LAT F2
6
5
-
-
5.VP1 at 4.2V- LAT F1=10000000, LAT F2=00000000.
At first glance, this would appear to be incorrect, since
SFD output should be at 1 (4.2V is an undervoltage
fault). However, in ramping down from 5.8V to 4.2V, the
supply passed into the UV/OV window, the SFD output
changed status from 1 to 0, ANYFLT was set high and
the register contents were latched. It is these values which
were read before being reset by reading LAT F2.
4
3
2
1
Logic Output of WDI
Logic Input on GPI4
Logic Input on GPI3
Logic Input on GPI2
Logic Input on GPI1
0
Table 25. Fault Plane of ADM1060
Each bit represents the logical status of its assigned func-
tion (ie) the logical output of the SFD’s and WDI and the
logic level on the GPI inputs.
T here are also two mask registers provided, which enable
the user to ignore a fault on a given function. T he bits of
the error mask registers are mapped in the same way as
REV. PrJ 11/02
–3 1 –
PRELIMINARY TECHNICAL DATA
ADM1060 STATUS/FAULTS
ADM1060
those of the fault registers with the exception that the
ANYFLT bit cannot be masked. Setting a 1 in the error
mask register results in the equivalent bit in the fault reg-
ister always remaining at 0, regardless of whether there is a
fault on that function or not. T he register and bit maps for
both the fault and error mask registers are shown below.
STATUS REGISTERS
TABLE 40. LIST O F STATUS RE GISTE RS
H ex
T able
Nam e
D efa u lt
D escr iption
Addr .
P ower O n Value
D 8
D 9
D A
D B
D E
D F
41
42
43
44
45
46
U VST AT
00h
00h
00h
00h
00h
00h
Logic output of the UV comparator on each of the 7 SFD’s
Logic output of the OV comparator on each of the 7 SFD’s
Logic output (post Fault T ype block) on each of the 7 SFD’s
Logic state of the 4 GPI’s and the Watchdog Fault Detector
Logic output of PDO’s 1 to 8
O VS T AT
SF D ST AT
G W ST AT
P D O ST AT 1
P D O ST AT 2
Logic output of PDO
9
TABLE 41. BIT MAP FO R UVSTAT RE GISTE R D 8H (P O WE R- O N D E FAULT 00H )
Bit
7
Nam e
R/W
N /A
R
D escr iption
Reserved
VP 4 U V
VP 3 U V
VP 2 U V
VP 1 U V
VH U V
Cannot be used
6
If high, then voltage on VP4 input is lower than the UV threshold
If high, then voltage on VP3 input is lower than the UV threshold
If high, then voltage on VP2 input is lower than the UV threshold
If high, then voltage on VP1 input is lower than the UV threshold
If high, then voltage on VH input is lower than the UV threshold
If high, then voltage on VB2 input is lower than the UV threshold
If high, then voltage on VB1 input is lower than the UV threshold
5
R
4
R
3
R
2
R
1
VB 2 U V
VB 1 U V
R
0
R
TABLE 42. BIT MAP FO R O VSTAT RE GISTE R D 9H (P O WE R- O N D E FAULT 00H )
Bit
7
Nam e
R/W
N /A
R
D escr iption
Reserved
VP 4 O V
VP 3 O V
VP 2 O V
VP 1 O V
VH O V
Cannot be used
6
If high, then voltage on VP4 input is higher than the OV threshold
If high, then voltage on VP3 input is higher than the OV threshold
If high, then voltage on VP2 input is higher than the OV threshold
If high, then voltage on VP1 input is higher than the OV threshold
If high, then voltage on VH input is higher than the OV threshold
If high, then voltage on VB2 input is higher than the OV threshold
If high, then voltage on VB1 input is higher than the OV threshold
5
R
4
R
3
R
2
R
1
VB 2 O V
VB 1 O V
R
0
R
REV. PrJ 11/02
–3 2 –
PRELIMINARY TECHNICAL DATA
ADM1060 STATUS/FAULTS
ADM1060
TABLE 43. BIT MAP FO R SFD STAT RE GISTE R D AH (P O WE R- O N D E FAULT 00H )
Bit
Nam e
R/W
D escr iption
7
6
5
4
3
2
1
0
Reserved
VP 4F L T
VP 3F L T
VP 2F L T
VP 1F L T
VH F L T
VB2 F L T
VB1 F L T
N /A
R
Cannot be used
If high, then fault (UV, OV or Out- of- Window) has occurred on VP4 input
If high, then fault (UV, OV or Out- of- Window) has occurred on VP3 input
If high, then fault (UV, OV or Out- of- Window) has occurred on VP2 input
If high, then fault (UV, OV or Out- of- Window) has occurred on VP1 input
If high, then fault (UV, OV or Out- of- Window) has occurred on VH input
If high, then fault (UV, OV or Out- of- Window) has occurred on VB2 input
If high, then fault (UV, OV or Out- of- Window) has occurred on VB1 input
R
R
R
R
R
R
TABLE 44. BIT MAP FO R GWSTAT RE GISTE R D BH (P O WE R- O N D E FAULT 00H )
Bit
7-5
4
Nam e
R/W
N /A
R
D escr iption
Reserved
Cannot be used
W D IST AT
G P I4ST AT
G P I3ST AT
G P I2ST AT
G P I1ST AT
If high, then timeout has elapsed on the Watchdog Detector
Logic level currently being driven on GPI4 input
Logic level currently being driven on GPI3 input
Logic level currently being driven on GPI2 input
Logic level currently being driven on GPI1 input
3
R
2
R
1
R
0
R
TABLE 45. BIT MAP FO R P D O STAT1 RE GISTE R D E H (P O WE R- O N D E FAULT 00H )
Bit
Nam e
R/W
D escr iption
7
6
5
4
3
2
1
0
P D O 8ST AT
P D O 7ST AT
P D O 6ST AT
P D O 5ST AT
P D O 4ST AT
P D O 3ST AT
P D O 2ST AT
P D O 1ST AT
R
R
R
R
R
R
R
R
Logic level currently being driven on PDO8 output
Logic level currently being driven on PDO7 output
Logic level currently being driven on PDO6 output
Logic level currently being driven on PDO5 output
Logic level currently being driven on PDO4 output
Logic level currently being driven on PDO3 output
Logic level currently being driven on PDO2 output
Logic level currently being driven on PDO1 output
TABLE 46. BIT MAP FO R P D O STAT2 RE GISTE R D FH (P O WE R- O N D E FAULT 00H )
Bit
Nam e
R/W
D escr iption
7-1
0
Reserved
N /A
R
Cannot be used
P D O 9ST AT
Logic level currently being driven on PDO9 output
REV. PrJ 11/02
–3 3 –
PRELIMINARY TECHNICAL DATA
ADM1060 STATUS/FAULTS
ADM1060
FAULT REGISTERS
TABLE 47. LIST O F FAULT RE GISTE RS
H ex
T able
Nam e
D efa u lt
D escr iption
Addr .
P ower O n Value
D C
D D
48
49
L AT F 1
L AT F 2
00h
00h
Fault Status Register for the 7 SFD’s
Fault Status Register for the 4 GPI’s and the Watchdog Detector
TABLE 48. BIT MAP FO R LATF1 RE GISTE R D C H (P O WE R- O N D E FAULT 00H )
Bit
Nam e
R/W
D escr iption
7
AN YF L T
R
If high, then a change in logic status (fault) has been logged on one of the 12 func-
monitored since the last time the Fault Registers were read.
tions
6
5
4
3
2
1
0
VP 4F L T
VP 3F L T
VP 2F L T
VP 1F L T
VH F L T
VB2 F L T
VB1 F L T
R
R
R
R
R
R
R
If high, then a fault has occurred on supply at input VP4
If high, then a fault has occurred on supply at input VP3
If high, then a fault has occurred on supply at input VP2
If high, then a fault has occurred on supply at input VP1
If high, then a fault has occurred on supply at input VH
If high, then a fault has occurred on supply at input VB2
If high, then a fault has occurred on supply at input VB1
TABLE 49. BIT MAP FO R LATF2 RE GISTE R D D H (P O WE R- O N D E FAULT 00H )
Bit
Nam e
R/W
D escr iption
7-5
4
Reserved
W D F L T
N /A
R
Cannot be used
If high, then the logic level on the WDI output has changed since the last
time that the fault registers were read
3
2
1
0
G P I4F LT
G P I3F LT
G P I2F LT
G P I1F LT
R
R
R
R
If high, then the logic level on GPI4 input has changed since the last
time that the fault registers were read
If high, then the logic level on GPI3 input has changed since the last
time that the fault registers were read
If high, then the logic level on GPI2 input has changed since the last
time that the fault registers were read
If high, then the logic level on GPI1 input has changed since the last
time that the fault registers were read
REV. PrJ 11/02
–3 4 –
PRELIMINARY TECHNICAL DATA
ADM1060 STATUS/FAULTS
ADM1060
MASKREGISTERS
TABLE 50. LIST O F MASK RE GISTE RS
H ex
T able
Nam e
D efa u lt
D escr iption
Addr .
P ower O n Value
9 D
9E
51
52
E R R M ASK 1
E R R M ASK 2
00h
00h
Error Mask Register for the 7 SFD’s
Error Mask Register for the 4 GPI’s and the Watchdog Detector
TABLE 51. BIT MAP FO R E RRMASK1 RE GISTE R 9D H (P O WE R- O N D E FAULT 00H )
Bit
Nam e
R/W
D escr iption
7
Reserved
X
U nused
6
5
4
3
2
1
0
VP 4 M AS K
VP 3 M AS K
VP 2 M AS K
VP 1 M AS K
VH M AS K
VB2 M AS K
VB1 M AS K
R /W
R /W
R /W
R /W
R /W
R /W
R /W
If high, then a fault occurring on the supply at input VP4 is ignored, and not logged in LAT F1
If high, then a fault occurring on the supply at input VP3 is ignored, and not logged in LAT F1
If high, then a fault occurring on the supply at input VP2 is ignored, and not logged in LAT F1
If high, then a fault occurring on the supply at input VP1 is ignored, and not logged in LAT F1
If high, then a fault occurring on the supply at input VH is ignored, and not logged in LAT F1
If high, then a fault occurring on the supply at input VB2 is ignored, and not logged in LAT F1
If high, then a fault occurring on the supply at input VB1 is ignored, and not logged in LAT F1
TABLE 52. BIT MAP FO R E RRMASK2 RE GISTE R 9E H (P O WE R- O N D E FAULT 00H )
Bit
Nam e
R/W
D escr iption
7-5
4
Reserved
X
U nused
W D I M AS K
G P I4 M ASK
G P I3 M ASK
G P I2 M ASK
G P I1 M ASK
R /W
R /W
R /W
R /W
R /W
If high, then a change in the logic level on the WDI output is ignored, and not logged in LAT F2
If high, then a change in the logic level on the GPI4 input is ignored, and not logged in LAT F2
If high, then a change in the logic level on the GPI3 input is ignored, and not logged in LAT F2
If high, then a change in the logic level on the GPI2 input is ignored, and not logged in LAT F2
If high, then a change in the logic level on the GPI1 input is ignored, and not logged in LAT F2
3
2
1
0
REV. PrJ 11/02
–3 5 –
PRELIMINARY TECHNICAL DATA
PROGRAMMING ADM1060
ADM1060
in the original setup until the instruction is given to
change.
C O NF IG URAT IO N D O WNLO AD AT P O WE R- UP
T he configuration of the ADM1060- the UV/OV thresh-
olds, glitch filter timeouts, PLB combinations, PDO pull-
ups etc, is dictated by the contents of the RAM. T he
RAM is comprised of local latches which set the configu-
ration. T hese latches are double buffered and are actually
comprised of 2 identical latches (Latch A and Latch B).
An update of the double- buffered latch updates Latch A
first then Latch B. T he advantage of this architecture is
explained below. T hese latches are volatile memory and
lose their contents at power- down. T herefore, at power-
up the configuration in the RAM must be restored. T his
is achieved by downoading the contents of the EEPROM
(non- volatile memory) to the local latches. T his down-
load occurs in a number of steps.
T he instruction to download from the EEPROM in option
3 above is also a useful way to restore the original
EEPROM contents if revisions to the configuration are
unsatisfactory to the user and they wish the ADM1060 to
return to a known operating mode.
T his type of operation is possible because of the topology
of the ADM1060. T he Local (volatile) registers, or RAM,
are all double buffered latches. Setting bit 0 of the
UPDCFG register to 1 leaves the double buffered latches
open at all times. If bit 0 is set to 0, then when RAM
write occurs across the SMBus only the first side of the
double buffered latch is written to. T he user must then
write a 1 to bit 1 of the UPDCFG register. T his gener-
ates a pulse to update all of the second latches at once.
Similarly with EEPROM writes.
1. With no power applied to the device, the PDO’s are all
high impedance.
A final bit in this register is used to enable EEPROM
page erasure. If this bit is set high, then the contents of an
EEPROM page can all be set to 0. If low, then the con-
tents of a page cannot be erased, even if the command
code for page erasure is programmed across the SMBus.
2. Once 1V appears on any of the inputs connected to the
VDD Arbitrator (VH or VPn), the PDO’s are all (weakly)
pulled to GND.
3. Once the supply rises above the Undervoltage Lockout
of the device (UVLO is 2.5V), the EEPROM starts to
download to the RAM.
T he bitmap for register UPDCFG is shown below.
A
flow chart for download at power up and subsequent con-
figuration updates is shown overleaf:-
4. T he EEPROM downloads its contents to all Latch A’s.
5. Once the contents of the EEPROM are completely
downloaded, the device controller outputs a control pulse
enabling all Latch A’s to download to all Latch B’s, thus
completing the configuration download. Any attempt to
communicate with the device prior to this download
completion will result in a NACK being issued from the
AD M 1060.
UP D AT ING T H E C O NF IG URAT IO N O F T H E
AD M 1060
Once powered up, with all of the configuration settings
loaded from EEPROM into the RAM registers, the user
may wish to alter the configuration of functions on the
ADM1060 (eg) change the UV or OV limit of an SFD,
change the fault output of an SFD, change the timeout of
the Watchdog Detector, change the rise time delay of one
of the PDO’s etc.
T he ADM1060 provides a number of options which allow
the user to update the configuration differently over the
SMBus interface. All of these options are controlled in
the register UPDCFG. T he options are:-
1. Update the configuration in real time. T he user writes
to RAM across the SMBus and the configuration is up-
dated immediately.
2. Update A Latches “offline” and then update all B
Latches at the same time. With this method, the configu-
ration of the ADM1060 will remain unchanged and con-
tinue to operate in the original setup until the instruction
is given to update the B Latches.
3. Change EEPROM register contents “offline” and then
download the revised EEPROM contents to the RAM
registers. Again, with this method, the configuration of the
ADM1060 will remain unchanged and continue to operate
REV. PrJ 11/02
–3 6 –
PRELIMINARY TECHNICAL DATA
PROGRAMMING ADM1060
ADM1060
T ABLE 52. LIST O F C O NF IGURAT IO N UP D AT E RE GIST E RS
H ex
T able
Nam e
D efa u lt
D escr iption
Addr .
P ower O n Value
90
53
U P D C F G
00h
Configuration Update Control register for changing
configuration of the ADM1060 after power- up
TABLE 53. BIT MAP FO R UP D C FG RE GISTE R 90H (P O WE R- O N D E FAULT 00H )
Bit
Nam e
R/W
D escr iption
7-4
3
Reserved
N /A
R /W
W
Cannot be used
E E _E RASE
EEP RO M LD
If set high, then EEPROM page erasure can be programmed.
2
If set high, the ADM1060 will download the contents of its EEPROM to the RAM
registers. T his bit self clears (returns to 0) after the download
1
0
R AM L D
U P D
W
If set high, the ADM1060 will download the buffered RAM register data into the
local latches. T his bit self clears (returns to 0) after the download
R /W
If set high, the ADM1060 will update its configuration in real time as a word is
written to a local RAM register via the SMBus
SMBus
DEVICE
CONTROLLER
POWER- UP
(Vcc >2.5V)
E
E
P
R
O
M
L
R
U
P
D
A
M
L
D
A
T
A
D
FUNCTION
(eg) OV Threshold
on VP1
D
LATCH A
LATCH B
EEPROM
Figure 8. Configuration Update Flow Diagram
REV. PrJ 11/02
–3 7 –
PRELIMINARY TECHNICAL DATA
PROGRAMMING ADM1060
ADM1060
SE RIAL BUS INT E RF AC E
INT E RNAL RE GIST E RS O F T H E AD M1060
T he ADM1060 contains a large number of data registers.
A brief description of the principal registers is given be-
low. More detailed descriptions are given in the relevant
sections of the data sheet.
Control of the ADM1060 is carried out via the serial Sys-
tem Management Bus (SMBus). T he ADM1060 is con-
nected to this bus as a slave device, under the control of a
master device. It takes approximately 2ms after power up
for the ADM1060 to download from it's EEPROM.
T herefore access is restricted to the ADM1060 until the
download is completed.
Address Pointer Register: This register contains the address
that selects one of the other internal registers. When writing to
the ADM1060, the first byte of data is always a register ad-
dress, which is written to the Address Pointer Register.
ID E NT IF YING T H E AD M1060 O N T H E SMBUS
Configuration Registers: Provide control and configuration
for various operating parameters of the ADM1060.
T he ADM1060 has a 7-bit serial bus slave address. When
the device is powered up, it will do so with a default serial
bus address. T he five MSB's of the address are set to
10101, the two LSB's are determined by the logical states
of pin A1 and A0. T his allows the connection of 4
ADM1060’s to the one SMBus. T he device also has a
number of identification registers (read only) which can be
read across the SMBus. T hese are:-
P olar ity Register s: T hese registers define the polarity of
inputs to the PLBA
Mask Register s: Allow masking of individual inputs to the
PLBA and also masking of faults in the fault reporting
registers.
Na m e Addr ess
M AN ID 93h
Valu e F u n ction
E E P R O M
41h
Manufacturer ID for
T he ADM1060 has 512 bytes of non-volatile, Electrically-
Erasable Programmable Read-Only M emory (EEPROM ),
from register addresses F800h to F9FFh. T his may be
used for permanent storage of data that will not be lost
when the ADM1060 is powered down, unlike the data in
the volatile registers. Although referred to as Read Only
Memory, the EEPROM can be written to (as well as read
from) via the serial bus in exactly the same way as the
other registers. T he only major differences between the
E2PROM and other registers are:
Analog D evices
D evice ID
Silicon Revision
S/w brand
D E VID 94h
REVID 95h
MARK1 96h
MARK2 97h
3Eh
--h
--h
--h
S/w brand
G E NE RAL SM BUS T IM ING
Figures 8a and 8b show timing diagrams for general read
and write operations using the SMBus. T he SMBus speci-
fication defines specific conditions for different types of
read and write operation, which are discussed later.
1. An EEPROM location must be blank before it can be
written to. If it contains data, it must first be erased.
T he general SMBus protocol operates as follows:
2. Writing to EEPROM is slower than writing to RAM.
1. T he master initiates data transfer by establishing a
ST ART condition, defined as a high to low transition
on the serial data line SDA whilst the serial clock line
SCL remains high. T his indicates that a data stream
will follow. All slave peripherals connected to the serial
bus respond to the ST ART condition, and shift in the
next 8 bits, consisting of a 7-bit slave address (MSB
first) plus a R/W bit, which determines the direction of
the data transfer, i.e. whether data will be written to or
read from the slave device (0 = write, 1 = read).
3. Writing to the EEPROM should be restricted because
it has a limited write/cycle life of typically 10,000 write
operations, due to the usual EEPROM wear-out
mechanisms.
T he EEPROM is split into 16 (0 to 15) pages of 32 Bytes
each. Pages 0 to 6, starting at address F800, hold the
configuration data for the applications on the ADM1060
(the PLB, SFD’s, GPI’s, WDI, PDO’s etc.). T hese
EEPROM addresses are the same as the RAM register
addresses, prefixed by F8. Page 7 is reserved. Pages 8 to
15 are for customer use. Data can be downloaded from
EEPROM to RAM in one of 2 ways:-
T he peripheral whose address corresponds to the trans-
mitted address responds by pulling the data line low
during the low period before the ninth clock pulse,
known as the Acknowledge Bit, and holding it low dur-
ing the high period of this clock pulse. All other de-
vices on the bus now remain idle whilst the selected
device waits for data to be read from or written to it. If
the R/W bit is a 0 then the master will write to the slave
device. If the R/W bit is a 1 the master will read from
the slave device.
1. At Power- up, pages 0 to 6 are downloaded.
2. Setting bit 2 of the UPDCFG Register (90h) performs
a user download of pages 0 to 6.
2. Data is sent over the serial bus in sequences of 9 clock
pulses, 8 bits of data followed by an Acknowledge Bit
from the slave device. Data transitions on the data line
must occur during the low period of the clock signal
and remain stable during the high period, as a low to
high transition when the clock is high may be inter-
preted as a ST OP signal.
REV. PrJ 11/02
–3 8 –
PRELIMINARY TECHNICAL DATA
PROGRAMMING ADM1060
ADM1060
If the operation is a write operation, the first data byte
after the slave address is a command byte. T his tells the
slave device what to expect next. It may be an instruc-
tion such as telling the slave device to expect a block
write, or it may simply be a register address that tells
the slave where subsequent data is to be written.
to assert a ST OP condition. In READ mode, the mas-
ter device will release the SDA line during the low
period before the 9th clock pulse, but the slave device
will not pull it low. T his is known as No Acknowledge.
T he master will then take the data line low during the
low period before the 10th clock pulse, then high dur-
ing the 10th clock pulse to assert a ST OP condition.
Since data can flow in only one direction as defined by
the R/W bit, it is not possible to send a command to a
slave device during a read operation. Before doing a
read operation, it may first be necessary to do a write
operation to tell the slave what sort of read operation to
expect and/or the address from which data is to be read.
3. When all data bytes have been read or written, stop
conditions are established. In WRIT E mode, the master
will pull the data line high during the 10th clock pulse
1
9
1
9
SCL
SDA
0
1
0
1
1
A1
A0
R/W
ACK. BY
SLAVE
D7
D6
D5
D4
D3
D2
D1
D0
START BY
MASTER
ACK. BY
SLAVE
FRAME 1
SLAVE
ADDRESS
FRAME 2
COMMAND
CODE
1
9
1
9
SCL
(CONTINUED
)
SDA
(CONTINUED
)
D6
D4
D2
D7
D5
D3
D1
D0
D2
D7
D6
D5
D4
D3
D1
D0
ACK. BY
SLAVE
ACK. BY
SLAVE
STOP
BY
MASTER
FRAME N
DATA
BYTE
FRAME 3
DATA BYTE
Figure 8a. General SMBus Write Tim ing Diagram
1
9
1
9
SCL
SDA
0
1
0
1
1
A1
A0
R/W
ACK. BY
SLAVE
D7
D6
D5
D4
D3
D2
D1
D0
START BY
MASTER
ACK. BY
MASTER
FRAME 2
DATA
BYTE
FRAME 1
SLAVE
ADDRESS
1
9
1
9
SCL
(CONTINUED
)
SDA
(CONTINUED
)
D6
D4
D2
D7
D5
D3
D1
D0
D2
D7
D6
D5
D4
D3
D1
D0
ACK. BY
MASTER
STOP
BY
MASTER
NO ACK.
FRAME 3
DATA BYTE
FRAME N
DATA
BYTE
Figure 8b. General SMBus Read Tim ing Diagram
t
t
R
F
t
t
HD;ST
LO
A
W
SCL
SDA
t
t
t
HIG
SU;STA
SU;ST
t
t
t
HD;ST
HD;DA
H
SU;DA
O
A
T
T
t
BUF
S
P
S
P
Figure 8c. Diagram for Serial Bus Tim ing
REV. PrJ 11/02
–3 9 –
PRELIMINARY TECHNICAL DATA
ADM1060
PROGRAMMING ADM1060
SMBUS P RO T O C O LS F O R RAM AND E E P RO M
3. Erase a page of EEPROM memory. EEPROM
memory can be written to only if it is unprogrammed.
Before writing to one or more EEPROM memory
locations that are already programmed, the page or
pages containing those locations must first be erased.
EEPROM memory is erased by writing a command
byte.
T he ADM1060 contains volatile registers (RAM) and
non-volatile EEPROM. User RAM occupies address loca-
tions from 00h to DFh, whilst EEPROM occupies ad-
dresses from F800h to F9FFh.
Data can be written to and read from both RAM and
EEPROM as single data bytes.
T he master sends a command code that tells the slave
device to erase the page. T he ADM1060 command
code for a pages(s) erasure is FEh (11111110). Note
that, in order for page erasure to take place, the page
address has to be given in the previous write word
transaction (see write byte below). Also, bit 3 in regis-
ter UPDCFG (address 90h) must be set to 1.
Data can only be written to unprogrammed EEPROM
locations. T o write new data to a programmed location it
is first necessary to erase it. EEPROM erasure cannot be
done at the byte level, the EEPROM is arranged as 16
pages of 32 bytes, and an entire page must be erased.
Page erasure is enabled by setting bit 3 in register
UPDCFG (address 90h) to 1. If this is not set then page
erasure cannot occur, even if the command byte (FEh) is
programmed across the SMBus.
1
2
3
4
5
6
COMMAND
BYTE
SLAVE
S
W
A
A
P
ADDRESS
(FEh)
AD M 1060 WRIT E O P E RAT IO NS
Figure 9b. EEPROM Page Erasure
T he SMBus specification defines several protocols for
different types of read and write operations. T he ones used
in the ADM1060 are discussed below. T he following ab-
breviations are used in the diagrams:
As soon as the ADM1060 receives the command byte,
page erasure begins. T he master device can send a
ST OP command as soon as it sends the command
byte. Page erasure takes approximately 20ms. If the
ADM1060 is accessed before erasure is complete, it
will respond with No Acknowledge.
S
-
-
-
-
-
-
ST ART
P
S T O P
Wr ite Byte/Wor d
R
W
A
A
RE AD
In this operation the master device sends a command byte
and one or two data bytes to the slave device, as follows:
WRIT E
AC K N O W L E D G E
N O AC K N O WLED G E
1. T he master device asserts a start condition on SDA.
2. T he master sends the 7-bit slave address followed by
the write bit (low).
T he ADM1060 uses the following SMBus write protocols:
Send Byte
3. T he addressed slave device asserts ACK on SDA.
4. T he master sends a command code.
5. T he slave asserts ACK on SDA.
In this operation the master device sends a single com-
mand byte to a slave device, as follows:
1. T he master device asserts a start condition on SDA.
6. T he master sends a data byte.
2. T he master sends the 7-bit slave address followed by
the write bit (low).
7. T he slave asserts ACK on SDA.
8. T he master sends a data byte (or may assert ST OP at
this point).
3. T he addressed slave device asserts ACK on SDA.
4. T he master sends a command code.
5. T he slave asserts ACK on SDA.
9. T he slave asserts ACK on SDA.
10.T he master asserts a ST OP condition on SDA to end
the transaction.
6. T he master asserts a ST OP condition on SDA and the
transaction ends.
In the ADM1060, the write byte/word protocol is used for
three purposes.
In the ADM1060, the send byte protocol is used for two
purposes.
1. Write a single byte of data to RAM. In this case the
command byte is the RAM address from 00h to DFh
and the (only) data byte is the actual data. T his is illus-
trated in Figure 9c.
1. T o write a register address to RAM for a subsequent
single byte read from the same address or block read or
write starting at that address. T his is illustrated in Figure
9a.
1
2
3
4
5
6
7
8
1
2
3
4
5
6
RAM
SLAVE
RAM
S
W
A
ADDRESS
(00h TO DFh)
A
DATA
A
P
SLAVE
ADDRESS
S
W
A
ADDRESS
(00h TO DFh)
A
P
ADDRESS
Figure 9c. Single Byte Write To RAM
Figure 9a. Setting A RAM Address For Subsequent Read
2. Set up a two byte EEPROM address for a subsequent
read, write, block read, block write or page erase. In
REV. PrJ 11/02
–4 0 –
PRELIMINARY TECHNICAL DATA
PROGRAMMING ADM1060
ADM1060
this case the command byte is the high byte of the
EEPROM address from F8h to F9h. T he (only) data
byte is the low byte of the EEPROM address. T his is
illustrated in Figure 9c.
Unlike some EEPROM devices which limit block writes to
within a page boundary, there is no limitation on the start
address when performing a block write to EEPROM, except:
1. T here must be at least N locations from the start ad-
dress to the highest EEPROM address (F9FFh), to avoid-
ing writing to invalid addresses.
1
2
3
4
5
6
7
8
EEPROM
ADDRESS
EEPROM
ADDRESS
SLAVE
A
S
W
A
A
P
2. If the addresses cross a page boundary, both pages must
be erased before programming.
HIGH BYTE
(F8h TO F9h)
LOW BYTE
(00h TO FFh)
ADDRESS
Note that the ADM1060 features a clock extend function
for writes to EEPROM. Programming an EEPROM byte
takes approximately 250µs, which would limit the SMBus
clock for repeated or block write operations. T he
ADM1060 pulls SCL low and extends the clock pulse
when it cannot accept any more data.
Figure 9d. Setting An EEPROM Address
Note for page erasure that as a page consists of 32
bytes only the three MSB’s of the address low byte are
important. T he lower 5 bits of the EEPROM address
low byte only specify addresses within a page and are
ignored during an erase operation.
3. Write a single byte of data to EEPROM. In this case
the command byte is the high byte of the EEPROM
address from F8h to F9h. T he first data byte is the low
byte of the EEPROM address and the second data byte
is the actual data. T his is illustrated in Figure 9e.
AD M 1060 RE AD O P E RAT IO NS
T he ADM1060 uses the following SMBus read protocols:
RE C E IVE B YT E
In this operation the master device receives a single byte
from a slave device, as follows:
1
2
3
4
5
6
7
8
9
10
EEPROM
ADDRESS
EEPROM
ADDRESS
1.T he master device asserts a ST ART condition on SDA.
SLAVE
S
W
A
A
A
DATA
A
P
HIGH BYTE
(F8h TO F9h)
LOW BYTE
(00h TO FFh)
ADDRESS
2.T he master sends the 7-bit slave address followed by the
read bit (high).
Figure 9e. Single Byte Write To EEPROM
3.T he addressed slave device asserts ACK on SDA.
4.T he master receives a data byte.
Block Wr ite
In this operation the master device writes a block of data
to a slave device. T he start address for a block write must
previously have been set. In the case of the ADM1060 this
is done by a Send Byte operation to set a RAM address or
a Write Byte/Word operation to set an EEPROM address.
5.T he master asserts NO ACK on SDA.
6.T he master asserts a ST OP condition on SDA and the
transaction ends.
In the ADM1060, the receive byte protocol is used to read
a single byte of data from a RAM or EEPROM location
whose address has previously been set by a send byte or
write byte/word operation. T his is illustrated in Figure 9g.
1. T he master device asserts a start condition on SDA.
2. T he master sends the 7-bit slave address followed by
the write bit (low).
1
2
3
4
5
6
3. T he addressed slave device asserts ACK on SDA.
SLAVE
S
R
A
A
P
DATA
ADDRESS
4. T he master sends a command code that tells the slave
device to expect a block write. T he ADM1060 com-
mand code for a block write is FCh (11111100).
Figure 9g. Single Byte Read From EEPROM Or RAM
Block Read
5. T he slave asserts ACK on SDA.
In this operation the master device reads a block of data
from a slave device. T he start address for a block read
must previously have been set. In the case of the
ADM1060 this is done by a Send Byte operation to set a
RAM address, or a Write Byte/Word operation to set an
EEPROM address. T he block read operation itself
consists of a Send Byte operation that sends a block read
command to the slave, immediately followed by a repeated
start and a read operation that reads out multiple data
bytes, as follows:
6. T he master sends a data byte that tells the slave device
how many data bytes will be sent. T he SMBus specifi-
cation allows a maximum of 32 data bytes to be sent in
a block write.
7. T he slave asserts ACK on SDA.
8. T he master sends N data bytes.
9. The slave asserts ACK on SDA after each data byte.
10. The master asserts a STOP condition on SDA to end the
transaction.
1.T he master device asserts a ST ART condition on SDA.
2.T he master sends the 7-bit slave address followed by the
write bit (low).
1
2
3
4
5
6
7
8
9
10
P
3.T he addressed slave device asserts ACK on SDA.
SLAVE
ADDRESS
COMMAND FCh
(BLOCK WRITE)
BYTE
COUNT
S
W A
A
A DATA 1 A DATA 2 A DATA N A
4.T he master sends a command code that tells the slave
device to expect a block read. T he ADM1060 command
code for a block read is FDh (11111101).
Figure 9f. Block Write To EEPROM Or RAM
REV. PrJ 11/02
–4 1 –
PRELIMINARY TECHNICAL DATA
PROGRAMMING ADM1060
ADM1060
5. T he slave asserts ACK on SDA.
6. T he master asserts a repeat start condition on SDA.
7. T he master sends the 7-bit slave address followed by the
read bit (high).
8. T he slave asserts ACK on SDA.
9. T he ADM1060 sends a byte count data byte that tells
the master how many data bytes to expect. T he ADM1060
will always return 32 data bytes (20h), which is the maxi-
mum allowed by the SMBus 1.1 specification.
10. T he master asserts ACK on SDA.
11. T he master receives 32 data bytes.
12. T he master asserts ACK on SDA after each data byte.
13. T he master asserts a ST OP condition on SDA to end
the transaction.
1
2
3
4
5
6
7
8
9
10
A
11
12
COMMAND FDh
(BLOCK READ)
BYTE
SLAVE
SLAVE
A
S
R
A
DATA 1 A
S
W
A
COUNT
ADDRESS
ADDRESS
14
P
13
DATA
32
A
Figure 9h. Block Read From EEPROM or RAM
E RRO R CO RRE CTIO N
T he ADM1060 provides the option of issuing a PEC
(Packet Error Correction) byte after a write to RAM, a
write to EEPROM, a block write to RAM/EEPROM or a
block read from RAM/EEPROM. T his enables the user
to verify that the data received by or sent from the
ADM1060 is correct.
T he PEC byte is an optional byte
sent after that last data byte has been written to or read
from the ADM1060. T he protocol is as follows:-
1. T he ADM1060 issues a PEC byte to the master. T he
master should check the PEC byte and issue another block
read if the PEC byte is incorrect.
2. A NACK is generated after the PEC byte to signal the
end of the read.
Note: T he PEC byte is calculated using CRC-8. T he
Frame Check Sequence (FCS) conforms to CRC-8 by the
polynomial:-
C(x) = x8 + x2 + x1 + 1
Consult SMBus 1.1 specification for more information.
An example of a block read with the optional PEC byte is
shown in figure 9i below.
1
2
3
4
5
6
7
8
9
10
A
11
12
COMMAND FDh
(BLOCK READ)
SLAVE
BYTE
SLAVE
A
S
R
A
DATA 1 A
S
W
A
COUNT
ADDRESS
ADDRESS
13 14
15
P
DATA
32
A
PEC A
Figure 9i. Block Read From EEPROM or RAM with PEC
REV. PrJ 11/02
–4 2 –
PRELIMINARY TECHNICAL DATA
ADM1060
+5V_IN
+5V_OUT
+5VSB_IN
+5VSB_OUT
+3.3V_OUT
+3.3V_IN
+3.3VSB_IN
+3.3VSB_OUT
0.1F
0.1F
VDDCAP
VCCP
+12V_IN
VH
VP1
VP2
VP3
VP4
PDO1
PDO2
PDO3
PDO4
PDO5
PDO6
PDO7
PDO8
PDO9
ADM1060
VB1
VB2
PWR_OK
-5V_IN
GPI1
GPI2
GPI3
GPI4
P
W
R
G
O
O
D
R
E
S
E
T
VIN_I/O
PWRGD
VOUT
VIN
WDI
LDO
ACK
A0 A1
SCL SDA
CLKOUT
EN
0.9V_OUT
+1.8V
VOUT
VIN_CORE
+3.3V
VIN
LDO
P
EN
VIN
VOUT
-5V_OUT
LDO
Figure 10. ADM1060 Application Diagram
REV. PrJ 11/02
–4 3 –
ADM1060Register Map
B LO C K
P LB1
P LB2
P LB3
P LB4
P LB5
P LB6
P LB7
P LB8
P LB9
0
1
2
3
4
5
6
7
8
9
A
B
C
D
0
1
2
3
4
5
6
7
8
9
P1PLBPOLA
P2PLBPOLA
P3PLBPOLA
P4PLBPOLA
P5PLBPOLA
P6PLBPOLA
P7PLBPOLA
P8PLBPOLA
P9PLBPOLA
UPDCFG
P1PLBIMKA
P2PLBIMKA
P3PLBIMKA
P4PLBIMKA
P5PLBIMKA
P6PLBIMKA
P7PLBIMKA
P8PLBIMKA
P9PLBIMKA
PDEN
P1SFDPOLA
P2SFDPOLA
P3SFDPOLA
P4SFDPOLA
P5SFDPOLA
P6SFDPOLA
P7SFDPOLA
P8SFDPOLA
P9SFDPOLA
P1SFDIMKA
P2SFDIMKA
P3SFDIMKA
P4SFDIMKA
P5SFDIMKA
P6SFDIMKA
P7SFDIMKA
P8SFDIMKA
P9SFDIMKA
MANID
P1GPIPOL
P2GPIPOL
P3GPIPOL
P4GPIPOL
P5GPIPOL
P6GPIPOL
P7GPIPOL
P8GPIPOL
P9GPIPOL
DEVID
P1GPIIMK
P2GPIIMK
P3GPIIMK
P4GPIIMK
P5GPIIMK
P6GPIIMK
P7GPIIMK
P8GPIIMK
P9GPIIMK
REVID
P1WDICFG
P2WDICFG
P3WDICFG
P4WDICFG
P5WDICFG
P6WDICFG
P7WDICFG
P8WDICFG
P9WDICFG
MARK1
P1EN
P2EN
P3EN
P4EN
P5EN
P6EN
P7EN
P8EN
P9EN
MARK2
P1PLBPOLB
P2PLBPOLB
P3PLBPOLB
P4PLBPOLB
P5PLBPOLB
P6PLBPOLB
P7PLBPOLB
P8PLBPOLB
P9PLBPOLB
GPI1CFG
P1PLBIMKB
P2PLBIMKB
P3PLBIMKB
P4PLBIMKB
P5PLBIMKB
P6PLBIMKB
P7PLBIMKB
P8PLBIMKB
P9PLBIMKB
GPI2CFG
P1SFDPOLB
P2SFDPOLB
P3SFDPOLB
P4SFDPOLB
P5SFDPOLB
P6SFDPOLB
P7SFDPOLB
P8SFDPOLB
P9SFDPOLB
GPI3CFG
P1SFDIMKB
P2SFDIMKB
P3SFDIMKB
P4SFDIMKB
P5SFDIMKB
P6SFDIMKB
P7SFDIMKB
P8SFDIMKB
P9SFDIMKB
GPI4CFG
P1PDBTIM
P2PDBTIM
P3PDBTIM
P4PDBTIM
P5PDBTIM
P6PDBTIM
P7PDBTIM
P8PDBTIM
P9PDBTIM
WDICFG
P1PDOCFG
P2PDOCFG
P3PDOCFG
P4PDOCFG
P5PDOCFG
P6PDOCFG
P7PDOCFG
P8PDOCFG
P9PDOCFG
F LT /ST S
GP I/WD I
ERRMASK1
ERRMASK2
E
B SF D 1/2
H /P SF D 1
P SF D 2/3
A
B
C
D
BS1OVTH
HSOVTH
PS2OVTH
PS4OVTH
BS1OVHYST
HSOVHYST
PS2OVHYST
PS4OVHYST
BS1UVTH
HSUVTH
PS2UVTH
PS4UVTH
BS1UVHYST
HSUVHYST
PS2UVHYST
PS4UVHYST
BS1SEL
HSSEL
PS2SEL
PS4SEL
BS2OVTH
PS1OVTH
PS3OVTH
UVSTAT
BS2OVHYST
PS1OVHYST
PS3OVHYST
OVSTAT
BS2UVTH
PS1UVTH
PS3UVTH
SFDSTAT
BS2UVHYST
PS1UVHYST
PS3UVHYST
GWSTAT
BS2SEL
PS1SEL
PS3SEL
LATF1
P SF D 4/
LATF2
F LT /ST S
E
F
PDOSTAT1
PDOSTAT2
PRELIMINARY TECHNICAL DATA
ADM1060
O UTLINE D IMENSIO NS
D im ensions shown in inches and (m m )
28- Lead TSSO P (RU-28)
0.386 (9.80)
0.378 (9.60)
28
15
14
1
PIN 1
0.006 (0.15)
0.002 (0.05)
0.0433
(1.10)
MAX
o
o
8
0
0.028 (0.70)
0.020 (0.50)
0.0118 (0.30)
0.0075 (0.19)
0.0256 (0.65)
BSC
SEATING
PLANE
0.0079 (0.20)
0.0035 (0.090)
Revision H istor y
Rev. H
1. Update of specs. pages
2. Inclusion of T able of Contents
3. Inclusion of EEPROM download at Power- Up (p.38)
2Rev. G
1. Update of specs. pages (better definition of supply conditions, inclusion of input impedance, better definition of PDO
output conditions).
2. Removal of PUEN (pull-up current source on logic inputs) function (See Rev. F-7).
Rev. F
1. Update of specs. to reflect 14V drive capability of charge pumped outputs.
2. Correction of features on bipolar SFD’s- only 1 range available in negative mode.
3. Better definition of SFD Glitch Filter
4. Completion of register map- addition of table numbers for each register, addition of register map matrix (p.43)
5. Improved definition of all ADM1060 blocks.
6. Definition of fault/status reporting on the ADM1060
7. Addition of Pull- Up/Down current source on logic inputs
8. Corrected version of how SMBus protocol is implemented on the ADM1060.
9. Inclusion of device ID registers (p.37)
REV. PrJ 11/02
–4 5 –
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