ADM1062ACPZ [ADI]
Super Sequencer with Margining Control and Temperature Monitoring; 超序与余量控制和温度监测
| 型号： | ADM1062ACPZ |
| 厂家： | 
ADI |
| 描述： | Super Sequencer with Margining Control and Temperature Monitoring |
| 文件： | 总36页 (文件大小：629K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Super Sequencer with Margining Control
and Temperature Monitoring
ADM1062
FEATURES
FUNCTIONAL BLOCK DIAGRAM
DP DN
REFIN REFOUT REFGND SDA SCL A1
A0
Complete supervisory and sequencing solution for up to
10 supplies
ADM1062
10 supply fault detectors enable supervision of supplies to
<0.5% accuracy at all voltages at 25°C
<1.0% accuracy across all voltages and temperatures
5 selectable input attenuators allow supervision of supplies to
14.4 V on VH
SMBus
INTERFACE
VREF
TEMP
SENSOR
INTERNAL
DIODE
12-BIT
SAR ADC
EEPROM
CLOSED-LOOP
MARGINING SYSTEM
6 V on VP1 to VP4 (VPx)
VX1
VX2
VX3
VX4
VX5
PDO1
PDO2
PDO3
PDO4
PDO5
PDO6
5 dual-function inputs, VX1 to VX5 (VXx)
High impedance input to supply fault detector with
thresholds between 0.573 V and 1.375 V
General-purpose logic input
10 programmable driver outputs, PDO1 to PDO10 (PDOx)
Open-collector with external pull-up
Push/pull output, driven to VDDCAP or VPx
Open collector with weak pull-up to VDDCAP or VPx
Internally charge-pumped high drive for use with external
N-FET (PDO1 to PDO6 only)
Sequencing engine (SE) implements state machine control of
PDO outputs
CONFIGURABLE
OUTPUT
DRIVERS
DUAL-
FUNCTION
INPUTS
(LOGIC INPUTS
OR
(HV CAPABLE OF
DRIVING GATES
OF N-FET)
SFDs)
SEQUENCING
ENGINE
VP1
VP2
VP3
VP4
VH
PDO7
PDO8
PDO9
CONFIGURABLE
OUTPUT
DRIVERS
PROGRAMMABLE
RESET
GENERATORS
(LV CAPABLE
OF DRIVING
LOGIC SIGNALS)
(SFDs)
PDO10
AGND
PDOGND
VDDCAP
VDD
ARBITRATOR
VOUT VOUT VOUT VOUT VOUT VOUT
DAC DAC DAC DAC DAC DAC
State changes conditional on input events
Enables complex control of boards
DAC1 DAC2 DAC3 DAC4 DAC5 DAC6
VCCP GND
Figure 1.
Power-up and power-down sequence control
Fault event handling
Interrupt generation on warnings
APPLICATIONS
Central office systems
Watchdog function can be integrated in SE
Program software control of sequencing through SMBus
Complete voltage margining solution for 6 voltage rails
6 voltage output, 8-bit DACs (0.300 V to 1.551 V) allow voltage
adjustment via dc-to-dc converter trim/feedback node
12-bit ADC for readback of all supervised voltages
Internal and external temperature sensors
Reference input (REFIN) has 2 input options
Driven directly from 2.048 V ( 0.25%) REFOUT pin
More accurate external reference for improved
ADC performance
Device powered by the highest of VPx, VH for improved
redundancy
User EEPROM: 256 bytes
Industry-standard 2-wire bus interface (SMBus)
Guaranteed PDO low with VH, VPx = 1.2 V
Available in 40-lead, 6 mm × 6 mm LFCSP and
48-lead, 7 mm × 7 mm TQFP packages
Servers/routers
Multivoltage system line cards
DSP/FPGA supply sequencing
In-circuit testing of margined supplies
GENERAL DESCRIPTION
The ADM1062 Super Sequencer® is a configurable supervisory/
sequencing device that offers a single-chip solution for supply
monitoring and sequencing in multiple-supply systems. In addition
to these functions, the ADM1062 integrates a 12-bit ADC and six
8-bit voltage output DACs. These circuits can be used to implement
a closed-loop margining system that enables supply adjustment
by altering either the feedback node or the reference of a dc-to-dc
converter using the DAC outputs.
For more information about the ADM1062 register map,
refer to the AN-698 Application Note at www.analog.com.
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2005–2011 Analog Devices, Inc. All rights reserved.
ADM1062
TABLE OF CONTENTS
Features .............................................................................................. 1
Sequencing Engine Application Example............................... 19
Fault and Status Reporting........................................................ 20
Voltage Readback............................................................................ 21
Supply Supervision with the ADC........................................... 21
Supply Margining ........................................................................... 22
Overview ..................................................................................... 22
Open-Loop Supply Margining ................................................. 22
Closed-Loop Supply Margining............................................... 22
Writing to the DACs .................................................................. 23
Choosing the Size of the Attenuation Resistor....................... 23
DAC Limiting and Other Safety Features ............................... 23
Temperature Measurement System.............................................. 24
Remote Temperature Measurement ........................................ 24
Applications Diagram.................................................................... 26
Communicating with the ADM1062........................................... 27
Configuration Download at Power-Up................................... 27
Updating the Configuration ..................................................... 27
Updating the Sequencing Engine............................................. 28
Internal Registers........................................................................ 28
EEPROM ..................................................................................... 28
Serial Bus Interface..................................................................... 28
SMBus Protocols for RAM and EEPROM.............................. 31
Write Operations........................................................................ 31
Read Operations......................................................................... 32
Outline Dimensions....................................................................... 34
Ordering Guide .......................................................................... 35
Functional Block Diagram .............................................................. 1
Applications....................................................................................... 1
General Description......................................................................... 1
Revision History ............................................................................... 3
Detailed Block Diagram .................................................................. 4
Specifications..................................................................................... 5
Absolute Maximum Ratings............................................................ 8
Thermal Resistance ...................................................................... 8
ESD Caution.................................................................................. 8
Pin Configurations and Function Descriptions ........................... 9
Typical Performance Characteristics ........................................... 11
Powering the ADM1062................................................................ 14
Inputs................................................................................................ 15
Supply Supervision..................................................................... 15
Programming the Supply Fault Detectors............................... 15
Input Comparator Hysteresis.................................................... 15
Input Glitch Filtering ................................................................. 16
Supply Supervision with VXx Inputs....................................... 16
VXx Pins as Digital Inputs ........................................................ 16
Outputs ............................................................................................ 17
Supply Sequencing Through Configurable Output Drivers. 17
Default Output Configuration.................................................. 17
Sequencing Engine ......................................................................... 18
Overview...................................................................................... 18
Warnings...................................................................................... 18
SMBus Jump (Unconditional Jump)........................................ 18
Rev. C | Page 2 of 36
ADM1062
REVISION HISTORY
6/11—Rev. B to Rev. C
12/06—Rev. 0 to Rev. A
Changes to Serial Bus Timing Parameter in Table 1 ....................5
Change to Figure 3 ............................................................................9
Added Exposed Pad Notation to Outline Dimensions ..............34
Changes to Ordering Guide...........................................................35
Updated Format ................................................................. Universal
Changes to Features..........................................................................1
Changes to Figure 2 ..........................................................................3
Changes to Table 1 ............................................................................4
Changes to Table 2 ............................................................................7
Changes to Absolute Maximum Ratings Section .........................9
Changes to Programming the Supply Fault Detectors Section ...14
Changes to Table 6 ..........................................................................14
Changes to Outputs Section ..........................................................16
Changes to Fault Reporting Section.............................................20
Changes to Table 9 ..........................................................................21
Changes to Identifying the ADM1062
5/08—Rev. A to Rev. B
Changes to Table 1 ............................................................................4
Changes to Powering the ADM1062 Section ..............................13
Changes to Table 5 ..........................................................................14
Changes to Sequence Detector Section........................................18
Changes to Temperature Measurement System Section............23
Changes to Table 11 ........................................................................24
Changes to Configuration Download at Power-Up Section .....26
Changes to Table 12 ........................................................................27
Changes to Figure 49 and Error Correction Section..................32
Changes to Ordering Guide...........................................................34
on the SMBus Section.....................................................................28
Changes to Figure 39 and Figure 30 .............................................30
4/05—Revision 0: Initial Version
Rev. C | Page 3 of 36
ADM1062
Supply margining can be performed with a minimum of external
components. The margining loop can be used for in-circuit
testing of a board during production (for example, to verify
board functionality at −5% of nominal supplies), or it can be
used dynamically to accurately control the output voltage of
a dc-to-dc converter.
Temperature measurement is possible with the ADM1062. The
device contains one internal temperature sensor and a differen-
tial input for a remote thermal diode. Both are measured by the
12-bit ADC.
The logical core of the device is a sequencing engine. This state-
machine-based construction provides up to 63 different states.
This design enables very flexible sequencing of the outputs,
based on the condition of the inputs.
The device also provides up to 10 programmable inputs for
monitoring undervoltage faults, overvoltage faults, or out-of-
window faults on up to 10 supplies. In addition, 10 programmable
outputs can be used as logic enables. Six of these programmable
outputs can also provide up to a 12 V output for driving the gate
of an N-FET that can be placed in the path of a supply.
The ADM1062 is controlled via configuration data that can be
programmed into an EEPROM. The entire configuration can
be programmed using an intuitive GUI-based software package
provided by Analog Devices, Inc.
DETAILED BLOCK DIAGRAM
REFIN REFOUT
DP DN
REFGND SDA SCL A1
SMBus
VREF
A0
TEMP
SENSOR
INTERNAL
DIODE
ADM1062
INTERFACE
OSC
12-BIT
SAR ADC
DEVICE
CONTROLLER
EEPROM
GPI SIGNAL
CONDITIONING
CONFIGURABLE
OUTPUT DRIVER
(HV)
PDO1
VX1
SFD
PDO2
PDO3
PDO4
PDO5
VX2
VX3
VX4
GPI SIGNAL
CONDITIONING
CONFIGURABLE
OUTPUT DRIVER
(HV)
PDO6
SEQUENCING
ENGINE
VX5
VP1
SFD
SFD
CONFIGURABLE
OUTPUT DRIVER
(LV)
SELECTABLE
ATTENUATOR
PDO7
VP2
VP3
VP4
PDO8
PDO9
CONFIGURABLE
OUTPUT DRIVER
(LV)
SELECTABLE
ATTENUATOR
VH
SFD
PDO10
AGND
PDOGND
REG 5.25V
CHARGE PUMP
V
V
OUT
DAC
OUT
DAC
VDDCAP
VDD
ARBITRATOR
GND
VCCP
DAC1 DAC2 DAC3 DAC4 DAC5 DAC6
Figure 2.
Rev. C | Page 4 of 36
ADM1062
SPECIFICATIONS
VH = 3.0 V to 14.4 V1, VPx = 3.0 V to 6.0 V1, TA = −40°C to +85°C, unless otherwise noted.
Table 1.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
POWER SUPPLY ARBITRATION
VH, VPx
VPx
VH
VDDCAP
3.0
V
V
V
V
Minimum supply required on one of the VH, VPx pins
Maximum VDDCAP = 5.1 V, typical
VDDCAP = 4.75 V
Regulated LDO output
Minimum recommended decoupling capacitance
6.0
14.4
5.4
2.7
10
4.75
CVDDCAP
μF
POWER SUPPLY
Supply Current, IVH, IVPx
Additional Currents
All PDO FET Drivers On
4.2
1
6
2
mA
VDDCAP = 4.75 V, PDO1 to PDO10 off, DACs off, ADC off
mA
mA
VDDCAP = 4.75 V, PDO1 to PDO6 loaded with 1 μA each,
PDO7 to PDO10 off
Maximum additional load that can be drawn from all
PDO pull-ups to VDDCAP
Current Available from VDDCAP
DAC Supply Currents
ADC Supply Current
EEPROM Erase Current
SUPPLY FAULT DETECTORS
VH Pin
2.2
1
10
mA
mA
mA
Six DACs on with 100 μA maximum load on each
Running round-robin loop
1 ms duration only, VDDCAP = 3 V
Input Impedance
Input Attenuator Error
Detection Ranges
High Range
52
0.05
kΩ
%
Midrange and high range
6
2.5
14.4
6
V
V
Midrange
VPx Pins
Input Impedance
Input Attenuator Error
Detection Ranges
Midrange
Low Range
Ultralow Range
VXx Pins
Input Impedance
Detection Range
Ultralow Range
Absolute Accuracy
52
0.05
kΩ
%
Low range and midrange
No input attenuation error
No input attenuation error
2.5
1.25
0.573
6
3
V
V
V
1.375
1
MΩ
0.573
1.375
1
V
%
VREF error + DAC nonlinearity + comparator offset error +
input attenuation error
Threshold Resolution
Digital Glitch Filter
8
0
100
Bits
μs
μs
Minimum programmable filter length
Maximum programmable filter length
ANALOG-TO-DIGITAL CONVERTER
Signal Range
0
VREFIN
V
The ADC can convert signals presented to the VH, VPx,
and VXx pins; VPx and VH input signals are attenuated
depending on the selected range; a signal at the pin
corresponding to the selected range is from 0.573 V to
1.375 V at the ADC input
Input Reference Voltage on REFIN Pin, VREFIN
Resolution
INL
2.048
12
V
Bits
LSB
%
2.5
0.05
Endpoint corrected, VREFIN = 2.048 V
VREFIN = 2.048 V
Gain Error
Rev. C | Page 5 of 36
ADM1062
Parameter
Min
Typ
0.44
84
Max
Unit
ms
ms
Test Conditions/Comments
One conversion on one channel
All 12 channels selected, 16× averaging enabled
VREFIN = 2.048 V
Conversion Time
Offset Error
2
LSB
Input Noise
0.25
LSB rms Direct input (no attenuator)
TEMPERATURE SENSOR2
Local Sensor Accuracy
3
−1.7
3
−3
200
12
°C
°C/V
°C
VDDCAP = 4.75 V
VDDCAP = 4.75 V
Local Sensor Supply Voltage Coefficient
Remote Sensor Accuracy
Remote Sensor Supply Voltage Coefficient
Remote Sensor Current Source
°C
μA
μA
°C
°C
°C
High level
Low level
VDDCAP = 4.75 V
VDDCAP = 4.75 V
Temperature for Code 0x800
Temperature for Code 0xC00
Temperature Resolution per Code
BUFFERED VOLTAGE OUTPUT DACs
Resolution
0
128
0.125
8
Bits
Code 0x80 Output Voltage
Six DACs are individually selectable for centering on
one of four output voltage ranges
Range 1
Range 2
Range 3
Range 4
Output Voltage Range
LSB Step Size
0.592 0.6
0.796 0.8
0.603
0.803
1.003
1.253
V
V
V
V
mV
mV
0.996
1.246 1.25
601.25
1
Same range, independent of center point
Endpoint corrected
2.36
INL
0.75 LSB
DNL
Gain Error
0.4
LSB
%
1
Maximum Load Current (Source)
Maximum Load Current (Sink)
Maximum Load Capacitance
Settling Time to 50 pF Load
Load Regulation
PSRR
100
100
μA
μA
pF
μs
mV
dB
dB
50
2
2.5
60
40
Per mA
DC
100 mV step in 20 ns with 50 pF load
REFERENCE OUTPUT
Reference Output Voltage
Load Regulation
2.043 2.048
2.053
V
No load
−0.25
+0.25
mV
mV
μF
dB
Sourcing current, IDACxMAX = −100 μA
Sinking current, IDACxMAX = +100 μA
Capacitor required for decoupling, stability
DC
Minimum Load Capacitance
PSRR
1
60
PROGRAMMABLE DRIVER OUTPUTS (PDOs)
High Voltage (Charge Pump) Mode
(PDO1 to PDO6)
Output Impedance
VOH
500
12.5
12
kΩ
V
V
11
10.5
14
13.5
IOH = 0 μA
IOH = 1 μA
IOUTAVG
20
μA
2 V < VOH < 7 V
Standard (Digital Output) Mode
(PDO1 to PDO10)
VOH
2.4
V
V
V
V
VPU (pull-up to VDDCAP or VPx) = 2.7 V, IOH = 0.5 mA
VPU to VPx = 6.0 V, IOH = 0 mA
VPU ≤ 2.7 V, IOH = 0.5 mA
4.5
VPU − 0.3
0
VOL
0.50
IOL = 20 mA
Rev. C | Page 6 of 36
ADM1062
Parameter
Min
Typ
Max
20
60
29
2
Unit
mA
mA
kΩ
Test Conditions/Comments
Maximum sink current per PDOx pin
Maximum total sink for all PDOx pins
Internal pull-up
Current load on any VPx pull-ups, that is, total source
current available through any number of PDOx pull-up
switches configured onto any one VPx pin
3
IOL
ISINK
3
RPULL-UP
ISOURCE (VPx)3
16
20
mA
Three-State Output Leakage Current
Oscillator Frequency
10
110
μA
kHz
VPDO = 14.4 V
All on-chip time delays derived from this clock
90
2.0
−1
100
DIGITAL INPUTS (VXx, A0, A1)
Input High Voltage, VIH
Input Low Voltage, VIL
Input High Current, IIH
Input Low Current, IIL
V
V
μA
μA
pF
μA
Maximum VIN = 5.5 V
Maximum VIN = 5.5 V
VIN = 5.5 V
0.8
1
VIN = 0 V
Input Capacitance
5
20
Programmable Pull-Down Current, IPULL-DOWN
SERIAL BUS DIGITAL INPUTS (SDA, SCL)
Input High Voltage, VIH
VDDCAP = 4.75 V TA = 25°C if known logic state is required
2.0
V
V
V
Input Low Voltage, VIL
Output Low Voltage, VOL
0.8
0.4
3
IOUT = −3.0 mA
SERIAL BUS TIMING4
Clock Frequency, fSCLK
Bus Free Time, tBUF
Start Setup Time, tSU;STA
Stop Setup Time, tSU;STO
Start Hold Time, tHD;STA
SCL Low Time, tLOW
SCL High Time, tHIGH
SCL, SDA Rise Time, tR
SCL, SDA Fall Time, tF
Data Setup Time, tSU;DAT
Data Hold Time, tHD;DAT
Input Low Current, IIL
SEQUENCING ENGINE TIMING
State Change Time
400
kHz
μs
μs
μs
μs
μs
μs
ns
ns
ns
ns
μA
1.3
0.6
0.6
0.6
1.3
0.6
300
300
100
5
1
VIN = 0 V
10
μs
1 At least one of the VH, VPx pins must be ≥3.0 V to maintain the device supply on VDDCAP.
2 All temperature sensor measurements are taken with round-robin loop enabled and at least one other voltage input being measured.
3 Specification is not production tested but is supported by characterization data at initial product release.
4 Timing specifications are guaranteed by design and supported by characterization data.
Rev. C | Page 7 of 36
ADM1062
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rating
Voltage on VH Pin
Voltage on VPx Pins
Voltage on VXx Pins
16 V
7 V
−0.3 V to +6.5 V
−0.3 V to +7 V
5 V
6.5 V
16 V
7 V
Voltage on A0, A1 Pins
Voltage on REFIN, REFOUT Pins
Voltage on VDDCAP, VCCP Pins
Voltage on PDOx Pins
Voltage on SDA, SCL Pins
Voltage on GND, AGND, PDOGND,
REFGND Pins
Voltage on DN, DP Pins
Input Current at Any Pin
Package Input Current
Maximum Junction Temperature (TJ max)
Storage Temperature Range
Lead Temperature,
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
−0.3 V to +0.3 V
Table 3. Thermal Resistance
−0.3 V to +5 V
5 mA
20 mA
150°C
−65°C to +150°C
215°C
Package Type
40-Lead LFCSP
48-Lead TQFP
θJA
25
50
Unit
°C/W
°C/W
ESD CAUTION
Soldering Vapor Phase, 60 sec
ESD Rating, All Pins
2000 V
Rev. C | Page 8 of 36
ADM1062
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
40 39 38 37 36 35 34 33 32 31
48 47 46 45 44 43 42 41 40 39 38 37
VX1
VX2
VX3
VX4
VX5
VP1
VP2
VP3
VP4
1
2
3
4
5
6
7
8
9
30 PDO1
29 PDO2
28 PDO3
27 PDO4
26 PDO5
25 PDO6
24 PDO7
23 PDO8
22 PDO9
21 PDO10
PIN 1
INDICATOR
NC
VX1
VX2
VX3
VX4
VX5
VP1
VP2
VP3
1
2
3
4
5
6
7
8
9
36 NC
PIN 1
INDICATOR
35 PDO1
34 PDO2
33 PDO3
32 PDO4
31 PDO5
30 PDO6
29 PDO7
28 PDO8
27 PDO9
26 PDO10
25 NC
ADM1062
TOP VIEW
(Not to Scale)
ADM1062
TOP VIEW
(Not to Scale)
VH 10
VP4 10
VH 11
NC 12
11 12 13 14 15 16 17 18 19 20
13 14 15 16 17 18 19 20 21 22 23 24
NOTES
1. THE LFCSP HAS AN EXPOSED PAD ON THE BOTTOM.
THIS PAD IS A NO CONNECT (NC). IF POSSIBLE, THIS
PAD SHOULD BE SOLDERED TO THE BOARD FOR
IMPROVED MECHANICAL STABILITY.
NC = NO CONNECT
Figure 3. LFCSP Pin Configuration
Figure 4. TQFP Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
LFCSP1 TQFP
Mnemonic
Description
1, 12, 13,
NC
No Connection.
24, 25, 36,
37, 48
1 to 5
6 to 9
2 to 6
VX1 to VX5 (VXx) High Impedance Inputs to Supply Fault Detectors. Fault thresholds can be set from 0.573 V to
1.375 V. Alternatively, these pins can be used as general-purpose digital inputs.
VP1 to VP4 (VPx) Low Voltage Inputs to Supply Fault Detectors. Three input ranges can be set by altering the input
attenuation on a potential divider connected to these pins, the output of which connects to a supply
fault detector. These pins allow thresholds from 2.5 V to 6.0 V, from1.25 V to 3.00 V, and from 0.573 V
to 1.375 V.
7 to 10
10
11
VH
High Voltage Input to Supply Fault Detectors. Two input ranges can be set by altering the input
attenuation on a potential divider connected to this pin, the output of which connects to a
supply fault detector. This pin allows thresholds from 6.0 V to 14.4 V and from 2.5 V to 6.0 V.
11
12
13
14
15
16
AGND2
REFGND2
REFIN
Ground Return for Input Attenuators.
Ground Return for On-Chip Reference Circuits.
Reference Input for ADC. Nominally, 2.048 V. This pin must be driven by a reference voltage.
The on-board reference can be used by connecting the REFOUT pin to the REFIN pin.
14
17
REFOUT
Reference Output, 2.048 V. Typically connected to REFIN. Note that the capacitor must be
connected between this pin and REFGND. A 10 μF capacitor is recommended for this purpose.
15 to 20 18 to 23
21 to 30 26 to 35
DAC1 to DAC6
PDO10 to PDO1
PDOGND2
Voltage Output DACs. These pins default to high impedance at power-up.
Programmable Output Drivers.
Ground Return for Output Drivers.
Central Charge Pump Voltage of 5.25 V. A reservoir capacitor must be connected between this
pin and GND. A 10 μF capacitor is recommended for this purpose.
31
32
38
39
VCCP
33
34
35
36
37
38
40
41
42
43
44
45
A0
A1
SCL
SDA
DN
DP
Logic Input. This pin sets the seventh bit of the SMBus interface address.
Logic Input. This pin sets the sixth bit of the SMBus interface address.
SMBus Clock Pin. Bidirectional open drain requires external resistive pull-up.
SMBus Data Pin. Bidirectional open drain requires external resistive pull-up.
External Temperature Sensor Cathode Connection.
External Temperature Sensor Anode Connection.
Rev. C | Page 9 of 36
ADM1062
Pin No.
LFCSP1 TQFP
Mnemonic
Description
39
46
VDDCAP
Device Supply Voltage. Linearly regulated from the highest of the VPx, VH pins to a typical of 4.75 V.
Note that the capacitor must be connected between this pin and GND. A 10 μF capacitor is
recommended for this purpose.
40
47
GND2
Supply Ground.
1 Note that the LFCSP has an exposed pad on the bottom. This pad is a no connect (NC). If possible, this pad should be soldered to the board for improved mechanical stability.
2 In a typical application, all ground pins are connected together.
Rev. C | Page 10 of 36
ADM1062
TYPICAL PERFORMANCE CHARACTERISTICS
180
160
140
120
100
80
6
5
4
3
2
1
0
60
40
20
0
0
1
2
3
4
5
6
0
1
2
3
4
5
6
V
(V)
V
(V)
VP1
VP1
Figure 5. VVDDCAP vs. VVP1
Figure 8. IVP1 vs. VVP1 (VP1 Not as Supply)
6
5
4
3
2
1
0
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
0
2
4
6
8
10
12
14
16
0
2
4
6
8
10
12
14
16
V
(V)
V
(V)
VH
VH
Figure 9. IVH vs. VVH (VH as Supply)
Figure 6. VVDDCAP vs. VVH
350
300
250
200
150
100
50
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
0
0
1
2
3
4
5
6
0
1
2
3
4
5
6
V
(V)
V
(V)
VP1
VH
Figure 7. IVP1 vs. VVP1 (VP1 as Supply)
Figure 10. IVH vs. VVH (VH Not as Supply)
Rev. C | Page 11 of 36
ADM1062
14
12
10
8
1.0
0.8
0.6
0.4
0.2
0
6
–0.2
–0.4
–0.6
–0.8
–1.0
4
2
0
0
2.5
5.0
7.5
(µA)
10.0
12.5
15.0
0
1000
2000
3000
4000
CODE
I
LOAD
Figure 11. Charge-Pumped VPDO1 (FET Drive Mode) vs. ILOAD
Figure 14. DNL for ADC
5.0
4.5
4.0
3.5
1.0
0.8
0.6
0.4
3.0
0.2
VP1 = 5V
2.5
2.0
0
VP1 = 3V
–0.2
–0.4
–0.6
–0.8
–1.0
1.5
1.0
0.5
0
0
1
2
3
4
5
6
0
1000
2000
3000
4000
I
(mA)
CODE
LOAD
Figure 12. VPDO1 (Strong Pull-Up to VPx) vs. ILOAD
Figure 15. INL for ADC
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
12000
10000
8000
6000
4000
2000
0
9894
VP1 = 5V
VP1 = 3V
25
81
0
10
20
30
(µA)
40
50
60
2047
2048
2049
CODE
I
LOAD
Figure 13. VPDO1 (Weak Pull-Up to VPx) vs. ILOAD
Figure 16. ADC Noise, Midcode Input, 10,000 Reads
Rev. C | Page 12 of 36
ADM1062
1.005
1.004
1.003
1.002
1.001
1.000
0.999
0.998
0.997
0.996
0.995
VP1 = 3.0V
VP1 = 4.75V
DAC
BUFFER
OUTPUT
20kΩ
47pF
PROBE
POINT
1
–40
–20
0
20
40
60
80
100
TEMPERATURE (°C)
CH1 200mV
M1.00µs
CH1
756mV
Figure 19. DAC Output vs. Temperature
Figure 17. Transient Response of DAC Code Change into Typical Load
2.058
2.053
2.048
2.043
2.038
VP1 = 3.0V
DAC
BUFFER
OUTPUT
100kΩ
VP1 = 4.75V
1V
PROBE
POINT
1
–40
–20
0
20
40
60
80
100
TEMPERATURE (°C)
CH1 200mV
M1.00µs
CH1
944mV
Figure 20. REFOUT vs. Temperature
Figure 18. Transient Response of DAC to Turn-On from High-Z State
Rev. C | Page 13 of 36
ADM1062
POWERING THE ADM1062
The ADM1062 is powered from the highest voltage input on either
the positive-only supply inputs (VPx) or the high voltage supply
input (VH). This technique offers improved redundancy because
the device is not dependent on any particular voltage rail to keep
it operational. The same pins are used for supply fault detection
(see the Supply Supervision section). A VDD arbitrator on the
device chooses which supply to use. The arbitrator can be
considered an OR’ing of five low dropout regulators (LDOs)
together. A supply comparator chooses the highest input to
provide the on-chip supply. There is minimal switching loss with
this architecture
When two or more supplies are within 100 mV of each other,
the supply that first takes control of VDD keeps control. For example,
if VP1 is connected to a 3.3 V supply, VDD powers up to approxi-
mately 3.1 V through VP1. If VP2 is then connected to another
3.3 V supply, VP1 still powers the device, unless VP2 goes 100 mV
higher than VP1.
VDDCAP
VP1
VP2
VP3
VP4
VH
IN
OUT
4.75V
LDO
EN
IN
OUT
4.75V
LDO
(~0.2 V), resulting in the ability to power the ADM1062 from
a supply as low as 3.0 V. Note that the supply on the VXx pins
cannot be used to power the device.
EN
IN
OUT
4.75V
LDO
EN
IN
An external capacitor to GND is required to decouple the on-chip
supply from noise. This capacitor should be connected to the
VDDCAP pin, as shown in Figure 21. The capacitor has another
use during brownouts (momentary loss of power). Under these
conditions, when the input supply (VPx or VH) dips transiently
below VDD, the synchronous rectifier switch immediately turns
off so that it does not pull VDD down. The VDD capacitor can
then act as a reservoir to keep the device active until the next
highest supply takes over the powering of the device. A 10 μF
capacitor is recommended for this reservoir/decoupling function.
OUT
4.75V
LDO
EN
IN
INTERNAL
DEVICE
SUPPLY
OUT
4.75V
LDO
EN
SUPPLY
COMPARATOR
The VH input pin can accommodate supplies up to 14.4 V, which
allows the ADM1062 to be powered using a 12 V backplane supply.
In cases where this 12 V supply is hot swapped, it is recommended
that the ADM1062 not be connected directly to the supply. Suitable
precautions, such as the use of a hot swap controller, should be
taken to protect the device from transients that could cause
damage during hot swap events.
Figure 21. VDD Arbitrator Operation
Rev. C | Page 14 of 36
ADM1062
INPUTS
SUPPLY SUPERVISION
The threshold value required is given by
VT = (VR × N)/255 + VB
where:
VT is the desired threshold voltage (undervoltage or overvoltage).
VR is the voltage range.
The ADM1062 has 10 programmable inputs. Five of these are
dedicated supply fault detectors (SFDs). These dedicated inputs
are called VH and VPx (VP1 to VP4) by default. The other five
inputs are labeled VXx (VX1 to VX5) and have dual functionality.
They can be used either as SFDs, with functionality similar to VH
and VPx, or as CMOS-/TTL-compatible logic inputs to the device.
Therefore, the ADM1062 can have up to 10 analog inputs,
a minimum of five analog inputs and five digital inputs, or
a combination thereof. If an input is used as an analog input,
it cannot be used as a digital input. Therefore, a configuration
requiring 10 analog inputs has no available digital inputs. Table 6
shows the details of each input.
N is the decimal value of the 8-bit code.
VB is the bottom of the range.
Reversing the equation, the code for a desired threshold is given by
N = 255 × (VT − VB)/VR
For example, if the user wants to set a 5 V overvoltage threshold
on VP1, the code to be programmed in the PS1OVTH register
(as discussed in the AN-698 Application Note at www.analog.com)
is given by
PROGRAMMING THE SUPPLY FAULT DETECTORS
The ADM1062 can have up to 10 SFDs on its 10 input channels.
These highly programmable reset generators enable the supervision
of up to 10 supply voltages. The supplies can be as low as 0.573 V
and as high as 14.4 V. The inputs can be configured to detect
an undervoltage fault (the input voltage drops below a prepro-
grammed value), an overvoltage fault (the input voltage rises
above a preprogrammed value), or an out-of-window fault (the
input voltage is outside a preprogrammed range). The thresholds
can be programmed to an 8-bit resolution in registers provided in
the ADM1062. This translates to a voltage resolution that is
dependent on the range selected.
N = 255 × (5 − 2.5)/3.5
Therefore, N = 182 (1011 0110 or 0xB6).
INPUT COMPARATOR HYSTERESIS
The UV and OV comparators shown in Figure 22 are always
monitoring VPx. To avoid chatter (multiple transitions when the
input is very close to the set threshold level), these comparators
have digitally programmable hysteresis. The hysteresis can be
programmed up to the values shown in Table 6.
RANGE
SELECT
ULTRA
OV
LOW
The resolution is given by
COMPARATOR
+
–
VPx
Step Size = Threshold Range/255
GLITCH
FILTER
FAULT
OUTPUT
VREF
Therefore, if the high range is selected on VH, the step size can
be calculated as follows:
+
–
LOW
MID
UV
FAULT TYPE
SELECT
COMPARATOR
(14.4 V − 6.0 V)/255 = 32.9 mV
Table 5 lists the upper and lower limits of each available range,
the bottom of each range (VB), and the range itself (VR).
Figure 22. Supply Fault Detector Block
The hysteresis is added after a supply voltage goes out of
Table 5. Voltage Range Limits
tolerance. Therefore, the user can program the amount above
the undervoltage threshold to which the input must rise before
an undervoltage fault is deasserted. Similarly, the user can program
the amount below the overvoltage threshold to which an input
must fall before an overvoltage fault is deasserted.
Voltage Range (V)
0.573 to 1.375
1.25 to 3.00
2.5 to 6.0
6.0 to 14.4
VB (V)
0.573
1.25
2.5
VR (V)
0.802
1.75
3.5
6.0
8.4
Table 6. Input Functions, Thresholds, and Ranges
Input Function Voltage Range (V)
Maximum Hysteresis
425 mV
1.02 V
97.5 mV
212 mV
425 mV
Voltage Resolution (mV)
Glitch Filter (μs)
0 to 100
0 to 100
0 to 100
0 to 100
0 to 100
0 to 100
0 to 100
VH
High Voltage Analog Input
2.5 to 6.0
13.7
32.9
3.14
6.8
13.7
3.14
N/A
6.0 to 14.4
0.573 to 1.375
1.25 to 3.00
2.5 to 6.0
VPx
Positive Analog Input
VXx
High-Z Analog Input
Digital Input
0.573 to 1.375
0 to 5.0
97.5 mV
N/A
Rev. C | Page 15 of 36
ADM1062
The hysteresis value is given by
An additional supply supervision function is available when the
VXx pins are selected as digital inputs. In this case, the analog
function is available as a second detector on each of the dedi-
cated analog inputs, VPx and VH. The analog function of VX1
is mapped to VP1, VX2 is mapped to VP2, and so on; VX5 is
mapped to VH. In this case, these SFDs can be viewed as secondary
or warning SFDs.
V
HYST = VR × NTHRESH/255
where:
V
HYST is the desired hysteresis voltage.
NTHRESH is the decimal value of the 5-bit hysteresis code.
Note that NTHRESH has a maximum value of 31. The maximum
hysteresis for the ranges is listed in Table 6.
The secondary SFDs are fixed to the same input range as the
primary SFDs. They are used to indicate warning levels rather
than failure levels. This allows faults and warnings to be gener-
ated on a single supply using only one pin. For example, if VP1
is set to output a fault when a 3.3 V supply drops to 3.0 V, VX1
can be set to output a warning at 3.1 V. Warning outputs are
available for readback from the status registers. They are also
OR’ed together and fed into the SE, allowing warnings to generate
interrupts on the PDOs. Therefore, in this example, if the
supply drops to 3.1 V, a warning is generated and remedial
action can be taken before the supply drops out of tolerance.
INPUT GLITCH FILTERING
The final stage of the SFDs is a glitch filter. This block provides
time-domain filtering on the output of the SFD comparators,
which allows the user to remove any spurious transitions, such
as supply bounce at turn-on. The glitch filter function is in addition
to the digitally programmable hysteresis of the SFD comparators.
The glitch filter timeout is programmable up to 100 μs.
For example, when the glitch filter timeout is 100 μs, any pulse
appearing on the input of the glitch filter block that is less than
100 μs in duration is prevented from appearing on the output of
the glitch filter block. Any input pulse that is longer than 100 μs
appears on the output of the glitch filter block. The output is
delayed with respect to the input by 100 μs. The filtering
process is shown in Figure 23.
VXx PINS AS DIGITAL INPUTS
As discussed in the Supply Supervision with VXX Inputs section,
the VXx input pins on the ADM1062 have dual functionality. The
second function is as a digital logic input to the device. Therefore,
the ADM1062 can be configured for up to five digital inputs. These
inputs are TTL-/CMOS-compatible. Standard logic signals can
be applied to the pins: RESET from reset generators, PWRGD
signals, fault flags, manual resets, and so on. These signals are
available as inputs to the SE and, therefore, can be used to control
the status of the PDOs. The inputs can be configured to detect
either a change in level or an edge.
INPUT PULSE SHORTER
THAN GLITCH FILTER TIMEOUT
INPUT PULSE LONGER
THAN GLITCH FILTER TIMEOUT
PROGRAMMED
TIMEOUT
PROGRAMMED
TIMEOUT
INPUT
INPUT
When configured for level detection, the output of the digital
block is a buffered version of the input. When configured for
edge detection, a pulse of programmable width is output from
the digital block once the logic transition is detected. The width
is programmable from 0 μs to 100 μs.
t0
tGF
t0
tGF
OUTPUT
OUTPUT
The digital blocks feature the same glitch filter function that is
available on the SFDs. This function enables the user to ignore
spurious transitions on the inputs. For example, the filter can be
used to debounce a manual reset switch.
t0
tGF
t0
tGF
Figure 23. Input Glitch Filter Function
When configured as digital inputs, each VXx pin has a weak
(10 μA) pull-down current source available for placing the input
into a known condition, even if left floating. The current source,
if selected, weakly pulls the input to GND.
SUPPLY SUPERVISION WITH VXx INPUTS
The VXx inputs have two functions. They can be used as either
supply fault detectors or digital logic inputs. When selected as
analog (SFD) inputs, the VXx pins have functionality that is
very similar to the VH and VPx pins. The primary difference is
that the VXx pins have only one input range: 0.573 V to 1.375 V.
Therefore, these inputs can directly supervise only the very low
supplies. However, the input impedance of the VXx pins is high,
allowing an external resistor divide network to be connected to the
pin. Thus, potentially any supply can be divided down into the
input range of the VXx pin and supervised, enabling the ADM1062
to monitor other supplies, such as +24 V, +48 V, and −5 V.
VXx
+
(DIGITAL INPUT)
TO
GLITCH
FILTER
SEQUENCING
ENGINE
DETECTOR
–
VREF = 1.4V
Figure 24. VXx Digital Input Function
Rev. C | Page 16 of 36
ADM1062
OUTPUTS
register (see the AN-698 Application Note at www.analog.com for
details).
SUPPLY SEQUENCING THROUGH
CONFIGURABLE OUTPUT DRIVERS
The data sources are as follows:
Supply sequencing is achieved with the ADM1062 using the
programmable driver outputs (PDOs) on the device as control
signals for supplies. The output drivers can be used as logic
enables or as FET drivers.
Output from the SE.
Directly from the SMBus. A PDO can be configured so that
the SMBus has direct control over it. This enables software
control of the PDOs. Therefore, a microcontroller can be used
to initiate a software power-up/power-down sequence.
On-chip clock. A 100 kHz clock is generated on the device.
This clock can be made available on any of the PDOs. It
can be used, for example, to clock an external device such
as an LED.
The sequence in which the PDOs are asserted (and, therefore,
the supplies are turned on) is controlled by the sequencing engine
(SE). The SE determines what action is taken with the PDOs,
based on the condition of the ADM1062 inputs. Therefore, the
PDOs can be set up to assert when the SFDs are in tolerance,
the correct input signals are received on the VXx digital pins,
no warnings are received from any of the inputs of the device,
and at other times. The PDOs can be used for a variety of func-
tions. The primary function is to provide enable signals for LDOs
or dc-to-dc converters that generate supplies locally on a board.
The PDOs can also be used to provide a PWRGD signal, when
all the SFDs are in tolerance, or a RESET output if one of the
SFDs goes out of specification (this can be used as a status signal
for a DSP, FPGA, or other microcontroller).
DEFAULT OUTPUT CONFIGURATION
All of the internal registers in an unprogrammed ADM1062
device from the factory are set to 0. Because of this, the PDOx pins
are pulled to GND by a weak (20 kΩ) on-chip pull-down resistor.
As the input supply to the ADM1062 ramps up on VPx or VH,
all the PDOx pins behave as follows:
Input supply = 0 V to 1.2 V. The PDOs are high impedance.
Input supply = 1.2 V to 2.7 V. The PDOs are pulled to GND
by a weak (20 kΩ) on-chip pull-down resistor.
The PDOs can be programmed to pull up to a number of differ-
ent options. The outputs can be programmed as follows:
Supply > 2.7 V. Factory-programmed devices continue to pull
all PDOs to GND by a weak (20 kΩ) on-chip pull-down
resistor. Programmed devices download current EEPROM
configuration data, and the programmed setup is latched. The
PDO then goes to the state demanded by the configuration.
This provides a known condition for the PDOs during
power-up.
Open-drain (allowing the user to connect an external
pull-up resistor).
Open-drain with weak pull-up to VDD.
Open-drain with strong pull-up to VDD.
Open-drain with weak pull-up to VPx.
Open-drain with strong pull-up to VPx.
Strong pull-down to GND.
The internal pull-down can be overdriven with an external pull-up
of suitable value tied from the PDOx pin to the required pull-up
voltage. The 20 kΩ resistor must be accounted for in calculating
a suitable value. For example, if PDOx must be pulled up to 3.3 V,
and 5 V is available as an external supply, the pull-up resistor value
is given by
Internally charge-pumped high drive (12 V, PDO1 to
PDO6 only).
The last option (available only on PDO1 to PDO6) allows the
user to directly drive a voltage high enough to fully enhance an
external N-FET, which is used to isolate, for example, a card-
side voltage from a backplane supply (a PDO can sustain greater
than 10.5 V into a 1 μA load). The pull-down switches can also
be used to drive status LEDs directly.
3.3 V = 5 V × 20 kΩ/(RUP + 20 kΩ)
Therefore,
The data driving each of the PDOs can come from one of three
sources. The source can be enabled in the PDOxCFG configuration
R
UP = (100 kΩ − 66 kΩ)/3.3 V = 10 kΩ
VFET (PDO1 TO PDO6 ONLY)
V
DD
VP4
VP1
SEL
CFG4 CFG5 CFG6
SE DATA
SMBus DATA
CLK DATA
PDO
Figure 25. Programmable Driver Output
Rev. C | Page 17 of 36
ADM1062
SEQUENCING ENGINE
OVERVIEW
MONITOR
FAULT
The ADM1062 sequencing engine (SE) provides the user with
powerful and flexible control of sequencing. The SE implements
a state machine control of the PDO outputs, with state changes
conditional on input events. SE programs can enable complex
control of boards, including power-up and power-down sequence
control, fault event handling, and interrupt generation on warnings.
A watchdog function that verifies the continued operation of a
processor clock can be integrated into the SE program. The SE
can also be controlled via the SMBus, giving software or firmware
control of the board sequencing.
STATE
TIMEOUT
SEQUENCE
Figure 26. State Cell
The ADM1062 offers up to 63 state definitions. The signals
monitored to indicate the status of the input pins are the
outputs of the SFDs.
The SE state machine comprises 63 state cells. Each state has the
following attributes:
WARNINGS
The SE also monitors warnings. These warnings can be generated
when the ADC readings violate their limit register value or when
the secondary voltage monitors on VPx and VH are triggered.
The warnings are OR’ed together and are available as a single
warning input to each of the three blocks that enable exiting
a state.
•
Monitors signals indicating the status of the 10 input pins,
VP1 to VP4, VH, and VX1 to VX5.
•
•
Can be entered from any other state.
Three exit routes move the state machine onto the next state:
sequence detection, fault monitoring, and timeout.
Delay timers for the sequence and timeout blocks can be
programmed independently and changed with each state
change. The range of timeouts is from 0 ms to 400 ms.
Output condition of the 10 PDO pins is defined and fixed
within a state.
Transition from one state to the next is made in less than
20 μs, which is the time needed to download a state
definition from EEPROM to the SE.
•
SMBus JUMP (UNCONDITIONAL JUMP)
The SE can be forced to advance to the next state uncondition-
ally. This enables the user to force the SE to advance. Examples
of the use of this feature include moving to a margining state or
debugging a sequence. The SMBus jump or go-to command can
be seen as another input to sequence and timeout blocks to
provide an exit from each state.
•
•
Table 7. Sample Sequence State Entries
State
IDLE1
IDLE2
EN3V3
Sequence
Timeout
Monitor
If VX1 is low, go to State IDLE2.
If VP1 is okay, go to State EN3V3.
If VP2 is okay, go to State EN2V5.
If VP2 is not okay after 10 ms,
go to State DIS3V3.
If VP1 is not okay, go to State IDLE1.
DIS3V3
EN2V5
If VX1 is high, go to State IDLE1.
If VP3 is okay, go to State PWRGD.
If VP3 is not okay after 20 ms,
go to State DIS2V5.
If VP1 or VP2 is not okay, go to State FSEL2.
DIS2V5
FSEL1
FSEL2
If VX1 is high, go to State IDLE1.
If VP3 is not okay, go to State DIS2V5.
If VP2 is not okay, go to State DIS3V3.
If VX1 is high, go to State DIS2V5.
If VP1 or VP2 is not okay, go to State FSEL2.
If VP1 is not okay, go to State IDLE1.
If VP1, VP2, or VP3 is not okay, go to State FSEL1.
PWRGD
Rev. C | Page 18 of 36
ADM1062
If a timer delay is specified, the input to the sequence detector
must remain in the defined state for the duration of the timer
delay. If the input changes state during the delay, the timer is reset.
SEQUENCING ENGINE APPLICATION EXAMPLE
The application in this section demonstrates operation of the
SE. Figure 28 shows how the simple building block of a single
SE state can be used to build a power-up sequence for a three-
supply system. Table 8 lists the PDO outputs for each state in the
same SE implementation. In this system, a good 5 V supply on the
VP1 pin and the VX1 pin held low are the triggers required to start
a power-up sequence. The sequence next turns on the 3.3 V supply,
then the 2.5 V supply (assuming successful turn-on of the 3.3 V
supply). When all three supplies are have turned on correctly, the
PWRGD state is entered, where the SE remains until a fault occurs
on one of the three supplies, or until it is instructed to go through
a power-down sequence by VX1 going high.
The sequence detector can also help to identify monitoring faults.
In the sample application shown in Figure 28, the FSEL1 and
FSEL2 states first identify which of the VP1, VP2, or VP3 pins
has faulted, and then they take appropriate action.
SEQUENCE
STATES
IDLE1
VX1 = 0
Faults are dealt with throughout the power-up sequence on
a case-by-case basis. The following three sections (the Sequence
Detector section, the Monitoring Fault Detector section, and
the Timeout Detector section) describe the individual blocks
and use the sample application shown in Figure 28 to demon-
strate the actions of the state machine.
IDLE2
VP1 = 1
MONITOR FAULT
STATES
TIMEOUT
STATES
Sequence Detector
EN3V3
10ms
VP1 = 0
The sequence detector block is used to detect when a step in a
sequence has been completed. It looks for one of the SE inputs
to change state and is most often used as the gate for successful
progress through a power-up or power-down sequence. A timer
block that is included in this detector can insert delays into a
power-up or power-down sequence, if required. Timer delays
can be set from 10 μs to 400 ms. Figure 27 is a block diagram of
the sequence detector.
VP2 = 1
EN2V5
DIS3V3
20ms
(VP1 + VP2) = 0
VX1 = 1
VP3 = 1
PWRGD
DIS2V5
VP2 = 0
(VP1 + VP2 + VP3) = 0
SUPPLY FAULT
DETECTION
VP1
VX1 = 1
SEQUENCE
DETECTOR
VX1 = 1
FSEL1
(VP1 +
VP2) = 0
LOGIC INPUT CHANGE
VX5
VP3 = 0
OR FAULT DETECTION
TIMER
FSEL2
VP1 = 0
WARNINGS
VP2 = 0
INVERT
FORCE FLOW
(UNCONDITIONAL JUMP)
SELECT
Figure 28. Sample Application Flow Diagram
Figure 27. Sequence Detector Block Diagram
Table 8. PDO Outputs for Each State
PDO Outputs
PDO1 = 3V3ON
PDO2 = 2V5ON
PDO3 = FAULT
IDLE1
IDLE2
EN3V3
EN2V5
DIS3V3
DIS2V5
PWRGD
FSEL1
FSEL2
0
0
0
0
0
0
1
0
0
1
1
0
0
1
1
1
0
1
1
1
0
1
1
1
1
1
1
Rev. C | Page 19 of 36
ADM1062
Monitoring Fault Detector
Timeout Detector
The monitoring fault detector block is used to detect a failure on an
input. The logical function implementing this is a wide OR gate
that can detect when an input deviates from its expected condition.
The clearest demonstration of the use of this block is in the
PWRGD state, where the monitor block indicates that a failure
on one or more of the VP1, VP2, or VP3 inputs has occurred.
The timeout detector allows the user to trap a failure to ensure
proper progress through a power-up or power-down sequence.
In the sample application shown in Figure 28, the timeout next-
state transition is from the EN3V3 and EN2V5 states. For the
EN3V3 state, the signal 3V3ON is asserted on the PDO1 output
pin upon entry to this state to turn on a 3.3 V supply. This supply
rail is connected to the VP2 pin, and the sequence detector looks
for the VP2 pin to go above its undervoltage threshold, which is
set in the supply fault detector (SFD) attached to that pin.
No programmable delay is available in this block because the
triggering of a fault condition is likely to be caused by a supply
falling out of tolerance. In this situation, the device needs to
react as quickly as possible.
The power-up sequence progresses when this change is detected.
If, however, the supply fails (perhaps due to a short circuit over-
loading this supply), the timeout block traps the problem. In this
example, if the 3.3 V supply fails within 10 ms, the SE moves to
the DIS3V3 state and turns off this supply by bringing PDO1
low. It also indicates that a fault has occurred by taking PDO3
high. Timeout delays of 100 μs to 400 ms can be programmed.
Some latency occurs when moving out of this state because it
takes a finite amount of time (~20 μs) for the state configuration
to download from the EEPROM into the SE. Figure 29 is a block
diagram of the monitoring fault detector.
MONITORING FAULT
DETECTOR
1-BIT FAULT
DETECTOR
FAULT AND STATUS REPORTING
FAULT
SUPPLY FAULT
DETECTION
VP1
The ADM1062 has a fault latch for recording faults. Two registers,
FSTAT1 and FSTAT2, are set aside for this purpose. A single bit
is assigned to each input of the device, and a fault on that input
sets the relevant bit. The contents of the fault register can be
read out over the SMBus to determine which input(s) faulted.
The fault register can be enabled or disabled in each state. To
latch data from one state, ensure that the fault latch is disabled
in the following state. This ensures that only real faults are
captured and not, for example, undervoltage conditions that
may be present during a power-up or power-down sequence.
MASK
SENSE
1-BIT FAULT
DETECTOR
FAULT
LOGIC INPUT CHANGE
OR FAULT DETECTION
VX5
MASK
SENSE
1-BIT FAULT
DETECTOR
The ADM1062 also has a number of status registers. These include
more detailed information, such as whether an undervoltage or
overvoltage fault is present on a particular input. The status regis-
ters also include information on ADC limit faults. Note that the
data in the status registers is not latched in any way and, therefore,
is subject to change at any time.
FAULT
WARNINGS
MASK
Figure 29. Monitoring Fault Detector Block Diagram
See the AN-698 Application Note at www.analog.com for full
details about the ADM1062 registers.
Rev. C | Page 20 of 36
ADM1062
VOLTAGE READBACK
The ADM1062 has an on-board, 12-bit, accurate ADC for
voltage readback over the SMBus. The ADC has a 12-channel
analog mux on the front end. The 12 channels consist of the
10 SFD inputs (VH, VPx, and VXx), plus two channels for
temperature readback (see the Temperature Measurement System
section). Any or all of these inputs can be selected to be read,
in turn, by the ADC. The circuit controlling this operation is
called the round-robin circuit. This circuit can be selected to
run through its loop of conversions once or continuously.
Averaging is also provided for each channel. In this case, the
round-robin circuit runs through its loop of conversions 16 times
before returning a result for each channel. At the end of this
cycle, the results are written to the output registers.
Table 9. ADC Input Voltage Ranges
SFD Input
ADC Input Voltage
Range (V)
Range (V)
0.573 to 1.375
1.25 to 3.00
2.5 to 6.0
Attenuation Factor
1
0 to 2.048
0 to 4.46
0 to 6.01
2.181
4.363
10.472
6.0 to 14.4
0 to 14.41
1 The upper limit is the absolute maximum allowed voltage on the VPx and
VH pins.
The typical way to supply the reference to the ADC on the
REFIN pin is to connect the REFOUT pin to the REFIN pin.
REFOUT provides a 2.048 V reference. As such, the supervising
range covers less than half the normal ADC range. It is possible,
however, to provide the ADC with a more accurate external
reference for improved readback accuracy.
The ADC samples single-sided inputs with respect to the AGND
pin. A 0 V input gives out Code 0, and an input equal to the
voltage on REFIN gives out full code (4095 decimal).
Supplies can also be connected to the input pins purely for ADC
readback, even though these pins may go above the expected
supervisory range limits (but not above the absolute maximum
ratings on these pins). For example, a 1.5 V supply connected to
the VX1 pin can be correctly read out as an ADC code of approxi-
mately 3/4 full scale, but it always sits above any supervisory limits
that can be set on that pin. The maximum setting for the REFIN
pin is 2.048 V.
The inputs to the ADC come directly from the VXx pins and
from the back of the input attenuators on the VPx and VH pins,
as shown in Figure 30 and Figure 31.
DIGITIZED
VOLTAGE
READING
NO ATTENUATION
12-BIT
ADC
VXx
2.048V VREF
SUPPLY SUPERVISION WITH THE ADC
Figure 30. ADC Reading on VXx Pins
In addition to the readback capability, another level of supervi-
sion is provided by the on-chip, 12-bit ADC. The ADM1062 has
limit registers with which the user can program a maximum or
minimum allowable threshold. Exceeding the threshold generates
a warning that can either be read back from the status registers
or input into the SE to determine what sequencing action the
ADM1062 should take. Only one register is provided for each
input channel. Therefore, either an undervoltage threshold or
overvoltage threshold (but not both) can be set for a given channel.
The round-robin circuit can be enabled via an SMBus write, or
it can be programmed to turn on in any state in the SE program.
For example, it can be set to start after a power-up sequence is
complete, and all supplies are known to be within expected
tolerance limits.
ATTENUATION NETWORK
(DEPENDS ON RANGE SELECTED)
VPx/VH
DIGITIZED
VOLTAGE
READING
12-BIT
ADC
2.048V VREF
Figure 31. ADC Reading on VPx/VH Pins
The voltage at the input pin can be derived from the following
equation:
ADCCode
V =
× Attenuation Factor × VREFIN
4095
Note that a latency is built into this supervision, dictated by the
conversion time of the ADC. With all 12 channels selected, the
total time for the round-robin operation (averaging off) is
approximately 6 ms (500 μs per channel selected). Supervision
using the ADC, therefore, does not provide the same real-time
response as the SFDs.
where VREFIN = 2.048 V when the internal reference is used (that is,
the REFIN pin is connected to the REFOUT pin).
The ADC input voltage ranges for the SFD input ranges are listed
in Table 9.
Rev. C | Page 21 of 36
ADM1062
SUPPLY MARGINING
OVERVIEW
CLOSED-LOOP SUPPLY MARGINING
A more accurate and comprehensive method of margining is to
implement a closed-loop system (see Figure 33). The voltage on
the rail to be margined can be read back to accurately margin the
rail to the target voltage. The ADM1062 incorporates all the circuits
required to do this, with the 12-bit successive approximation ADC
used to read back the level of the supervised voltages, and the six
voltage output DACs, implemented as described in the Open-Loop
Supply Margining section, used to adjust supply levels. These
circuits can be used along with other intelligence, such as a
microcontroller, to implement a closed-loop margining system
that allows any dc-to-dc converter or LDO supply to be set to
any voltage, accurate to within 0.5% of the target.
It is often necessary for the system designer to adjust supplies,
either to optimize their level or force them away from nominal
values to characterize the system performance under these condi-
tions. This is a function typically performed during an in-circuit
test (ICT), such as when a manufacturer wants to guarantee that
a product under test functions correctly at nominal supplies
minus 10%.
OPEN-LOOP SUPPLY MARGINING
The simplest method of margining a supply is to implement an
open-loop technique (see Figure 32). A popular way to do this is
to switch extra resistors into the feedback node of a power module,
such as a dc-to-dc converter or LDO. The extra resistor alters
the voltage at the feedback or trim node and forces the output
voltage to margin up or down by a certain amount.
To implement closed-loop margining
1. Disable the six DACx outputs.
2. Set the DAC output voltage equal to the voltage on the
feedback node.
The ADM1062 can perform open-loop margining for up to six
supplies. The six on-board voltage DACs (DAC1 to DAC6) can
drive into the feedback pins of the power modules to be margined.
The simplest circuit to implement this function is an attenuation
resistor that connects the DACx pin to the feedback node of a
dc-to-dc converter. When the DACx output voltage is set equal
to the feedback voltage, no current flows into the attenuation
resistor, and the dc-to-dc converter output voltage does not
change. Taking DACx above the feedback voltage forces current
into the feedback node, and the output of the dc-to-dc converter
is forced to fall to compensate for this. The dc-to-dc converter
output can be forced high by setting the DACx output voltage
lower than the feedback node voltage. The series resistor can
be split in two, and the node between them can be decoupled
with a capacitor to ground. This can help to decouple any noise
picked up from the board. Decoupling to a ground local to
the dc-to-dc converter is recommended.
3. Enable the DAC.
4. Read the voltage at the dc-to-dc converter output that is
connected to one of the VPx, VH, or VXx pins.
5. If necessary, modify the DACx output code up or down to
adjust the dc-to-dc converter output voltage. Otherwise,
stop because the target voltage has been reached.
6. Set the DAC output voltage to a value that alters the supply
output by the required amount (for example, 5%).
7. Repeat Step 4 through Step 6 until the measured supply
reaches the target voltage.
Step 1 to Step 3 ensure that when the DACx output buffer is
turned on, it has little effect on the dc-to-dc converter output.
The DAC output buffer is designed to power up without glitching
by first powering up the buffer to follow the pin voltage. It does
not drive out onto the pin at this time. Once the output buffer is
properly enabled, the buffer input is switched over to the DAC,
and the output stage of the buffer is turned on. Output glitching
is negligible.
The ADM1062 can be commanded to margin a supply up or
down over the SMBus by updating the values on the relevant
DAC output.
VIN
MICROCONTROLLER
V
OUT
ADM1062
DEVICE
CONTROLLER
(SMBus)
OUTPUT
DC-TO-DC
ATTENUATION
RESISTOR
CONVERTER
DACx
FEEDBACK
DAC
PCB
GND
TRACE NOISE
DECOUPLING
CAPACITOR
Figure 32. Open-Loop Margining System Using the ADM1062
Rev. C | Page 22 of 36
ADM1062
MICROCONTROLLER
VIN
ADM1062
MUX
VH/VPx/VXx
DACx
DC-TO-DC
CONVERTER
ADC
ATTENUATION
RESISTOR, R3
OUTPUT
FEEDBACK
GND
DEVICE
CONTROLLER
(SMBus)
R1
R2
DAC
PCB
TRACE NOISE
DECOUPLING
CAPACITOR
Figure 33. Closed-Loop Margining System Using the ADM1062
the current flowing through R3. Therefore, a direct relationship
exists between the extra voltage drop across R1 during margining
and the voltage drop across R3.
WRITING TO THE DACS
Four DAC ranges are offered. They can be placed with midcode
(Code 0x7F) at 0.6 V, 0.8 V, 1.0 V, and 1.25 V. These voltages are
placed to correspond to the most common feedback voltages.
Centering the DAC outputs in this way provides the best use of
the DAC resolution. For most supplies, it is possible to place the
DAC midcode at the point where the dc-to-dc converter output
is not modified, thereby giving half of the DAC range to margin
up and the other half to margin down.
This relationship is given by the following equation:
R1
R3
ΔVOUT
=
(VFB − VDACOUT)
where:
ΔVOUT is the change in VOUT
VFB is the voltage at the feedback node of the dc-to-dc converter.
DACOUT is the voltage output of the margining DAC.
.
The DAC output voltage is set by the code written to the DACx
register. The voltage is linear with the unsigned binary number
in this register. Code 0x7F is placed at the midcode voltage, as
described previously. The output voltage is given by the following
equation:
V
This equation demonstrates that if the user wants the output
voltage to change by 300 mV, then R1 = R3. If the user wants the
output voltage to change by 600 mV, then R1 = 2 × R3, and so on.
It is best to use the full DAC output range to margin a supply.
Choosing the attenuation resistor in this way provides the most
resolution from the DAC, meaning that with one DAC code
change, the smallest effect on the dc-to-dc converter output
voltage is induced. If the resistor is sized up to use a code such as
27 decimal to 227 decimal to move the dc-to-dc converter output
by 5%, it takes 100 codes to move 5% (each code moves the
output by 0.05%). This is beyond the readback accuracy of the
ADC, but it should not prevent the user from building a circuit to
use the most resolution.
DAC Output = (DACx − 0x7F)/255 × 0.6015 + VOFF
where VOFF is one of the four offset voltages.
There are 256 DAC settings available. The midcode value is
located at DAC Code 0x7F, as close as possible to the middle
of the 256 code range. The full output swing of the DACs is
+302 mV (+128 codes) and −300 mV (−127 codes) around the
selected midcode voltage. The voltage range for each midcode
voltage is shown in Table 10.
Table 10. Ranges for Midcode Voltages
DAC LIMITING AND OTHER SAFETY FEATURES
Midcode
Voltage (V)
Minimum Voltage
Output (V)
Maximum Voltage
Output (V)
Limit registers (called DPLIMx and DNLIMx) on the device
offer the user some protection from firmware bugs that can cause
catastrophic board problems by forcing supplies beyond their
allowable output ranges. Essentially, the DAC code written into
the DACx register is clipped such that the code used to set the
DAC voltage is given by
0.6
0.8
1.0
1.25
0.300
0.500
0.700
0.950
0.902
1.102
1.302
1.552
CHOOSING THE SIZE OF THE ATTENUATION
RESISTOR
DAC Code
= DACx, DACx ≥ DNLIMx and DACx ≤ DPLIMx
= DNLIMx, DACx < DNLIMx
= DPLIMx, DACx > DPLIMx
The size of the attenuation resistor, R3, determines how much
the DAC voltage swing affects the output voltage of the dc-to-dc
converter that is being margined (see Figure 33).
In addition, the DAC output buffer is three-stated if DNLIMx >
DPLIMx. By programming the limit registers this way, the user
can make it very difficult for the DAC output buffers to be turned
on during normal system operation. The limit registers are among
the registers downloaded from the EEPROM at startup.
Because the voltage at the feedback pin remains constant, the
current flowing from the feedback node to GND through R2 is a
constant. In addition, the feedback node itself is high impedance.
This means that the current flowing through R1 is the same as
Rev. C | Page 23 of 36
ADM1062
TEMPERATURE MEASUREMENT SYSTEM
The ADM1062 contains an on-chip, band gap temperature
sensor whose output is digitized by the on-chip, 12-bit ADC.
Theoretically, the temperature sensor and the ADC can measure
temperatures from −128°C to +128°C with a resolution of 0.125°C.
Because this exceeds the operating temperature range of the device,
local temperature measurements outside this range are not possible.
Temperature measurements from −128°C to +128°C are possible
using a remote sensor. The output code is in offset binary format,
with −128°C given by Code 0x400, 0°C given by Code 0x800,
and +128°C given by Code 0xC00.
Figure 36 shows the input signal conditioning used to measure the
output of a remote temperature sensor. This figure shows the
external sensor as a substrate transistor provided for temperature
monitoring on some microprocessors, but it could equally be
a discrete transistor such as a 2N3904 or 2N3906.
If a discrete transistor is used, the collector is not grounded and
should be linked to the base. If a PNP transistor is used, the base
is connected to the DN input, and the emitter is connected to
the DP input. If an NPN transistor is used, the emitter is connected
to the DN input, and the base is connected to the DP input.
Figure 34 and Figure 35 show how to connect the ADM1062 to
an NPN or PNP transistor for temperature measurement. To
prevent ground noise from interfering with the measurement,
the more negative terminal of the sensor is not referenced to
ground but is biased above ground by an internal diode at the
DN input.
As with the other analog inputs to the ADC, a limit register is
provided for each of the temperature input channels. Therefore,
a temperature limit can be set such that if it is exceeded, a warning
is generated and available as an input to the sequencing engine.
This enables users to control their sequence or monitor functions
based on an overtemperature or undertemperature event.
REMOTE TEMPERATURE MEASUREMENT
ADM1062
The ADM1062 can measure the temperature of a remote diode
sensor or diode-connected transistor connected to Pin DN and
Pin DP (Pin 37 and Pin 38 on the LFCSP package and Pin 44
and Pin 45 on the TQFP package).
2N3904
NPN
DP
DN
Figure 34. Measuring Temperature Using an NPN Transistor
The forward voltage of a diode or diode-connected transistor
operated at a constant current exhibits a negative temperature
coefficient of about −2 mV/°C. Unfortunately, the absolute value
of VBE varies from device to device, and individual calibration
is required to null it, making the technique unsuitable for mass
production. The technique used in the ADM1062 is to measure
the change in VBE when the device is operated at two different
currents.
ADM1062
DP
2N3906
DN
PNP
Figure 35. Measuring Temperature Using a PNP Transistor
The change in VBE is given by
ΔVBE = kT/q × ln(N)
where:
k is Boltzmann’s constant.
q is the charge on the carrier.
T is the absolute temperature in Kelvin.
N is the ratio of the two currents.
V
DD
CPU
I
BIAS
I
N × I
V
V
OUT+
OUT–
THERM DA DP
THERM DC DN
REMOTE
SENSING
TRANSISTOR
TO ADC
BIAS
DIODE
LOW-PASS FILTER
fC = 65kHz
Figure 36. Signal Conditioning for Remote Diode Temperature Sensors
Rev. C | Page 24 of 36
ADM1062
To measure ΔVBE, the sensor is switched between operating
currents of I and N × I. The resulting waveform is passed through
a 65 kHz low-pass filter to remove noise and through a chopper-
stabilized amplifier that amplifies and rectifies the waveform
to produce a dc voltage proportional to ΔVBE. This voltage is
measured by the ADC to produce a temperature output in 12-bit
offset binary. To further reduce the effects of noise, digital filtering
is performed by averaging the results of 16 measurement cycles.
A remote temperature measurement takes nominally 600 ms.
The results of remote temperature measurements are stored in
12-bit, offset binary format, as shown in Table 11. This format
provides temperature readings with a resolution of 0.125°C.
Table 11. Temperature Data Format
Temperature Digital Output (Hex) Digital Output (Binary)
−128°C
−125°C
−100°C
−75°C
0x400
0x418
0x4E0
0x5A8
0x670
0x738
0x7B0
0x800
0x852
0x8CC
0x996
0xA58
0XB20
0xBE8
0xC00
010000000000
010000011000
010011100000
010110101000
011001110000
011100111000
011110110000
100000000000
100001010010
100011001100
100110010110
101001011000
101100100000
101111101000
110000000000
−50°C
−25°C
−10°C
0°C
+10.25°C
+25.5°C
+50.75°C
+75°C
+100°C
+125°C
+128°C
Rev. C | Page 25 of 36
ADM1062
APPLICATIONS DIAGRAM
12V IN
5V IN
3V IN
12V OUT
5V OUT
3V OUT
IN
DC-TO-DC1
EN
OUT
3.3V OUT
2.5V OUT
1.8V OUT
VH
ADM1062
5V OUT
3V OUT
VP1
VP2
VP3
VP4
VX1
VX2
VX3
PDO1
PDO2
3.3V OUT
2.5V OUT
1.8V OUT
1.2V OUT
0.9V OUT
IN
DC-TO-DC2
EN OUT
PDO3
PDO4
PDO5
PWRGD
POWRON
PDO6
PDO7
VX4
VX5
SIGNAL VALID
SYSTEM RESET
RESET
IN
DC-TO-DC3
PDO8
PDO9
PDO10
DAC1*
DP
EN
OUT
3.3V OUT
REFOUT
IN
DN
LDO
REFIN VCCP VDDCAP GND
EN
OUT
0.9V OUT
1.2V OUT
3.3V OUT
10µF
10µF
10µF
IN
OUT
*ONLY ONE MARGINING CIRCUIT
SHOWN FOR CLARITY. DAC1 TO DAC6
ALLOW MARGINING FOR UP TO SIX
VOLTAGE RAILS.
EN
TRIM
DC-TO-DC4
TEMPERATURE
DIODE
3.3V OUT
MICRO-
PROCESSOR
2.5V OUT
Figure 37. Applications Diagram
Rev. C | Page 26 of 36
ADM1062
COMMUNICATING WITH THE ADM1062
The ADM1062 provides several options that allow the user to
update the configuration over the SMBus interface. The following
three options are controlled in the UPDCFG register:
CONFIGURATION DOWNLOAD AT POWER-UP
The configuration of the ADM1062 (undervoltage/overvoltage
thresholds, glitch filter timeouts, PDO configurations, and so on)
is dictated by the contents of the RAM. The RAM comprises
digital latches that are local to each of the functions on the device.
The latches are double-buffered and have two identical latches,
Latch A and Latch B. Therefore, when an update to a function
occurs, the contents of Latch A are updated first, and then the
contents of Latch B are updated with identical data. The advantages
of this architecture are explained in detail in the Updating the
Configuration section.
Option 1
Update the configuration in real time. The user writes to the RAM
across the SMBus, and the configuration is updated immediately.
Option 2
Update the Latch As without updating the Latch Bs. With this
method, the configuration of the ADM1062 remains unchanged
and continues to operate in the original setup until the instruction
is given to update the Latch Bs.
The two latches are volatile memory and lose their contents at
power-down. Therefore, the configuration in the RAM must be
restored at power-up by downloading the contents of the EEPROM
(nonvolatile memory) to the local latches. This download occurs
in six steps, as follows:
Option 3
Change the EEPROM register contents without changing the
RAM contents, and then download the revised EEPROM contents
to the RAM registers. With this method, the configuration of
the ADM1062 remains unchanged and continues to operate in
the original setup until the instruction is given to update the RAM.
With no power applied to the device, the PDOs are all
high impedance.
When 1.2 V appears on any of the inputs connected to the VDD
arbitrator (VH or VPx), the PDOs are all weakly pulled to
GND with a 20 kΩ resistor.
When the supply rises above the undervoltage lockout of the
device (UVLO is 2.5 V), the EEPROM starts to download
to the RAM.
The EEPROM downloads its contents to all Latch As.
When the contents of the EEPROM are completely downloaded
to the Latch As, the device controller signals all Latch As to
download to all Latch Bs simultaneously, completing the
configuration download.
The instruction to download from the EEPROM in Option 3 is
also a useful way to restore the original EEPROM contents if
revisions to the configuration are unsatisfactory. For example,
if the user needs to alter an overvoltage threshold, the RAM
register can be updated, as described in Option 1. However,
if the user is not satisfied with the change and wants to revert to
the original programmed value, the device controller can issue
a command to download the EEPROM contents to the RAM
again, as described in Option 3, restoring the ADM1062 to its
original configuration.
The topology of the ADM1062 makes this type of operation
possible. The local, volatile registers (RAM) are all double-
buffered latches. Setting Bit 0 of the UPDCFG register to 1 leaves
the double-buffered latches open at all times. If Bit 0 is set to 0
when a RAM write occurs across the SMBus, only the first side
of the double-buffered latch is written to. The user must then write
a 1 to Bit 1 of the UPDCFG register. This generates a pulse to
update all the second latches at once. EEPROM writes occur in
a similar way.
At 0.5 ms after the configuration download completes, the first
state definition is downloaded from the EEPROM into the SE.
Note that any attempt to communicate with the device prior to
the completion of the download causes the ADM1062 to issue
a no acknowledge (NACK).
UPDATING THE CONFIGURATION
After power-up, with all the configuration settings loaded from
the EEPROM into the RAM registers, the user may need to alter
the configuration of functions on the ADM1062, such as changing
the undervoltage or overvoltage limit of an SFD, changing the
fault output of an SFD, or adjusting the rise time delay of one of
the PDOs.
The final bit in this register can enable or disable EEPROM
page erasure. If this bit is set high, the contents of an EEPROM
page can all be set to 1. If this bit is set low, the contents of a
page cannot be erased, even if the command code for page
erasure is programmed across the SMBus. The bit map for the
UPDCFG register is shown in the AN-698 Application Note at
www.analog.com. A flow diagram for download at power-up
and subsequent configuration updates is shown in Figure 38.
Rev. C | Page 27 of 36
ADM1062
SMBus
POWER-UP
CC
DEVICE
(V > 2.5V)
CONTROLLER
E
E
P
R
O
M
L
R
A
M
L
U
P
D
D
A
T
D
A
LATCH A
LATCH B
FUNCTION
(OV THRESHOLD
ON VP1)
D
EEPROM
Figure 38. Configuration Update Flow Diagram
The major differences between the EEPROM and other
registers are as follows:
UPDATING THE SEQUENCING ENGINE
Sequencing engine (SE) functions are not updated in the same way
as regular configuration latches. The SE has its own dedicated
512-byte nonvolatile, electrically erasable, programmable, read-
only memory (EEPROM) for storing state definitions. The
EEPROM provides 63 individual states, each with a 64-bit word
(one state is reserved). At power-up, the first state is loaded from
the SE EEPROM into the engine itself. When the conditions of this
state are met, the next state is loaded from the EEPROM into the
engine, and so on. The loading of each new state takes approxi-
mately 10 μs.
•
An EEPROM location must be blank before it can be
written to. If it contains data, the data must first be erased.
Writing to the EEPROM is slower than writing to the RAM.
Writing to the EEPROM should be restricted because it has
a limited write/cycle life of typically 10,000 write operations
due to the usual EEPROM wear-out mechanisms.
•
•
The first EEPROM is split into 16 (0 to 15) pages of 32 bytes
each. Page 0 to Page 6, starting at Address 0xF800, hold the
configuration data for the applications on the ADM1062 (such
as the SFDs and PDOs). These EEPROM addresses are the same
as the RAM register addresses, prefixed by F8. Page 7 is reserved.
Page 8 to Page 15 are for customer use.
To alter a state, the required changes must be made directly to
the EEPROM. RAM for each state does not exist. The relevant
alterations must be made to the 64-bit word, which is then
uploaded directly to the EEPROM.
Data can be downloaded from the EEPROM to the RAM in one
of the following ways:
INTERNAL REGISTERS
The ADM1062 contains a large number of data registers. The
principal registers are the address pointer register and the
configuration registers.
•
•
At power-up, when Page 0 to Page 6 are downloaded
By setting Bit 0 of the UDOWNLD register (0xD8), which
performs a user download of Page 0 to Page 6
Address Pointer Register
SERIAL BUS INTERFACE
The address pointer register contains the address that selects
one of the other internal registers. When writing to the ADM1062,
the first byte of data is always a register address that is written to
the address pointer register.
The ADM1062 is controlled via the serial system management
bus (SMBus) and is connected to this bus as a slave device under
the control of a master device. It takes approximately 1 ms after
power-up for the ADM1062 to download from its EEPROM.
Therefore, access to the ADM1062 is restricted until the download
is complete.
Configuration Registers
The configuration registers provide control and configuration
for various operating parameters of the ADM1062.
Identifying the ADM1062 on the SMBus
EEPROM
The ADM1062 has a 7-bit serial bus slave address (see Table 12).
The device is powered up with a default serial bus address. The
five MSBs of the address are set to 00101; the two LSBs are
determined by the logical states of Pin A1 and Pin A0. This
allows the connection of four ADM1062s to one SMBus.
The ADM1062 has two 512-byte cells of nonvolatile EEPROM
from Register Address 0xF800 to Register Address 0xFBFF. The
EEPROM is used for permanent storage of data that is not lost
when the ADM1062 is powered down. One EEPROM cell contains
the configuration data of the device; the other contains the state
definitions for the SE. Although referred to as read-only memory,
the EEPROM can be written to, as well as read from, using the
serial bus in exactly the same way as the other registers.
Table 12. Serial Bus Slave Address
A1 Pin
A0 Pin
Hex Address
7-Bit Address
0010100x1
0010101x1
0010110x1
0010111x1
Low
Low
High
High
Low
High
Low
0x28
0x2A
0x2C
0x2E
High
1 x = Read/Write bit. The address is shown only as the first 7 MSBs.
Rev. C | Page 28 of 36
ADM1062
The device also has several identification registers (read-only)
that can be read across the SMBus. Table 13 lists these registers
with their values and functions.
All other devices on the bus remain idle while the selected device
W
waits for data to be read from or written to it. If the R/ bit is
W
a 0, the master writes to the slave device. If the R/ bit is a 1,
the master reads from the slave device.
Table 13. Identification Register Values and Functions
Step 2
Name
MANID 0xF4
REVID 0xF5
MARK1 0xF6
MARK2 0xF7
Address Value Function
0x41
0x02
0x00
0x00
Manufacturer ID for Analog Devices
Silicon revision
Software brand
Data is sent over the serial bus in sequences of nine clock pulses:
eight bits of data followed by an acknowledge bit from the slave
device. Data transitions on the data line must occur during the
low period of the clock signal and remain stable during the high
period because a low-to-high transition when the clock is high
could be interpreted as a stop signal. If the operation is a write
operation, the first data byte after the slave address is a command
byte. This command byte tells the slave device what to expect next.
It may be an instruction telling the slave device to expect a block
write, or it may be a register address that tells the slave where subse-
quent data is to be written. Because data can flow in only one
Software brand
General SMBus Timing
Figure 39, Figure 40, and Figure 41 are timing diagrams for
general read and write operations using the SMBus. The SMBus
specification defines specific conditions for different types of
read and write operations, which are discussed in the Write
Operations and Read Operations sections.
W
direction, as defined by the R/ bit, sending a command to a
The general SMBus protocol operates as follows:
slave device during a read operation is not possible. Before a read
operation, it may be necessary to perform a write operation to
tell the slave what sort of read operation to expect and/or the
address from which data is to be read.
Step 1
The master initiates data transfer by establishing a start condition,
defined as a high-to-low transition on the serial data-line SDA,
while the serial clock-line SCL remains high. This indicates that
a data stream follows. All slave peripherals connected to the
serial bus respond to the start condition and shift in the next eight
Step 3
When all data bytes have been read or written, stop conditions
are established. In write mode, the master pulls the data line
high during the 10th clock pulse to assert a stop condition. In
read mode, the master device releases the SDA line during the
low period before the ninth clock pulse, but the slave device
does not pull it low. This is known as a no acknowledge. The
master then takes the data line low during the low period before
the 10th clock pulse and then high during the 10th clock pulse
to assert a stop condition.
W
bits, consisting of a 7-bit slave address (MSB first) plus an R/
bit. This bit determines the direction of the data transfer, that is,
whether data is written to or read from the slave device (0 =
write, 1 = read).
The peripheral whose address corresponds to the transmitted
address responds by pulling the data line low during the low
period before the ninth clock pulse, known as the acknowledge
bit, and by holding it low during the high period of this clock pulse.
1
9
1
9
SCL
SDA
0
0
1
0
1
A1
A0 R/W
D7
D6 D5 D4
D3 D2
D1
D0
ACK. BY
SLAVE
ACK. BY
SLAVE
START BY
MASTER
FRAME 1
SLAVE ADDRESS
FRAME 2
COMMAND CODE
1
9
1
9
SCL
(CONTINUED)
SDA
(CONTINUED)
D7 D6
D5 D4
D3 D2
D1
D7
D6 D5 D4
D3 D2
D1
D0
D0
STOP
BY
MASTER
ACK. BY
SLAVE
ACK. BY
SLAVE
FRAME 3
FRAME N
DATA BYTE
DATA BYTE
Figure 39. General SMBus Write Timing Diagram
Rev. C | Page 29 of 36
ADM1062
1
9
1
9
SCL
SDA
0
0
1
0
1
A1
A0 R/W
D7
D6 D5 D4
D3 D2
D1
D0
ACK. BY
SLAVE
ACK. BY
MASTER
START BY
MASTER
FRAME 1
SLAVE ADDRESS
FRAME 2
DATA BYTE
1
9
1
9
SCL
(CONTINUED)
SDA
(CONTINUED)
D7 D6
D5 D4
D3 D2
D1
D7
D6 D5 D4
D3 D2
D1
D0
NO ACK.
D0
STOP
BY
MASTER
ACK. BY
MASTER
FRAME 3
FRAME N
DATA BYTE
DATA BYTE
Figure 40. General SMBus Read Timing Diagram
tR
tF
tHD;STA
tLOW
tHD;STA
tHD;DAT
SCL
SDA
tHIGH
tSU;STA
tSU;STO
tSU;DAT
tBUF
P
S
S
P
Figure 41. Serial Bus Timing Diagram
Rev. C | Page 30 of 36
ADM1062
To erase a page of EEPROM memory. EEPROM memory
can be written to only if it is unprogrammed. Before writing
to one or more EEPROM memory locations that are already
programmed, the page(s) containing those locations must
first be erased. EEPROM memory is erased by writing a
command byte.
SMBus PROTOCOLS FOR RAM AND EEPROM
The ADM1062 contains volatile registers (RAM) and non-
volatile registers (EEPROM). User RAM occupies Address 0x00
to Address 0xDF; the EEPROM occupies Address 0xF800 to
Address 0xFBFF.
Data can be written to and read from both the RAM and the
EEPROM as single data bytes. Data can be written only to unpro-
grammed EEPROM locations. To write new data to a programmed
location, the location contents must first be erased. EEPROM
erasure cannot be done at the byte level. The EEPROM is arranged
as 32 pages of 32 bytes each, and an entire page must be erased.
The master sends a command code telling the slave device
to erase the page. The ADM1062 command code for a page
erasure is 0xFE (1111 1110). Note that for a page erasure to
take place, the page address must be given in the previous
write word transaction (see the Write Byte/Word section).
In addition, Bit 2 in the UPDCFG register (Address 0x90)
must be set to 1.
Page erasure is enabled by setting Bit 2 in the UPDCFG register
(Address 0x90) to 1. If this bit is not set, page erasure cannot
occur, even if the command byte (0xFE) is programmed across
the SMBus.
1
2
3
4
5
6
COMMAND
BYTE
(0xFE)
SLAVE
ADDRESS
S
W
A
A
P
WRITE OPERATIONS
Figure 43. EEPROM Page Erasure
The SMBus specification defines several protocols for different
types of read and write operations. The following abbreviations
are used in Figure 42 to Figure 50:
As soon as the ADM1062 receives the command byte,
page erasure begins. The master device can send a stop
command as soon as it sends the command byte. Page
erasure takes approximately 20 ms. If the ADM1062 is
accessed before erasure is complete, it responds with a no
acknowledge (NACK).
S = Start
P = Stop
R = Read
W = Write
A = Acknowledge
Write Byte/Word
In a write byte/word operation, the master device sends a
command byte and one or two data bytes to the slave device,
as follows:
A
= No acknowledge
The ADM1062 uses the following SMBus write protocols.
1. The master device asserts a start condition on SDA.
2. The master sends the 7-bit slave address followed by the
write bit (low).
3. The addressed slave device asserts an ACK on SDA.
4. The master sends a command code.
5. The slave asserts an ACK on SDA.
6. The master sends a data byte.
7. The slave asserts an ACK on SDA.
8. The master sends a data byte or asserts a stop condition.
9. The slave asserts an ACK on SDA.
10. The master asserts a stop condition on SDA to end
the transaction.
Send Byte
In a send byte operation, the master device sends a single
command byte to a slave device, as follows:
1. The master device asserts a start condition on SDA.
2. The master sends the 7-bit slave address followed by the
write bit (low).
3. The addressed slave device asserts an acknowledge (ACK)
on SDA.
4. The master sends a command code.
5. The slave asserts an ACK on SDA.
6. The master asserts a stop condition on SDA, and the
transaction ends.
In the ADM1062, the write byte/word protocol is used for three
purposes:
In the ADM1062, the send byte protocol is used for two purposes:
To write a register address to the RAM for a subsequent single
byte read from the same address, or for a block read or a
block write starting at that address, as shown in Figure 42.
To write a single byte of data to the RAM. In this case, the
command byte is RAM Address 0x00 to RAM Address 0xDF,
and the only data byte is the actual data, as shown in Figure 44.
1
2
3
4
5
6
1
2
3
4
5
6
7
8
RAM
SLAVE
ADDRESS
RAM
S
W
A
ADDRESS
A
P
SLAVE
ADDRESS
S
W
A
ADDRESS
A
DATA
A
P
(0x00 TO 0xDF)
(0x00 TO 0xDF)
Figure 42. Setting a RAM Address for Subsequent Read
Figure 44. Single Byte Write to the RAM
Rev. C | Page 31 of 36
ADM1062
7. The slave asserts an ACK on SDA.
8. The master sends N data bytes.
9. The slave asserts an ACK on SDA after each data byte.
10. The master asserts a stop condition on SDA to end the
transaction.
•
To set up a 2-byte EEPROM address for a subsequent read,
write, block read, block write, or page erase. In this case, the
command byte is the high byte of EEPROM Address 0xF8
to EEPROM Address 0xFB. The only data byte is the low
byte of the EEPROM address, as shown in Figure 45.
1
2
3
4
5
6
7
8
9
10
P
1
2
3
4
5
6
7
8
EEPROM
ADDRESS
HIGH BYTE
(0xF8 TO 0xFB)
EEPROM
ADDRESS
LOW BYTE
(0x00 TO 0xFF)
SLAVE
ADDRESS
COMMAND 0xFC
(BLOCK WRITE)
BYTE
COUNT
DATA
1
DATA
2
DATA
A
N
SLAVE
ADDRESS
S
W
A
A
A
A
A
S
W
A
A
A
P
Figure 45. Setting an EEPROM Address
Figure 47. Block Write to the EEPROM or RAM
Because a page consists of 32 bytes, only the three MSBs
of the address low byte are important for page erasure. The
lower five bits of the EEPROM address low byte specify the
addresses within a page and are ignored during an erase
operation.
To write a single byte of data to the EEPROM. In this case,
the command byte is the high byte of EEPROM Address 0xF8
to EEPROM Address 0xFB. The first data byte is the low
byte of the EEPROM address, and the second data byte is
the actual data, as shown in Figure 46.
Unlike some EEPROM devices that limit block writes to within
a page boundary, there is no limitation on the start address
when performing a block write to EEPROM, except when
•
There must be at least N locations from the start address to
the highest EEPROM address (0xFBFF) to avoid writing to
invalid addresses.
•
•
An address crosses a page boundary. In this case, both
pages must be erased before programming.
Note that the ADM1062 features a clock extend function for
writes to EEPROM. Programming an EEPROM byte takes
approximately 250 μs, which limits the SMBus clock for repeated
or block write operations. The ADM1062 pulls SCL low and
extends the clock pulse when it cannot accept any more data.
1
2
3
4
5
6
7
8
9
10
EEPROM
ADDRESS
HIGH BYTE
(0xF8 TO 0xFB)
EEPROM
ADDRESS
LOW BYTE
(0x00 TO 0xFF)
SLAVE
ADDRESS
S
W
A
A
A
DATA
A
P
Figure 46. Single Byte Write to the EEPROM
READ OPERATIONS
Block Write
The ADM1062 uses the following SMBus read protocols.
Receive Byte
In a block write operation, the master device writes a block of
data to a slave device. The start address for a block write must
have been set previously. In the ADM1062, a send byte opera-
tion sets a RAM address, and a write byte/word operation sets
an EEPROM address, as follows:
In a receive byte operation, the master device receives a single
byte from a slave device, as follows:
1. The master device asserts a start condition on SDA.
2. The master sends the 7-bit slave address followed by the
read bit (high).
3. The addressed slave device asserts an ACK on SDA.
4. The master receives a data byte.
5. The master asserts a NACK on SDA.
6. The master asserts a stop condition on SDA, and the
transaction ends.
1. The master device asserts a start condition on SDA.
2. The master sends the 7-bit slave address followed by
the write bit (low).
3. The addressed slave device asserts an ACK on SDA.
4. The master sends a command code that tells the slave
device to expect a block write. The ADM1062 command
code for a block write is 0xFC (1111 1100).
5. The slave asserts an ACK on SDA.
In the ADM1062, the receive byte protocol is used to read a
single byte of data from a RAM or EEPROM location whose
address has previously been set by a send byte or write
byte/word operation, as shown in Figure 48.
6. The master sends a data byte that tells the slave device how
many data bytes are being sent. The SMBus specification
allows a maximum of 32 data bytes in a block write.
1
2
3
4
5
6
SLAVE
ADDRESS
S
R
A
DATA
A
P
Figure 48. Single Byte Read from the EEPROM or RAM
Rev. C | Page 32 of 36
ADM1062
Block Read
Error Correction
In a block read operation, the master device reads a block of
data from a slave device. The start address for a block read must
have been set previously. In the ADM1062, this is done by a
send byte operation to set a RAM address, or a write byte/word
operation to set an EEPROM address. The block read operation
itself consists of a send byte operation that sends a block read
command to the slave, immediately followed by a repeated start
and a read operation that reads out multiple data bytes, as follows:
The ADM1062 provides the option of issuing a packet error
correction (PEC) byte after a write to the RAM, a write to the
EEPROM, a block write to the RAM/EEPROM, or a block read
from the RAM/ EEPROM. This option enables the user to verify
that the data received by or sent from the ADM1062 is correct.
The PEC byte is an optional byte sent after the last data byte has
been written to or read from the ADM1062. The protocol is the
same as a block read for Step 1 to Step 12 and then proceeds as
follows:
1. The master device asserts a start condition on SDA.
2. The master sends the 7-bit slave address followed by the
write bit (low).
3. The addressed slave device asserts an ACK on SDA.
4. The master sends a command code that tells the slave
device to expect a block read. The ADM1062 command
code for a block read is 0xFD (1111 1101).
13. The ADM1062 issues a PEC byte to the master. The master
checks the PEC byte and issues another block read if the
PEC byte is incorrect.
14. A NACK is generated after the PEC byte to signal the end
of the read.
15. The master asserts a stop condition on SDA to end the
transaction.
5. The slave asserts an ACK on SDA.
6. The master asserts a repeat start condition on SDA.
7. The master sends the 7-bit slave address followed by the
read bit (high).
Note that the PEC byte is calculated using CRC-8. The frame
check sequence (FCS) conforms to CRC-8 by the polynomial
C(x) = x8 + x2 + x1 + 1
8. The slave asserts an ACK on SDA.
9. The ADM1062 sends a byte-count data byte that tells the
master how many data bytes to expect. The ADM1062
always returns 32 data bytes (0x20), which is the maximum
allowed by the SMBus Version 1.1 specification.
10. The master asserts an ACK on SDA.
See the SMBus Version 1.1 specification for details.
An example of a block read with the optional PEC byte is shown
in Figure 50.
1
2
3
4
5
6
7
8
9
10 11 12
SLAVE
ADDRESS
COMMAND 0xFD
(BLOCK READ)
SLAVE
ADDRESS
BYTE
COUNT
DATA
1
11. The master receives 32 data bytes.
S
W
A
A
S
R A
A
A
12. The master asserts an ACK on SDA after each data byte.
13. The master asserts a stop condition on SDA to end
the transaction.
13 14 15
DATA
32
A
PEC A P
1
2
3
4
5
6
7
8
9
10 11 12
Figure 50. Block Read from the EEPROM or RAM with PEC
SLAVE
ADDRESS
COMMAND 0xFD
(BLOCK READ)
SLAVE
ADDRESS
BYTE
COUNT
DATA
1
S
W
A
A
S
R A
A
A
13
P
DATA
32
A
Figure 49. Block Read from the EEPROM or RAM
Rev. C | Page 33 of 36
ADM1062
OUTLINE DIMENSIONS
6.00
BSC SQ
0.60 MAX
0.60 MAX
PIN 1
INDICATOR
31
40
1
30
PIN 1
INDICATOR
0.50
BSC
TOP
VIEW
4.25
4.10 SQ
3.95
5.75
BSC SQ
EXPOSED
PAD
(BOT TOM VIEW)
0.50
0.40
0.30
21
10
20
11
0.25 MIN
4.50
REF
12° MAX
0.80 MAX
0.65 TYP
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.05 MAX
0.02 NOM
1.00
0.85
0.80
0.30
0.23
0.18
COPLANARITY
0.08
0.20 REF
SECTION OF THIS DATA SHEET.
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-220-VJJD-2
Figure 51. 40-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
6 mm × 6 mm Body, Very Thin Quad
(CP-40-1)
Dimensions shown in millimeters
1.20
9.00
0.75
0.60
0.45
MAX
BSC SQ
37
36
48
1
PIN 1
7.00
BSC SQ
TOP VIEW
(PINS DOWN)
0° MIN
1.05
1.00
0.95
0.20
0.09
7°
3.5°
0°
0.08 MAX
COPLANARITY
12
25
24
0.15
0.05
13
SEATING
PLANE
VIEW A
0.50
BSC
0.27
0.22
0.17
LEAD PITCH
VIEW A
ROTATED 90° CCW
COMPLIANT TO JEDEC STANDARDS MS-026ABC
Figure 52. 48-Lead Thin Plastic Quad Flat Package [TQFP]
(SU-48)
Dimensions shown in millimeters
Rev. C | Page 34 of 36
ADM1062
ORDERING GUIDE
Model1
ADM1062ACPZ
ADM1062ACPZ-REEL7
ADM1062ASUZ
ADM1062ASUZ-REEL7
EVAL-ADM1062TQEBZ
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
40-Lead LFCSP_VQ
40-Lead LFCSP_VQ
48-Lead TQFP
48-Lead TQFP
Evaluation Kit (TQFP Version)
Package Option
CP-40-1
CP-40-1
SU-48
SU-48
1 Z = RoHS Compliant Part.
Rev. C | Page 35 of 36
ADM1062
NOTES
©2005–2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04433-0-6/11(C)
Rev. C | Page 36 of 36
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