ADM1176-1ARMZ-R7 [ADI]
Hot Swap Controller and I2C㈢ Power Monitor with Convert Pin; 热插拔控制器和I2C㈢电源监控与转换针脚
| 型号： | ADM1176-1ARMZ-R7 |
| 厂家： | 
ADI |
| 描述： | Hot Swap Controller and I2C㈢ Power Monitor with Convert Pin |
| 文件： | 总24页 (文件大小：676K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Hot Swap Controller and
I2C® Power Monitor with Convert Pin
ADM1176
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Allows safe board insertion and removal from a live backplane
Controls supply voltages from 3.15 V to 16.5 V
Precision current sense amplifier
ADM1176
MUX
V
VCC
0
Precision voltage input
SDA
SCL
12-BIT
ADC
2
12-bit ADC for current and voltage readback
Charge pumped gate drive for external N-channel FET
Adjustable analog current limit with circuit breaker
3ꢀ accurate hot swap current limit level
Fast response limits peak fault current
Automatic retry or latch-off on current fault
Programmable hot swap timing via TIMER pin
Active-high ON pin
I C
I
1
A
A1
A0
SENSE
CURRENT
SENSE
AMPLIFIER
FET DRIVE
CONTROLLER
ON
GATE
1.3V
UV COMPARATOR
GND
I2C® fast mode-compliant interface (400 kHz maximum)
Two address pins allow 16 devices on the same bus
10-lead MSOP
TIMER
Figure 1.
APPLICATIONS
3.15V TO 16.5V
R
N-CHANNEL FET
SENSE
Power monitoring/power budgeting
Central office equipment
VCC
SENSE
GATE
Telecommunication and data communication equipment
PCs/servers
CONTROLLER
P = VI
ADM1176
SDA
SDA
SCL
ON
GENERAL DESCRIPTION
SCL
The ADM1176 is an integrated hot swap controller that offers
digital current and voltage monitoring via an on-chip, 12-bit
analog-to-digital converter (ADC), communicated through an
I2C interface.
TIMER
A1
A0
GND
Figure 2. Applications Diagram
An internal current sense amplifier senses voltage across the sense
resistor in the power path via the VCC pin and the SENSE pin.
The ADM1176 limits the current through this resistor by control-
ling the gate voltage of an external N-channel FET in the power
path, via the GATE pin. The sense voltage (and, therefore, the
inrush current) is kept below a preset maximum.
A 12-bit ADC can measure the current seen in the sense
resistor, as well as the supply voltage on the VCC pin. An
industry-standard I2C interface allows a controller to read
current and voltage data from the ADC. Measurements can be
initiated by an I2C command. Alternatively, the ADC can run
continuously, and the user can read the latest conversion data
whenever it is required. Up to 16 unique I2C addresses can be
created, depending on the way the A0 and A1 pins are connected.
The ADM1176 protects the external FET by limiting the time
that it spends with maximum current running through it. This
current limit period is set by the choice of capacitor attached to
the TIMER pin. Additionally, the device provides protection from
overcurrent events that may occur once the hot swap event is
complete. In the case of a short-circuit event, the current in the
sense resistor exceeds an overcurrent trip threshold, and the FET
is switched off immediately by pulling down the GATE pin.
The ADM1176 is packaged in a 10-lead MSOP.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2006 Analog Devices, Inc. All rights reserved.
ADM1176
TABLE OF CONTENTS
Features .............................................................................................. 1
Initial Timing Cycle ................................................................... 14
Hot Swap Retry on the ADM1176-1 ....................................... 15
Voltage and Current Readback..................................................... 16
Serial Bus Interface..................................................................... 16
Identifying the ADM1176 on the I2C Bus............................... 16
General I2C Timing.................................................................... 16
Write and Read Operations ...................................................... 18
Quick Command........................................................................ 18
Write Command Byte................................................................ 18
Write Extended Byte .................................................................. 19
Read Voltage and/or Current Data Bytes................................ 20
Applications Waveforms................................................................ 22
Kelvin Sense Resistor Connection ........................................... 23
Outline Dimensions....................................................................... 24
Ordering Guide .......................................................................... 24
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions............................. 7
Typical Performance Characteristics ............................................. 8
Overview of the Hot Swap Function............................................ 13
Undervoltage Lockout ............................................................... 13
ON Function ............................................................................... 13
TIMER Function ........................................................................ 13
GATE and TIMER Functions During a Hot Swap ................ 14
Calculating Current Limits and Fault Current Limit Time.. 14
REVISION HISTORY
9/06—Revision 0: Initial Version
Rev. 0 | Page 2 of 24
ADM1176
SPECIFICATIONS
VCC = 3.15 V to 16.5 V; TA = −40°C to +85°C; typical values at TA = 25°C, unless otherwise noted.
Table 1.
Parameter
Min
Typ
Max
Unit Conditions
VCC PIN
Operating Voltage Range, VVCC
Supply Current, ICC
Undervoltage Lockout, VUVLO
Undervoltage Lockout Hysteresis, VUVLOHYST
ON PIN
3.15
16.5
2.5
V
mA
V
mV
1.7
2.8
80
VCC rising
Input Current, IINON
−100
+100
nA
ON < 1.5 V
ON rising
−2
1.26
35
+2
1.34
65
μA
V
mV
μs
Rising Threshold, VONTH
Trip Threshold Hysteresis, VONHYST
Glitch Filter Time
1.3
50
3
SENSE PIN
Input Leakage, ISENSE
Overcurrent Fault Timing Threshold, VOCTIM
−1
92
+1
μA
mV
VSENSE = VVCC
VOCTRIM = (VVCC − VSENSE), fault timing starts on the
TIMER pin
Overcurrent Limit Threshold, VLIM
97
100
103
115
mV
mV
VLIM = (VVCC − VSENSE), closed-loop regulation to a
current limit
VOCFAST = (VVCC − VSENSE), gate pull-down current
turned on
Fast Overcurrent Trip Threshold, VOCFAST
GATE PIN
Drive Voltage, VGATE
3
9
7
8
6
9
V
V
V
μA
mA
mA
mA
VGATE − VVCC, VVCC = 3.15 V
VGATE − VVCC, VVCC = 5 V
VGATE − VVCC, VVCC = 16.5 V
VGATE = 0 V
VGATE = 3 V, VVCC = 3.15 V
VGATE = 3 V, VVCC = 5 V
VGATE = 3 V, VVCC = 16.5 V
11
10
12.5
1.5
5
13
13
17
Pull-Up Current
Pull-Down Current
7
TIMER PIN
Pull-Up Current (Power On Reset), ITIMERUPPOR
Pull-Up Current (Fault Mode), ITIMERUPFAULT
Pull-Down Current (Retry Mode), ITIMERDNRETRY
−3.5
−40
−5
−60
2
−6.5
−80
3
μA
μA
μA
Initial cycle, VTIMER = 1 V
During current fault, VTIMER = 1 V
After current fault and during a cool-down
period on a retry device, VTIMER = 1 V
Pull-Down Current, ITIMERDN
Trip Threshold High, VTIMERH
Trip Threshold Low, VTIMERL
A0 PIN, A1 PIN
100
1.3
0.2
μA
V
V
Normal operation, VTIMER = 1 V
TIMER rising
TIMER falling
1.26
0.175
1.34
0.225
Set Address to 00, VADRLOWV
Set Address to 01, RADRLOWZ
0
135
0.8
165
V
kΩ
Low state
150
Resistor to ground state, load pin with specified
resistance for 01 decode
Set Address to 10, IADRHIGHZ
−1
2
+1
μA
Open state, maximum load allowed on the A0
pin and the A1 pin for 10 decode
High state
VADR = 2.0 V to 5.5 V
VADR = 0 V to 0.8 V
Set Address to 11, VADRHIGHV
Input Current for 11 Decode, IADRLOW
Input Current for 00 Decode, IADRHIGH
5.5
10
V
μA
μA
3
−22
−40
Rev. 0 | Page 3 of 24
ADM1176
Parameter
MONITORING ACCURACY1
Min
Typ
Max
Unit Conditions
Current Sense Absolute Accuracy
−1.45
−1.8
+1.45
+1.8
%
%
%
%
%
%
%
%
%
%
%
%
mV
VSENSE = 75 mV
VSENSE = 50 mV
VSENSE = 25 mV
VSENSE = 12.5 mV
VSENSE = 75 mV
VSENSE = 50 mV
VSENSE = 25 mV
VSENSE = 12.5 mV
VSENSE = 75 mV
VSENSE = 50 mV
VSENSE = 25 mV
VSENSE = 12.5 mV
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +85°C
0°C to +85°C
0°C to +85°C
0°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−2.8
+2.8
−5.7
+5.7
−1.5
+1.5
−1.8
+1.8
−2.95
−6.1
+2.95
+6.1
−1.95
−2.45
−3.85
−6.7
+1.95
+2.45
+3.85
+6.7
VSENSE for ADC Full Scale
Voltage Sense Accuracy
105.84
This is an absolute value to be used when
converting ADC codes to current readings;
any inaccuracy in this value is factored into
absolute current accuracy values (see specs
for Current Sense Absolute Accuracy)
−0.85
−0.9
+0.85
+0.9
%
%
%
%
%
%
V
VVCC = 3.0 V to 5.5 V
(low range)
VVCC = 10.8 V to 16.5 V
(high range)
0°C to +70°C
0°C to +70°C
0°C to +85°C
0°C to +85°C
−40°C to +85°C
−40°C to +85°C
−0.85
−0.9
+0.85
+0.9
VVCC = 3.0 V to 5.5 V
(low range)
VVCC = 10.8 V to 16.5 V
(high range)
−0.9
+0.9
VVCC = 3.0 V to 5.5 V
(low range)
VVCC = 10.8 V to 16.5 V
(high range)
−1.15
+1.15
VCC for ADC Full Scale,
Low Range (VRANGE = 1)
VCC for ADC Full Scale,
High Range (VRANGE = 0)
6.65
These are absolute values to be used when
converting ADC codes to current readings;
any inaccuracy in these values is factored into
voltage accuracy values (see specs for Current
Sense Absolute Accuracy)
26.52
V
I2C TIMING
Low Level Input Voltage, VIL
High Level Input Voltage, VIH
Low Level Output Voltage on SDA, VOL
0.3 VBUS
V
V
V
0.7 VBUS
0.4
IOL = 3 mA
Output Fall Time on SDA from VIHMIN to VILMAX 20 +
0.1 CB
250
ns
CB = bus capacitance from SDA to GND
Maximum Width of Spikes Suppressed by
Input Filtering on SDA and SCL Pins
Input Current, II, on SDA/SCL When Not
Driving Out a Logic Low
50
250
+10
ns
−10
μA
Input Capacitance on SDA/SCL
SCL Clock Frequency, fSCL
Low Period of the SCL Clock
High Period of the SCL Clock
5
pF
kHz
ns
400
600
1300
ns
Rev. 0 | Page 4 of 24
ADM1176
Parameter
Min
Typ
Max
Unit Conditions
Setup Time for a Repeated Start Condition,
tSU;STA
600
ns
SDA Output Data Hold Time, tHD;DAT
Setup Time for a Stop Condition, tSU;STO
Bus Free Time Between a Stop and a Start
Condition, tBUF
100
600
1300
900
ns
ns
ns
Capacitive Load for Each Bus Line
400
pF
1 Monitoring accuracy is a measure of the error in a code that is read back for a particular voltage/current. This is a combination of amplifier error, reference error, ADC
error, and error in ADC full-scale code conversion factor.
Rev. 0 | Page 5 of 24
ADM1176
ABSOLUTE MAXIMUM RATINGS
Table 3. Thermal Resistance
Package Type
Table 2.
θJA
Unit
Parameter
Rating
10-Lead MSOP
137.5
°C/W
VCC Pin
20 V
SENSE Pin
20 V
TIMER Pin
ON Pin
GATE Pin
−0.3 V to +6 V
−0.3 V to +20 V
30 V
ESD CAUTION
SDA Pin, SCL Pin
A0 Pin, A1 Pin
Storage Temperature Range
Operating Temperature Range
Lead Temperature (Soldering, 10 sec)
Junction Temperature
−0.3 V to +7 V
−0.3 V to +6 V
−65°C to +125°C
−40°C to +85°C
300°C
150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. 0 | Page 6 of 24
ADM1176
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
VCC
SENSE
ON
1
2
3
4
5
10 GATE
9
8
7
6
A1
ADM1176
TOP VIEW
(Not to Scale)
A0
GND
SDA
SCL
TIMER
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Mnemonic Description
1
VCC
Positive Supply Input Pin. The operating supply voltage range is from 3.15 V to 16.5 V. An undervoltage
lockout (UVLO) circuit resets the ADM1176 when a low supply voltage is detected.
2
SENSE
Current Sense Input Pin. A sense resistor between the VCC pin and the SENSE pin sets the analog current
limit. The hot swap operation of the ADM1176 controls the external FET gate to maintain the (VVCC − VSENSE
voltage at 100 mV or below.
)
3
ON
Undervoltage Input Pin. Active-high pin. An internal ON comparator has a trip threshold of 1.3 V, and the
output of this comparator is used as an enable for the hot swap operation. With an external resistor divider
from VCC to GND, this pin can be used to enable the hot swap operation on a specific voltage on VCC, giving
an undervoltage function.
4
5
GND
TIMER
Chip Ground Pin.
Timer Pin. An external capacitor, CTIMER, sets a 270 ms/μF initial timing cycle delay and a 21.7 ms/μF fault delay.
The GATE pin turns off when the TIMER pin is pulled beyond the upper threshold. An overvoltage detection
with an external Zener can be used to force this pin high.
6
7
8
SCL
SDA
A0
I2C Clock Pin. Open-drain input requires an external resistive pull-up.
I2C Data I/O Pin. Open-drain input/output. Requires an external resistive pull-up.
I2C Address Pin. This pin can be tied low, tied high, left floating, or tied low through a resistor. Sixteen different
I2C address options are available, depending on the external configuration of the A0 pin and A1 pin.
9
A1
I2C Address Pin. This pin can be tied low, tied high, left floating or tied low through a resistor. Sixteen different
I2C address options are available, depending on the external configuration of the A0 pin and the A1 pin.
10
GATE
GATE Output Pin. This pin is the high-side gate drive of an external N-channel FET. This pin is driven by the
FET drive controller, which utilizes a charge pump to provide a 12.5 μA pull-up current to charge the FET
GATE pin. The FET drive controller regulates to a maximum load current (100 mV through the sense resistor)
by modulating the GATE pin.
Rev. 0 | Page 7 of 24
ADM1176
TYPICAL PERFORMANCE CHARACTERISTICS
2.0
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
0
2
4
6
8
10
(V)
12
14
16
18
–40
–20
0
20
40
60
80
V
TEMPERATURE (°C)
CC
Figure 4. Supply Current vs. Supply Voltage
Figure 7. Supply Current vs. Temperature (Gate On)
12
10
8
12
10
8
5V V
CC
3.15V V
CC
6
6
4
4
2
2
0
0
–40
0
2
4
6
8
10
(V)
12
14
16
18
–20
0
20
40
60
80
V
TEMPERATURE (°C)
CC
Figure 5. Drive Voltage (VGATE − VCC) vs. Supply Voltage
Figure 8. Drive Voltage (VGATE − VCC) vs. Temperature
0
–2
0
–2
–4
–4
–6
–6
–8
–8
–10
–12
–14
–10
–12
–14
0
2
4
6
8
10
(V)
12
14
16
18
–40
–20
0
20
40
60
80
V
TEMPERATURE (°C)
CC
Figure 6. Gate Pull-Up Current vs. Supply Voltage
Figure 9. Gate Pull-Up Current vs. Temperature
Rev. 0 | Page 8 of 24
ADM1176
12
10
8
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
HIGH
6
4
2
LOW
8
0
0
2
4
6
8
10
(V)
12
14
16
18
0
2
4
6
10
(V)
12
14
16
18
V
V
CC
CC
Figure 10. Gate Pull-Down Current vs. VCC at VGATE = 5 V
Figure 13. Timer Threshold vs. Supply Voltage
2
0
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
–2
HIGH
–4
–6
–8
–10
–12
–14
LOW
0
2
4
6
8
10
12
14
16
–40
–20
0
20
40
60
80
V
(V)
TEMPERATURE (°C)
GATE
Figure 11. Gate Pull-Up Current vs. Gate Voltage at VCC = 5 V
Figure 14. Timer Threshold vs. Temperature
100
90
80
70
60
50
40
30
20
10
0
20
V
= 12V
CC
15
10
5
V
= 5V
CC
V
= 3V
CC
0
0
5
10
15
20
25
0
0.5
1.0
1.5
2.0
2.5
3.0
(µF)
3.5
4.0
4.5
5.0
V
(V)
GATE
C
TIMER
Figure 12. Gate Pull-Down Current vs. Gate Voltage
Figure 15. Current Limit On Time vs. Timer Capacitance
Rev. 0 | Page 9 of 24
ADM1176
0
–1
–2
–3
–4
–5
0
–1
–2
–3
–4
–5
–6
–6
0
–40
–20
0
20
40
60
80
2
4
6
8
10
(V)
12
14
16
18
V
TEMPERATURE (°C)
CC
Figure 16.Timer Pull-Up Current (Initial Cycle) vs. Supply Voltage
Figure 19. Timer Pull-Up Current (Initial Cycle) vs. Temperature
0
–10
–20
–30
–40
–50
–60
–70
–80
0
–10
–20
–30
–40
–50
–60
–70
–80
0
2
4
6
8
10
(V)
12
14
16
18
–40
–20
0
20
40
60
80
V
TEMPERATURE (°C)
CC
Figure 17. Timer Pull-Up Current (C. B. Delay) vs. Supply Voltage
Figure 20. Timer Pull-Up Current (C. B. Delay) vs. Temperature
3.0
3.0
2.5
2.0
1.5
1.0
0.5
0
2.5
2.0
1.5
1.0
0.5
0
0
2
4
6
8
10
(V)
12
14
16
18
–40
–20
0
20
40
60
80
V
CC
TEMPERATURE (°C)
Figure 18. Timer Pull-Down Current (Cool-Off Cycle) vs. Supply Voltage
Figure 21. Timer Pull-Down Current (Cool-Off Cycle) vs. Temperature
Rev. 0 | Page 10 of 24
ADM1176
1000
900
800
700
600
500
400
300
200
100
0
120
115
110
105
100
95
90
85
80
2
4
6
8
10
(V)
12
14
16
18
2046
2047
2048
2049
2050
V
CODE
CC
Figure 22. Circuit Breaker Limit Voltage vs. Supply Voltage
Figure 25. ADC Noise, Current Channel, Midcode Input, 1000 Reads
1000
900
800
700
600
500
400
300
200
100
0
110
108
106
104
102
100
98
V
OCFAST
V
LIM
V
OCTIM
96
94
92
90
–40
–20
0
20
40
60
80
779
780
781
782
783
TEMPERATURE (°C)
CODE
Figure 23. VOCTIM, VLIM, VOCFAST vs. Temperature
Figure 26. ADC Noise, 14:1 Voltage Channel, 5 V Input, 1000 Reads
1000
900
800
700
600
500
400
300
200
100
0
11 DECODE
10 DECODE
01 DECODE 00 DECODE
3.2
3.0
2.8
2.6
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
3078
3079
3080
3081
3082
–35
–30
–25
–20
–15
–10
–5
0
5
10
CODE
I (A0/A1) (µA)
Figure 24. Address Pin Voltage vs. Address Pin Current
for Four Addressing Options
Figure 27. ADC Noise, 7:1 Voltage Channel, 5 V Input, 1000 Reads
Rev. 0 | Page 11 of 24
ADM1176
4
4
3
3
2
2
1
1
0
0
–1
–2
–3
–4
–1
–2
–3
–4
0
500
1000 1500 2000 2500 3000 3500 4000
CODE
0
500
1000 1500 2000 2500 3000 3500 4000
CODE
Figure 28. INL for ADC
Figure 29. DNL for ADC
Rev. 0 | Page 12 of 24
ADM1176
OVERVIEW OF THE HOT SWAP FUNCTION
When circuit boards are inserted into a live backplane, discharged
supply bypass capacitors draw large transient currents from the
backplane power bus as they charge. Such transient currents can
cause permanent damage to connector pins, as well as dips on
the backplane supply that can reset other boards in the system.
The ADM1176 is designed to turn a circuit board supply voltage on
and off in a controlled manner, allowing the circuit board to be
safely inserted into or removed from a live backplane. The
ADM1176 can reside either on the backplane or on the circuit
board itself.
If the fault current limit time is reached before the load drops
below the current limit, a fault has been detected, and the hot
swap operation is aborted by pulling down on the GATE pin to
turn off the FET. The ADM1176-2 latches off at this point and
attempts to hot swap again only when the ON pin is deasserted
and then asserted again.
The ADM1176-1 retries the hot swap operation indefinitely,
keeping the FET in its safe operating area (SOA) by using the
TIMER pin to time a cool-down period in between hot swap
attempts. The current and voltage threshold combinations on
the TIMER pin set the retry duty cycle to 3.8%.
The ADM1176 controls the inrush current to a fixed maximum
level by modulating the gate of an external N-channel FET placed
between the live supply rail and the load. This hot swap function
protects the card connectors and the FET itself from damage and
limits any problems that can be caused by high current loads on
the live supply rail.
The ADM1176 is designed to operate over a range of supplies
from 3.15 V to 16.5 V.
UNDERVOLTAGE LOCKOUT
An internal undervoltage lockout (UVLO) circuit resets the
ADM1176 if the VCCsupply is too low for normal operation.
The UVLO has a low-to-high threshold of 2.8 V, with 80 mV
hysteresis. Above 2.8 V supply voltage, the ADM1176 starts the
initial timing cycle.
The ADM1176 holds the GATE pin down (and, thus, the FET is
held off) until a number of conditions are met. An undervoltage
lockout circuit ensures that the device is provided with an adequate
input supply voltage. Once the input supply voltage has been
successfully detected, the device goes through an initial timing
cycle to provide a delay before it attempts to hot swap. This delay
ensures that the board is fully seated in the backplane before
the board is powered up.
ON FUNCTION
The ADM1176-1 has an active-high ON pin. The ON pin is the
input to a comparator that has a low-to-high threshold of 1.3 V,
a 50 mV hysteresis, and a glitch filter of 3 μs. A low input on the
ON pin turns off the hot swap operation by pulling the GATE pin
to ground, turning off the external FET. The TIMER pin is also
reset by turning on a pull-down current on this pin. A low-to-
high transition on the ON pin starts the hot swap operation.
A 10 kΩ pull-up resistor connecting the ON pin to the supply
is recommended.
Once the initial timing cycle is complete, the hot swap function
is switched on under control of the ON pin. When the ON pin
is asserted high, the hot swap operation starts.
The ADM1176 charges up the gate of the FET to turn on the
load. It continues to charge up the GATE pin until the linear
current limit (set to 100 mV/RSENSE) is reached. For some combi-
nations of low load capacitance and high current limit, this limit
may not be reached before the load is fully charged up. If current
limit is reached, the ADM1176 regulates the GATE pin to keep
the current at this limit. For currents above the overcurrent
fault timing threshold, nominally 100 mV/RSENSE, the current
fault is timed by sourcing a current out to the TIMER pin. If the
load becomes fully charged before the fault current limit time is
reached (when the TIMER pin reaches 1.3 V), the current drops
below the overcurrent fault timing threshold. The ADM1176
then charges the GATE pin higher to fully enhance the FET for
lowest RON, and the TIMER pin is pulled down again.
Alternatively, an external resistor divider at the ON pin can be
used to program an undervoltage lockout value higher than the
internal UVLO circuit, thereby setting a voltage level at the
VCC supply where the hot swap operation is to start. An RC
filter can be added at the ON pin to increase the delay time at
card insertion if the initial timing cycle delay is insufficient.
TIMER FUNCTION
The TIMER pin handles several timing functions with an
external capacitor, CTIMER. There are two comparator thresholds:
VTIMERH (0.2 V) and VTIMERL (1.3 V). The four timing current
sources are a 5 ꢀA pull-up, a 60 ꢀA pull-up, a 2 ꢀA pull-down,
and a 100 ꢀA pull-down. The 100 ꢀA pull-down is a non-ideal
current source approximating a 7 kΩ resistor below 0.4 V.
These current and voltage levels, together with the value of CTIMER
chosen by the user, determine the initial timing cycle time, the
fault current limit time, and the hot swap retry duty cycle.
Rev. 0 | Page 13 of 24
ADM1176
GATE AND TIMER FUNCTIONS DURING
A HOT SWAP
CALCULATING CURRENT LIMITS AND FAULT
CURRENT LIMIT TIME
During hot insertion of a board onto a live supply rail at VCC,
the abrupt application of supply voltage charges the external
FET drain/gate capacitance, which can cause an unwanted gate
voltage spike. An internal circuit holds GATE low before the
internal circuitry wakes up. This reduces the FET current surges
substantially at insertion. The GATE pin is also held low during
the initial timing cycle and until the ON pin has been taken
high to start the hot swap operation.
The nominal linear current limit is determined by a sense
resistor connected between the VCC pin and the SENSE pin
as given by Equation 1.
I
LIMIT(NOM) = VLIM(NOM)/RSENSE = 100 mV/RSENSE
(1)
(2)
(3)
The minimum linear fault current is given by Equation 2.
ILIMIT(MIN) = VLIM(MIN)/RSENSE(MAX) = 90 mV/RSENSE(MAX)
The maximum linear fault current is given by Equation 3.
ILIMIT(MAX) = VLIM(MAX)/RSENSE(MIN) = 110 mV/RSENSE(MIN)
During hot swap operation, the GATE pin is first pulled up by
a 12 μA current source. If the current through the sense resistor
reaches the overcurrent fault timing threshold, VOCTIM, a pull-up
current of 60 ꢀA on the TIMER pin, is turned on; and this pin
starts charging up. At a slightly higher voltage in the sense
resistor, the error amplifier servos the GATE pin to maintain a
constant current to the load by controlling the voltage across
The power rating of the sense resistor should be rated at the
maximum linear fault current level.
The minimum overcurrent fault timing threshold current is
given by Equation 4.
the sense resistor to the linear current limit, VLIM
.
IOCTIM(MIN) = VOCTIM(MIN)/RSENSE(MAX) = 85 mV/RSENSE(MAX)
(4)
A normal hot swap is complete when the board supply capaci-
tors near full charge and the current through the sense resistor
drops to eventually reach the level of the board load current.
As soon as the current drops below the overcurrent fault timing
threshold, the current into the TIMER pin switches from being a
60 μA pull-up to a 100 μA pull-down. The ADM1176 then drives
the GATE voltage as high as it can to fully enhance the FET and
reduce RON losses to a minimum.
The maximum fast overcurrent trip threshold current is given
by Equation 5.
I
OCFAST(MAX) = VOCFAST(MAX)/RSENSE(MIN) = 115 mV/RSENSE(MIN) (5)
The fault current limit time is the time that a device spends
timing an overcurrent fault, and is given by Equation 6.
t
FAULT ≈ 21.7 × CTIMER ms/μF
(6)
A hot swap fails if the load current does not drop below the
over-current fault timing threshold, VOCTIM, before the TIMER
pin has charged up to 1.3 V. In this case the GATE pin is then
pulled down with a 2 mA current sink. The GATE pull-down
stays on until a hot swap retry starts, which can be forced by
deasserting and then reasserting the ON pin. On the ADM1176-1,
the device retries automatically after a cool-down period.
INITIAL TIMING CYCLE
When VCC is first connected to the backplane supply, the
internal supply (Time Point (1) in Figure 30) of the ADM1176
must be charged up. A very short time later (significantly less
than 1 ms), the internal supply is fully up and, because the
undervoltage lockout voltage has been exceeded at VCC, the
device comes out of reset. During this first short reset period,
the GATE pin is held down with a 25 mA pull-down current,
and the TIMER pin is pulled down with a 100 μA current sink.
The ADM1176 also features a method of protection from
sudden load current surges, such as a low impedance fault,
when the current seen across the sense resistor may go well
beyond the linear current limit. If the fast overcurrent trip
threshold, VOCFAST, is exceeded, the 2 mA GATE pull-down is
turned on immediately. This pulls the GATE voltage down
quickly to enable the ADM1176 to limit the length of the
current spike that gets through and also to bring the current
through the sense resistor back into linear regulation as quickly
as possible. This process protects the backplane supply from
sustained overcurrent conditions that can otherwise cause the
backplane supply to droop during the overcurrent event.
The ADM1176 then goes through an initial timing cycle. At
Time Point (2), the TIMER pin is pulled high with 5 ꢀA. At
Time Point (3), the TIMER reaches the VTIMERL threshold, and
the first portion of the initial cycle ends. The 100 ꢀA current
source then pulls down the TIMER pin until it reaches 0.2 V at
Time Point (4). The initial cycle delay (Time Point (2) to Time
Point (4)) is related to CTIMER by Equation 7.
t
INITIAL ≈ 270 × CTIMER ms/μF
(7)
Rev. 0 | Page 14 of 24
ADM1176
(1)
(2)
(3)(4)
(5)(6)
(7)
When the initial timing cycle terminates, the device is ready to
start a hot swap operation (assuming ON pin is asserted). In the
example shown in Figure 30, the ON pin is asserted at the same
time that VCC is applied, so the hot swap operation starts
immediately after Time Point (4). At this point, the FET gate is
charged up with a 12 μA current source.
V
VCC
V
ON
At Time Point (5), the threshold voltage of the FET is reached,
and the load current begins to flow. The FET is controlled to
keep the sense voltage at 100 mV (this corresponds to a
maximum load current level defined by the value of RSENSE).
V
TIMER
V
GATE
At Time Point (6), VGATE and VOUT have reached their full
potential, and the load current has settled to its nominal level.
Figure 31 illustrates the situation where the ON pin is asserted
after VCC is applied.
V
SENSE
V
OUT
(1)
(2)
(3)(4)(5)
(6)
INITIAL TIMING
CYCLE
V
Figure 31. Startup (ON Asserts After Power Is Applied)
VCC
HOT SWAP RETRY ON THE ADM1176-1
V
With the ADM1176-1, the device turns off the FET after an
overcurrent fault and then uses the TIMER pin to time a delay
before automatically retrying to hot swap.
ON
V
TIMER
As with all ADM1176 devices, on overcurrent fault is timed by
charging the TIMER cap with a 60 μA pull-up current. When
the TIMER pin reaches 1.3 V, the fault current limit time has
been reached, and the GATE pin is pulled down. On the
ADM1176-1, the TIMER pin is then pulled down with a 2 μA
current sink. When the TIMER pin reaches 0.2 V, it automati-
cally restarts the hot swap operation.
V
GATE
V
SENSE
V
OUT
The cool-down period is related to CTIMER by Equation 8.
INITIAL TIMING
CYCLE
t
COOL ≈ 550 × CTIMER ms/μF
(8)
(9)
Figure 30. Startup (ON Asserts as Power Is Applied)
Thus, the retry duty cycle is given by Equation 9.
tFAULT/(tCOOL + tFAULT ) × 100% = 3.8%
Rev. 0 | Page 15 of 24
ADM1176
VOLTAGE AND CURRENT READBACK
In addition to providing hot swap functionality, the ADM1176
contains the components to allow voltage and current readback
over an Inter-IC (I2C) bus. The voltage output of the current sense
amplifier and the voltage on the VCC pin are fed into a 12-bit
ADC via a multiplexer. The device can be instructed to convert
voltage and/or current at any time during operation via an I2C
command. When all conversions are complete, the voltage
and/or current values can be read out to 12-bit accuracy in
two or three bytes.
1. The master initiates data transfer by establishing a start
condition, defined as a high-to-low transition on the serial
data line, SDA, while the serial clock line SCL remains
high. This indicates that a data stream follows. All slave
peripherals connected to the serial bus respond to the start
condition and shift in the next eight bits, consisting of a 7-
W
bit slave address (MSB first) plus an R/ bit that
determines the direction of the data transfer; that is,
whether data is to be written to or read from the slave
device (0 = write, 1 = read).
SERIAL BUS INTERFACE
Control of the ADM1176 is carried out via the I2C bus. This
interface is compatible with fast mode I2C (400 kHz maximum).
The ADM1176 is connected to this bus as a slave device under
the control of a master device.
The peripheral whose address corresponds to the transmitted
address responds by pulling the data line low during the
low period before the ninth clock pulse, known as the
acknowledge bit, and holding it low during the high period of
this clock pulse. All other devices on the bus now remain
idle while the selected device waits for data to be read from
IDENTIFYING THE ADM1176 ON THE I2C BUS
W
it or written to it. If the R/ bit is 0, the master writes to the
The ADM1176 has a 7-bit serial bus slave address. When the
device powers up, it does so with a default serial bus address.
The three MSBs of the address are set to 100, and the four LSBs
are determined by the state of the A0 pin and the A1 pin. There
are 16 different configurations available on the A0 pin and the
A1 pin that correspond to 16 different I2C addresses for the four
LSBs (see Table 5). This scheme allows sixteen ADM1176 devices
to operate on a single I2C bus.
W
slave device. If the R/ bit is 1, the master reads from the
slave device.
2. Data is sent over the serial bus in sequences of nine clock
pulses: eight bits of data followed by an acknowledge bit
from the slave device. Data transitions on the data line
must occur during the low period of the clock signal and
remain stable during the high period, because a low-to-
high transition when the clock is high can be interpreted as
a stop signal.
Table 5. Setting I2C Addresses via the A0 Pin and the A1 Pin
A0 Configuration
A1 Configuration Address
If the operation is a write operation, the first data byte after
the slave address is a command byte. This tells the slave
device what to expect next. It can be an instruction, such
as telling the slave device to expect a block write;
or it can be a register address that tells the slave where
subsequent data is to be written.
Low state
Low state
Low state
Low state
Resistor to GND
Resistor to GND
Resistor to GND
Resistor to GND
Floating
Floating
Floating
Floating
High state
High state
High state
High state
Low state
Resistor to GND
Floating
High state
Low state
Resistor to GND
Floating
High state
Low state
Resistor to GND
Floating
High state
Low state
Resistor to GND
Floating
0x80
0x88
0x90
0x98
0x82
0x8A
0x92
0x9A
0x84
0x8C
0x94
0x9C
0x86
0x8E
0x96
0x9E
Because data can flow in only one direction, as defined by
W
the R/ bit, it is not possible to send a command to a slave
device during a read operation. Before doing a read
operation, it may first be necessary to do a write operation
to tell the slave what sort of read operation to expect
and/or the address from which data is to be read.
3. When all data bytes have been read or written, stop
conditions are established. In write mode, the master pulls
the data line high during the 10th clock pulse to assert a
stop condition. In read mode, the master device releases
the SDA line during the low period before the ninth clock
pulse, but the slave device does not pull it low. This is
known as a no acknowledge. The master then takes the data
line low during the low period before the 10th clock pulse,
then high during the 10th clock pulse to assert a stop
condition.
High state
GENERAL I2C TIMING
Figure 32 and Figure 33 show timing diagrams for general read
and write operations using the I2C. The I2C specification defines
conditions for different types of read and write operations, which
are discussed later. The general I2C protocol operates as follows:
Rev. 0 | Page 16 of 24
ADM1176
9
9
1
1
SCL
SDA
0
0
A1
A0
R/W
D7
D6
D5
1
D4
D3
D2
D1
D0
1
1
1
ACKNOWLEDGE BY
SLAVE
ACKNOWLEDGE BY
SLAVE
START BY MASTER
FRAME 1
SLAVE ADDRESS
FRAME 2
COMMAND CODE
1
9
9
SCL
(CONTINUED)
SDA
(CONTINUED)
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
STOP
BY
MASTER
ACKNOWLEDGE BY
SLAVE
ACKNOWLEDGE BY
SLAVE
FRAME 3
DATA BYTE
FRAME N
DATA BYTE
Figure 32. General I2C Write Timing Diagram
9
9
1
1
SCL
SDA
0
0
A1
A0 R/W
D7
D6
D5
1
D4
D3
D2
D1
D0
1
1
1
ACKNOWLEDGE BY
SLAVE
ACKNOWLEDGE BY
MASTER
START BY MASTER
FRAME 1
SLAVE ADDRESS
FRAME 2
DATA BYTE
1
9
9
SCL
(CONTINUED)
SDA
(CONTINUED)
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
STOP
BY
MASTER
ACKNOWLEDGE BY
MASTER
NO ACKNOWLEDGE
FRAME 3
DATA BYTE
FRAME N
DATA BYTE
Figure 33. General I2C Read Timing Diagram
tHD;STA
tLOW
tR
tF
SCL
tHIGH
tSU;STA
tSU;STO
tHD;STA
tSU;DAT
tHD;DAT
SDA
tBUF
S
P
P
S
Figure 34. Serial Bus Timing Diagram
Rev. 0 | Page 17 of 24
ADM1176
WRITE COMMAND BYTE
WRITE AND READ OPERATIONS
The I2C specification defines several protocols for different
types of read and write operations. The operations used in the
ADM1176 are discussed in the sections that follow. Table 6
shows the abbreviations used in the command diagrams.
In the write command byte operation, the master device sends
a command byte to the slave device, as follows:
1. The master device asserts a start condition on SDA.
Table 6. I2C Abbreviations
Abbreviation
2. The master sends the 7-bit slave address, followed by the
write bit (low).
Condition
Start
Stop
S
P
3. The addressed slave device asserts an acknowledge on SDA.
4. The master sends the command byte. The command byte
is identified by an MSB = 0. An MSB = 1 indicates an
extended register write (see the Write Extended Byte section).
R
Read
Write
Acknowledge
No acknowledge
W
A
N
5. The slave asserts an acknowledge on SDA.
QUICK COMMAND
6. The master asserts a stop condition on SDA to end the
transaction.
The quick command operation allows the master to check if the
slave is present on the bus, as follows:
1
2
3
4
5
6
1. The master device asserts a start condition on SDA.
SLAVE
ADDRESS
COMMAND
BYTE
S
W A
A
P
2. The master sends the 7-bit slave address, followed by the
write bit (low).
Figure 36. Write Command Byte
The seven LSBs of the command byte are used to configure and
control the ADM1176. Table 7 provides details of the function
of each bit.
3. The addressed slave device asserts an acknowledge on SDA.
1
2
3
SLAVE
ADDRESS
S
W A
Figure 35. Quick Command
Table 7. Command Byte Operations
Bit Default Name Function
C0
0
V_CONT
Set to convert voltage continuously. If readback is attempted before the first conversion is complete, the
ADM1176 asserts an acknowledge and returns all 0s in the returned data.
C1
C2
C3
C4
0
0
0
0
V_ONCE
I_CONT
I_ONCE
VRANGE
Set to convert voltage once. Self-clears. I2C asserts a no acknowledge on attempted reads until the ADC
conversion is complete.
Set to convert voltage continuously. If readback is attempted before the first conversion is complete, the
ADM1176 asserts an acknowledge and returns all 0s in the returned data.
Set to convert current once. Self-clears. I2C asserts a no acknowledge on attempted reads until the ADC
conversion is complete.
Selects different internal attenuation resistor networks for voltage readback. A 0 in C4 selects a 14:1 voltage
divider. A 1 in C4 selects a 7:2 voltage divider. With an ADC full scale of 1.902 V, the voltage at the VCC pin for
an ADC full-scale result is 26.35 V for VRANGE = 0 and 6.65 V for VRANGE = 1.
C5
C6
0
0
N/A
Unused.
STATUS_RD Status read. When this bit is set, the data byte read back from the ADM1176 is the STATUS byte. This contains
the status of the device alerts. See Table 15 for full details of the STATUS byte.
Rev. 0 | Page 18 of 24
ADM1176
WRITE EXTENDED BYTE
In the write extended byte operation, the master device writes
to one of the three extended registers of the slave device, as
follows:
7. The slave asserts an acknowledge on SDA.
8. The master asserts a stop condition on SDA to end the
transaction.
1. The master device asserts a start condition on SDA.
1
2
3
4
5
6
7
8
SLAVE
REGISTER
ADDRESS
REGISTER
DATA
2. The master sends the 7-bit slave address, followed by the
write bit (low).
S
W A
A
A
P
ADDRESS
Figure 37. Write Extended Byte
3. The addressed slave device asserts an acknowledge on SDA.
Table 9, Table 10, and Table 11 give details of each extended
register.
4. The master sends the register address byte. The MSB of
this byte is set to 1 to indicate an extended register write.
The two LSBs indicate which of the three extended
registers are to be written to (see Table 8). All other bits
should be set to 0.
Table 8. Extended Register Addresses
A6 A5 A4 A3 A2 A1 A0 Extended Register
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
1
ALERT_EN
ALERT_TH
CONTROL
5. The slave asserts an acknowledge on SDA.
6. The master sends the command byte. The command byte
is identified by MSB = 0. MSB = 1 indicates an extended
register write.
Table 9. ALERT_EN Register Operations
Bit Default Name
Function
0
1
2
3
4
0
0
1
0
0
EN_ADC_OC1
EN_ADC_OC4
EN_HS_ALERT
Enabled if a single ADC conversion on the I channel has exceeded the threshold set in the ALERT_TH
register.
Enabled if four consecutive ADC conversions on the I channel have exceeded the threshold set in the
ALERT_TH register.
Enabled if the hot swap has either latched off or entered a cool down cycle because of an overcurrent
event.
EN_OFF_ALERT Enables an alert if the HS operation is turned off by a transition that deasserts the ON pin or by an
operation that writes the SWOFF bit high.
CLEAR
Clears the ON_ALERT, HS_ALERT and ADC_ALERT status bits in the STATUS register. These may
immediately reset if the source of the alert has not been cleared or disabled with the other bits in this
register. This bit self-clears to 0 after the STATUS register bits have been cleared.
Table 10. ALERT_TH Register Operations
Bit Default Function
7:0 FF
The ALERT_TH register sets the current level at which an alert occurs. Defaults to ADC full scale. The ALERT_TH 8-bit
number corresponds to the top eight bits of the current channel data.
Table 11. CONTROL Register Operations
Bit
Default
Name
Function
0
0
SWOFF
Forces hot swap off. Equivalent to deasserting the ON pin.
Rev. 0 | Page 19 of 24
ADM1176
READ VOLTAGE AND/OR CURRENT DATA BYTES
The ADM1176 can be set up to provide information in three
different ways (see the Write Command Byte section). Depending
on how the device is configured, the following data can be read
out of the device after a conversion (or conversions).
For cases where the master is reading voltage only or current
only, only two data bytes are read. Step 7 and Step 8 are not
required.
1
2
3
4
5
6
7
8
9 10
SLAVE
ADDRESS
Voltage and Current Readback
S
R
A
DATA 1
A
DATA 2
A
DATA 3
N
P
The ADM1176 digitizes both voltage and current. Three bytes
are read out of the device in the format shown in Table 12.
Figure 38. Three-Byte Read from ADM1176
Table 12. Voltage and Current Readback Format
1
2
3
4
5
6
7
8
Byte Contents B7
B6
B5 B4 B3 B2 B1 B0
SLAVE
REGISTER
ADDRESS
REGISTER
DATA
S
R
A
A
N
P
ADDRESS
1
2
3
Voltage
MSBs
Current
MSBs
V11 V10 V9 V8 V7 V6 V5 V4
Figure 39. Two-Byte Read from ADM1176
I11
V3
I10
V2
I9
I8
I7
I6
I2
I5
I1
I4
I0
Converting ADC Codes to Voltage and Current Readings
LSBs
V1 V0 I3
The following equations can be used to convert ADC codes
representing voltage and current from the ADM1175 12-bit
ADC into actual voltage and current values.
Voltage Readback
The ADM1176 digitizes voltage only. Two bytes are read out of
the device in the format shown in Table 13.
Voltage = (VFULLSCALE/4096) × Code
Table 13. Voltage Only Readback Format
where:
Byte Contents
B7 B6 B5 B4 B3 B2 B1 B0
Voltage MSBs V11 V10 V9 V8 V7 V6 V5 V4
Voltage LSBs V3 V2 V1 V0
V
FULLSCALE = 6.65 (7:2 range) or 26.35 (14:1 range).
1
2
Code is the ADC voltage code read from the device (Bit V0
0
0
0
0
to V11).
Current Readback
Current = ((IFULLSCALE/4096) × Code)/Sense Resistor
The ADM1176 digitizes current only. Two bytes are read out of
the device in the format shown in Table 14.
where:
I
FULLSCALE = 105.84 mV.
Table 14. Current Only Readback Format
Code is the ADC current code read from the device (Bit I0
Byte Contents
B7 B6 B5 B4 B3 B2 B1 B0
to Bit I11).
1
2
Current MSBs I11 I10 I9 I8 I7 I6
Current LSBs I3 I2 I1 I0
I5
0
I4
0
0
0
Read Status Register
A single register of status data can also be read from the
ADM1176.
The following series of events occur when the master receives
three bytes (voltage and current data) from the slave device:
1. The master device asserts a start condition on SDA.
1. The master device asserts a start condition on SDA.
2. The master sends the 7-bit slave address, followed by the
read bit (high).
2. The master sends the 7-bit slave address, followed by the
read bit (high).
3. The addressed slave device asserts an acknowledge on SDA.
4. The master receives the status byte.
3. The addressed slave device asserts an acknowledge on SDA.
4. The master receives the first data byte.
5. The master asserts an acknowledge on SDA.
5. The master asserts an acknowledge on SDA.
6. The master receives the second data byte.
7. The master asserts an acknowledge on SDA.
8. The master receives the third data byte.
1
2
3
4
5
SLAVE
ADDRESS
S
R
A
DATA 1
A
Figure 40. Status Read from ADM1176
9. The master asserts a no acknowledge on SDA.
Table 15 shows the ADM1176 status registers in detail. Note
that Bit 1, Bit 3, and Bit 5 are cleared by writing to Bit 4 of the
ALERT_EN register (CLEAR).
10. The master asserts a stop condition on SDA, and the
transaction ends.
Rev. 0 | Page 20 of 24
ADM1176
Table 15. Status Byte Operations
Bit Name
Function
0
1
ADC_OC
An ADC-based overcurrent comparison has been detected on the last three conversions
ADC_ALERT An ADC-based overcurrent trip has happened, which has caused the alert. Cleared by writing to Bit 4 of the ALERT_EN
register.
2
HS_OC
The hot swap is off due to an analog overcurrent event. On parts that latch off, this is the same as the HS_ALERT status
bit (if EN_HS_ALERT = 1). On the retry parts, this indicates the current state: a 0 may indicate that the data was read
during a period when the device was retrying, or that it has successfully hot swapped by retrying after at least one
overcurrent timeout.
3
4
HS_ALERT
The hot swap has failed since the last time this was reset. Cleared by writing to Bit 4 of the ALERT_EN register.
OFF_STATUS The state of the ON pin. Set to 1 if the input pin is deasserted. Can also be set to 1 by writing to the SWOFF bit of the
CONTROL register.
5
OFF_ALERT
An alert has been caused by either the ON pin or the SWOFF bit. Cleared by writing to Bit 4 of the ALERT_EN register.
Rev. 0 | Page 21 of 24
ADM1176
APPLICATIONS WAVEFORMS
1
1
2
2
3
3
4
4
CH1 1.5A
CH2 1.00V
M40.0ms
CH1 1.5A
CH2 1.00V
M10.0ms
CH3 20.0V CH4 10.0V
CH3 20.0V CH4 10.0V
Figure 41. Inrush Current Control into 220 μF Load
(CH1 = ILOAD, CH2 = VTIMER, CH3 = VGATE, CH4 = VOUT
Figure 44. Overcurrent Condition During Operation (ADM1176-1 Model)
(CH1 = ILOAD, CH2 = VTIMER, CH3 = VGATE, CH4 = VOUT
)
)
1
1
2
2
3
3
4
4
CH1 1.5A
CH3 20.0V CH4 10.0V
CH2 1.00V
M10.0ms
CH1 1.5A
CH3 20.0V CH4 10.0V
CH2 1.00V
M20.0ms
Figure 42. Overcurrent Condition at Startup (ADM1176-1 Model)
(CH1 = ILOAD, CH2 = VTIMER, CH3 = VGATE, CH4 = VOUT
Figure 45. Overcurrent Condition During Operation (ADM1176-2 Model)
(CH1 = ILOAD, CH2 = VTIMER, CH3 = VGATE, CH4 = VOUT
)
)
1
2
3
4
CH1 1.5A
CH2 1.00V
M20.0ms
CH3 20.0V CH4 10.0V
Figure 43. Overcurrent Condition at Startup (ADM1176-2 Model)
(CH1 = ILOAD, CH2 = VTIMER, CH3 = VGATE, CH4 = VOUT
)
Rev. 0 | Page 22 of 24
ADM1176
SENSE RESISTOR
KELVIN SENSE RESISTOR CONNECTION
When using a low value sense resistor for high current
CURRENT
FLOW FROM
SUPPLY
CURRENT
FLOW TO
LOAD
measurement, the problem of parasitic series resistance may
arise. The lead resistance can be a substantial fraction of the
rated resistance, making the total resistance a function of lead
length. This problem can be avoided by using a Kelvin sense
connection. This type of connection separates the current path
through the resistor and the voltage drop across the resistor.
Figure 46 shows the correct way to connect the sense resistor
between the VCC pin and the SENSE pin of the ADM1176.
KELVIN SENSE TRACES
VCC
SENSE
ADM1176
Figure 46. Kelvin Sense Connections
Rev. 0 | Page 23 of 24
ADM1176
OUTLINE DIMENSIONS
3.10
3.00
2.90
6
10
5.15
4.90
4.65
3.10
3.00
2.90
1
5
PIN 1
0.50 BSC
0.95
0.85
0.75
1.10 MAX
0.80
0.60
0.40
8°
0°
0.15
0.05
0.33
0.17
SEATING
PLANE
0.23
0.08
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187-BA
Figure 47. 10-Lead Mini Small Outline Package [MSOP]
(RM-10)
Dimensions shown in millimeters
ORDERING GUIDE
Model
ADM1176-1ARMZ-R71
ADM1176-2ARMZ-R71
EVAL-ADM1176EBZ1
Hot Swap Retry Option
Automatic Retry Version
Latched Off Version
Temperature Range
−40°C to +85°C
−40°C to +85°C
Package Description
10-Lead MSOP
10-Lead MSOP
Package Option
RM-10
RM-10
Branding
M5U
M5V
Evaluation Board
1 Z = Pb-free part.
Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent
Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06046-0-9/06(0)
Rev. 0 | Page 24 of 24
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