ADM1185ARMZ-1 [ADI]
Quad Voltage Monitor and Sequencer; 四电压监视和音序器
| 型号： | ADM1185ARMZ-1 |
| 厂家： | 
ADI |
| 描述： | Quad Voltage Monitor and Sequencer |
| 文件： | 总16页 (文件大小：320K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Quad Voltage Monitor and Sequencer
ADM1185
FEATURES
FUNCTIONAL BLOCK DIAGRAM
VCC
Powered from 2.7 V to 5.5 V on the VCC pin
Monitors 4 supplies via 0.8% accurate comparators
Logical core with internal timeouts provides power supply
sequencing and fault protection
4 inputs can be programmed to monitor different voltage
levels with resistor dividers
3 open-drain enable outputs
POWER AND
REF = 0.6V
REFERENCE
GENERATOR
ADM1185
REF = 0.6V
REF = 0.6V
REF = 0.6V
REF = 0.6V
OUT1
VIN1
VIN2
VIN3
VIN4
OUT2
Open-drain power-good output (PWRGD)
10-lead MSOP
STATE
MACHINE
CORE
OUT3
APPLICATIONS
Monitor and alarm functions
Power supply sequencing
Telecommunication and data communication equipment
PC/servers
PWRGD
GND
Figure 1.
GENERAL DESCRIPTION
The ADM1185 is an integrated, four-channel, voltage
monitoring and sequencing device. A 2.7 V to 5.5 V power
supply is required on the VCC pin to power the device.
Internal time delays can be used for sequencing the startup of
subsequent power supplies enabled by the outputs. Supplies
falling out of range are also detected and, as a result, appropriate
outputs are disabled.
Four precision comparators monitor four voltage rails.
All comparators have a 0.6 V reference with a worst-case
accuracy of 0.8%. Resistor networks that are external to the
VIN1, VIN2, VIN3, and VIN4 pins set the trip points for
the monitored supply rails.
The ADM1185 has four open-drain outputs. In a typical
configuration, OUT1 to OUT3 are used to enable power
supplies, while PWRGD is a common power-good output
indicating the status of all monitored supplies.
A digital core interprets the status of the comparator outputs.
The ADM1185 is available in a 10-lead mini small outline
package (MSOP).
APPLICATIONS DIAGRAM
3.3V IN
2.5V OUT
1.8V OUT
1.2V OUT
VCC
IN
ADM1185
REGULATOR1
2.5V OUT
VIN1
OUT1
OUT2
OUT3
EN
OUT
GND
VIN2
VIN3
IN
REGULATOR2
1.8V OUT
1.2V OUT
EN
OUT
GND
VIN4
GND
PWRGD
IN
REGULATOR3
EN
OUT
GND
POWER
GOOD
Figure 2.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2007 Analog Devices, Inc. All rights reserved.
ADM1185
TABLE OF CONTENTS
Features .............................................................................................. 1
Pin Configuration and Function Descriptions..............................5
Typical Performance Characteristics ..............................................6
Theory of Operation .........................................................................9
Power-On Sequencing and Monitoring .....................................9
Voltage Monitoring after Power-On........................................ 10
Cascading Multiple Devices...................................................... 12
Outline Dimensions....................................................................... 13
Ordering Guide .......................................................................... 13
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Applications Diagram ...................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 4
ESD Caution.................................................................................. 4
REVISION HISTORY
3/07—Revision 0: Initial Version
Rev. 0 | Page 2 of 16
ADM1185
SPECIFICATIONS
VCC = 2.7 V to 5.5 V, TA = −40°C to +85°C.
Table 1.
Parameter
Min
Typ
Max
Unit Conditions
VCC Pin
Operating Voltage Range, VCC
Supply Current, IVCC
VIN1 to VIN4 (VINx) Pins
Input Current, IVINLEAK
Input Rising Threshold, VTHR
OUT1 to OUT3 (OUTx), PWRGD Pins
Output Low Voltage, VOUTL
2.7
3.3
24
5.5
80
V
μA
−20
+20
nA
V
VVINx = 0.7 V
0.5952 0.6000 0.6048
0.4
0.4
V
V
VCC = 2.7 V, ISINK = 2 mA
VCC = 1 V, ISINK =100 μA
Leakage Current, IALERT
VCC that Guarantees Valid Outputs
−1
1
+1
μA
V
All outputs are guaranteed to be either low or giving
a valid output level from VCC = 1 V
TIMING DELAYS
Delays only applicable to certain operations states;
refer to state diagram (Figure 19) for more details
VIN1 to OUT1 Rising Delay
VIN4 to PWRGD Rising Delay
100
100
190
190
280
280
ms
ms
VCC = 3.3 V, see Figure 7
VCC = 3.3 V, see Figure 7
VIN2 to OUT2, VIN3 to OUT3
Low-to-High Propagation Delay
High-to-Low Propagation Delay, All Inputs
30
30
μs
μs
VCC = 3.3 V, see Figure 9
VCC = 3.3 V, see Figure 10
Rev. 0 | Page 3 of 16
ADM1185
ABSOLUTE MAXIMUM RATINGS
Ambient temperature = 25°C, unless otherwise noted.
Table 3. Thermal Resistance
Package Type
Table 2.
Parameter
θJA
Unit
Rating
10-Lead MSOP
137.5
°C/W
VCC Pin
VINx Pins
−0.3 V to +6 V
−0.3 V to +6 V
−0.3 V to +6 V
−65°C to +125°C
−40°C to +85°C
300°C
OUTx, PWRGD Pins
Storage Temperature Range
Operating Temperature Range
Lead Temperature Soldering (10 sec)
Junction Temperature
ESD CAUTION
150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. 0 | Page 4 of 16
ADM1185
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
GND
VIN1
VIN2
VIN3
VIN4
1
2
3
4
5
10 VCC
9
8
7
6
OUT1
ADM1185
TOP VIEW
(Not to Scale)
OUT2
OUT3
PWRGD
Figure 3.
Table 4. Pin Function Descriptions
Pin No. Mnemonic Description
1
2
GND
VIN1
Chip Ground Pin.
Noninverting Input of Comparator 1. The voltage on this pin is compared with a 0.6 V reference. Can be used to
monitor a voltage rail via a resistor divider. The output of this comparator is monitored by the state machine core.
This input can also be driven by a logic signal to initiate a power-up sequence.
3
4
5
6
VIN2
Noninverting Input of Comparator 2. The voltage on this pin is compared with a 0.6 V reference. Can be used to
monitor a voltage rail via a resistor divider. The output of this comparator is monitored by the state machine core.
Noninverting Input of Comparator 3. The voltage on this pin is compared with a 0.6 V reference. Can be used to
monitor a voltage rail via a resistor divider. The output of this comparator is monitored by the state machine core.
Noninverting Input of Comparator 4. The voltage on this pin is compared with a 0.6 V reference. Can be used to
monitor a voltage rail via a resistor divider. The output of this comparator is monitored by the state machine core.
Active-High, Open-Drain Output. This output is pulled low once VCC = 1 V. When the voltage on each VINx input
exceeds 0.6 V, the state machine moves from STATE4 to STATE5, and PWRGD is asserted. Once in State 5 (the
PWRGD state), this output is driven low if the voltage on VIN1, VIN2, VIN3, or VIN4 falls below 0.6 V.
VIN3
VIN4
PWRGD
7
8
9
OUT3
OUT2
OUT1
Active-High, Open-Drain Output. This output is pulled low once VCC = 1 V. When the voltage on VIN3 exceeds 0.6 V,
the state machine moves from STATE3 to STATE4, and OUT3 is asserted. Once the power-up sequence is complete
and STATE5 (the PWRGD state) is reached, this output is driven low if the voltage on VIN1 falls below 0.6 V.
Active-High, Open-Drain Output. This output is pulled low once VCC = 1 V. When the voltage on VIN2 exceeds 0.6 V,
the state machine moves from STATE2 to STATE3, and OUT2 is asserted. Once the power-up sequence is complete
and STATE5 (the PWRGD state) is reached, this output is driven low if the voltage on VIN1 falls below 0.6 V.
Active-High, Open-Drain Output. This output is pulled low once VCC = 1 V. When the voltage on VIN1 exceeds 0.6 V,
the state machine moves from STATE1 to STATE2, and OUT1 is asserted. A time delay of 190 ms (typical) is included
before the assertion of this pin. Once the power-up sequence is complete and STATE5 (the PWRGD state) is
reached, this output is driven low if the voltage on VIN1 falls below 0.6 V.
10
VCC
Positive Supply Input Pin. The operating supply voltage range is 2.7 V to 5.5 V.
Rev. 0 | Page 5 of 16
ADM1185
TYPICAL PERFORMANCE CHARACTERISTICS
50
45
40
35
30
25
20
15
10
5
280
260
240
220
200
180
160
140
120
100mV OVERDRIVE
VIN4 TO PWRGD DELAY
VIN1 TO OUT1 DELAY
0
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
SUPPLY VOLTAGE (V)
2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.5
VOLTAGE (V)
Figure 4. Supply Current vs. Supply Voltage
Figure 7. VIN1/VIN4 to OUT1/PWRGD Rising Delay vs. Supply Voltage
50
45
40
35
30
25
20
15
10
5
50
VCC = 3.3V, 100mV OVERDRIVE
45
40
35
VCC = 5V
VIN3 TO OUT3 DELAY
VCC = 3.3V
30
25
VIN2 TO OUT2 DELAY
20
VCC = 2.7V
15
10
5
0
0
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90
TEMPERATURE (°C)
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90
TEMPERATURE (°C)
Figure 5. Supply Current vs. Temperature
Figure 8. VIN2/VIN3 to OUT2/OUT3 Rising Delay vs. Temperature
280
260
240
220
200
180
160
140
120
50
100mV OVERDRIVE
VCC = 3.3V, 100mV OVERDRIVE
45
40
35
30
25
20
15
10
5
VIN3 TO OUT3 DELAY
VIN2 TO OUT2 DELAY
VIN4 TO PWRGD DELAY
VIN1 TO OUT1 DELAY
0
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90
TEMPERATURE (°C)
2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.5
VOLTAGE (V)
Figure 6. VIN1/VIN4 to OUT1/PWRGD Rising Delay vs. Temperature
Figure 9. VIN2/VIN3 to OUT2/OUT3 Rising Delay vs. Supply Voltage
Rev. 0 | Page 6 of 16
ADM1185
60
50
40
30
20
10
0
180
160
140
120
100
80
100mV OVERDRIVE
60
40
20
0
2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.5
0
10
20
30
40
50
60
70
80
90
100
VOLTAGE (V)
OVERDRIVE (mV)
Figure 10. VIN1 to OUT1 Falling Delay vs. Supply Voltage (100 mV Overdrive)
Figure 13. Trip Threshold Maximum Transient Duration vs. Input Overdrive
50
200
VCC = 3.3V, 100mV OVERDRIVE
APPLICABLE ONLY TO
CHANNEL 2 AND CHANNEL 3
180
40
30
20
10
0
160
140
120
100
80
60
40
20
0
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90
TEMPERATURE (°C)
0
10
20
30
40
50
60
70
80
90
100
OVERDRIVE (mV)
Figure 11. VINx to Output Falling Delay vs. Temperature
Figure 14. Propagation Delay vs. Input Overdrive
0.610
400
0.608
0.606
0.604
0.602
0.600
0.598
0.596
0.594
0.592
0.590
350
300
250
200
150
100
50
0
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90
TEMPERATURE (°C)
0
2
4
6
8
10 12 14 16 18 20 22 24
OUTPUT SINK CURRENT (mA)
Figure 12. VINx Trip Threshold vs. Temperature
Figure 15. Output Low Voltage vs. Output Sink Current
Rev. 0 | Page 7 of 16
ADM1185
100
90
80
70
60
50
40
30
20
10
0
1mA SINK
100µA SINK
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
SUPPLY VOLTAGE (V)
Figure 16. Output Low Voltage vs. Supply Voltage
Rev. 0 | Page 8 of 16
ADM1185
THEORY OF OPERATION
OUT1 is an open-drain active high output. In this application,
OUT1 is connected to the enable pin of a regulator. Before the
voltage on VIN1 has reached 0.6 V, this output is switched to
ground, disabling Regulator 1. Note that all outputs are driven
to ground as long as there is 1 V on the VCC pin of the ADM1185.
When the main system voltage reaches 2.9 V, VIN1 detects 0.6 V.
This causes OUT1 to assert after a 190 ms (typical) delay. When
this occurs, the open-drain output switches high, and the external
pull-up resistor pulls the voltage on the Regulator 1 enable pin
above its turn-on threshold, turning on the output of Regulator 1.
The operation of the ADM1185 is explained in this section in
the context of the device in a voltage monitoring and sequencing
application (see Figure 18). In this application, the ADM1185
monitors four separate voltage rails, turns on three regulators in
a predefined sequence, and generates a power-good signal to
turn on a controller when all power supplies are up and stable.
POWER-ON SEQUENCING AND MONITORING
The main supply, in this case 3.3 V, powers up the device via the
VCC pin as the voltage rises. A supply voltage of 2.7 V to 5.5 V
is needed to power the device.
The assertion of OUT1 turns on Regulator 1. The 2.5 V output
of this regulator begins to rise. This is detected by input VIN2
(with a similar resistor divider scheme as shown in Figure 18).
When VIN2 detects the 2.5 V rail rising above its UV point, it
asserts output OUT2, which turns on Regulator 2. A capacitor
can be placed on the VIN2 pin to slow the rise of the voltage on
this pin. This effectively sets a time delay between the 2.5 V rail
powering up and the next enabled regulator.
The VIN1 pin monitors the main 3.3 V supply. An external
resistor divider scales this voltage down for monitoring at the
VIN1 pin. The resistor ratio is chosen so that the VIN1 voltage
is 0.6 V when the main voltage rises to the preferred level at start-
up (a voltage below the nominal 3.3 V level). R1 is 4.6 kΩ and
R2 is 1.2 kΩ, so a voltage level of 2.9 V corresponds to 0.6 V on
the noninverting input of the first comparator (see Figure 17).
V
The same scheme is implemented with the other input and
output pins. Every rail that is turned on via an output pin,
OUTx, is monitored via an input pin VIN(x+1).
3.3V
2.9V
The final comparator inside the VIN4 pin detects the final supply
turning on, which is 1.2 V in this case. The output pins, OUT1
to OUT3 are logically AND’ed together to generate a system
power-good signal (PWRGD). There is an internal 190 ms delay
(typical) associated with the assertion of the PWRGD output.
0V
t
4.6kΩ
ADM1185
2.9V SUPPLY
GIVES 0.6V
AT VIN1 PIN
VIN1
TO LOGIC
CORE
1.2kΩ
0.6V
Table 5 is a truth table that steps through the power-on sequence of
the outputs. Any associated internal time delays are also shown.
Figure 17. Setting the Undervoltage Threshold with an
External Resistor Divider
3.3V IN
2.5V OUT
1.8V OUT
1.2V OUT
VCC
IN
ADM1185
REGULATOR1
2.5V OUT
VIN1
OUT1
OUT2
OUT3
EN
OUT
GND
VIN2
VIN3
IN
REGULATOR2
1.8V OUT
1.2V OUT
EN
OUT
GND
VIN4
GND
PWRGD
IN
REGULATOR3
EN
OUT
GND
POWER
GOOD
Figure 18. Voltage Monitoring and Sequencing Application Diagram
Table 5. Truth Table
State State Name
OUT1 OUT2 OUT3 OUT4 Next Event
Next State
1
2
3
4
5
Reset
OUT1 On
OUT1, OUT2 On
OUT1, OUT2, OUT3 On
Power Good
0
1
1
1
1
0
0
1
1
1
0
0
0
1
1
0
0
0
0
1
VIN1 high for 190 ms
OUT1 On
VIN1 and VIN2 high for 30 μs
VIN1 and VIN3 high for 30 μs
All high for 190 ms
OUT1, OUT2 On
OUT1, OUT2, OUT3 On
Power Good
VIN2 , VIN3, or VIN4 low for 30 μs
OUT1, OUT2, OUT3 On
Rev. 0 | Page 9 of 16
ADM1185
VOLTAGE MONITORING AFTER POWER-ON
STATE1 START
VIN1 = OK
Once PWRGD is asserted, the logical core latches into a different
mode of operation. During the initial power-up phase, each
output directly depends on an input (for example, VIN3 asserting
causes OUT3 to assert). When power-up is complete, this
function is redundant.
(DELAY = 190ms TYP)
STATE2 OUT1
ON
Once in the PWRGD state, the following behavior can be observed:
VIN2 = OK
VIN1 = FAULT
•
If the main 3.3 V supply monitored via VIN1 faults in the
power-good state, the PWRGD output is deasserted to
warn the downstream controller. All outputs (OUT1 to
OUT3) are immediately turned off, disabling all locally
generated supplies.
STATE3 OUT1, OUT2
ON
VIN3 = OK
VIN1 = FAULT
•
If a supply monitored by VIN2 to VIN4 fails, the PWRGD
output is deasserted to warn the controller, but the other
outputs are not deasserted.
STATE4 OUT1, OUT2, OUT3
ON
VIN4 = OK
VIN1 = FAULT
(DELAY = 100ms MIN)
Figure 20 and Figure 21 are waveforms that highlight the
behavior of the ADM1185 under various fault situations during
normal operation (that is, in the mode of operation after
PWRGD is asserted).
STATE5 PWRGD
VIN1 = FAULT
VIN2. VIN3. VIN4 = FAULT
Figure 19. Flow Diagram Highlighting the Different Modes of Operation
of the Logical Core
Rev. 0 | Page 10 of 16
ADM1185
V
V
(RISING)
T
T
V
(RISING)
T
VIN1
(FALLING) = 0.6V
VIN1
tPROP
tPROP
OUT1
OUT1
OUT2
tPROP
190ms
190ms
OUT2
OUT3
OUT3
PWRGD
PWRGD
190ms
190ms
NOTES
NOTES
1. THE RISING THRESHOLD ON THE VIN1 TO VIN4 PINS IS SLIGHTLY
HIGHER THAN 0.6V AS THERE IS HYSTERESIS ON THIS PIN.
1. THE RISING THRESHOLD ON THE VIN1 TO VIN4 PINS IS SLIGHTLY
HIGHER THAN 0.6V AS THERE IS HYSTERESIS ON THIS PIN.
Figure 20. Power-Up Waveforms
Figure 21. Waveforms Showing Reaction to a Temporary Low Glitch
on the Main Supply
OUT1
1
OUT2
2
OUT3
3
PWRGD
4
CH1 1.00V CH2 1.00V
CH3 1.00V CH4 1.00V
M50.0ms
CH1
380mV
Figure 22. Plot of OUT1, OUT2, OUT3, and PWRGD Outputs at Startup
in an Application Similar to that Shown in Figure 18
Rev. 0 | Page 11 of 16
ADM1185
CASCADING MULTIPLE DEVICES
Multiple ADM1185 devices can be cascaded in situations where a large number of supplies must be monitored and/or sequenced. There
are numerous configurations for interconnecting devices. The most suitable configuration depends on the application. Figure 23 and
Figure 24 show two methods for cascading multiple ADM1185 devices.
3.3V
3.3V
VCC
REGULATOR1
EN1
ADM1185-A
3.3V
V1
VIN1
VIN2
VIN3
OUT1
V1
V2
V3
REGULATOR2
SUPPLIES
SCALED
DOWN WITH
RESISTOR
DIVIDERS
OUT2
EN2
REGULATOR3
EN3
V2
OUT3
V3
VIN4
GND
PWRGD
3.3V
VCC
REGULATOR4
EN4
ADM1185-B
VIN1
VIN2
VIN3
OUT1
V4
V5
V6
REGULATOR5
V4
V5
V6
SUPPLIES
SCALED
DOWN WITH
RESISTOR
DIVIDERS
OUT2
EN5
REGULATOR6
EN6
OUT3
VIN4
GND
PWRGD
POWER
GOOD
Figure 23. Cascading Multiple ADM1185 Devices, Option 1
3.3V
3.3V
VCC
REGULATOR1
ADM1185-A
3.3V
V1
VIN1
VIN2
VIN3
OUT1
EN1
V1
V2
V3
SUPPLIES
SCALED
DOWN WITH
RESISTOR
DIVIDERS
REGULATOR2
EN2
OUT2
REGULATOR3
V2
OUT3
EN3
3.3V
VIN4
GND
PWRGD
3.3V
VCC
REGULATOR4
EN4
ADM1185-B
VIN1
VIN2
VIN3
OUT1
V4
V5
V6
V3
V4
V5
V6
REGULATOR5
SUPPLIES
SCALED
DOWN WITH
RESISTOR
DIVIDERS
OUT2
EN5
REGULATOR6
EN6
OUT3
VIN4
GND
PWRGD
POWER
GOOD
Figure 24. Cascading Multiple ADM1185 Devices, Option 2
Rev. 0 | Page 12 of 16
ADM1185
OUTLINE DIMENSIONS
3.10
3.00
2.90
10
6
5.15
4.90
4.65
3.10
3.00
2.90
1
5
PIN 1
0.50 BSC
0.95
0.85
0.75
1.10 MAX
0.80
0.60
0.40
8°
0°
0.15
0.05
0.33
0.17
SEATING
PLANE
0.23
0.08
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187-BA
Figure 25. 10-Lead Mini Small Outline Package [MSOP]
(RM-10)
Dimensions shown in millimeters
ORDERING GUIDE
Model
ADM1185ARMZ-11
ADM1185ARMZ-1REEL71
Temperature Range
−40°C to +85°C
−40°C to +85°C
Package Description
Package Option
RM-10
RM-10
Branding
M9W
M9W
10-Lead Mini Small Outline Package [MSOP]
10-Lead Mini Small Outline Package [MSOP]
1 Z = RoHS compliant part.
Rev. 0 | Page 13 of 16
ADM1185
NOTES
Rev. 0 | Page 14 of 16
ADM1185
NOTES
Rev. 0 | Page 15 of 16
ADM1185
NOTES
©2007 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06196-0-3/07(0)
Rev. 0 | Page 16 of 16
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