ADM1186-1ARQZ-REEL [ADI]
Quad Voltage Up and Down Sequencer and Monitor with Programmable Timing; 四路电压上下序和监控，具有可编程定时
| 型号： | ADM1186-1ARQZ-REEL |
| 厂家： | 
ADI |
| 描述： | Quad Voltage Up and Down Sequencer and Monitor with Programmable Timing |
| 文件： | 总28页 (文件大小：446K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Quad Voltage Up and Down Sequencer
and Monitor with Programmable Timing
ADM1186
FEATURES
GENERAL DESCRIPTION
Powered from 2.7 V to 5.5 V on the VCC pin
The ADM1186-1 and ADM1186-2 are integrated, four-channel
Monitors four supplies via 0.8% accurate comparators
Digital core supports up and down supply sequencing
Multiple devices can be cascaded (ADM1186-1)
Four inputs can be programmed to monitor different voltage
levels with resistor dividers
Capacitor programmable supply sequence time delays
and a timeout delay to 5% accuracy at 25°C
Four open-drain enable outputs
voltage monitoring and sequencing devices. A 2.7 V to 5.5 V
power supply is required on the VCC pin for power.
Four precision comparators, VIN1 to VIN4, monitor four
voltage rails. All four comparators share a 0.6 V reference and
have a worst-case accuracy of 0.8%. Resistor networks that are
external to the VIN1, VIN2, VIN3, and VIN4 pins set the
undervoltage (UV) trip points for the monitored supply rails.
The ADM1186-1 and ADM1186-2 have four open-drain enable
outputs, OUT1 to OUT4, that are used to enable power supplies.
An open-drain power-good output, PWRGD, indicates whether
the four VINx inputs are above their UV thresholds.
Open-drain power-good output
Open-drain sequence complete pin and bidirectional
open-drain fault pin (ADM1186-1 only)
APPLICATIONS
DOWN
A state machine monitors the state of the UP and
pins
Monitor and alarm functions
DOWN
on the ADM1186-1 or the UP/
pin on the ADM1186-2
Up and down power supply sequencing
Telecommunication and data communication equipment
PCs, servers, and notebook PCs
to control the supply sequencing direction (see Figure 2). In the
WAIT START state, a rising edge transition on the UP or
DOWN
UP/
transition on the
DONE state triggers a power-down sequence.
pin triggers a power-up sequence. A falling edge
DOWN DOWN
or UP/
pin in the POWER-UP
APPLICATION DIAGRAM
5V
5V
IN
ADP1706
2.5V
1.8V
EN
OUT
5V
5V
IN
ADP2107
EN
OUT
3.3V AUX
3.3V AUX
IN
3.3V AUX
1µF
ADP1821
1.2V
3.3V
EN
OUT
5V
5V
IN
ADP1706
100nF
EN
OUT
3.3V AUX
VCC
OUT1
OUT2
OUT3
OUT4
FAULT
VIN1
VIN2
VIN3
VIN4
UP
SEQUENCE CONTROL
DOWN
ADM1186-1
DLY_EN_OUT1
DLY_EN_OUT2
DLY_EN_OUT3
DLY_EN_OUT4
BLANK_DLY
2.5V AUX
3.3V AUX
PWRGD
SEQ_DONE
GND
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2008 Analog Devices, Inc. All rights reserved.
ADM1186
TABLE OF CONTENTS
Features .............................................................................................. 1
UVLO Behavior.......................................................................... 13
Power-Up Sequencing and Monitoring................................... 13
Operation in POWER-UP DONE State.................................. 14
Power-Down Sequencing and Monitoring............................. 14
Input Glitch Filtering................................................................. 14
Fault Conditions and Fault Handling...................................... 14
Defining Time Delays................................................................ 15
Sequence Control Using a Supply Rail.................................... 16
Cascading Multiple Devices.......................................................... 23
Outline Dimensions....................................................................... 26
Ordering Guide .......................................................................... 26
Applications....................................................................................... 1
General Description......................................................................... 1
Application Diagram........................................................................ 1
Revision History ............................................................................... 2
Specifications..................................................................................... 4
Absolute Maximum Ratings............................................................ 6
ESD Caution.................................................................................. 6
Pin Configurations and Function Descriptions ........................... 7
Typical Performance Characteristics ............................................. 9
Theory of Operation ...................................................................... 13
REVISION HISTORY
5/08—Revision 0: Initial Version
Rev. 0 | Page 2 of 28
ADM1186
During a power-up sequence, the state machine enables each
power supply in turn. The supply output voltage is monitored to
determine whether it rises above the UV threshold level within
a user defined duration called the blanking time. If a supply
rises above the UV threshold, the next enable output in the
sequence is turned on. In addition to the blanking time, the
user can also define a sequence time delay before each enable
output is turned on.
During sequencing and when powered up, the state machine
continuously monitors the part for any fault conditions. Faults
include a UV condition on any of the inputs or an unexpected
control input. Any fault causes the state machine to enter a fault
handler, which immediately turns off all enable outputs and
then ensures that the device is ready to start a new power-up
sequence.
FAULT
The ADM1186-1 has a bidirectional pin,
fault handling when using multiple devices. If an ADM1186-1
FAULT
, that facilitates
The ADM1186-1 provides an open-drain pin, SEQ_DONE,
that is asserted high to provide an indication that a power-up
sequence is complete. The SEQ_DONE pin allows multiple
cascaded ADM1186-1 devices to perform controlled power-up
and power-down sequences.
experiences a fault condition, the
pin is driven low,
causing other connected ADM1186-1 devices to enter their own
fault handling states.
The ADM1186-1 is available in a 20-lead QSOP package, and
the ADM1186-2 is available in a 16-lead QSOP package.
During a power-down sequence, the enable outputs turn off
in reverse order. The same sequence time delays used during
the power-up sequence are also used during the power-down
sequence as each enable output is turned off; no blanking time
is used during a power-down sequence. At the end of a power-
down sequence, the SEQ_DONE pin is brought low.
SEQUENCE UP
TRIGGER
SEQUENCE
SUPPLY 1 ON
POWER-DOWN
WAIT START
DONE
SEQUENCE
SUPPLY 1 OFF
SEQUENCE
SUPPLY 2 ON
FAULT HANDLER
SEQUENCE
SUPPLY 2 OFF
SEQUENCE
SUPPLY 3 ON
FAULT CONDITION OCCURS
IN ANY STATE
SEQUENCE
SEQUENCE
SUPPLY 3 OFF
SUPPLY 4 ON
SEQUENCE DOWN TRIGGER
SEQUENCE
SUPPLY 4 OFF
POWER-UP DONE
Figure 2. Simplified State Machine Diagram
Rev. 0 | Page 3 of 28
ADM1186
SPECIFICATIONS
VVCC = 2.7 V to 5.5 V, TA = −40°C to +85°C; typical values at TA = 25°C, unless otherwise noted.
Table 1.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
VCC PIN
Operating Voltage Range, VVCC
Undervoltage Lockout, VUVLO
Undervoltage Lockout Hysteresis
Supply Current, IVCC
VIN1 TO VIN4 (VINx) PINS
Input Current
2.7
3.3
2.46
50
5.5
V
V
mV
μA
VVCC falling
146
210
Steady state; sequence complete
−25
−100
0.5952
+25
+100
0.6048
nA
nA
V
VVINx = 0 V to 1 V
VVINx = 0 V to 5.5 V; VVINx can be greater than VVCC
Input Threshold1
0.6000
Input Glitch Immunity
Positive Glitch Duration
Negative Glitch Duration
UP, DOWN, AND UP/DOWN PINS
Input Current
19.9
2.75
26.6
4.7
33.2
6.6
μs
μs
50 mV input overdrive
50 mV input overdrive
−100
+100
nA
VUP/DOWN = 0 V to 5.5 V; VUP/DOWN can be greater than VVCC
Input Threshold1
Input Glitch Immunity
1.372
3.3
2.7
1.4
6.8
4.9
1.428
9.7
7.9
V
μs
μs
100 mV input overdrive
1 V input overdrive
DLY_EN_OUTx AND BLANK_DLY PINS
Time Delay Accuracy
5
9
%
External capacitor values of 10 nF to 2.2 ꢀF; excludes
external capacitor tolerance
Time Delay Charge Current
Time Delay Threshold
Time Delay Discharge Resistor
OUT1 TO OUT4 (OUTx) PINS
Output Low Voltage, VOUTL
Leakage Current
14
1.4
450
μA
V
Ω
0.4
1
V
μA
V
VVCC = 2.7 V, ISINK = 2 mA
OUTx = 5.5 V
Output is guaranteed to be either low (VOUTL = 0.4 V)
VVCC That Guarantees Valid Outputs
1
1
or giving a valid output level from VVCC = 1 V, ISINK
=
30 μA or VVCC = 1.1 V, ISINK = 100 μA
PWRGD PIN
Output Low Voltage, VPWRGDL
Leakage Current
0.4
1
V
μA
V
VVCC = 2.7 V, ISINK = 2 mA
PWRGD = 5.5 V
Output is guaranteed to be either low (VPWRGDL = 0.4 V)
VVCC That Guarantees Valid Outputs
or giving a valid output level from VVCC = 1 V, ISINK
30 μA or VVCC = 1.1 V, ISINK = 100 μA
=
FAULT PIN
Input Threshold1
Input Glitch Immunity
Output Low Voltage, VFAULTL
1.372
3.1
1.4
5.6
1.428
8.1
0.4
V
μs
V
1 V input overdrive
VVCC = 2.7 V, ISINK = 2 mA
Leakage Current
1
μA
V
FAULT = 5.5 V
VVCC That Guarantees Valid Outputs
1
Output is guaranteed to be either low (VFAULTL = 0.4 V)
or giving a valid output level from VVCC = 1 V, ISINK
30 μA or VVCC = 1.1 V, ISINK = 100 μA
=
Rev. 0 | Page 4 of 28
ADM1186
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
SEQ_DONE PIN
Output Low Voltage, VSEQ_DONEL
Leakage Current
VVCC That Guarantees Valid Outputs
0.4
1
V
μA
V
VVCC = 2.7 V, ISINK = 2 mA
SEQ_DONE = 5.5 V
Output is guaranteed to be either low (VSEQ_DONEL = 0.4 V)
or giving a valid output level from VVCC = 1 V, ISINK = 30 μA
or VVCC = 1.1 V, ISINK = 100 μA
1
RESPONSE TIMING
Includes input glitch filter and all other internal
delays
VINx to PWRGD
VINx Going Low to High
VINx Going High to Low
VINx to FAULT, OUTx Low
21.9
5.8
28.8
7.3
35.2
8.9
μs
μs
50 mV input overdrive
50 mV input overdrive
VINx Going High to Low (UV Fault)
UP, DOWN, and UP/DOWN to FAULT,
OUTx Low, tUDOUT
6.1
5.5
7.5
8.6
9.2
12.1
μs
μs
50 mV input overdrive
100 mV input overdrive
5.8
35
7.7
44
10.5
10
μs
μs
μs
1 V input overdrive
1 V input overdrive
UP, UP/DOWN held low
External FAULT to OUTx Low
Fault Hold Time
54
1 Input comparators do not include hysteresis on their inputs. The comparator output passes through a digital glitch filter to remove short transients from the input
signal that would otherwise drive the state machine.
Rev. 0 | Page 5 of 28
ADM1186
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 2.
Parameter
Table 3. Thermal Resistance
Package Type
Rating
θJA
Unit
°C/W
°C/W
VCC Pin
VINx Pins
UP, DOWN, UP/DOWN Pins
DLY_EN_OUTx, BLANK_DLY Pins
PWRGD, SEQ_DONE, OUTx Pins
FAULT Pin
−0.3 V to +6 V
−0.3 V to +6 V
−0.3 V to +6 V
−0.3 V to VCC + 0.3 V
−0.3 V to +6 V
−0.3 V to +6 V
−40°C to +85°C
−65°C to +150°C
16-Lead QSOP
20-Lead QSOP
149.97
125.80
ESD CAUTION
Operating Temperature Range
Storage Temperature Range
Lead Temperature Convection Reflow
Peak Temperature
260°C
Time at Peak Temperature
Junction Temperature
≤30 sec
125°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. 0 | Page 6 of 28
ADM1186
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
1
20
19
18
17
16
15
14
13
12
11
GND
VCC
2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
GND
VIN1
VIN1
OUT1
VCC
3
VIN2
OUT2
OUT1
ADM1186-1
TOP VIEW
(Not to Scale)
ADM1186-2
TOP VIEW
(Not to Scale)
4
VIN3
OUT3
VIN2
OUT2
5
VIN4
OUT4
VIN3
OUT3
6
UP
PWRGD
SEQ_DONE
BLANK_DLY
DLY_EN_OUT4
DLY_EN_OUT3
VIN4
OUT4
7
UP/DOWN
DLY_EN_OUT2
DLY_EN_OUT3
PWRGD
BLANK_DLY
DOWN
8
FAULT
9
DLY_EN_OUT1
DLY_EN_OUT2
DLY_EN_OUT4
10
Figure 3. ADM1186-1 Pin Configuration
Figure 4. ADM1186-2 Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
Mnemonic
GND
VIN1
Description
ADM1186-1 ADM1186-2
1
2
1
2
Chip Ground Pin.
Noninverting Comparator Input. The voltage on this pin is compared with a 0.6 V
reference. Can be used to monitor a voltage rail via a resistor divider. The output of this
comparator is monitored by the state machine.
3
4
5
3
4
5
VIN2
VIN3
VIN4
Noninverting Comparator Input. The voltage on this pin is compared with a 0.6 V
reference. Can be used to monitor a voltage rail via a resistor divider. The output of this
comparator is monitored by the state machine.
Noninverting Comparator Input. The voltage on this pin is compared with a 0.6 V
reference. Can be used to monitor a voltage rail via a resistor divider. The output of this
comparator is monitored by the state machine.
Noninverting Comparator Input. The voltage on this pin is compared with a 0.6 V
reference. Can be used to monitor a voltage rail via a resistor divider. The output of this
comparator is monitored by the state machine.
6
7
UP
Noninverting Comparator Input. A rising edge on this pin initiates a power-up sequence
when the ADM1186-1 is in the WAIT START state.
Noninverting Comparator Input. A falling edge on this pin initiates a power-down
sequence when the ADM1186-1 is in the POWER-UP DONE state.
Noninverting Comparator Input. A rising edge on this pin initiates a power-up sequence
when the ADM1186-2 is in the WAIT START state. A falling edge on this pin initiates a
power-down sequence when the ADM1186-2 is in the POWER-UP DONE state.
DOWN
UP/DOWN
6
8
FAULT
Active Low, Bidirectional, Open-Drain Pin. When an internal fault is detected by the
ADM1186-1 state machine, this pin is asserted low and the SET FAULT state is entered.
An external device pulling this pin low also causes the ADM1186-1 to enter the SET
FAULT state.
9
DLY_EN_OUT1
DLY_EN_OUT2
DLY_EN_OUT3
Timing Input. The capacitor connected to this input sets the time delay between the UP
input initiating a power-up sequence and OUT1 being asserted high. During a power-
down sequence, this input sets the time delay between OUT1 being asserted low and
SEQ_DONE being asserted low.
Timing Input. The capacitor connected to this input sets the time delay between VIN1
coming into compliance and OUT2 being asserted high during a power-up sequence.
During a power-down sequence, this input sets the time delay between OUT2 being
asserted low and OUT1 being asserted low.
Timing Input. The capacitor connected to this input sets the time delay between VIN2
coming into compliance and OUT3 being asserted high during a power-up sequence.
During a power-down sequence, this input sets the time delay between OUT3 being
asserted low and OUT2 being asserted low.
10
11
7
8
Rev. 0 | Page 7 of 28
ADM1186
Pin No.
ADM1186-1 ADM1186-2
Mnemonic
Description
12
9
DLY_EN_OUT4
Timing Input. The capacitor connected to this input sets the time delay between VIN3
coming into compliance and OUT4 being asserted high during a power-up sequence.
During a power-down sequence, this input sets the time delay between OUT4 being
asserted low and OUT3 being asserted low.
13
14
10
BLANK_DLY
SEQ_DONE
Timing Input. The capacitor connected to this input sets the blanking time. This is the
time allowed between OUTx being asserted and VINx coming into compliance; otherwise,
the SET FAULT state is entered.
Active High, Open-Drain Output. This output is pulled low when VCC = 1 V. When the
power-up sequence is complete, SEQ_DONE is asserted high. During a power-down
sequence, the pin remains asserted until the time delay set by DLY_EN_OUT1 has
elapsed. When a fault occurs, this pin is asserted low.
15
16
17
18
19
11
12
13
14
15
PWRGD
OUT4
OUT3
OUT2
OUT1
Active High, Open-Drain Output. This output is pulled low when VCC = 1 V. The output
state of this pin is a logical AND function of the UV threshold state of the VINx pins. When
the voltage on all VINx inputs exceeds 0.6 V, PWRGD is asserted. This output is driven low
if the voltage on any VINx pin is below 0.6 V.
Active High, Open-Drain Output. This output is pulled low when VCC = 1 V. During a
power-up sequence, this output is asserted high after the time delay set by the capacitor
on DLY_EN_OUT4 has elapsed. The output is asserted low immediately after a power-
down sequence has been initiated.
Active High, Open-Drain Output. This output is pulled low when VCC = 1 V. During a
power-up sequence, this output is asserted high after the time delay set by the capacitor
on DLY_EN_OUT3 has elapsed. During a power-down sequence, the output is asserted
low after the time delay set by the capacitor on DLY_EN_OUT4 has elapsed.
Active High, Open-Drain Output. This output is pulled low when VCC = 1 V. During a
power-up sequence, this output is asserted high after the time delay set by the capacitor
on DLY_EN_OUT2 has elapsed. During a power-down sequence, the output is asserted
low after the time delay set by the capacitor on DLY_EN_OUT3 has elapsed.
Active High, Open-Drain Output. This output is pulled low when VCC = 1 V. During a
power-up sequence, this output is asserted high after the time delay set by the capacitor
on DLY_EN_OUT1 has elapsed (ADM1186-1) or immediately after a rising edge on
UP/DOWN (ADM1186-2). During a power-down sequence, the output is asserted low
after the time delay set by the capacitor on DLY_EN_OUT2 has elapsed.
20
16
VCC
Positive Supply Input Pin. The operating supply voltage range is 2.7 V to 5.5 V.
Rev. 0 | Page 8 of 28
ADM1186
TYPICAL PERFORMANCE CHARACTERISTICS
160
38
36
140
120
100
80
34
32
30
28
V
= 3.3V
CC
60
40
20
0
26
24
22
20
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
SUPPLY VOLTAGE (V)
0
50
100
OVERDRIVE (mV)
150
200
Figure 5. Supply Current vs. Supply Voltage
Figure 8. VINx Input Positive Glitch Immunity vs. Input Overdrive
150
18
16
14
12
10
8
V
= 5.5V
CC
145
140
135
V
V
= 3.3V
= 2.7V
CC
CC
130
125
120
6
V
= 3.3V
CC
4
2
0
–40
–20
0
20
40
60
80
0
50
100
OVERDRIVE (mV)
150
200
TEMPERATURE (°C)
Figure 6. Supply Current vs. Temperature
Figure 9. VINx Input Negative Glitch Immunity vs. Input Overdrive
605
604
603
602
601
600
599
598
597
596
595
31.0
30.5
30.0
29.5
V = 3.3V
CC
V
= 3.3V
CC
29.0
28.5
28.0
27.5
27.0
26.5
26.0
–40
–20
0
20
40
60
80
–40
–20
0
20
40
60
80
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 7. VINx Input Threshold vs. Temperature
Figure 10. VINx Input Positive Glitch Immunity vs. Temperature
Rev. 0 | Page 9 of 28
ADM1186
10.0
6.0
5.8
5.6
5.4
5.2
5.0
9.5
9.0
8.5
8.0
7.5
7.0
V
= 3.3V
CC
4.8
4.6
4.4
4.2
V
= 3.3V
CC
6.5
6.0
5.5
5.0
4.0
–40
–20
0
20
40
60
80
–40
–20
0
20
40
60
80
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 11. VINx Input Negative Glitch Immunity vs. Temperature
DOWN
DOWN
, and UP/ Input Glitch Immunity vs. Temperature
Figure 14. UP,
1.43
1.42
1.41
10.0
9.5
9.0
8.5
8.0
7.5
7.0
6.5
6.0
5.5
V
= 3.3V
CC
1.40
1.39
1.38
1.37
V
= 3.3V
CC
5.0
0
–40
–20
0
20
40
60
80
200
400
600
800
1000
TEMPERATURE (°C)
OVERDRIVE (mV)
DOWN
DOWN FAULT
, and Time Delay Trip Threshold
FAULT
Input Glitch Immunity vs. Input Overdrive
Figure 12. UP,
, UP/
,
Figure 15.
vs. Temperature
10.0
9.5
9.0
8.5
8.0
7.5
7.0
6.5
6.0
5.5
7.0
6.5
6.0
5.5
5.0
V
= 3.3V
CC
V
= 3.3V
CC
5.0
0
–40
–20
0
20
40
60
80
50
100
OVERDRIVE (mV)
150
200
TEMPERATURE (°C)
DOWN
DOWN
Input Glitch Immunity
Figure 13. UP,
, and UP/
vs. Input Overdrive
FAULT
Figure 16.
Input Glitch Immunity vs. Temperature
Rev. 0 | Page 10 of 28
ADM1186
400
15.0
14.8
14.6
14.4
14.2
14.0
13.8
13.6
13.4
13.2
13.0
350
300
250
200
V
= 5.5V
CC
V
= 3.3V
CC
150
100
50
V
= 2.7V
CC
1mA
100µA
1.5
0
1.0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
–40
–20
0
20
40
60
10k
25
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
Figure 17. Time Delay Charge Current vs. Temperature
Figure 20. Output Low Voltage vs. Supply Voltage
1k
100
10
9.0
8.5
8.0
7.5
7.0
6.5
6.0
5.5
5.0
1
10
2.7
3.2
3.7
4.2
4.7
5.2
100
1k
SUPPLY VOLTAGE (V)
CAPACITOR (nF)
Figure 18. Time Delay vs. Capacitor Value
FAULT
, OUTx Low Response Time vs. Supply Voltage
Figure 21. VINx to
600
500
400
300
9.0
8.5
8.0
V
= 2.7V
CC
7.5
7.0
6.5
6.0
5.5
5.0
V
= 3.3V
CC
200
100
0
V
= 5.5V
CC
0
5
10
15
20
–40
–20
0
20
40
60
80
OUTPUT SINK CURRENT (mA)
TEMPERATURE (°C)
Figure 19. Output Low Voltage vs. Output Sink Current
FAULT
, OUTx Low Response Time vs. Temperature
Figure 22. VINx to
Rev. 0 | Page 11 of 28
ADM1186
30
10.0
9.5
9.0
8.5
8.0
7.5
7.0
6.5
6.0
25
20
15
10
V
= 3.3V
CC
5
0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
50
100
OVERDRIVE (mV)
150
200
SUPPLY VOLTAGE (V)
FAULT
, OUTx Low Response Time vs. Input Overdrive
DOWN
DOWN FAULT
, UP/ to , OUTx Low Response Time
vs. Supply Voltage
Figure 23. VINx to
Figure 24. UP,
Rev. 0 | Page 12 of 28
ADM1186
THEORY OF OPERATION
The operation of the ADM1186 is described in the following
sections. Where necessary, differences between the ADM1186-1
and the ADM1186-2 are noted. Figure 28 is a detailed functional
block diagram of the ADM1186-1, and Figure 30 is a detailed
functional block diagram of the ADM1186-2.
After the fault hold time elapses, the state machine moves to the
DOWN
CLEAR FAULT state. If the UP (ADM1186-1) or UP/
(ADM1186-2) pin is low, the state machine can exit the CLEAR
FAULT state. This change is indicated on the ADM1186-1 by
FAULT
the
pin being asserted high. For the ADM1186-2, there
is no external indication that the part is ready to perform
sequencing, so 0.5 ms should be allowed after VCC comes up
before attempting to start a power-up sequence.
The operation of the ADM1186 is described in the context of a
typical voltage monitoring and sequencing application, as shown
in Figure 1. This example uses the ADM1186-1, because it is
essentially a superset of the functionality of the ADM1186-2. In
the example application, the ADM1186-1 turns on four regulators,
monitors four separate voltage rails, and generates a power-good
signal to turn on a microcontroller when all power supplies are
on and above their UV threshold level. Figure 34 shows a typical
ADM1186-2 voltage sequencing and monitoring application.
POWER-UP SEQUENCING AND MONITORING
In the example shown in Figure 1, the main supply of 3.3 V
powers up the device via the VCC pin. The state machine remains
in the WAIT START state until either a rising edge on the UP
pin initiates a power-up sequence, or a fault condition occurs.
DOWN
The ADM1186-2 requires a rising edge on the UP/
to start a power-up sequence.
pin
UVLO BEHAVIOR
The ADM1186 is designed to ensure that the outputs are always
in a known state for a VCC supply voltage of 1 V or greater; if the
If a rising edge on the UP pin is detected, the state machine
moves to the DELAY 1 state. The ADM1186-2 does not have a
DLY_EN_OUT1 pin, so it omits the DELAY 1 state. Figure 29
shows the ADM1186-1 state machine in detail; Figure 31 shows
the ADM1186-2 state machine. The waveforms for a typical
power-up and power-down sequence when no faults occur are
shown in Figure 32 (ADM1186-1) and Figure 33 (ADM1186-2).
VCC supply voltage is below 1 V, the state of the outputs is not
guaranteed. Figure 25 shows the behavior of the outputs over
the full VCC supply range.
V
CC
5.5V
In the DELAY 1 state, a time delay, set by the capacitor
connected to the DLY_EN_OUT1 pin, is allowed to elapse.
Then, in the ENABLE OUT1 state, the OUT1 pin is asserted
high. OUT1 is an open-drain, active high output, and in this
application it enables the output of a 2.5 V regulator.
UNDER STATE
MACHINE CONTROL
2.7V
V
UVLO
During the ENABLE OUT1 state, the VIN1 pin monitors the
2.5 V supply after a blanking delay, set by the capacitor on the
BLANK_DLY pin. The blanking delay, which is the same for all
supplies, is set to allow the slowest rising supply sufficient time
to switch on.
ALL OUTPUTS
LOW
UVLO
ACTIVE
1V
0V
OUTPUTS
NOT GUARANTEED
An external resistor divider scales the supply voltage down for
monitoring at the VIN1 pin (see Figure 26). The resistor ratio is
selected so that the VIN1 voltage is 0.6 V when the supply voltage
rises to the UV level at start-up (a voltage below the nominal 2.5 V
level). In Figure 26, R1 is 7.4 kΩ and R2 is 2.5 kΩ, so a voltage
level of 2.375 V corresponds to 0.6 V on the noninverting input
of the first comparator.
Figure 25. ADM1186 Output Behavior over VCC Supply
As the VCC supply begins to rise, an undervoltage lockout (UVLO)
circuit becomes active and begins to pull the outputs of the
ADM1186 low. The outputs are not guaranteed to be low until
the VCC supply has reached 1 V. State machine operation is also
disabled, so it is not possible to initiate a power-up sequence.
V
2.5V
This behavior ensures that enable pins on dc-to-dc converters
or point-of-load (POL) devices connected to the OUTx pins are
held low as the supplies are rising. This prevents the dc-to-dc
converters or the POLs from switching on briefly and then
switching off as the supply rails stabilize.
2.375V
t
R1
7.4kΩ
0V
2.375V SUPPLY
ADM1186
VIN1
GIVES 0.6V
AT VIN1 PIN
TO LOGIC
CORE
R2
2.5kΩ
When VCC rises above VUVLO and the internal reference is stable,
the UVLO circuit enables the state machine. The state machine
takes control of the outputs and begins operation from the SET
FAULT state.
0.6V
Figure 26. Setting the Undervoltage Threshold
with an External Resistor Divider
Rev. 0 | Page 13 of 28
ADM1186
If the output of the 2.5 V regulator meets the UV level when the
blanking time elapses, the state machine continues the power-up
sequence, moving into the DELAY 2 state. A time delay, set by
the capacitor connected to the DLY_EN_OUT2 pin, elapses
before turning on the next enable output, OUT2, in the
ENABLE OUT2 state.
This sequence of steps is repeated until all four regulators
are switched off and the device is in the WAIT START state.
Because the ADM1186-2 does not have a DLY_EN_OUT1 pin,
there is no delay between the OUT1 pin being brought low and
the state machine returning to the WAIT START state. When
the device is in the WAIT START state, the SEQ_DONE pin is
brought low.
If the 1.8 V supply does not rise to the UV level before the
blanking time elapses, sequencing immediately stops and the
state machine enters the SET FAULT state.
During a power-down sequence, the state machine monitors the
supplies that are still on. If a supply drops below its UV threshold
before it is turned off, the power-down sequence immediately
stops and the state machine enters the SET FAULT state.
The same scheme is implemented with the other output and
input pins. Every supply turned on via an output pin, OUTx, is
monitored via an input pin, VINx, to check that the supply has
risen above the UV level within the blanking time before the
state machine moves on to the next supply.
DOWN
A rising edge on the UP or UP/
pin during a power-
down sequence generates a fault.
The PWRGD pin is asserted low, independently of the state
machine power-down sequence, when one or more of the
VINx pins drops below 0.6 V.
When a supply is on and operating correctly, the ADM1186
continues to monitor it for the duration of the power-up
sequence. If any supply drops below its UV threshold level
during a power-up sequence, sequencing stops and the state
machine enters the SET FAULT state.
INPUT GLITCH FILTERING
DOWN
and the VINx and UP/
FAULT
inputs on the ADM1186-1
inputs on the ADM1186-2 use a
The VINx, UP,
, and
DOWN
When the state machine is in the WAIT START state, or at any
time-based glitch filter to prevent false triggering. The glitch
filter avoids the need to use some of the operating supply range
to provide hysteresis on an input. This helps to maximize the
available operating supply range for a system, which is especially
important in systems where low supply voltages are being used.
DOWN
time during a power-up sequence, a falling edge on the
DOWN
pin (ADM1186-1) or the UP/
a fault.
pin (ADM1186-2) generates
The PWRGD pin is asserted high, independently of the state
machine, when all four VINx pins are above their UV threshold.
The state machine in the ADM1186-1 indicates that the power-
up sequence is complete by asserting the SEQ_DONE pin high.
The VINx inputs use a positive glitch filter that is approximately
five times longer than the negative glitch filter. This provides
additional glitch immunity during the power-up sequence as a
supply is rising, but still allows for a quick response in the event
of an undervoltage event on an input.
OPERATION IN POWER-UP DONE STATE
When the power-up sequence is complete, the state machine
remains in the POWER-UP DONE state until one of the
following events occurs:
FAULT CONDITIONS AND FAULT HANDLING
During supply sequencing and operation in the POWER-UP
DONE state, the ADM1186 continuously monitors the VINx,
DOWN
(ADM1186-1) or
(ADM1186-2) pin, initiating a power-down
•
A falling edge occurs on the
DOWN
DOWN
DOWN
UP/
UP,
FAULT
, and UP/
pins for fault conditions. The
sequence.
pin on the ADM1186-1 is monitored to detect external
•
•
•
An undervoltage condition occurs on one or more of VIN1
to VIN4, generating a fault.
A rising edge occurs on the UP pin, generating a fault
(ADM1186-1 only).
faults generated by other devices, which is important during
cascade operation.
The following faults are internally generated:
•
A supply fails to reach the UV threshold within the time
defined by the BLANK_DLY capacitor during a power-up
sequence.
FAULT
An external device brings the
fault (ADM1186-1 only).
pin low, causing a
POWER-DOWN SEQUENCING AND MONITORING
•
•
•
•
A UV condition occurs on VINx after the blanking time
has elapsed during a power-up sequence.
A UV condition occurs on VINx before the supply is
disabled during a power-down sequence.
When the ADM1186 is in the POWER-UP DONE state, a
DOWN
DOWN
falling edge on the
or UP/
pin initiates a
power-down sequence (see Figure 29 or Figure 31).
DOWN
DOWN
A falling edge occurs on the
during a power-up sequence or in the WAIT START state.
DOWN
or UP/
pin
The state machine moves to the DISABLE OUT4 state, bringing
the OUT4 pin low and switching off the 3.3 V regulator. A time
delay, set by the capacitor on the DLY_EN_OUT4 pin, elapses
before the state machine moves to the DISABLE OUT3 state.
A rising edge occurs on the UP or UP/
pin during a
power-down sequence or in the POWER-UP DONE state.
Rev. 0 | Page 14 of 28
ADM1186
The action taken by the ADM1186 state machine is the same
for an internal or external fault. The state machine enters the
The blanking time is controlled by the capacitor on the
BLANK_DLY pin. This capacitor sets the time allowed between
an enable output being asserted, turning on a supply, and the
output of the supply rising above its defined UV threshold.
FAULT
SET FAULT state, asserts the SEQ_DONE and
pins low
(ADM1186-1 only), and asserts all four OUTx enable pins low.
A constant current source is connected to a capacitor through a
switch that is under the control of the state machine. This current
source charges a capacitor until the threshold voltage is reached.
For all capacitors, the duration of the time delay is defined by
the following formula:
The ADM1186 remains in the SET FAULT state for the fault
hold time before moving into the CLEAR FAULT state. If the
DOWN
UP or UP/
pin is low for a time of t ≥ tUDOUT before the
state machine enters the CLEAR FAULT state, the state machine
can move immediately into the WAIT ALL OK state.
t
DELAY = CDELAY × 0.1
where:
DELAY is the time delay in seconds.
DELAY is the capacitor value in microfarads (μF).
The length of time from entering the SET FAULT state to
DOWN
reaching the WAIT ALL OK state, with the UP or UP/
pin held low, is the fault hold time. The fault hold time is the
FAULT
t
C
minimum amount of time that the
pin is held low. If the
pin is high when the state machine enters
DOWN
UP or UP/
For capacitor values from 10 nF to 2.2 ꢀF, the time delay is in
the range of 1 ms to 220 ms. If a capacitor is not connected to
a timing pin, the time delay is minimal, in the order of several
microseconds.
FAULT
the CLEAR FAULT state, the time that the
low is extended.
pin is held
When the ADM1186-1 is in the CLEAR FAULT state and the
UP pin is low, the WAIT ALL OK state is entered and the
When a capacitor is not being charged by the current source,
it is connected via a resistor to ground. Each capacitor has a
dedicated resistor with a typical value of 450 ꢁ. To ensure
accurate time delays, time must be allowed for a capacitor to
discharge after it has been used. Typically, allowing five RC time
constants is sufficient for the capacitor to discharge to less than
1% of the threshold voltage.
FAULT
FAULT
pin is deasserted. If an external device is driving the
pin low, the state machine remains in the WAIT ALL
pin returns high. The state machine
then transitions into the WAIT START state, ready for the next
power-up sequence.
FAULT
OK state until the
DEFINING TIME DELAYS
If the capacitors are not sufficiently discharged after use, the
time delays will be smaller than expected. This can happen if
very small capacitor values are used or if a power-up or power-
down sequence is performed immediately after another
sequence has been completed. Examples of when this behavior
can occur include, but are not limited to, the following:
The ADM1186 allows the user to define sequence and blanking
time delays using capacitors. The ADM1186-1 has four
DLY_EN_OUTx pins, and the ADM1186-2 has three
DLY_EN_OUTx pins. Capacitors connected to these pins
control the time delay between supplies turning on or off
during the power-up and power-down sequences. Both devices
provide one pin (BLANK_DLY) to set the blanking time delay.
•
A power-down sequence is initiated immediately after
entering the POWER-UP DONE state.
The ADM1186-1 has a pin called DLY_EN_OUT1 that the
ADM1186-2 does not have. The capacitor on this pin sets the
time delay used before enabling OUT1 during a power-up
sequence, as well as the time delay between disabling OUT1 and
returning to the WAIT START state during a power-down
sequence. Although this time delay is not essential when a
single ADM1186-1 device is used, the time delay is essential
when multiple devices are cascaded (see the Cascading Multiple
Devices section).
•
A fault occurs in the ENABLE OUT1 state when the
DLY_EN_OUT1 capacitor is charged and a power-up
sequence is started very quickly after the fault has been
handled.
•
The DLY_EN_OUTx time delay is very short and is insuffi-
cient to allow the BLANK_DLY capacitor to fully discharge.
To achieve the best timing accuracy over the operational
temperature range, the choice of capacitor is critical. Capacitors
are typically specified with a value tolerance of 5%, 10%, or
20%, but in addition to the value tolerance, there is also a
variation in capacitance over temperature.
When ADM1186-1 devices are used in cascade, the capacitor
on the DLY_EN_OUT1 pin of Device N + 1 sets the sequence
time delay between the last supply of Device N and the first
supply of Device N + 1 being turned on and off.
Where high accuracy timing is important, the use of capacitors
that use a C0G, sometimes called NPO, dielectric results in a
capacitance variation of only 0.3% over the full temperature
range. This capacitance variation contrasts with typical varia-
tions of 15% for X5R and X7R dielectrics and 22% for X7S
capacitor dielectrics.
During the power-up sequence, the capacitors connected to the
DLY_EN_OUTx pins set the time from the end of the blanking
period to the next enable output being asserted high. During
the power-down sequence, the capacitors set the time between
consecutive enable outputs being asserted low.
Rev. 0 | Page 15 of 28
ADM1186
SEQUENCE CONTROL USING A SUPPLY RAIL
R2
R1+ R2
⎛
⎜
⎝
⎞
⎟
⎠
VSHYS
=
(
VH −VL ×
)
DOWN
The UP and
DOWN
inputs on the ADM1186-1 and the
UP/
input on the ADM1186-2 are used to initiate
In the example application shown in Figure 27, the following
values could be used:
power-up and power-down sequences. These inputs are
designed for use with digital or analog signals, such as power
supply rails. Using a power supply rail to control the up and
down sequencing allows the ADM1186 to perform sequencing
and monitoring functions for five supply rails.
RP = 10 kꢁ
VP = 5 V
VIN = 3.3 V
When using a supply rail to control an ADM1186-1 (with
DOWN
The values of the R1 and R2 resistors determine the midpoint
of the hysteresis, VMID, about which VH and VL set the levels at
which power-up and power-down sequences are initiated. For a
3.3 V supply, a threshold just below 3 V could be used, making
R1 = 11 kꢁ and R2 = 10 kꢁ and giving a midpoint of 2.94 V.
the UP and
pins connected) or an ADM1186-2,
some hysteresis is required. The hysteresis is added on the
DOWN
joined UP and
pins of the ADM1186-1 or on the
pin of the ADM1186-2 to ensure that a slowly
DOWN
UP/
ramping supply rail does not cause spurious rising or falling
edges that would otherwise cause state machine faults.
VIN × R2 3.3×10 k
R1+ R2 11k+10 k
VMID
=
=
To provide the necessary hysteresis, a single additional resistor
(RH in Figure 27) is connected between the joined UP and
V
MID = 2.94 V
As a general rule, the value for RH is approximately 60 times
the value of R1 in parallel with R2. In this example, R1 in
parallel with R2 is 5.24 kꢁ, so RH would be approximately
314 kꢁ. Taking a value of 300 kꢁ for RH and using this value
in the previous equations for VH, VL, and VSHYS, the following
values are obtained:
DOWN
pins of the ADM1186-1 and the OUT1 pin of the
DOWN
device, or between the UP/
pin of the ADM1186-2 and
the OUT1 pin of the device.
RH
VIN
VP
3.3V
⎡
10 k + 300 k ⎤
⎞
⎛
⎝
VH =1.4 × 1 + 11k ×
VCC
⎜
⎟
⎥
⎢
⎣
R1
ADM1186-1
RP
10 k ×300 k
⎠
⎦
OUT1
UP
+
–
VH = 2.991 V
R2
STATE
MACHINE
⎡
⎤
⎥
⎛
⎜
⎜
⎝
⎞
⎟
⎟
⎠
5 −1.4
10 k 300 k +10 k
1.4
DOWN
1.4V
+
–
V =1.4 + 11k ×
−
⎢
L
⎢
⎣
⎥
⎦
VL = 2.812 V
Figure 27. Using a Supply Rail to Control Sequencing with Hysteresis
10 k
11k+10 k
⎛
⎜
⎝
⎞
⎟
⎠
VSHYS
= 2.991 − 2.812 ×
( )
When OUT1 is low, the resistor RH sinks current from the
node at the midpoint of R1 and R2, slightly increasing the VIN
voltage needed to start a power-up sequence, referred to as VH.
When OUT1 is high, RH sources current into the midpoint of
R1 and R2, decreasing the VIN voltage necessary to start a
power-down sequence, referred to as VL.
V
SHYS = 0.085 V
Because the value of VSHYS is greater than the 75 mV of scaled
hysteresis required, the RH resistor value selected is sufficient.
If the value of VSHYS obtained is too small, the value of RH can
be reduced, increasing the scaled hysteresis provided.
The hysteresis at the VIN node is simply VH − VL. As the R1
and R2 resistors scale VIN down, the hysteresis on VIN is also
scaled down. The scaled hysteresis, VSHYS, at the inputs to the
It should be noted that it is not possible to directly connect the
VCC supply to the UP pin (ADM1186-1) or to the UP/
DOWN
pin (ADM1186-2) to start a sequence as the VCC comes up.
When the UVLO circuit enables the state machine, it begins
in the fault handler states. To reach the WAIT START state so
that sequencing can begin, the UP pin (ADM1186-1) or the
DOWN
DOWN
UP and
pins (ADM1186-1) or the UP/
pin
(ADM1186-2) must be at least 75 mV. The value of RH is
selected to ensure that this is the case.
R2 + RH
R2× RH
⎡
⎤
⎛
⎝
⎞
⎟
⎠
DOWN
UP/
pin (ADM1186-2) must be held low after the state
VH =1.4 × 1 + R1×
⎜
⎢
⎣
⎥
⎦
machine is enabled.
⎡
⎤
⎥
⎛
⎜
⎜
⎝
⎞
⎟
⎟
⎠
1.4
R2
VP −1.4
RH + RP
VL =1.4 + ⎢R1 ×
−
⎢
⎣
⎥
⎦
Rev. 0 | Page 16 of 28
ADM1186
VCC
ADM1186-1
VIN1
VIN2
GLITCH FILTER
GLITCH FILTER
GLITCH FILTER
GLITCH FILTER
PWRGD
VIN3
VIN4
OUT1
OUT2
OUT3
OUT4
0.6V
UP
DOWN
FAULT
RISING EDGE
DETECT
GLITCH FILTER
GLITCH FILTER
GLITCH FILTER
STATE
MACHINE
FALLING EDGE
DETECT
1.4V
SEQ_DONE
14µA
DLY_EN_OUT1
DLY_EN_OUT2
DLY_EN_OUT3
DLY_EN_OUT4
BLANK_DLY
CAPACITOR MUX
AND DISCHARGE
450Ω
1.4V
GND
Figure 28. Functional Block Diagram of the ADM1186-1
Rev. 0 | Page 17 of 28
ADM1186
FAULT IN: HIGH
WAIT ALL OK
FAULT OUT: HIGH
UP: LOW
FAULT IN: LOW
WAIT START
OUT1: LOW OUT4: LOW
CLEAR FAULT
OUT2: LOW SEQ_DONE: LOW
OUT3: LOW FAULT OUT: HIGH
DOWN: FALLING EDGE
F
F
FAULT HOLD
TIMES OUT
UP: RISING EDGE
SET FAULT
OUT1: LOW OUT4: LOW
OUT2: LOW SEQ_DONE: LOW
OUT3: LOW FAULT OUT: LOW
FAULT IN: LOW
DOWN: FALLING EDGE
DELAY 1
AFTER DLY_EN_OUT1 TIME DELAY
AFTER DLY_EN_OUT1
TIME DELAY
FAULT IN: LOW
F
EXIT UVLO
FAULT IN: LOW
UP: RISING EDGE
DOWN: FALLING EDGE
AFTER BLANKING DELAY VIN1: LOW
DISABLE OUT1
OUT1: LOW
ENABLE OUT1
OUT1: HIGH
AFTER BLANKING DELAY VIN1: HIGH
F
F
F
FAULT IN: LOW
DOWN: FALLING EDGE
VIN1: LOW
DELAY 2
AFTER DLY_EN_OUT2 TIME DELAY
FAULT IN: LOW
AFTER DLY_EN_OUT2
TIME DELAY
FAULT IN: LOW
DOWN: FALLING EDGE
VIN1: LOW
UP: RISING EDGE
VIN1: LOW
AFTER BLANKING DELAY VIN2: LOW
DISABLE OUT2
OUT2: LOW
ENABLE OUT2
OUT2: HIGH
F
F
F
AFTER BLANKING DELAY VIN2: HIGH
FAULT IN: LOW
DOWN: FALLING EDGE
VIN1 OR VIN2: LOW
DELAY 3
AFTER DLY_EN_OUT3 TIME DELAY
FAULT IN: LOW
FAULT IN: LOW
UP: RISING EDGE
VIN1 OR VIN2: LOW
AFTER DLY_EN_OUT3
TIME DELAY
DOWN: FALLING EDGE
VIN1 OR VIN2: LOW
AFTER BLANKING DELAY VIN3: LOW
DISABLE OUT3
OUT3: LOW
ENABLE OUT3
F
F
F
OUT3: HIGH
AFTER BLANKING DELAY VIN3: HIGH
FAULT IN: LOW
DOWN: FALLING EDGE
VIN1 OR VIN2 OR VIN3: LOW
DELAY 4
AFTER DLY_EN_OUT4 TIME DELAY
FAULT IN: LOW
FAULT IN: LOW
UP: RISING EDGE
VIN1 OR VIN2 OR VIN3: LOW
AFTER DLY_EN_OUT4
TIME DELAY
DOWN: FALLING EDGE
VIN1 OR VIN2 OR VIN3: LOW
AFTER BLANKING DELAY VIN4: LOW
DISABLE OUT4
OUT4: LOW
ENABLE OUT4
OUT4: HIGH
AFTER BLANKING DELAY VIN4: HIGH
F
F
F
FAULT IN: LOW
UP: RISING EDGE
VIN1 OR VIN2 OR VIN3 OR VIN4: LOW
POWER-UP DONE
SEQ_DONE: HIGH
DOWN: FALLING EDGE
Figure 29. ADM1186-1 State Machine Operation
Rev. 0 | Page 18 of 28
ADM1186
VCC
ADM1186-2
VIN1
VIN2
GLITCH FILTER
PWRGD
GLITCH FILTER
GLITCH FILTER
GLITCH FILTER
VIN3
VIN4
OUT1
OUT2
0.6V
STATE
MACHINE
UP/DOWN
EDGE
DETECT
GLITCH FILTER
OUT3
OUT4
1.4V
14µA
DLY_EN_OUT2
DLY_EN_OUT3
DLY_EN_OUT4
BLANK_DLY
CAPACITOR MUX
AND DISCHARGE
450Ω
1.4V
GND
Figure 30. Functional Block Diagram of the ADM1186-2
Rev. 0 | Page 19 of 28
ADM1186
WAIT START
OUT1: LOW OUT3: LOW
OUT2: LOW OUT4: LOW
UP/DOWN: LOW
CLEAR FAULT
UP/DOWN: RISING EDGE
UP/DOWN: FALLING EDGE
AFTER BLANKING DELAY VIN1: LOW
UP/DOWN: RISING EDGE
DISABLE OUT1
OUT1: LOW
ENABLE OUT1
OUT1: HIGH
F
F
F
F
F
FAULT HOLD
TIMES OUT
AFTER BLANKING DELAY VIN1: HIGH
SET FAULT
OUT1: LOW OUT3: LOW
OUT2: LOW OUT4: LOW
UP/DOWN: FALLING EDGE
VIN1: LOW
DELAY 2
AFTER DLY_EN_OUT2 TIME DELAY
AFTER DLY_EN_OUT2
TIME DELAY
UP/DOWN: FALLING EDGE
VIN1: LOW
F
EXIT UVLO
UP/DOWN: RISING EDGE
VIN1: LOW
AFTER BLANKING DELAY VIN2: LOW
ENABLE OUT2
DISABLE OUT2
OUT2: LOW
F
OUT2: HIGH
AFTER BLANKING DELAY VIN2: HIGH
UP/DOWN: FALLING EDGE
VIN1 OR VIN2: LOW
DELAY 3
AFTER DLY_EN_OUT3 TIME DELAY
AFTER DLY_EN_OUT3
TIME DELAY
UP/DOWN: FALLING EDGE
VIN1 OR VIN2: LOW
AFTER BLANKING DELAY VIN3: LOW
UP/DOWN: RISING EDGE
VIN1 OR VIN2: LOW
ENABLE OUT3
OUT3: HIGH
DISABLE OUT3
OUT3: LOW
F
F
F
F
F
AFTER BLANKING DELAY VIN3: HIGH
UP/DOWN: FALLING EDGE
VIN1 OR VIN2 OR VIN3: LOW
DELAY 4
AFTER DLY_EN_OUT4 TIME DELAY
AFTER DLY_EN_OUT4
TIME DELAY
UP/DOWN: FALLING EDGE
UP/DOWN: RISING EDGE
VIN1 OR VIN2 OR VIN3: LOW
VIN1 OR VIN2 OR VIN3: LOW
AFTER BLANKING DELAY VIN4: LOW
DISABLE OUT4
OUT4: LOW
ENABLE OUT4
OUT4: HIGH
AFTER BLANKING DELAY VIN4: HIGH
F
VIN1 OR VIN2 OR VIN3 OR VIN4: LOW
POWER-UP DONE
UP/DOWN: FALLING EDGE
Figure 31. ADM1186-2 State Machine Operation
Rev. 0 | Page 20 of 28
ADM1186
1
2
3
4
5
6
7
8
9
10
11
12
13
14
1
UP
DOWN
DLY_EN_OUT1
OUT1
DLY_EN_OUT2
OUT2
DLY_EN_OUT3
OUT3
DLY_EN_OUT4
OUT4
BLANK_DLY
SEQ_DONE
PWRGD
STATE NAMES
7 - ENABLE OUT3 10 - POWER-UP DONE 13 - DISABLE OUT2
1 - WAIT START
2 - DELAY 1
4 - DELAY 2
5 - ENABLE OUT2 8 - DELAY 4
11 - DISABLE OUT4
14 - DISABLE OUT1
3 - ENABLE OUT1 6 - DELAY 3
9 - ENABLE OUT4 12 - DISABLE OUT3
Figure 32. ADM1186-1 Typical Power-Up and Power-Down Sequence Waveforms with Corresponding State Names
1
2
3
4
5
6
7
8
9
10
11
12 13
1
UP/DOWN
OUT1
DLY_EN_OUT2
OUT2
DLY_EN_OUT3
OUT3
DLY_EN_OUT4
OUT4
BLANK_DLY
PWRGD
STATE NAMES
4 - ENABLE OUT2 7 - DELAY 4
2 - ENABLE OUT1 5 - DELAY 3 8 - ENABLE OUT4
3 - DELAY 2
1 - WAIT START
10 - DISABLE OUT4 13 - DISABLE OUT1
11 - DISABLE OUT3
6 - ENABLE OUT3 9 - POWER-UP DONE 12 - DISABLE OUT2
Figure 33. ADM1186-2 Typical Power-Up and Power-Down Sequence Waveforms with Corresponding State Names
Rev. 0 | Page 21 of 28
ADM1186
5V
5V
IN
ADP1706
2.5V
1.8V
EN
OUT
5V
5V
IN
ADP2107
EN
OUT
3.3V AUX
3.3V AUX
IN
3.3V AUX
1µF
ADP1821
1.2V
3.3V
EN
OUT
5V
5V
IN
ADP1706
100nF
EN
OUT
VCC
OUT1
OUT2
OUT3
OUT4
VIN1
VIN2
VIN3
VIN4
SEQUENCE CONTROL
UP/DOWN
ADM1186-2
DLY_EN_OUT2
DLY_EN_OUT3
DLY_EN_OUT4
BLANK_DLY
2.5V AUX
PWRGD
GND
Figure 34. ADM1186-2 Typical Application
Rev. 0 | Page 22 of 28
ADM1186
CASCADING MULTIPLE DEVICES
Figure 36 shows two independent sequences of four supplies,
each with common status outputs. In this example, both devices
share the same sequence control signal, so they start their
power-up and power-down sequences at the same time. Both
devices must complete their power-up sequences before the
POWER GOOD signal goes high.
Multiple ADM1186-1 devices can be cascaded in applications
that require more than four supplies to be sequenced and
monitored. When ADM1186-1 devices are cascaded, the
controlled power-up and power-down of all the cascaded
supplies is maintained using only three pins on each device.
There are several configurations for interconnecting these
devices. The most suitable configuration depends on the
application. Figure 35 and Figure 36 show two methods for
cascading multiple ADM1186-1 devices.
FAULT
The
Connecting the
on one device, or an unexpected event such as a rising or falling
DOWN
pins of all devices in a cascade should be connected.
FAULT
pins ensures that an undervoltage fault
edge on the UP or
all the other devices.
When an internal fault condition occurs on a device, it pulls its
pin, generates a fault condition on
Figure 35 shows a single sequence of 12 supplies. The capacitors
used for timing are not shown in the figure for clarity. To ensure
controlled power-up and power-down sequencing of all 12 sup-
plies, the following connections are made:
FAULT
pin low. This in turns causes the other ADM1186-1
FAULT
devices to enter the SET FAULT state and pull their
pins
DOWN
pin of the
•
•
•
The UP pin of the first device and the
last device in the cascade chain are connected.
low. Each device waits for the fault hold time to elapse and then
moves to the CLEAR FAULT state.
The SEQ_DONE pin of Device N is connected to the UP
pin of Device N + 1.
The SEQ_DONE pin of Device N is connected to the
If the VCC supply for an ADM1186-1 drops below VUVLO, the
FAULT
UVLO circuit becomes active, and the
This generates a fault condition on all other connected devices.
FAULT
pin is pulled low.
DOWN
pin of Device N − 1.
A device in the CLEAR FAULT state holds its
until its UP input pin is low. The device then moves into the
FAULT
pin low
When the SEQUENCE CONTROL line goes high, Device A
begins the power-up sequence, turning on each enable output
in turn, with the associated delays, according to the state
machine. When Device A completes its power-up sequence, the
SEQ_DONE pin goes from low to high, initiating a power-up
sequence on Device B. When Device B completes its power-up
sequence, the Device B SEQ_DONE pin goes high, initiating a
power-up sequence on Device C. When Device C completes its
power-up sequence and all supplies are above the UV threshold,
the system POWER GOOD signal goes high.
WAIT ALL OK state and releases the
pin.
If, for example, a UV fault occurs on a VINx pin during a
power-up sequence, the UP pin will be high on the first device
FAULT
in the cascade. The first device in the cascade holds the
line low until the UP pin is brought low. All other devices will
FAULT
have released their
OK state.
pins and will be in the WAIT ALL
FAULT
When the UP pin goes low, the first device releases its
If the SEQUENCE CONTROL line goes low, Device C starts a
power-down sequence, turning off its enable outputs. When all
Device C enable outputs are off, the SEQ_DONE pin on Device C
FAULT
pin so the
line returns high, which allows all devices to
move together from the WAIT ALL OK state back into the
WAIT START state, ready for the next power-up sequence.
DOWN
goes low, causing a high-to-low transition on the
pin of
An external device such as a microcontroller, field programmable
gate array (FPGA), or an overtemperature sensor can cause a
Device B. This transition initiates a power-down sequence on
Device B, which takes all its OUTx pins low, causing SEQ_DONE
to be taken low. This high-to-low transition is seen by Device A,
which starts its power-down sequence, thus completing the
ordered shutdown of the 12 supplies.
FAULT
fault condition by briefly bringing
ADM1186-1 behaves as described. If the external device continues
FAULT
low. In this case, the
to hold the
line low, all the ADM1186-1 devices remain
in the WAIT ALL OK state, effectively preventing a power-up
sequence from starting.
Note that the capacitor on the DLY_EN_OUT1 pin of Device B
(not shown in Figure 35) sets the sequence time delay between
the last supply of Device A and the first supply of Device B
being turned on and off.
Rev. 0 | Page 23 of 28
ADM1186
3 5 0 3 - 1 5 0 7
Figure 35. Cascading Multiple ADM1186-1 Devices, Option 1
Rev. 0 | Page 24 of 28
ADM1186
3.3V
VCC
ADM1186-1A
V1
V2
V3
V4
VIN1
VIN2
VIN3
VIN4
OUT1
EN1
EN2
SUPPLIES
SCALED
DOWN WITH
RESISTOR
DIVIDERS
ENABLE
OUT2
OUTPUTS TO
REGULATORS
WITH PULL-UPs
AS REQUIRED
OUT3
OUT4
EN3
EN4
3.3V
FAULT
UP
SEQUENCE CONTROL
DOWN PWRGD
NO CONNECT
SEQ_DONE
GND
3.3V
VCC
ADM1186-1B
EN5
EN6
V5
V6
V7
V8
VIN1
VIN2
VIN3
VIN4
OUT1
OUT2
OUT3
EN7
EN8
OUT4
5V
FAULT
UP
POWER
GOOD
DOWN PWRGD
NO CONNECT
SEQ_DONE
GND
Figure 36. Cascading Multiple ADM1186-1 Devices, Option 2
Rev. 0 | Page 25 of 28
ADM1186
OUTLINE DIMENSIONS
0.345 (8.76)
0.341 (8.66)
0.337 (8.55)
20
1
11
10
0.158 (4.01)
0.154 (3.91)
0.150 (3.81)
0.244 (6.20)
0.236 (5.99)
0.228 (5.79)
0.010 (0.25)
0.006 (0.15)
0.020 (0.51)
0.010 (0.25)
0.069 (1.75)
0.053 (1.35)
0.065 (1.65)
0.049 (1.25)
0.010 (0.25)
0.004 (0.10)
0.041 (1.04)
REF
SEATING
PLANE
8°
0°
0.025 (0.64)
BSC
0.050 (1.27)
0.016 (0.41)
COPLANARITY
0.004 (0.10)
0.012 (0.30)
0.008 (0.20)
COMPLIANT TO JEDEC STANDARDS MO-137-AD
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETERS DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 37. 20-Lead Shrink Small Outline Package [QSOP] (RQ-20)
Dimensions shown in inches and (millimeters)
0.197 (5.00)
0.193 (4.90)
0.189 (4.80)
16
1
9
8
0.158 (4.01)
0.154 (3.91)
0.150 (3.81)
0.244 (6.20)
0.236 (5.99)
0.228 (5.79)
0.010 (0.25)
0.006 (0.15)
0.020 (0.51)
0.010 (0.25)
0.069 (1.75)
0.053 (1.35)
0.065 (1.65)
0.049 (1.25)
0.010 (0.25)
0.004 (0.10)
0.041 (1.04)
REF
SEATING
PLANE
8°
0°
0.025 (0.64)
BSC
0.050 (1.27)
0.016 (0.41)
COPLANARITY
0.004 (0.10)
0.012 (0.30)
0.008 (0.20)
COMPLIANT TO JEDEC STANDARDS MO-137-AB
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETERS DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 38. 16-Lead Shrink Small Outline Package [QSOP] (RQ-16)
Dimensions shown in inches and (millimeters)
ORDERING GUIDE
Model
Temperature Range
Package Description
Package Option
RQ-20
RQ-20
RQ-16
RQ-16
ADM1186-1ARQZ1
ADM1186-1ARQZ-REEL1
ADM1186-2ARQZ1
ADM1186-2ARQZ-REEL1
EVAL-ADM1186-1EBZ1
EVAL-ADM1186-1MBZ1
EVAL-ADM1186-2EBZ1
EVAL-ADM1186-2MBZ1
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
20-Lead Shrink Small Outline Package [QSOP]
20-Lead Shrink Small Outline Package [QSOP]
16-Lead Shrink Small Outline Package [QSOP]
16-Lead Shrink Small Outline Package [QSOP]
Evaluation Kit
Micro-Evaluation Kit
Evaluation Kit
Micro-Evaluation Kit
1 Z = RoHS Compliant Part.
Rev. 0 | Page 26 of 28
ADM1186
NOTES
Rev. 0 | Page 27 of 28
ADM1186
NOTES
©2008 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07153-0-5/08(0)
Rev. 0 | Page 28 of 28
相关型号：
ADM1201AUJ
IC 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO8, MO-193BA, TSOT-8, Power Management Circuit
ADI
ADM1202-1AUJ
IC 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO8, MO-193BA, TSOT-8, Power Management Circuit
ADI
ADM1202-2AUJ
IC 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO8, MO-193BA, TSOT-8, Power Management Circuit
ADI
©2020 ICPDF网 联系我们和版权申明