ADM1232AARNZ [ADI]

Microprocessor Supervisory Circuit;


型号：	ADM1232AARNZ
厂家：	ADI
描述：	Microprocessor Supervisory Circuit 微处理器监控
文件：	总6页 (文件大小：125K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

Microprocessor

Supervisory Circuit

ADM1232

FEATURES

FUNCTIO NAL BLO CK D IAGRAM

Superior Upgrade for MAX1232 and Dallas DS1232

Low Pow er Consum ption (500 ␮A m ax)

Adjustable Precision Voltage Monitor w ith +4.5 V and

+4.75 V Options

Adjustable STROBE Monitor w ith 150 m s, 600 m s or

1.2 sec Options

5%/10%

TOLERANCE

SELECT

RESET

GENERATOR

TOLERANCE

VREF

PB RESET

DEBOUNCE

No External Com ponents

WATCHDOG

TIMER

WATCHDOG

TIMEBASE

SELECT

APPLICATIONS

Microprocessor System s

Portable Equipm ent

Com puters

ADM1232

GND

Controllers

Intelligent Instrum ents

Autom otive System s

Protection Against Dam age Caused by ␮P Failure

GENERAL D ESCRIP TIO N

+5V

T he ADM1232 is a superior, pin-compatible upgrade for the

MAX1232 and the DS1232LP and DS1232. T he Analog

Devices ADM1232 is a microprocessor monitoring circuit that

can monitor:

10k⍀

+5V

MICROPROCESSOR

ADM1232

1. Microprocessor Supply Voltage.

2. Whether a Microprocessor has locked-up.

3. An External Interrupt.

ADM1232

I/O

RESET

STROBE

RESET

T he ADM1232 is available in four different packages:

GND TD

TOLERANCE

1. T he ADM1232ARM in an 8-lead microSOIC (RM-8).

2. T he ADM1232AN in an 8-lead PDIP (N-8).

3. T he ADM1232ARW in a 16-lead wide SOIC (R-16).

4. T he ADM1232ARN is an 8-lead narrow SOIC (R-8).

Figure 1. Typical Supply Monitoring Application

REV. B

Inform ation furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assum ed by Analog Devices for its

use, nor for any infringem ents of patents or other rights of third parties

which m ay result from its use. No license is granted by im plication or

otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.

Tel: 781/ 329-4700

Fax: 781/ 326-8703

World Wide Web Site: http:/ / w w w .analog.com

(V = Full Operating Range, T = T_MINto T_MAXunless otherwise noted)

ADM1232–SPECIFICATIONS

aram eter

Min

Typ

Max

Units Test Conditions/Com m ents

T EMPERAT URE

–40

+85

°C

T_A= T _MINto T _MAX

POWER SUPPLY

Voltage

Current

4.5

5.0

200

5.5

500

µA

V_IL, V_IH= CMOS Levels

V_IL, V_IH= T T L Levels

STROBE AND PB RESET INPUT S

Input High Level

Input Low Level

2.0

–0.3

V_CC+ 0.3

+0.8

INPUT LEAKAGE CURRENT

(STROBE, T OLERANCE)

T D

–1.0

+1.0

µA

1.6

OUT PUT CURRENT

RESET

RESET, RESET

–8

–12

When V_CCIs at 4.5 V–5.5 V

OUT PUT VOLT AGE

RESET/RESET

V_CC– 0.5 V_CC– 0.1

While sourcing less than 500 µA, RESET remains

within 0.5 V of V_CCon power-down until V_CC

drops below 2.0 V. While sinking less than

500 µA, RESET remains within 0.5 V of GND

on power-down until V_CCdrops below 2.0 V.

RESET/RESET High Level

RESET/RESET Low Level

0.4

2.4

1 V OPERAT ION

RESET Output Voltage

V_CC– 0.1

0.1

While Sourcing Less than 50 µA

While Sinking Less than 50 µA

V_CCT RIP POINT

10%

4.5

4.25

4.62

4.37

4.74

4.49

T OLERANCE = GND

T OLERANCE = V_CC

CAPACIT ANCE

Input (STROBE, T OLERANCE)

Output (RESET , RESET)

T _A= +25°C

T_A= +25°C

PB RESET

T ime

Delay

PB RESET Must Be Held Low for a Minimum

of 20 ms to Guarantee a Reset

RESET ACT IVE T IME

250

610

1000

STROBE

Pulse Width

T imeout Period

62.5

250

500

150

600

1200

250

1000

2000

T D = 0 V

T D = Floating

T D = V_CC

V_CC

Fall Time

Rise T ime

µS

Guaranteed by Design

V_CCFAIL DETECT TO RESET OUTPUT DELAY

RESET AND RESET Are Logically Correct

µs

After V_CCFalls Below the Set Tolerance Voltage

(Figure 5)

250

610

1000

After V_CCRises Above the Set Tolerance Voltage

Specifications subject to change without notice.

REV. B

–2–

ADM1232

ABSO LUTE MAXIMUM RATINGS*

(T _A= +25°C unless otherwise noted)

RM-8

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . 900 mW

Derate by 12 mW/°C above 25°C

θ_JAT hermal Impedance (Still Air) . . . . . . . . . . . . . 206°C/W

R-8

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 900 µW

Derate by 12 mW/°C above 25°C

θ_JAT hermal Impedance (Still Air) . . . . . . . . . . . . . 153°C/W

V_CC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5.5 V

Logic Inputs . . . . . . . . . . . . . . . . . . . . . –0.3 V to V_CC+ 0.3 V

Storage T emperature Range . . . . . . . . . . . . –65°C to +150°C

Lead T emperature (Soldering, 10 sec) . . . . . . . . . . . . +300°C

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . +215°C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C

N-8

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . 1000 mW

Derate by 13.5 mW/°C above 25°C

θ_JAT hermal Impedance . . . . . . . . . . . . . . . . . . . . . 100°C/W

R-16

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. T his is a stress rating only; functional operation of the

device at these or any other conditions above those listed in the operational

sections of this specification is not implied. Exposure to absolute maximum ratings

for extended periods of time may affect device reliability.

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . 900 mW

Derate by 12 mW/°C above 25°C

θ_JAT hermal Impedance (Still Air) . . . . . . . . . . . . . . 73°C/W

O RD ERING GUID E

Tem perature

P ackage

Model

Range

O ptions*

ADM1232ARM

ADM1232AN

ADM1232ARW

ADM1232ARN

–40°C to +85°C

RM-8

N-8

R-16

R-8

*N= Plastic DIP; R = Small Outline; RM = microSOIC.

CAUTIO N

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily

accumulate on the human body and test equipment and can discharge without detection.

Although the ADM1232 features proprietary ESD protection circuitry, permanent damage may

occur on devices subjected to high energy electrostatic discharges. T herefore, proper ESD

precautions are recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

REV. B

–3–

ADM1232

P IN FUNCTIO N D ESCRIP TIO NS

Mnem onic

Function

PB RESET

Push Button Reset Input. T his debounced input will ignore pulses of less than 1 ms and is guaranteed to re-

spond to pulses greater than 20 ms.

T D

T ime Delay Set allows the user to select the maximum amount of time the ADM1232 will allow the STROBE

input to remain inactive (i.e., STROBE is not receiving any high-to-low transitions), without forcing the

ADM1232 to generate a RESET pulse. (See STROBE specifications, Figure 4 and the note on STROBE

timeout selection.)

T OLERANCE

T olerance Input. T his input will determine how much the supply voltage will be allowed to decrease (as a per-

centage tolerance) before a RESET is asserted. Connect to V_CCfor 10% and GND for 5%.

GND

0 V ground reference for all signals.

RESET

Active high logic output. Will be asserted when:

1. V_CCdecreases below the amount specified by the T OLERANCE input or,

2. PB RESET is forced low or,

3. If there are no high-to-low transitions within the limits set by T D at STROBE or,

4. During power-up.

RESET

Inverse of RESET , with an open drain output.

STROBE

T he STROBE input is used to monitor the activity of a microprocessor. If there are no high-to-low transi-

tions within the time specified by T D, a reset will be asserted.

V_CC

Power supply input +5 V.

P IN CO NFIGURATIO NS

R-16

RM-8

N-8 and R-8

PB RESET

ADM1232

TOP VIEW

(Not to Scale)

ADM1232

TOP VIEW

(Not to Scale)

PB RESET

STROBE

RESET

STROBE

RESET

TOLERANCE

GND

TOLERANCE

GND

ADM1232

STROBE

TOP VIEW

(Not to Scale)

TOLERANCE

11 RESET

GND

RESET

NC = NO CONNECT

REV. B

–4–

ADM1232

CIRCUIT INFO RMATIO N

STROBE Tim eout Selection

PB RESET

T D or time delay set is used to set the Strobe T imeout Period.

T he Strobe T imeout Period is defined as being the maximum

time between high-to-low transitions (Figure 4) that STROBE

will accept before a reset will be asserted. T he Strobe timeout

settings are listed in T able I.

The PB RESET input makes it possible to manually reset a system

using either a standard push-button switch or a logic low

input. An internal debounce circuit provides glitch immunity

when used with a switch, reducing the effects of glitches on the

line. T he debounce circuit is guaranteed to cause the ADM1232

to assert a reset if PB RESET is brought low for more than 20 ms

and is guaranteed to ignore low inputs of less than 1 ms.

Table I.

Condition

Min

Typ

Max

Units

T D = 0 V

T D = Floating

T D = V_CC

62.5

250

500

150

600

1200

250

1000

2000

STROBE

PULSE WIDTH

ADM1232

MICROPROCESSOR

ADM1232

STROBE

PB RESET

ESET

STROBE

I/O

SRTERSOEBTE

RESET

TOLERANCE

GND

STROBE TIMEOUT PERIOD

Figure 4. STROBE Param eters

Figure 2. Typical Push Button Reset Application

+5V

+4.5V (5% TRIP POINT)

+4.25V (10%TRIP POINT)

PB RESET TIME

PB RESET

RESET OUTPUT DELAY

PB RESET

WHEN IS V FALLING

WHEN IS V RISING

DELAY

RESET

RESET ACTIVE

TIME

RESET

Figure 5. Reset Output Delay

TO LERANCE

T he T OLERANCE input is used to determine the level V_CCcan

vary below 5 V without the ADM1232 asserting a reset. Con-

necting T OLERANCE to ground will select a –5% tolerance

level and will cause the ADM1232 to generate a reset if V_CC

falls below 4.75 V (typical). If T OLERANCE is connected to

V_CCa –10% tolerance level is selected and will cause the

ADM1232 to generate a reset if V_CCfalls below 4.5 V (typical).

Check the parameters for the V_CCtrip point in the ADM1232

Specifications for more information.

Figure 3. PB RESET

RESET AND RESET O UTP UTS

While RESET is capable of sourcing and sinking current,

RESET is an open drain MOSFET which sinks current only.

T herefore, it is necessary to pull this output high.

REV. B

–5–

ADM1232

O UTLINE D IMENSIO NS

D imensions shown in inches and (mm).

8-Lead P D IP

(N-8)

16-Lead Wide SO IC

(R-16)

0.4133 (10.50)

0.3977 (10.00)

0.430 (10.92)

0.348 (8.84)

0.280 (7.11)

0.240 (6.10)

0.325 (8.25)

0.300 (7.62)

0.060 (1.52)

0.015 (0.38)

PIN 1

0.195 (4.95)

0.115 (2.93)

0.210 (5.33)

MAX

0.130

(3.30)

MIN

0.160 (4.06)

0.1043 (2.65)

0.0926 (2.35)

0.0291 (0.74)

PIN 1

x 45°

0.115 (2.93)

0.0118 (0.30)

0.0040 (0.10)

0.0098 (0.25)

0.015 (0.381)

SEATING

PLANE

0.100

(2.54)

BSC

0.022 (0.558)

0.014 (0.356)

0.070 (1.77)

0.045 (1.15)

0.008 (0.204)

0.0500 (1.27)

0.0157 (0.40)

8°

0°

0.0500

(1.27)

BSC

0.0192 (0.49)

SEATING

PLANE

0.0125 (0.32)

0.0091 (0.23)

0.0138 (0.35)

8-Lead m icroSO IC

(RM-8)

8-Lead Narrow SO IC

(R-8)

0.122 (3.10)

0.114 (2.90)

0.1968 (5.00)

0.1890 (4.80)

0.199 (5.05)

0.187 (4.75)

0.122 (3.10)

0.114 (2.90)

0.1574 (4.00)

0.1497 (3.80)

0.2440 (6.20)

0.2284 (5.80)

PIN 1

0.102 (2.59)

0.094 (2.39)

PIN 1

0.0196 (0.50)

0.0099 (0.25)

x 45°

0.0256 (0.65) BSC

0.120 (3.05)

0.112 (2.84)

0.120 (3.05)

0.112 (2.84)

0.0098 (0.25)

0.0040 (0.10)

0.043 (1.09)

0.037 (0.94)

8°

0°

0.006 (0.15)

0.002 (0.05)

0.0500 0.0192 (0.49)

0.0500 (1.27)

0.0160 (0.41)

0.0098 (0.25)

0.0075 (0.19)

SEATING

PLANE

33°

27°

(1.27)

0.0138 (0.35)

0.018 (0.46)

BSC

0.011 (0.28)

0.003 (0.08)

0.028 (0.71)

0.016 (0.41)

SEATING

PLANE

0.008 (0.20)

REV. B

–6–

ADM1232AARNZ [ADI]

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