ADM1232AARN [ADI]

Microprocessor Supervisory Circuit; 微处理器监控电路


型号：	ADM1232AARN
厂家：	ADI
描述：	Microprocessor Supervisory Circuit 微处理器监控电路微处理器监控
文件：	总6页 (文件大小：90K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

Microprocessor

Supervisory Circuit

ADM1232A

FEATURES

FUNCTIONAL BLOCK DIAGRAM

Superior Upgrade for MAX1232 and Dallas DS1232

Low Power Consumption (500 ␮A max)

Adjustable Precision Voltage Monitor with +4.5 V and

+4.75 V Options

RESET

5%/10%

TOLERANCE

SELECT

RESET

GENERATOR

TOLERANCE

Adjustable STROBE Monitor with 150 ms, 600 ms or

1.2 sec Options

No External Components

VREF

RESET

PB RESET

DEBOUNCE

Fast (20 ns) Strobe Pulsewidth

WATCHDOG

TIMER

WATCHDOG

TIMEBASE

SELECT

STROBE

APPLICATIONS

Microprocessor Systems

Portable Equipment

Computers

ADM1232A

GND

Controllers

Intelligent Instruments

Automotive Systems

Protection Against Damage Caused by ␮P Failure

+5V

GENERAL DESCRIPTION

The ADM1232A is a superior, pin-compatible upgrade for the

MAX1232 and the DS1232LP and DS1232. The ADM1232A

can detect strobe pulsewidths as narrow as 20 ns, making it

compatible with high speed microprocessors. The Analog

Devices ADM1232A is a microprocessor monitoring circuit

that can monitor:

10k⍀

+5V

MICROPROCESSOR

ADM1232A

ADM1232

I/O

RESET

STROBE

1. Microprocessor Supply Voltage.

2. Whether a Microprocessor has locked up.

3. An External Interrupt.

STROBE

RESET

GND TD

TOLERANCE

The ADM1232A is available in four different packages:

1. The ADM1232AARM in an 8-lead µSOIC (RM-8).

2. The ADM1232AAN in an 8-lead PDIP (N-8).

3. The ADM1232AARW in a 16-lead wide SOIC (R-16).

4. The ADM1232AARN is an 8-lead narrow SOIC (R-8).

Figure 1. Typical Supply Monitoring Application

REV. 0

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, nor for any infringements of patents or other rights of third parties

which may result from its use. No license is granted by implication or

otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781/329-4700

Fax: 781/326-8703

World Wide Web Site: http://www.analog.com

(V = Full Operating Range, T = T_MINto T_MAXunless otherwise noted)

ADM1232A–SPECIFICATIONS

arameter

Min

Typ

Max

Units Test Conditions/Comments

TEMPERATURE

–40

+85

°C

T_A= T_MINto T_MAX

POWER SUPPLY

Voltage

Current

4.5

5.0

200

5.5

500

µA

V_IL, V_IH= CMOS Levels

V_IL, V_IH= TTL Levels

STROBE AND PB RESET INPUTS

Input High Level

Input Low Level

2.0

–0.3

V_CC+ 0.3

+0.8

INPUT LEAKAGE CURRENT

(STROBE, TOLERANCE)

–1.0

+1.0

µA

1.6

OUTPUT CURRENT

RESET

RESET, RESET

–8

–12

When V_CCIs at 4.5 V–5.5 V

OUTPUT VOLTAGE

RESET/RESET

V_CC– 0.5 V_CC– 0.1

While sourcing less than 500 µA, RESET remains

within 0.5 V of V_CCon power-down until V_CC

drops below 2.0 V. While sinking less than

500 µA, RESET remains within 0.5 V of GND

on power-down until V_CCdrops below 2.0 V.

RESET/RESET High Level

RESET/RESET Low Level

0.4

2.4

1 V OPERATION

RESET Output Voltage

V_CC– 0.1

0.1

While Sourcing Less than 50 µA

While Sinking Less than 50 µA

V_CCTRIP POINT

10%

4.5

4.25

4.62

4.37

4.74

4.49

TOLERANCE = GND

TOLERANCE = V_CC

CAPACITANCE

Input (STROBE, TOLERANCE)

Output (RESET, RESET)

T_A= +25°C

PB RESET

Time

Delay

PB RESET Must Be Held Low for a Minimum

of 20 ms to Guarantee a Reset

RESET ACTIVE TIME

250

610

1000

STROBE

Pulsewidth

Timeout Period

62.5

250

500

150

600

1200

250

1000

2000

TD = 0 V

TD = Floating

TD = V_CC

V_CC

Fall Time

Rise Time

µS

Guaranteed by Design

V_CCFAIL DETECT TO RESET OUTPUT DELAY

RESET AND RESET Are Logically Correct

µs

After V_CCFalls Below the Set Tolerance Voltage

(Figure 5)

250

610

1000

After V_CCRises Above the Set Tolerance Voltage

Specifications subject to change without notice.

REV. 0

–2–

ADM1232A

ABSOLUTE MAXIMUM RATINGS*

RM-8

(T_A= +25°C unless otherwise noted)

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . 900 mW

Derate by 12 mW/°C above 25°C

θ_JAThermal Impedance (Still Air) . . . . . . . . . . . . . 206°C/W

R-8

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 900 µW

Derate by 12 mW/°C above 25°C

θ_JAThermal Impedance (Still Air) . . . . . . . . . . . . . 153°C/W

V_CC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5.5 V

Logic Inputs . . . . . . . . . . . . . . . . . . . . . –0.3 V to V_CC+ 0.3 V

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . +300°C

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . +215°C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C

N-8

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . 1000 mW

Derate by 13.5 mW/°C above 25°C

θ_JAThermal Impedance . . . . . . . . . . . . . . . . . . . . . 100°C/W

R-16

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the

device at these or any other conditions above those listed in the operational

sections of this specification is not implied. Exposure to absolute maximum ratings

for extended periods of time may affect device reliability.

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . 900 mW

Derate by 12 mW/°C above 25°C

θ_JAThermal Impedance (Still Air) . . . . . . . . . . . . . . 73°C/W

ORDERING GUIDE

Temperature

Package

Options*

Model

Range

ADM1232AARM

ADM1232AAN

ADM1232AARW

ADM1232AARN

–40°C to +85°C

RM-8

N-8

R-16

R-8

*N = Plastic DIP; R = Small Outline; RM = µSOIC.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily

accumulate on the human body and test equipment and can discharge without detection.

Although the ADM1232A features proprietary ESD protection circuitry, permanent damage may

occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD

precautions are recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

REV. 0

–3–

ADM1232A

PIN FUNCTION DESCRIPTIONS

Mnemonic

Function

PB RESET

Push Button Reset Input. This debounced input will ignore pulses of less than 1 ms and is guaranteed to re-

spond to pulses greater than 20 ms.

Time Delay Set allows the user to select the maximum amount of time the ADM1232A will allow the STROBE

input to remain inactive (i.e., STROBE is not receiving any high-to-low transitions), without forcing the

ADM1232A to generate a RESET pulse. (See STROBE specifications, Figure 4 and the note on STROBE

timeout selection.)

TOLERANCE

Tolerance Input. This input will determine how much the supply voltage will be allowed to decrease (as a per-

centage tolerance) before a RESET is asserted. Connect to V_CCfor 10% and GND for 5%.

GND

0 V ground reference for all signals.

RESET

Active high logic output. Will be asserted when:

1. V_CCdecreases below the amount specified by the TOLERANCE input or,

2. PB RESET is forced low or,

3. If there are no high-to-low transitions within the limits set by TD at STROBE or,

4. During power-up.

RESET

Inverse of RESET, with an open drain output.

STROBE

The STROBE input is used to monitor the activity of a microprocessor. If there are no high-to-low transi-

tions within the time specified by TD, a reset will be asserted.

V_CC

Power supply input +5 V.

PIN CONFIGURATIONS

R-16

RM-8

N-8 and R-8

PB RESET

ADM1232A

PB RESET

STROBE

RESET

STROBE

RESET

TOP VIEW

(Not to Scale)

TOLERANCE

GND

TOLERANCE

GND

ADM1232A ₁₃

STROBE

RESET

TOP VIEW

(Not to Scale)

TOLERANCE

RESET

GND

RESET

NC = NO CONNECT

REV. 0

–4–

ADM1232A

CIRCUIT INFORMATION

PB RESET

STROBE Timeout Selection

TD or time delay set is used to set the Strobe Timeout Period.

The Strobe Timeout Period is defined as being the maximum

time between high-to-low transitions (Figure 4) that STROBE

will accept before a reset will be asserted. The Strobe timeout

settings are listed in Table I.

The PB RESET input makes it possible to manually reset a system

using either a standard push-button switch or a logic low

input. An internal debounce circuit provides glitch immunity

when used with a switch, reducing the effects of glitches on the

line. The debounce circuit is guaranteed to cause the ADM1232A

to assert a reset if PB RESET is brought low for more than 20 ms

and is guaranteed to ignore low inputs of less than 1 ms.

Table I.

Condition

Min

Typ

Max

Units

TD = 0 V

TD = Floating

TD = V_CC

62.5

250

500

150

600

1200

250

1000

2000

STROBE

PULSEWIDTH

ADM1232A

MICROPROCESSOR

ADM1232

STROBE

RESET

STROBE

PB RESET

I/O

SRTERSOEBTE

RESET

TOLERANCE

GND

STROBE TIMEOUT PERIOD

Figure 4. STROBE Parameters

Figure 2. Typical Push Button Reset Application

+5V

+4.5V (5% TRIP POINT)

PB RESET TIME

+4.25V (10% TRIP POINT)

RESET OUTPUT DELAY

PB RESET

WHEN IS V FALLING

WHEN IS V RISING

DELAY

RESET

RESET ACTIVE

TIME

RESET

Figure 5. Reset Output Delay

RESET

TOLERANCE

The TOLERANCE input is used to determine the level V_CCcan

vary below 5 V without the ADM1232A asserting a reset. Con-

necting TOLERANCE to ground will select a –5% tolerance

level and will cause the ADM1232A to generate a reset if V_CC

falls below 4.75 V (typical). If TOLERANCE is connected to

V_CCa –10% tolerance level is selected and will cause the

ADM1232A to generate a reset if V_CCfalls below 4.5 V (typical).

Check the parameters for the V_CCtrip point in the ADM1232A

Specifications for more information.

Figure 3. PB RESET

RESET AND RESET OUTPUTS

While RESET is capable of sourcing and sinking current,

RESET is an open drain MOSFET which sinks current only.

Therefore, it is necessary to pull this output high.

REV. 0

–5–

ADM1232A

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

16-Lead Wide SOIC

(R-16)

8-Lead PDIP

(N-8)

0.430 (10.92)

0.348 (8.84)

0.4133 (10.50)

0.3977 (10.00)

0.280 (7.11)

0.240 (6.10)

0.325 (8.25)

0.300 (7.62)

0.060 (1.52)

0.015 (0.38)

PIN 1

0.195 (4.95)

0.115 (2.93)

0.210 (5.33)

MAX

0.130

(3.30)

MIN

0.160 (4.06)

0.115 (2.93)

0.0291 (0.74)

0.1043 (2.65)

0.0926 (2.35)

PIN 1

0.015 (0.381)

0.008 (0.204)

45؇

SEATING

PLANE

0.100

(2.54)

BSC

0.0118 (0.30)

0.0040 (0.10)

0.022 (0.558)

0.014 (0.356)

0.070 (1.77)

0.045 (1.15)

0.0098 (0.25)

0.0500 (1.27)

0.0157 (0.40)

8؇

0؇

0.0500

(1.27)

BSC

0.0192 (0.49)

0.0138 (0.35)

SEATING

PLANE

0.0125 (0.32)

0.0091 (0.23)

8-Lead ␮SOIC

8-Lead Narrow SOIC

(R-8)

(RM-8)

0.122 (3.10)

0.114 (2.90)

0.1968 (5.00)

0.1890 (4.80)

0.199 (5.05)

0.187 (4.75)

0.122 (3.10)

0.114 (2.90)

0.1574 (4.00)

0.1497 (3.80)

0.2440 (6.20)

0.2284 (5.80)

PIN 1

0.102 (2.59)

0.094 (2.39)

0.0196 (0.50)

0.0099 (0.25)

PIN 1

45؇

0.0256 (0.65) BSC

0.120 (3.05)

0.112 (2.84)

0.0098 (0.25)

0.0040 (0.10)

0.112 (2.84)

0.043 (1.09)

0.037 (0.94)

8؇

0؇

0.006 (0.15)

0.002 (0.05)

0.0500 0.0192 (0.49)

0.0500 (1.27)

0.0160 (0.41)

0.0098 (0.25)

0.0075 (0.19)

SEATING

PLANE

(1.27)

BSC

33؇

27؇

0.0138 (0.35)

0.018 (0.46)

0.008 (0.20)

0.011 (0.28)

0.003 (0.08)

0.028 (0.71)

0.016 (0.41)

SEATING

PLANE

–6–

REV. 0

ADM1232AARN [ADI]

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