ADM1487EARZ-REEL7 [ADI]
5 V, 【15 kV ESD Protected Half-Duplex, RS-485/RS-422 Transceivers; 5 V ， 【 15千伏ESD保护的半双工RS - 485 / RS -422收发器
| 型号： | ADM1487EARZ-REEL7 |
| 厂家： | 
ADI |
| 描述： | 5 V, 【15 kV ESD Protected Half-Duplex, RS-485/RS-422 Transceivers |
| 文件： | 总16页 (文件大小：410K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
5 V, ± ±5 ꢀV ꢁES ꢂProteotꢃ
Half-Supltx, RE-485/RE-422 TPansetivtPs
ASM485ꢁ/ASM487ꢁ/ASM±487ꢁ
FUNCTIONAL BLOCK DIAGRAM
FEATURES
V
CC
TIA/EIA RS-485-/RS-422-compliant
ESD protection on RS-485 I/O pins
15 kV human body model
ADM485E/
ADM487E/
ADM1487E
Data rates
ADM487E: 250 kbps
ADM485E/ADM1487E: 2.5 Mbps
Half-duplex options
RO
RE
R
A
B
Reduced slew rates for low EMI
−7 V to +12 V common-mode input range
Thermal shutdown and short-circuit protection
8-lead SOIC packages
DE
DI
D
GND
APPLICATIONS
Figure 1.
Energy/power metering
Lighting systems
Industrial control
Telecommunications
Security systems
Instrumentation
GENERAL DESCRIPTION
The ADM485E/ADM487E/ADM1487E are 5 V, low power
data transceivers with 15 kV ESD protection suitable for half-
duplex communication on multipoint bus transmission lines.
They are designed for balanced data transmission and comply
with Telecommunication Industry Association/Electronics Indus-
tries Association (TIA/EIA) standards RS-485 and RS-422. The
ADM487E and ADM1487E have a 1/4 unit load receiver input
impedance that allows up to 128 transceivers on a bus, whereas
the ADM485E allows up to 32 transceivers on a bus. Because
only one driver is enabled at any time, the output of a disabled or
power-down driver is three-stated to avoid overloading the bus.
The driver outputs are slew rate-limited to reduce EMI and data
errors caused by reflections from improperly terminated buses.
Excessive power dissipation caused by bus contention or output
shorting is prevented with a thermal shutdown circuit.
The parts are fully specified over the industrial temperature
ranges and are available in 8-lead SOIC packages.
Table 1. Selection Table
Guaranteed
Half-/Full- Data Rate
Part
Number
Slew Rate Low Power Driver/Receiver Quiescent
Number of
Nodes on Bus Count
Pin
Duplex
(Mbps)
Limited
Shutdown
Enable
Current (μA)
ADM485E
ADM487E
ADM1487E Half
Half
Half
2.5
0.25
2.5
No
Yes
No
No
Yes
No
Yes
Yes
Yes
300
120
230
32
128
128
8
8
8
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2007 Analog Devices, Inc. All rights reserved.
ADM485E/ADM487E/ADM1487E
TABLE OF CONTENTS
Features .............................................................................................. 1
Typical Performance Characteristics ..............................................8
Test Circuits and Switching Characteristics................................ 11
Theory of Operation ...................................................................... 13
Circuit Description .................................................................... 13
Applications Information.............................................................. 15
Differential Data Transmission ................................................ 15
Cable and Data Rate................................................................... 15
Outline Dimensions....................................................................... 16
Ordering Guide .......................................................................... 16
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Specifications .................................................................. 4
Absolute Maximum Ratings............................................................ 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions............................. 7
REVISION HISTORY
1/07—Revision 0: Initial Version
Rev. 0 | Page 2 of 16
ADM485E/ADM487E/ADM1487E
SPECIFICATIONS
VCC = 5 V 5ꢀ, TA = TMIN to TMAX, unless otherwise noted.
Table 2. ADM485E/ADM487E/ADM1487E
Parameter
Symbol Min
Typ
Max
Unit
Test Conditions/Comments
DRIVER
Differential Outputs
Differential Output Voltage (no Load)
Differential Output Voltage (with Load) VOD2
VOD1
5
V
V
V
V
2
1.5
RL = 50 Ω (RS-422)
RL = 27 Ω (RS-485) (see Figure 18)
RL = 27 Ω or 50 Ω (see Figure 18)
5
0.2
Δ |VOD| for Complementary Output
States
Common-Mode Output Voltage
Δ |VOC| for Complementary Output
States
VOC
3
0.2
V
V
RL = 27 Ω or 50 Ω (see Figure 18)
RL = 27 Ω or 50 Ω (see Figure 18)
Logic Inputs
Input High Voltage
Input Low Voltage
Logic Input Current
VIH
VIL
IIN1
2.0
V
DE, DI, RE
DE, DI, RE
DE, DI, RE
0.8
2
V
μA
RECEIVER
Input Current (A, B)
IIN2
1.0
mA
mA
mA
mA
DE = 0 V, VIN = 12 V
VCC = 0 V or +5.25 V, VIN = −7V (ADM485E)
DE = 0 V, VIN = 12 V
VCC = 0 V or +5.25 V, VIN = −7 V
(ADM487E/ADM1487E)
−0.8
−0.2
0.25
Differential Inputs
Differential Input Threshold Voltage
Input Hysteresis
Receiver Output Logic
Output Voltage High
Output Voltage Low
Three-State Output Leakage Current
Receiver Input Resistance
VTH
ΔVTH
−0.2
3.5
+0.2
V
mV
−7 V < VCM < +12 V
VCM = 0 V
70
VOH
VOL
IOZR
RIN
V
V
μA
kΩ
kΩ
IOUT = −4 mA, VID = +200 mV
IOUT = +4 mA, VID = −200 mV
0.4 V < VO < 2.4 V
−7 V < VCM < +12 V (ADM485E)
−7 V< VCM < +12 V (ADM487E/ADM1487E)
0.4
1
12
48
POWER SUPPLY
No Load Supply Current
ICC
500
300
300
230
250
120
0.5
900
500
500
400
400
250
10
μA
μA
μA
μA
μA
μA
μA
mA
RE = 0 V or VCC, DE = VCC (ADM485E)
RE = 0 V or VCC, DE = 0 V (ADM485E)
RE = 0 V or VCC, DE = VCC (ADM1487E)
RE = 0 V or VCC, DE = 0 V (ADM1487E)
RE = 0 V or VCC, DE = VCC (ADM487E)
RE = 0 V, DE = 0 V (ADM487E)
Supply Current in Shutdown
Driver Short-Circuit Current, VO High
Driver Short-Circuit Current, VO Low
Receiver Short-Circuit Current
ESD PROTECTION
ISHDN
IOSD1
IOSD2
IOSR
DE = 0 V, RE = VCC (ADM487E)
35
35
7
250
250
95
−7 V ≤ VO ≤ +12 V, applies to peak current
−7 V ≤ VO ≤ +12 V, applies to peak current
0 V ≤ VO ≤ VCC
mA
kV
A, B Pins
15
Human body model
Rev. 0 | Page 3 of 16
ADM485E/ADM487E/ADM1487E
TIMING SPECIFICATIONS
VCC = 5 V 5ꢀ, TA = TMIN to TMAX, unless otherwise noted.
Table 3. ADM485E/ADM1487E
Parameter
DRIVER
Symbol Min
Typ Max
Unit
Test Conditions/Comments
Input to Output
tDPLH
10
10
40
40
5
60
60
10
40
ns
ns
ns
ns
RDIFF = 54 Ω, CL1 = CL2 = 100 pF
(see Figure 19 and Figure 20)
RDIFF = 54 Ω, CL1 = CL2 = 100 pF
(see Figure 19 and Figure 20)
RDIFF = 54 Ω, CL1 = CL2 = 100 pF
(see Figure 19 and Figure 20)
RDIFF = 54 Ω, CL1 = CL2 = 100 pF
(see Figure 19 and Figure 20)
tDPHL
Output Skew to Output
Rise/Fall Time
tSKEW
tDR, tDF
3
20
Enable Time to High Level
Enable Time to Low Level
Disable Time from Low Level
Disable Time from High Level
RECEIVER
tDZH
tDZL
tDLZ
tDHZ
45
45
45
45
70
70
70
70
ns
ns
ns
ns
CRL = 100 pF, S2 closed (see Figure 21)
CRL = 100 pF, S1 closed (see Figure 22)
CRL = 15 pF, S1 closed (see Figure 22)
CRL = 15 pF, S2 closed (see Figure 21)
Input to Output
tRPLH
tSKEW
20
60
5
200
ns
ns
RDIFF = 54 Ω, CL1 = CL2 = 100 pF
(see Figure 23 and Figure 24)
|tPLH − tPHL| Differential Receiver Skew
RDIFF = 54 Ω, CL1 = CL2 = 100 pF
(see Figure 4 and Figure 5)
Enable Time to Low Level
Enable Time to High Level
Disable Time from Low Level
Disable Time from High Level
MAXIMUM DATA RATE
tRZL
tRZL
tRLZ
tRHZ
fMAX
25
20
20
20
50
50
50
50
ns
ns
ns
ns
CRL = 15 pF, S2 closed (see Figure 25)
CRL = 15 pF, S1 closed (see Figure 25)
CRL = 15 pF, S2 closed (see Figure 25)
tPLH, tPHL < 50% of data period
2.5
Mbps
Rev. 0 | Page 4 of 16
ASM485ꢁ/ASM487ꢁ/ASM±487ꢁ
VCC = 5 V 5ꢀ, TA = TMIN to TMAX, unless otherwise noted.
Table 4. ADM487E
Parameter
Symbol Min
Typ
Max
Unit
Test Conditions/Comments
DRIVER
Input to Output
tDPLH
250
250
250
250
800
800
20
2000
2000
800
ns
ns
ns
ns
RDIFF = 54 Ω, CL1 = CL2 = 100 pF
(see Figure 19 and Figure 20)
RDIFF = 54 Ω, CL1 = CL2 = 100 pF
(see Figure 19 and Figure 20)
RDIFF = 54 Ω, CL1 = CL2 = 100 pF
(see Figure 19 and Figure 20)
RDIFF = 54 Ω, CL1 = CL2 = 100 pF
(see Figure 19 and Figure 20)
tDPHL
Output Skew to Output
Rise/Fall Time
tSKEW
tDR, tDF
2000
Enable Time to High Level
Enable Time to Low Level
Disable Time from Low Level
Disable Time from High Level
RECEIVER
tDZH
tDZL
tDLZ
tDHZ
250
2000
2000
3000
3000
ns
ns
ns
ns
CRL = 100 pF, S2 closed (see Figure 21)
CRL = 100 pF, S1 closed (see Figure 22)
CRL = 15 pF, S1 closed (see Figure 22)
CRL = 15 pF, S2 closed (see Figure 21)
300
300
Input to Output
tRPLH
tRPHL
250
250
2000
2000
ns
ns
RDIFF = 54 Ω, CL1 = CL2 = 100 pF
RDIFF = 54 Ω, CL1 = CL2 = 100 pF
(see Figure 19 and Figure 20)
|tPLH − tPHL| Differential Receiver Skew
tSKEW
100
ns
CRL = 15 pF, S1 closed
(see Figure 23 and Figure 24)
Enable Time to Low Level
Enable Time to High Level
Disable Time from Low Level
Disable Time from High Level
Maximum Data Rate
Time to Shutdown1
Driver Enable from Shutdown to Output High
Driver Enable from Shutdown to Output Low
tRZL
tRZL
tRLZ
tRHZ
fMAX
tDZH(SHDN) 50
tDZL(SHDN)
tRZL(SHDN)
25
25
25
25
50
50
50
50
ns
ns
ns
ns
kbps
ns
ns
ns
ns
CRL = 15 pF, S2 closed (see Figure 25)
CRL = 15 pF, S1 closed (see Figure 25)
CRL = 15 pF, S2 closed (see Figure 25)
tPLH, tPHL < 50% of data period
250
200
600
CL = 100 pF, S2 closed (see Figure 21)
CL = 100 pF, S1 closed (see Figure 22)
CL = 15 pF, S2 closed (see Figure 25)
CL = 15 pF, S1 closed (see Figure 25)
5000
5000
5000
Receiver Enable from Shutdown to Output High tRZH(SHDN)
1
RE
The ADM487E is put into shutdown mode by bringing the high and the DE low. If the inputs are in this state for less than 50 ns, the parts are guaranteed not to
enter shutdown. If the inputs are in this state for at least 600 ns, the ADM487E is guaranteed to enter shutdown.
Rev. 0 | Page 5 of 16
ASM485ꢁ/ASM487ꢁ/ASM±487ꢁ
ABEOLUTꢁ MAXIMUM RATINGE
TA = 25°C, unless otherwise noted.
Table 5.
Parameter
VCC to GND
Digital I/O Voltage (DE, RE)
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rating
−0.5 V to +6 V
−0.5 V to (VCC + 0.5 V)
−0.5 V to (VCC + 0.5 V)
−0.5 V to (VCC + 0.5 V)
−9 V to +14 V
Driver Input Voltage (DI)
Receiver Output Voltage (RO)
Driver Output/Receiver Input Voltage
(A, B)
Operating Temperature Range
Storage Temperature Range
θJA Thermal Impedance
ESD CAUTION
−40° to +85°C
−65° to +150°C
158°C/W
SOIC-8
Lead Temperature
Soldering (10 sec)
260°C
Rev. 0 | Page 6 of 16
ASM485ꢁ/ASM487ꢁ/ASM±487ꢁ
ꢂIN CONFIGURATION ANS FUNCTION SꢁECRIꢂTIONE
RO
RE
DE
DI
1
2
3
4
8
7
6
5
V
CC
ADM485E/
ADM487E/
ADM1487E
B
A
TOP VIEW
(Not to Scale)
GND
Figure 2. Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
2
3
RO
RE
Receiver Output. When enabled, if A > B by 200 mV, then RO = high. If A < B by 200 mV, then RO = low.
Receiver Output Enable. A low level enables the RO; a high level places it in a high impedance state.
DE
Driver Output Enable. A high level enables the driver differential outputs, Pin A and Pin B; a low level places it
in a high impedance state.
4
DI
Driver Input. When the driver is enabled, a Logic L = low on DI forces A low and B high; a Logic H = high on DI
forces Pin A high and Pin B low.
5
6
7
8
GND
A
B
Ground Connection (0 V).
Noninverting Receiver Input A/Driver Output A.
Inverting Receiver Input B/Driver Output B.
Power Supply (5 V 5%).
VCC
Rev. 0 | Page 7 of 16
ASM485ꢁ/ASM487ꢁ/ASM±487ꢁ
TYꢂICAL ꢂꢁRFORMANCꢁ CHARACTꢁRIETICE
50
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
45
40
35
30
25
20
15
10
5
I
= 8mA
RO
0
0
0.5
1.0
1.5
2.0
2.5
–40
–20
0
20
40
60
80
OUTPUT LOW VOLTAGE (V)
TEMPERATURE (°C)
Figure 3. Output Current vs. Receiver Output Low Voltage
Figure 6. Receiver Output Low Voltage vs. Temperature
–30
–25
–20
–15
–10
–5
45
40
35
30
25
20
15
10
5
0
1.5
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
OUTPUT HIGH VOLTAGE (V)
DIFFERENTIAL OUTPUT VOLTAGE (V)
Figure 4. Output Current vs. Receiver Output High Voltage
Figure 7. Driver Output Current vs. Differential Output Voltage
4.5
2.3
2.2
2.1
2.0
1.9
1.8
1.7
1.6
1.5
4.4
4.3
4.2
I
= –8mA
RO
4.1
4.0
3.9
–40
–20
0
20
40
60
80
–40
–20
0
20
40
60
80
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 5. Receiver Output High Voltage vs. Temperature
Figure 8. Driver Differential Output Voltage vs. Temperature
Rev. 0 | Page 8 of 16
ASM485ꢁ/ASM487ꢁ/ASM±487ꢁ
140
120
100
80
600
500
400
300
200
100
0
60
40
DE = V AND RE = X
CC
20
DE = 0 AND RE = Ø
40 60
TEMPERATURE (°C)
0
0
2
4
6
8
10
12
–40
–20
0
20
80
OUTPUT LOW VOLTAGE (V)
Figure 12. ADM487E Supply Current vs. Temperature
Figure 9. Output Current vs. Driver Output Low Voltage
10
9
8
7
6
5
4
3
2
1
0
–140
–120
–100
–80
–60
–40
–20
0
–60
–40
–20
0
20
40
60
80
100
–8
–6
–4
–2
0
2
4
6
TEMPERATURE (°C)
OUTPUT HIGH VOLTAGE (V)
Figure 10. Output Current vs. Driver Output High Voltage
Figure 13. Shutdown Current vs. Temperature
600
T
3
B
500
400
300
200
100
0
2
DE = V AND RE = X
CC
A
DE = 0 AND RE = X
1
R
O
CH1 5.00V CH2 500mV
CH3 500mV
M200ns
57.60%
A
CH1
2.80V
–40
–20
0
20
40
60
80
T
TEMPERATURE (°C)
Figure 11. ADM485E/ADM1487E Supply Current vs. Temperature
Figure 14. ADM487E Receiver tPHL
Rev. 0 | Page 9 of 16
ASM485ꢁ/ASM487ꢁ/ASM±487ꢁ
T
T
3
3
A
B
2
2
B
A
R
R
O
1
1
O
CH1 5.00V CH2 500mV
CH3 500mV
M200ns
60.80%
A
CH1
2.80V
CH1 5.00V CH2 500mV
CH3 500mV
M20ns
60.80%
A
CH1
2.70V
T
T
Figure 17. ADM485E/ADM1487E Receiver tPLH
Figure 15. ADM487E Receiver tPLH Driven by External RS-485 Device
T
3
A
2
B
R
O
1
CH1 5.00V CH2 500mV
CH3 500mV
M20ns
60.80%
A
CH1
2.70V
T
Figure 16. ADM485E/ADM1487E Receiver tPHL
Rev. 0 | Page 10 of 16
ASM485ꢁ/ASM487ꢁ/ASM±487ꢁ
TꢁET CIRCUITE ANS EWITCHING CHARACTꢁRIETICE
Y
R
L
V
CC
V
OD
R
= 500Ω
L
S1
0V OR 5V
OUT
V
D
OC
R
L
C
L
Z
Figure 18. Driver DC Test Load
GENERATOR
50Ω
V
DD
5V
0V
DE
DE
V
/2
C
C
CC
L
A
DI
V
R
L
tDZL,
tDZL(SHDN)
OD
tDLZ
B
V
CC
OUT
L
2.3V
0.5V
V
OL
Figure 19. Driver Timing Test Circuit
Figure 22. Driver Enable and Disable Times (tDZL, tDLZ, tDZL(SHDN)
)
RECEIVER
OUTPUT
B
A
V
ATE
ID
R
5V
DI
1.5V
0V
tDPLH
tDPHL
1/2 V
O
Figure 23. Receiver Propagation Delay Test Circuit
B
A
V
O
+1V
–1V
A
B
1/2V
O
V
= V (A) – V (B)
DIFF
tRPLH
tRPHL
V
O
V
80%
80%
DIFF
0V
–V
20%
20%
tDF
V
OH
O
RO
tDR
1.5V
V
OL
tSKEW
= tDPLH – tDPHL
THE RISE TIME AND FALL TIME OF INPUT A AND INPUT B < 4ns
Figure 24. Receiver Propagation Delays
Figure 20. Driver Propagation Delays
S1
0 OR 5V
D
OUT
C
L
R
= 500Ω
L
GENERATOR
50Ω
5V
0V
DE
1.5V
tDZH,
tDZH(SHDN)
0.5V
V
OH
OUT
2.3V
0V
tDHZ
Figure 21. Driver Enable and Disable Times (tDHZ, tDZH, tDZH(SHDN)
)
Rev. 0 | Page 11 of 16
ASM485ꢁ/ASM487ꢁ/ASM±487ꢁ
S1
S2
S3
+1.5V
–1.5V
V
CC
1kΩ
V
ID
0V OR 5V
C
L
15pF
GENERATOR
50Ω
S1 CLOSED
S2 OPEN
S3 = –1.5V
S1 OPEN
S2 CLOSED
S3 = +1.5V
+5V
0V
+5V
0V
RE
RO
RE
RO
+1.5V
tRZL, tRZL(SHDN)
tRZH, tRZH(SHDN)
V
V
OH
CC
OL
+1.5V
0V
+1.5V
V
S1 OPEN
S2 CLOSED
S3 = +1.5V
S1 CLOSED
S2 OPEN
S3 = +1.5V
+5V
0V
+5V
RE
RO
RE
RO
+1.5V
tRHZ
+1.5V
0V
tRLZ
V
V
CC
OL
V
OH
+0.5V
0V
+0.5V
Figure 25. Receiver Enable and Disable Times
Rev. 0 | Page 12 of 16
ASM485ꢁ/ASM487ꢁ/ASM±487ꢁ
THꢁORY OF OꢂꢁRATION
5V
5V
The ADM485E/ADM487E/ADM1487E are ruggedized RS-485
transceivers that operate from a single 5 V supply. They contain
protection against high levels of electrostatic discharge and are
ideally suited for operation in electrically harsh environments
or where cables can be plugged or unplugged. These devices are
intended for balanced data transmission and comply with TIA/
EIA standards RS-485 and RS-422. They contain a differential
line driver and a differential line receiver and are suitable for
half-duplex data transmission, as the driver and receiver share
the same differential pins.
0.1µF
0.1µF
V
DE
DI
V
CC
RE
RO
CC
B
A
B
A
ADM485E/
ADM487E/
ADM1487E
ADM485E/
ADM487E/
ADM1487E
RS485/RS-422 LINK
DI
RO
The input impedance on the ADM485E is 12 kΩ, allowing up
to 32 transceivers on the differential bus. The ADM487E/
ADM1487E are 48 kΩ, allowing up to 128 transceivers on the
differential bus.
DE
RE
GND
GND
Figure 26. Typical Half-Duplex Link Application
CIRCUIT DESCRIPTION
Table 7 and Table 8 show the truth tables for transmitting and
receiving.
The ADM485E/ADM487E/ADM1487E are operated from
a single 5 V 1ꢁꢀ power supply. Excessive power dissipation
caused by bus contention or output shorting is prevented by
a thermal shutdown circuit. If, during fault conditions, a sig-
nificant temperature increase is detected in the internal driver
circuitry, this feature forces the driver output into a high
impedance state.
Table 7. Transmitting Truth Table
Transmitting Inputs
Transmitting Outputs
A
RE
DE
DI
B
X1
X1
0
1
1
0
0
1
0
X1
X1
0
1
1
0
The receiver contains a fail-safe feature that results in a logic
high output state if the inputs are unconnected (floating).
High-Z
High-Z
High-Z
High-Z
1
1 X = don’t care.
A high level of robustness is achieved using internal protection
circuitry, eliminating the need for external protection compo-
nents such as tranzorbs or surge suppressors.
Table 8. Receiving Truth Table
Receiving Inputs
Receiving Outputs
RO
Low electromagnetic emissions are achieved using slew-rate-
limited drivers, minimizing both conducted and radiated
interference.
RE
DE
A to B
0
0
0
1
0
0
0
0
≥ +0.2 V
≤ −0.2 V
1
0
The ADM485E/ADM487E/ADM1487E can transmit at data
rates up to 25ꢁ kbps.
Inputs Open Circuit
X1
1
High-Z
1 X = don’t care.
A typical application for the ADM485E/ADM487E/ADM1487E
is illustrated in Figure 26, which shows a half-duplex link where
data can be transferred at rates up to 25ꢁ kbps. A terminating
resistor is shown at both ends of the link. This termination is
not critical, because the slew rate is controlled by the ADM485E/
ADM487E/ADM1487E and reflections are minimized.
ESD Transient Protection Scheme
The ADM485E/ADM487E/ADM1487E use protective clamping
structures on their inputs and outputs that clamp the voltage to
a safe level and dissipate the energy present in ESD (electrostatic).
The protection structure achieves ESD protection up to 15 kV
human body model (HBM).
The communications network can be extended to include
multipoint connections, as shown in Figure 29. As many as
32 ADM485E transceivers or 128 ADM487E/ADM1487E
transceivers can be connected to the bus.
Rev. 0 | Page 13 of 16
ASM485ꢁ/ASM487ꢁ/ASM±487ꢁ
ESD Testing
The ESD discharge can induce latch-up in the device under test.
Therefore, it is important that ESD testing on the I/O pins be
carried out while device power is applied. This type of testing
is more representative of a real-world I/O discharge where the
equipment is operating normally when the discharge occurs.
Two coupling methods are used for ESD testing: contact
discharge and air-gap discharge. Contact discharge calls for
a direct connection to the unit being tested; air-gap discharge
uses a higher test voltage but does not make direct contact with
the unit under test. With air discharge, the discharge gun is moved
toward the unit under test, developing an arc across the air gap;
hence the term air discharge. This method is influenced by
humidity, temperature, barometric pressure, distance, and rate
of closure of the discharge gun. The contact-discharge method,
though less realistic, is more repeatable and is gaining accep-
tance and preference over the air-gap method.
100%
90%
36.8%
10%
Although very little energy is contained within an ESD pulse,
the extremely fast rise time, coupled with high voltages, can
cause failures in unprotected semiconductors. Catastrophic
destruction can occur immediately as a result of arcing or heating.
Even if catastrophic failure does not occur immediately, the
device can suffer from parametric degradation, which can result
in degraded performance. The cumulative effects of continuous
exposure can eventually lead to complete failure.
TIME (t)
tDL
tRL
Figure 28. Human Body Model ESD Current Waveform
Table 9. ADM483E ESD Test Results
ESD Test Method
HIGH
I/O Pins
Other Pins
R2
VOLTAGE
GENERATOR
Human Body Model (HBM)
15 kV
3.5 V
DEVICE
UNDER TEST
C1
ESD TEST METHOD
HUMAN BODY MODEL
R2
C1
±15kV
100pF
Figure 27. ESD Generator
I/O lines are particularly vulnerable to ESD damage. Simply
touching or plugging in an I/O cable can result in a static
discharge that can damage or completely destroy the inter
face product connected to the I/O port. It is, therefore, extremely
important to have high levels of ESD protection on the I/O lines.
Rev. 0 | Page 14 of 16
ASM485ꢁ/ASM487ꢁ/ASM±487ꢁ
AꢂꢂLICATIONE INFORMATION
DIFFERENTIAL DATA TRANSMISSION
CABLE AND DATA RATE
The transmission line of choice for RS-485 communications is
a twisted pair. A twisted pair cable can cancel common-mode
noise and can also cause cancellation of the magnetic fields
generated by the current flowing through each wire, thereby
reducing the effective inductance of the pair.
Differential data transmission is used to reliably transmit data
at high rates over long distances and through noisy environ-
ments. Differential transmission nullifies the effects of ground
shifts and noise signals that appear as common-mode voltages
on the line. There are two main standards approved by TIA/EIA
that specify the electrical characteristics of transceivers used in
differential data transmission.
A typical application showing a multipoint transmission net-
work is illustrated in Figure 29. An RS-485 transmission line
can have as many as 32 transceivers on the bus. Only one driver
can transmit at a particular time, but multiple receivers can be
enabled simultaneously.
The RS-422 standard specifies data rates up to 1ꢁ MB and line
lengths up to 4ꢁꢁꢁ feet. A single driver can drive a transmission
line with up to 1ꢁ receivers.
RT
RT
To cater to true multipoint communications, the RS-485 standard
is defined. This standard meets or exceeds all the requirements
of RS-422, but also allows for up to 32 drivers and 32 receivers
to be connected to a single bus. An extended common-mode
range of −7 V to +12 V is defined. The most significant differ-
ence between RS-422 and RS-485 is that the drivers can be
disabled, thereby allowing as many as 32 drivers to be connected
to a single line. Only one driver is enabled at a time, but the
RS-485 standard contains additional specifications to guarantee
device safety in the event of line contention.
D
D
R
R
R
R
D
D
Figure 29. Typical RS-485 Network
Rev. 0 | Page 15 of 16
ASM485ꢁ/ASM487ꢁ/ASM±487ꢁ
OUTLINꢁ SIMꢁNEIONE
5.00 (0.1968)
4.80 (0.1890)
8
1
5
4
6.20 (0.2440)
5.80 (0.2284)
4.00 (0.1574)
3.80 (0.1497)
0.50 (0.0196)
0.25 (0.0099)
1.27 (0.0500)
BSC
45°
1.75 (0.0688)
1.35 (0.0532)
0.25 (0.0098)
0.10 (0.0040)
8°
0°
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
1.27 (0.0500)
0.40 (0.0157)
0.25 (0.0098)
0.17 (0.0067)
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MS-012-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 30. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
ORDERING GUIDE
Model
Temperature Range
Package Description
Package Option
ADM485EARZ1
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
8-Lead Standard Small Outline Package (SOIC_N)
8-Lead Standard Small Outline Package (SOIC_N)
8-Lead Standard Small Outline Package (SOIC_N)
8-Lead Standard Small Outline Package (SOIC_N)
8-Lead Standard Small Outline Package (SOIC_N)
8-Lead Standard Small Outline Package (SOIC_N)
R-8
R-8
R-8
R-8
R-8
R-8
ADM485EARZ-REEL71
ADM487EARZ1
ADM487EARZ-REEL71
ADM1487EARZ1
ADM1487EARZ-REEL71
1 Z = Pb-free part.
©2007 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06356-0-1/07(0)
Rev. 0 | Page 16 of 16
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