ADM2563EBRNZ-RL7_技术文档

3 kV RMS Signal and Power Isolated

RS-485 Transceiver with 15 kV IEC ESD

ADM2561E/ADM2563E/ADM2565E/ADM2567E

Data Sheet

FEATURES

GENERAL DESCRIPTION

3 kV rms isolated RS-485/RS-422 transceiver

The ADM2561E, ADM2563E, ADM2565E, and ADM2567E

Low radiated emissions, integrated, isolated dc-to-dc

converter

Passes EN 55032 Class B with margin on a 2-layer PCB

Cable invert smart feature

Correct reversed cable connection on A, B, Y, and Z bus

pins while maintaining full receiver fail-safe feature

ESD protection on RS-485 A, B, Y and Z pins

≥ 12 kV IEC61000-4-2 contact discharge

≥ 15 kV IEC61000-4-2 air discharge

High speed 25 Mbps data rate (ADM2565E/ADM2567E)

Low speed 500 kbps data rate for EMI control

(ADM2561E/ADM2563E)

are 3 kV rms signal and power isolated RS-485 transceivers.

These devices are designed for balanced transmission lines and

comply with ANSI/TIA/EIA-485-A-98 and ISO 8482:1987(E).

The devices pass radiated emissions testing to the EN 55032

Class B standard with margin on a 2-layer printed circuit board

(PCB) using two small external 0402 ferrites on isolated power

and ground pins. The device features an integrated, low electro-

magnetic interference (EMI), isolated dc-to-dc converter, which

eliminates the need for an external isolated power supply. The

isolation barrier provides immunity to system level electromag-

netic compatibility (EMC) standards. The family of isolator

devices features 12 kV contact and 15 kV air IEC61000-4-2

ESD protection on the RS-485 A, B, Y, and Z pins. The devices

also features cable invert pins, allowing the user to quickly

correct reversed cable connection on the A, B, Y, and Z bus

pins while maintaining full receiver fail-safe performance.

Flexible power supplies

Input V_CCsupply of 3 V to 5.5 V

Logic V_IOsupply of 1.7 V to 5.5 V

V_SELpin to select V_ISOsupply of 5 V (V_CC> 4.5 V) or 3.3 V

PROFIBUS compliant for 5 V V_ISO

Slew rate limited versions are available, which are optimized for

low speed over long cable runs, and have a maximum data rate

of 500 kbps. Half duplex and full duplex variants are available.

The full duplex generics allow independent cable inversion of

the driver and receiver for additional flexibility.

Wide operating temperature range: −40°C to +105°C

High common-mode transient immunity: 250 kV/µs

Short-circuit, open-circuit, and floating input receiver fail-safe

Supports 192 bus nodes (72 kΩ receiver input impedance)

Full hot swap support (glitch free power-up/power-down)

Safety and regulatory approvals (pending)

Table 18 shows the summary description of each generic.

CSA Component Acceptance Notice 5A, DIN V VDE V 0884-

11, UL 1577, CQC11-471543-2012, IEC 61010-1

Complies with ANSI/TIA/EIA-485-A-98 and ISO 8482:1987(E)

28-lead, fine pitch SOIC_W package (10.15 mm × 10.05 mm)

with >8.0 mm creepage and clearance

APPLICATIONS

Heating, ventilation, and air conditioning (HVAC) networks

Industrial field buses

Building automation

Utility networks

Energy meters

Rev. B

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rights of third parties that may result from its use. Specifications subject to change without notice.

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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Technical Support

www.analog.com

ADM2561E/ADM2563E/ADM2565E/ADM2567E

Data Sheet

TABLE OF CONTENTS

Features.............................................................................................. 1

Robust Low Power Digital Isolator.......................................... 20

High Driver Differential Output Voltage............................... 20

IEC61000-4-2 ESD Protection ................................................. 20

Truth Tables................................................................................ 21

Receiver Fail-Safe ....................................................................... 22

Driver And Receiver Cable Inversion ..................................... 22

Hot Swap Inputs......................................................................... 22

192 Transceivers on the Bus ..................................................... 23

Driver Output Protection ......................................................... 23

1.7 V To 5.5 V V_IOLogic Supply .............................................. 23

Applications Information ............................................................. 24

PCB Layout and Electromagnetic Interference (EMI) ......... 24

Device Power-Up ....................................................................... 24

Maximum Data Rate vs. Ambient Temperature ................... 24

Isolated PROFIBUS Solution ................................................... 25

EMC, EFT, and Surge................................................................ 25

Insulation Lifetime..................................................................... 25

Typical Applications.................................................................. 26

Outline Dimensions....................................................................... 28

Ordering Guide .......................................................................... 28

Applications ...................................................................................... 1

General Description......................................................................... 1

Revision History ............................................................................... 2

Functional Block Diagrams............................................................. 3

Specifications .................................................................................... 4

Timing Specifications .................................................................. 6

Package Characteristics ............................................................... 9

Regulatory Information............................................................... 9

Insulation and Safety Related Specifications............................ 9

DIN VDE V 0884-11 (VDE V 0884-11) Insulation

Characteristics (Pending).......................................................... 10

Absolute Maximum Ratings ......................................................... 11

Thermal Resistance.................................................................... 11

Electrostatic Discharge (ESD) Ratings.................................... 11

ESD Caution................................................................................ 11

Pin Configurations and Function Descriptions......................... 12

Typical Performance Characteristics........................................... 14

Test Circuits .................................................................................... 19

Theory of Operation ...................................................................... 20

Low EMI Integrated DC-to-DC Converter............................ 20

REVISION HISTORY

8/2020—Rev. A to Rev. B

6/2020—Rev. 0 to Rev. A

Changed ADM2565E Status and ADM2567E Status from

Pending to Released ............................................................Throughout

Changes to Features Section and General Description Section.......1

Changes to Table 5...................................................................................9

Changes to 192 Transceivers on the Bus Section....................... 23

Changes to Ordering Guide.......................................................... 28

Deleted Pending Products Section and Table 22....................... 29

Changes to General Description Section .......................................1

Changes to DIN VDE V 0884-11 (VDE V 0884-11) Insulation

Characteristics (Pending) Section................................................ 10

Changes to Table 8......................................................................... 11

Added Electrostatic Discharge (ESD) Ratings Section, ESD

Ratings for ADM2561E/ADM2563E/ADM2565E/ADM2567E

Section, and Table 11; Renumbered Sequentially...................... 11

Changes to Ordering Guide.......................................................... 28

Changes to Table 21....................................................................... 29

5/2020—Revision 0: Initial Version

Rev. B | Page 2 of 28

Data Sheet

ADM2561E/ADM2563E/ADM2565E/ADM2567E

FUNCTIONAL BLOCK DIAGRAMS

V

CC

V

ISOIN

ISOOUT

OSCILLATOR

RECTIFIER

REGULATOR

LOW RADIATED

EMISSIONS DC-TO-DC

V

IO

DIGITAL ISOLATOR

iCoupler

RS-485

TRANSCEIVER

RE

A

B

CABLE

R

DECODE

ENCODE

DECODE

RxD

INVERT

INVR

INVD

TxD

Z

Y

D

DE

ADM2563E/ADM2567E

GND

ISOLATION

BARRIER

ISO

GND

2

1

Figure 1. ADM2563E/ADM2567E

V

CC

V

ISOIN

ISOOUT

OSCILLATOR

RECTIFIER

REGULATOR

LOW RADIATED

EMISSIONS DC-TO-DC

V

IO

DIGITAL ISOLATOR

iCoupler

RS-485

TRANSCEIVER

RE

DECODE

ENCODE

DECODE

R

RxD

B

CABLE

INVERT

DE

TxD

INV

A

D

ADM2561E/ADM2565E

GND

ISOLATION

BARRIER

ISO

GND

2

1

Figure 2. ADM2561E/ADM2565E

Rev. B | Page 3 of 28

ADM2561E/ADM2563E/ADM2565E/ADM2567E

SPECIFICATIONS

Data Sheet

All voltages are relative to their respective ground: 3.0 V ≤ V_CC≤ 5.5 V, 1.7 V ≤ V_IO≤ 5.5 V, T_MIN(−40°C) to T_MAX(+105°C). All minimum

and maximum specifications apply over the entire recommended operation range, unless otherwise noted. All typical specifications are at

T_A= 25°C, V_CC= V_IO= 5 V, V_ISOOUToutput voltage (V_ISO) = 3.3 V (V_SEL= GND_ISO), unless otherwise noted. All parameters are

characterized with a BLM15HD182SN1 ferrite bead between the V_ISOOUTand V_ISOINpins, and between the GND_ISOand GND₂pins.

Table 1.

Parameter

Symbol Min

Typ

Max

Unit

Test Conditions/Comments

PRIMARY SUPPLY CURRENT

V_CCSupply Current—Unloaded I_CC

21

28

20

26

0.65

5

46

48

53

51

0.9

8

mA

V_SEL= GND_ISO(DE = 0 V)

V_CC≥ 4.5 V, V_SEL= V_ISO(DE =0 V)

V_SEL= GND_ISO(DE = V_IO)

V_CC≥ 4.5 V, V_SEL= V_ISO(DE = V_IO)

DE = 0 V

V_IOLogic Supply Current

I_IO

DE = V_IO

ISOLATED SUPPLY CURRENT

ADM2561E/ADM2563E

(Data Rate = 500 kbps)

ADM2565E/ADM2567E

(Data Rate = 25 Mbps )

I_ISOIN

50

55

75

V_ISOIN= 3 V to 3.465 V, 54 Ω between Y and Z

mA

ISOLATED DC-TO-DC CONVERTER

V_ISOOUTOutput Voltage

V_ISO

3

3.3

5.0

3.465

5.25

V

_SEL= GND_ISO, I_ISOOUT= 10 mA minimum to 55 mA

maximum¹

4.5

90

V

V_CC≥ 4.5 V, V_SEL= V_ISO, I_ISOOUT= 10 mA minimum to

90 mA maximum¹

Output Current Available from I_ISOOUT

V_ISOOUTSupply Pin

mA

V_CC≥ 4.5 V, V_SEL= V_ISO, V_ISO≥ 4.5 V

V_CCMinimum Start-Up Voltage

Start-Up Time

V_START

t_START

3.135

V

ms

DE = GND₁, see the Device Power-Up section

10

DRIVER

Differential Output Voltage

Loaded

|V_OD2

|

2.0

2.4

V_ISO

V

V_CC≥ 3.0 V, V_SEL= GND_ISO, R_L= 100 Ω, see Figure 40

1.5

2.1

1.5

2

3.1

1.9

V_ISO

V

V_CC≥ 3.0 V, V_SEL= GND_ISO, R_L= 54 Ω, see Figure 40

V_CC≥ 4.5 V, V_SEL= V_ISO, R_L= 54 Ω, see Figure 40

V_CC≥ 3.0 V, V_SEL= GND_ISO, −7 V ≤ common-mode

voltage (V_CM) ≤ 12 V, see Figure 41

Over Common-Mode Range |V_OD3

|

2.1

3.1

1.5

V_ISO

0.2

V

V_CC≥ 4.5 V, V_SEL= V_ISO, −7 V ≤ V_CM≤ 12 V, see Figure 41

R_L= 54 Ω or 100 Ω, see Figure 40

Δ|V_OD2| for Complementary

Output States

Δ|V_OD2|

Common-Mode Output Voltage V_OC

3.0

0.2

V

R_L= 54 Ω or 100 Ω, see Figure 40

Δ|V_OC| for Complementary

Output States

Δ|V_OC|

Short-Circuit Output Current

Output Leakage Current (Y, Z)²

I_OS

I_O

−250

−50

+250

50

mA

µA

pF

−7 V ≤ output voltage (V_O) ≤ +12 V

1

DE = RE = 0 V, V_CC= 0 V or 5.5 V, V_IN= 12 V

DE = RE = 0 V, V_CC= 0 V or 5.5 V, V_IN= −7 V

Input voltage (V_IN) = 0.4sin(10πt × 10⁶)

10

28

Pin Capacitance (A, B, Y, Z)

C_IN

RECEIVER

Differential Input Threshold

Voltage, Noninverted

Differential Input Threshold

Voltage, Inverted

Input Voltage Hysteresis

Input Current (A, B)

V_TH

−200

30

−125 −30

mV

−7 V ≤ V_CM≤ +12 V, INV/INVR = 0 V

−7 V ≤ V_CM≤ +12 V, INV/INVR = V_IO

125

25

200

167

V_HYS

I_I

mV

µA

pF

−7 V ≤ V_CM≤ +12 V

DE = 0 V, V_CC= powered/unpowered, V_IN= 12 V

DE = 0 V, V_CC= powered/unpowered, V_IN= −7 V

Input voltage (V_IN) = 0.4sin(10πt × 10⁶)

−133

Pin Capacitance (A, B)

C_IN

4

Rev. B | Page 4 of 28

Data Sheet

ADM2561E/ADM2563E/ADM2565E/ADM2567E

Parameter

Symbol Min

Typ

Max

Unit

Test Conditions/Comments

DIGITAL LOGIC INPUTS

Input Low Voltage

Input High Voltage

Input Leakage Current

V_IL

0.3 × V_IO

V

DE, RE, TxD, INV, INVR, INVD

DE, RE, TxD, V_IN= 0 V or V_IO

INV, INVR, INVD, V_IN= 0 V or V_IO

V_IH

I_I

0.7 × V_IO

V

−1

0.1

10

2

µA

30

RxD DIGITAL OUTPUT

Output Low Voltage

V_OL

0.4

V

V_IO= 3.6 V, output current (I_OUT) = 2.0 mA, differential

input voltage (V_ID) ≤ −0.2 V

0.4

0.2

V

mA

µA

V_IO= 2.7 V, I_OUT= 1.0 mA, V_ID≤ −0.2 V

V_IO= 1.95 V, I_OUT= 500 µA, V_ID≤ −0.2 V

V_IO= 3.0 V, I_OUT= −2.0 mA, V_ID≥ −0.03 V

V_IO= 2.3 V, I_OUT= −1.0 mA, V_ID≥ −0.03 V

V_IO= 1.7 V, I_OUT= −500 µA, V_ID≥ −0.03 V

V_O= 0 V or V_IO, RE = 0 V

Output High Voltage

Short-Circuit Current

V_OH

2.4

2.0

V_IO− 0.2

100

Three-State Output Leakage

Current

I_OZR

−1

+0.01 +1

RE = V_IO, RxD = 0 V or V_IO

COMMON-MODE TRANSIENT

IMMUNITY³

CMTI

250

kV/µs

V

_CM≥ 1 kV, transient magnitude measured at between

20% and 80% of V_CM, see Figure 46 and Figure 47

¹These parameters include the voltage drop across the dc resistance of the BLM15HD182SN1 ferrite beads.

²The ADM2563E and ADM2567E only.

³CMTI is the maximum common-mode voltage slew rate that can be sustained while maintaining specification compliant operation. V_CMis the common-mode

potential difference between the logic and bus sides. The transient magnitude is the range over which the common mode is slewed. The common-mode voltage slew

rates apply to both rising and falling common-mode voltage edges.

Rev. B | Page 5 of 28

ADM2561E/ADM2563E/ADM2565E/ADM2567E

Data Sheet

TIMING SPECIFICATIONS

ADM2565E/ADM2567E

All minimum and maximum specifications apply over the entire recommended operation range, V_CC= 3.0 V to 5.5 V, V_IO= 1.7 V to 5.5

V, T_A= T_MIN(−40°C) to T_MAX(+105°C). All typical specifications are at T_A= 25°C, V_CC= V_IO= 5 V, V_ISO= 3.3 V (V_SEL= GND_ISO). All

parameters are characterized with a BLM15HD182SN1 ferrite bead between the V_ISOOUTand V_ISOINpins, and between the GND_ISOand

GND₂pins.

Table 2.

Parameter

Symbol

Min Typ

Max Unit

Test Conditions/Comments

DRIVER

Maximum Data Rate

Propagation Delay

Output Skew

Rise Time/Fall Time

Enable Time

25

18

1.5

4.5

25

20

Mbps

t_DPLH, t_DPHL

t_SKEW

t_DR, t_DF

t_ZL, t_ZH

t_LZ, t_HZ

25

5

10

40

ns

R_L= 54 Ω, C_L1= C_L2= 100 pF, see Figure 3 and Figure 42

R_L= 110 Ω, C_L= 50 pF, see Figure 5 and Figure 43

Disable Time

RECEIVER

Propagation Delay

Output Skew

Enable Time

t_RPLH, t_RPHL

t_SKEW

t_ZL, t_ZH

t_LZ, t_HZ

32

2

4

50

6

25

ns

C_L= 15 pF, see Figure 4 and Figure 44

R_L= 1 kΩ, C_L= 15 pF, see Figure 6 and Figure 45

Disable Time

8

RECEIVER CABLE INVERT, INVR

Propagation Delay

High to Low

t_INVRPHL

t_INVRPLH

25

35

ns

V_ID≥ +200 mV or V_ID≤ −200 mV, see Figure 7

Low to High

DRIVER CABLE INVERT, INVD

Propagation Delay

High to Low

t_INVDPHL

t_INVDPLH

18

25

ns

TxD = 0 V or TxD = V_IO, see Figure 8

Low to High

ADM2561E/ADM2563E

All minimum and maximum specifications apply over the entire recommended operation range, V_CC= 3.0 V to 5.5 V, V_IO= 1.7 V to 5.5

V, T_A= T_MIN(−40°C) to T_MAX(+105°C). All typical specifications are at T_A= 25°C, V_CC= V_IO= 5 V, V_ISO= 3.3 V (V_SEL= GND_ISO).

Table 3.

Parameter

Symbol

Min

Typ Max

Unit

Test Conditions/Comments

DRIVER

Maximum Data Rate

Propagation Delay

Output Skew

Rise Time/Fall Time

Enable Time

500

kbps

ns

t_DPLH, t_DPHL

t_SKEW

t_DR, t_DF

t_ZL, t_ZH

t_LZ, t_HZ

220

5

280

130

800

400

100

600

R_L= 54 Ω, C_L1= C_L2= 100 pF, see Figure 3 and Figure 42

R_L= 110 Ω, C_L= 50 pF, see Figure 5 and Figure 43

200

ns

1000 ns

2000 ns

Disable Time

RECEIVER

Propagation Delay

Output Skew

Enable Time

t_RPLH, t_RPHL

t_SKEW

t_ZL, t_ZH

t_LZ, t_HZ

35

2

10

200

50

100

ns

C_L= 15 pF, see Figure 4 and Figure 44

R_L= 1 kΩ, C_L= 15 pF, see Figure 6 and Figure 45

Disable Time

RECEIVER CABLE INVERT, INVR

Propagation Delay

High to Low

t_INVRPHL

t_INVRPLH

25

200

ns

V_ID≥ +200 mV or V_ID≤ −200 mV, see Figure 7

Low to High

DRIVER CABLE INVERT, INVD

Propagation Delay

High to Low

t_INVDPHL

t_INVDPLH

220

400

ns

TxD = 0 V or TxD = V_IO, see Figure 8

Low to High

Rev. B | Page 6 of 28

Data Sheet

ADM2561E/ADM2563E/ADM2565E/ADM2567E

Timing Diagrams

V

IO

V

/2

V

/2

IO

0V

Z

t_DPLH

t_DPHL

t

= │t

– t

DPHL

│

1/2V

SKEW

DPLH

O

V

O

Y

+V

O

90% POINT

V

= V – V

(Y) (Z)

DIFF

V

DIFF

10% POINT

–V

O

t_DF

t_DR

NOTES

1. Y = A, Z = B FOR ADM2561E/ADM2565E

Figure 3. Driver Propagation Delay, Rise/Fall Timing (See Figure 42 for Test Circuit)

A – B

0V

t_RPHL

t_RPLH

V

OH

0.5V

IO

RxD

t_SKEW

= |t_RPLH– t_RPHL|

OL

Figure 4. Receiver Propagation Delay (See Figure 44 for Test Circuit)

V

IO

0.5V

t_ZL

0.5V

IO

DE

0V

t_LZ

0.5 (V

+ V

)

ISOIN

OL

Y, Z

V

+ 0.5V

– 0.5V

OL

V

OL

t_ZH

t_HZ

V

OH

Y, Z

OH

0.5 V

OH

NOTES

1. Y = A, Z = B FORADM2561E/ADM2565E

Figure 5. Driver Enable or Disable Timing (See Figure 43 for Test Circuit)

Rev. B | Page 7 of 28

ADM2561E/ADM2563E/ADM2565E/ADM2567E

Data Sheet

V

IO

RE

0.5V

t_ZL

0.5V

IO

0V

t_LZ

0.5V

IO

RxD

V

+ 0.5V

OL

OUTPUT LOW

V

OL

t_HZ

t_ZH

OUTPUT HIGH

IO

OH

V

– 0.5V

RxD

0V

OH

0.5V

Figure 6. Receiver Enable or Disable Timing (See Figure 45 for Test Circuit)

V

IO

INVR

0.5V

IO

0V

t_INVRPHL

t_INVRPLH

V

OH

0.5V

IO

RxD (V ≥ +200 mV)

ID

V

OL

V

OH

RxD (V ≤ –200 mV)

ID

0.5V

IO

V

OL

NOTES

1. INVR = INV FOR ADM2561E/ADM2565E

Figure 7. Receiver Cable Invert Timing

V

IO

INVD

0.5V

IO

t_INVDPLH

t_INVDPHL

Z

1/2|V

|

|V

|

O

OD

TxD = 0

Y

1/2|V

|

|V

|

O

OD

TxD = 1

Z

NOTES

1. INVD = INV, Y = A, Z = B FORADM2561E/ADM2565E

Figure 8. Driver Cable Invert Timing

Rev. B | Page 8 of 28

Data Sheet

ADM2561E/ADM2563E/ADM2565E/ADM2567E

PACKAGE CHARACTERISTICS

Table 4.

Parameter

Symbol

R_I-O

C_I-O

Min

Typ

10¹³

2.2

Max

Unit

Ω

pF

Test Conditions/Comments

Resistance (Input to Output)¹

Capacitance (Input to Output)¹

Input Capacitance²

f = 1 MHz

Input capacitance

C_I

3.0

pF

¹Device considered a 2-terminal device: short together Pin 1 to Pin 14 and short together Pin 15 to Pin 28.

²Input capacitance is from any input data pin to ground.

REGULATORY INFORMATION

For additional information, see www.analog.com/icouplersafety.

Table 5. ADM2561E/ADM2563E/ADM2565E/ADM2567E Approvals

UL (Pending)

CSA (Pending)

VDE (Pending)

To be certified under DIN V VDE 0884-11²

CQC (Pending)

Recognized Under UL 1577

Component Recognition

Program¹

Approved under CSA Component

Acceptance Notice 5A

Certified under

CQC11-471543-2012

Single Protection, 3 kV rms

CSA 62368-1-14, EN 62368-1:2014/A11:2017

and IEC 62368-1:2014 second edition:

Basic insulation:

GB4943.1-2011:

Basic insulation at 800 V rms (1131 V peak)

Working voltage (V_IOWM) = 400 V rms

Basic insulation at

800 V rms (1131 V peak)

Reinforced insulation at 400 V rms

(565 V peak)

Repetitive maximum voltage (V_IORM) =

565 V peak

Reinforced insulation at

400 V rms (565 V peak)

IEC 60601-1 Edition 3.1:

Surge isolation voltage (V_IOSM) = 10 kV peak

1 means of patient protection (MOPP),

250 V rms (354 V peak)

Highest allowable overvoltage (V_IOTM) =

8000 V peak)

CSA 61010-1-12 and IEC 61010-1 third edition:

Reinforced insulation:

Basic insulation at 300 V rms mains, 800 V

rms (1131 V peak) from secondary circuit

Working voltage (V_IOWM) =

330 V rms

Reinforced insulation at 300 V rms mains,

Repetitive maximum voltage (V_IORM) =

400 V rms (565 V peak) from secondary circuit 466 V peak

Surge isolation voltage (V_IOSM) = 6.25 kV

peak

Highest allowable overvoltage (V_IOTM) =

8000 V peak)

File (Pending)

File 205078 (basic, reinforced pending)

File (pending)

¹In accordance with UL 1577, each ADM2561E/ADM2563E/ADM2565E/ADM2567E is proof tested by applying an insulation test voltage ≥ 3600 V rms for 1 sec.

²In accordance with DIN V VDE 0884-11, each ADM2561E/ADM2563E/ADM2565E/ADM2567E is proof tested by applying an insulation test voltage ≥ 1060 V peak for

1 sec (partial discharge detection limit = 5 pC).

INSULATION AND SAFETY RELATED SPECIFICATIONS

Table 6. Critical Safety Related Dimensions and Material Properties

Parameter

Symbol Value

Unit

Test Conditions/Comments

Rated Dielectric Insulation Voltage

Minimum External Air Gap (Clearance)

3

kV rms

mm

1-minute duration

Measured from input terminals to output terminals,

shortest distance through air

Measured from input terminals to output terminals,

shortest distance along body

Measured from input terminals to output terminals,

shortest distance through air, line of sight, in the

PCB mounting plane

L(I01)

L(I02)

L (PCB)

8.3

8.1

Minimum External Tracking (Creepage)

mm

Minimum Clearance in the Plane of the Printed

Circuit Board (PCB Clearance)

Minimum Internal Gap (Internal Clearance)

22

µm min Insulation distance through insulation

Tracking Resistance (Comparative Tracking Index) CTI

Material Group

>600

I

V

DIN IEC 112/VDE 0303 Part 1

Material Group (DIN VDE 0110: 1989-01, Table 1)

Rev. B | Page 9 of 28

ADM2561E/ADM2563E/ADM2565E/ADM2567E

Data Sheet

DIN VDE V 0884-11 (VDE V 0884-11) INSULATION CHARACTERISTICS (PENDING)

The ADM2561E/ADM2563E/ADM2565E/ADM2567E are suitable for reinforced electrical isolation only within the safety limit data.

Maintenance of the safety data must be ensured by means of protective circuits. The asterisk (*) marking on packages denotes DIN VDE

V 0884-11 approval.

Table 7.

Test Conditions/Comments

Description

Symbol Characteristic

Unit

CLASSIFICATIONS

Installation Classification per DIN VDE V 0110 for

Rated Mains Voltage

≤150 V rms

I to IV

≤300 V rms

I to II

≤400 V rms

I

Climatic Classification

Pollution Degree

40/105/21

2

Per DIN VDE V 0110, Table 1

VOLTAGE

Maximum Working Insulation Voltage

Maximum Repetitive Peak Insulation Voltage

Input to Output Test Voltage

Method b1

V_IOWM

V_IORM

V_PR

400

565

V rms

V peak

V_IORM× 1.875 = V_PR, 100% production tested,

t_m= 1 sec, partial discharge < 5 pC

1060

V peak

Method a

After Environmental Tests, Subgroup 1

V_IORM× 1.5 = V_{pd (m)}, t_ini= 60 sec, t_m= 10 sec, partial

discharge < 5 pC

V_IORM× 1.2 = V_{pd (m)}, t_ini= 60 sec, t_m= 10 sec, partial

discharge < 5 pC

848

678

V peak

After Input and/or Safety Test,

Subgroup 2/Subgroup 3

Highest Allowable Overvoltage

Surge Isolation Voltage, Basic

Transient overvoltage, t_TR= 10 sec

Peak voltage (V_PEAK) = 10 kV, 1.2 µs rise time, 50 µs,

50% fall time

V_IOTM

V_IOSM

8000

10,000

V peak

Surge Isolation Voltage, Reinforced

SAFETY LIMITING VALUES

Case Temperature

Total Power Dissipation at T_A= 25°C

Insulation Resistance at T_S

3.0

V_PEAK= 10 kV, 1.2 µs rise time, 50 µs, 50% fall time

Maximum value allowed in the event of a failure

V_IOSM

6250

V peak

T_S

P_S

R_S

150

2.87

>10⁹

°C

W

Ω

V_IO= 500 V

2.7

2.4

2.1

1.8

1.5

1.2

0.9

0.6

0.3

0

50

100

150

AMBIENT TEMPERATURE (°C)

Figure 9. Thermal Derating Curve for 28-Lead Standard Small Outline,

Wide Body, with Finer Pitch (SOIC_W_FP), Dependence of Safety Limiting

Values with Ambient Temperature per DIN VDE V 0884-11

Rev. B | Page 10 of 28

Data Sheet

ADM2561E/ADM2563E/ADM2565E/ADM2567E

ABSOLUTE MAXIMUM RATINGS

T_A= 25°C, unless otherwise noted. All voltages are relative to

their respective ground.

Table 10. Maximum Continuous Working Voltage^{1, 2}

Parameter

Max Unit

Reference Standard

Table 8.

AC Voltage

Parameter

Rating

Bipolar Waveform

Basic Insulation

V_CCto GND₁

V_IOto GND₁

Digital Input Voltage (DE, RE, TxD, INV,

INVR, INVD) to GND₁

Digital Output Voltage (RxD) to GND₁

−0.5 V to +6.0 V

−0.5 V to +7.0 V

−0.3 V to V_IO+ 0.3 V

565

V peak 50-year minimum

lifetime

V peak 50-year minimum

lifetime

Reinforced Insulation 565

Unipolar Waveform

−0.3 V to V_IO+ 0.3 V

−9 V to +14 V

Basic Insulation

1131 V peak 50-year minimum

lifetime

Driver Output/Receiver Input Voltage

(A, B, Y, Z) to GND₂

Reinforced Insulation 1131 V peak 50-year minimum

lifetime

DC Voltage

V_SELto GND₂

−0.5 V to +7.0 V

−40°C to +105°C

−55°C to +150°C

Operating Temperature Range

Storage Temperature Range

Lead Temperature

Soldering (10 sec)

Vapor Phase (60 sec)

Infrared (15 sec)

Basic Insulation

565

V dc

50-year minimum

lifetime

50-year minimum

lifetime

260°C

215°C

220°C

Reinforced Insulation 565

¹Refers to continuous voltage magnitude imposed across the isolation

barrier. See the Insulation Lifetime section for more details.

²Values quoted for Material Group I, Pollution Degree II.

Stresses at or above those listed under Absolute Maximum

Ratings may cause permanent damage to the product. This is a

stress rating only; functional operation of the product at these

or any other conditions above those indicated in the

operational section of this specification is not implied.

Operation beyond the maximum operating conditions for

extended periods may affect product reliability.

ELECTROSTATIC DISCHARGE (ESD) RATINGS

The following ESD information is provided for handling of

ESD sensitive devices in an ESD protected area only.

Human body model (HBM) per ANSI/ESDA/JEDEC JS-001.

Charged device model (CDM) per ANSI/ESDA/JEDEC JS-002.

THERMAL RESISTANCE

International Electrotechnical Commission (IEC) electromagnetic

compatibility: Part 4-2 (IEC) per IEC 61000-4-2.

Thermal performance is directly linked to PCB design and

operating environment. Careful attention to PCB thermal

design is required.

ESD Ratings for ADM2561E/ADM2563E/

ADM2565E/ADM2567E

θ_JAis the natural convection junction to ambient thermal

resistance measured in a one cubic foot sealed enclosure.

Table 11. ADM2561E/ADM2563E/ADM2565E/ADM2567E,

28-Lead SOIC_W_FP

Table 9. Thermal Resistance

ESD Model

Withstand Threshold (kV)

Class

Package Type

θ_JA

Unit

HBM

4

3A

RN-28-1¹

43.45

°C/W

CDM

IEC¹

1.25

C5

¹Thermal impedance simulated values are based on JEDEC 2S2P thermal test

board with no bias. See JEDEC JESD-51.

12 (contact discharge) to GND₂

15 (air discharge) to GND₂

8 (across isolation barrier) to GND₁

Level 4

Level 4²

¹Pin A, Pin B, Pin Y, and Pin Z only.

²Limited by clearance across isolation barrier.

ESD CAUTION

Rev. B | Page 11 of 28

ADM2561E/ADM2563E/ADM2565E/ADM2567E

Data Sheet

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

1

2

28

27

26

25

24

23

22

21

20

19

18

17

16

15

GND

ISO

1

V

1

SEL

GND

3

1

ISO

4

V

ISOOUT

CC

5

GND

V

1

ISO

6

ADM2561E/

ADM2565E

1

ISOIN

7

V

GND

NIC

B

IO

2

TOP VIEW

8

RxD

RE

(Not to Scale)

9

10

DE

TxD 11

12

13

INV

NIC

A

GND

2

GND 14

1

NIC = NOT INTERNALLY CONNECTED

Figure 10. ADM2561E/ADM2565E Pin Configuration

Table 12. ADM2561E/ADM2565E Pin Function Descriptions

Pin No.

Mnemonic

Description

1, 2, 3, 5, 6, 14

4

GND₁

V_CC

Ground 1, Logic Side.

3.0 V to 3.6 V, or 4.5 V to 5.5 V Logic Side Power Supply. It is recommended that a 10 µF and a 0.1 µF

decoupling capacitor be connected between V_CCand GND₁(Pin 1, Pin 2, and Pin 3).

7

8

V_IO

1.7 V to 5.5 V Logic Side Flexible I/O Supply. It is recommended that a 0.1 µF decoupling capacitor be

connected between V_IOand GND₁(Pin 5 and Pin 6).

Receiver Output Data. When the INV pin is logic low, this output is high when (A − B) ≥ −30 mV and low

when (A − B) ≤ −200 mV. When the INV pin is high, this output is high when (A − B) ≤ 30 mV and low

when (A − B) ≥ 200 mV. This output is tristated when the receiver is disabled by driving the RE pin high.

RxD

9

RE

Receiver Enable Input. This pin is an active low input. Driving this input low enables the receiver, and

driving it high disables the receiver.

10

11

12

DE

Driver Output Enable. A high level on this pin enables the driver differential outputs, Y and Z. A low level

places these outputs in a high impedance state.

Transmit Data Input. Data to be transmitted by the driver is applied to this input. When the INV pin is

logic high, the data applied to this input is inverted.

Inversion Enable. This pin is active high input. Driving this pin high inverts the TxD signal applied and

inverts the A and B receiver inputs.

TxD

INV

13, 19, 20

15, 16, 21, 22

17

18

23

NIC

GND₂

A

B

V_ISOIN

Not Internally Connected. This pin is not internally connected.

Isolated Ground 2 for the Integrated RS-485 Transceiver, Bus Side.

Noninverting Driver Output/Receiver Input.

Inverting Driver Output/Receiver Input.

Isolated Power Supply Input. This pin must be connected externally to V_ISOOUT(Pin 25) through one

BLM15HD182SN1 ferrite. It is recommended that a reservoir capacitor of 10 µF and a 0.1 µF decoupling

capacitor be connected between V_ISOIN(Pin 23) and GND₂(Pin 21).

24, 26

25

GND_ISO

V_ISOOUT

Isolated Power Supply Ground. These pins must be connected externally to Pin 28.

Isolated Power Supply Output. This pin must be connected externally to V_ISOIN(Pin 23) through one

BLM15HD182SN1 ferrite. It is recommended that a decoupling capacitor of 0.1 µF be connected

between V_ISOOUTand GND_ISO(Pin 28).

27

28

V_SEL

Output Voltage Selection. When V_SEL= V_ISO, the V_ISOset point is 5.0 V. When V_SEL= GND_ISO, the V_ISOset

point is 3.3 V.

Isolated Power Supply Ground. This pin must be connected externally to GND₂(Pin 22) through one

BLM15HD182SN1 ferrite.

GND_ISO

Rev. B | Page 12 of 28

Data Sheet

ADM2561E/ADM2563E/ADM2565E/ADM2567E

1

2

28

27

26

25

24

23

22

21

20

19

18

17

16

15

GND

ISO

1

V

SEL

GND

3

1

ISO

4

V

ISOOUT

CC

5

GND

V

1

ISO

6

ADM2563E/

ADM2567E

ISOIN

7

V

GND

A

IO

2

TOP VIEW

8

RxD

RE

(Not to Scale)

9

10

DE

B

TxD 11

Z

12

13

INVD

INVR

Y

GND

2

GND 14

1

Figure 11. ADM2563E/ADM2567E Pin Configuration

Table 13. ADM2563E/ADM2567E Pin Function Descriptions

Pin No.

Mnemonic Description

1, 2, 3, 5, 6, 14

4

GND₁

V_CC

Ground 1, Logic Side.

3.0 V to 3.6 V, or 4.5 V to 5.5 V Logic Side Power Supply. It is recommended that a 10 µF and a 0.1 µF

decoupling capacitor be connected between V_CCand GND₁(Pin 1, Pin 2, and Pin 3).

7

8

V_IO

1.7 V to 5.5 V Logic Side Flexible Input/Output (I/O) Supply. It is recommended that a 0.1 µF decoupling

capacitor be connected between V_IOand GND₁(Pin 5 and Pin 6).

Receiver Output Data. When the INVR pin is logic low, this output is high when (A − B) ≥ −30 mV and low

when (A − B) ≤ −200 mV. When the INVR pin is high, this output is high when (A − B) ≤ 30 mV and low

when (A − B) ≥ 200 mV. This output is tristated when the receiver is disabled by driving the RE pin high.

RxD

9

RE

Receiver Enable Input. This pin is an active low input. Driving this input low enables the receiver, and

driving it high disables the receiver.

10

11

DE

TxD

Driver Output Enable. A high level on this pin enables the driver differential outputs, Y and Z. A low level

places these outputs in a high impedance state.

Transmit Data Input. Data to be transmitted by the driver is applied to this input. When the INVD pin is

logic high, the data applied to this input is inverted.

12

13

INVD

INVR

Driver Inversion Enable. This pin is active high input. Driving this pin high inverts the TxD signal applied.

Receiver Inversion Enable. This pin is active high input. Driving this pin high inverts the A and B receiver

inputs.

15, 16, 21, 22

GND₂

Y

Z

B

A

V_ISOIN

Isolated Ground 2 for the Integrated RS-485 Transceiver, Bus Side.

Driver Noninverting Output.

Driver Inverting Output.

Receiver Inverting Input.

Receiver Noninverting Input.

Isolated Power Supply Input. This pin must be connected externally to V_ISOOUT(Pin 25) through one

BLM15HD182SN1 ferrite. It is recommended that a reservoir capacitor of 10 µF and a 0.1 µF decoupling

capacitor be connected between V_ISOIN(Pin 23) and GND₂(Pin 21).

17

18

19

20

23

24, 26

25

GND_ISO

V_ISOOUT

Isolated Power Supply Ground. These pins must be connected externally to Pin 28.

Isolated Power Supply Output. This pin must be connected externally to V_ISOIN(Pin 23) through one

BLM15HD182SN1 ferrite. It is recommended that a decoupling capacitor of 0.1 µF be connected between

V

_ISOOUTand GND_ISO(Pin 28).

27

28

V_SEL

Output Voltage Selection. When V_SEL= V_ISO, the V_ISOset point is 5.0 V. When V_SEL= GND_ISO, the V_ISOset point

is 3.3 V.

Isolated Power Supply Ground. This pin must be connected externally to GND₂(Pin 22) through one

BLM15HD182SN1 ferrite.

GND_ISO

Rev. B | Page 13 of 28

ADM2561E/ADM2563E/ADM2565E/ADM2567E

Data Sheet

TYPICAL PERFORMANCE CHARACTERISTICS

0.20

0.18

0.16

0.14

0.12

0.10

0.08

0.06

0.04

0.02

0

V

= 3.3V, V

= 3.3V

CC

ISO

= 3.3V

= 5V, V

ISO

0.18

= 5V

V

= 3.3V, V

= 3.3V

CC

ISO

= 3.3V

= 5V, V

ISO

0.16

0.14

0.12

0.10

0.08

0.06

0.04

= 5V

–40 –30 –20 –10

0

10 20 30 40 50 60 70 80 90 100

TEMPERATURE (°C)

0

100

200

300

400

500

FREQUENCY (kHz)

Figure 12. V_CCSupply Current vs. Temperature at 500 kbps, No Load,

500 kbps Models (ADM2561E and ADM2563E)

Figure 15. V_CCSupply Current vs. Frequency, T_A= 25°C, No Load,

500 kbps Models (ADM2561E and ADM2563E)

0.30

0.33

V

= 3.3V, V

= 3.3V

ISO

V

= 3.3V, V

= 3.3V

ISO

CC

= 5V, V

= 3.3V

= 5V, V

= 3.3V

ISO

= 5V, V

ISO

= 5V, V

= 5V

ISO

0.25

0.20

0.15

0.10

0.05

0.28

0.23

0.18

0.13

0.08

–40 –30 –20 –10

0

10 20 30 40 50 60 70 80 90 100

TEMPERATURE (°C)

0

100

200

300

400

500

FREQUENCY (kHz)

Figure 13. V_CCSupply Current vs. Temperature at 500 kbps, 120 Ω Load,

500 kbps Models (ADM2561E and ADM2563E)

Figure 16. V_CCSupply Current vs. Frequency, T_A= 25°C, 120 Ω Load,

500 kbps Models (ADM2561E and ADM2563E)

0.35

V

= 3.3V, V

= 3.3V

CC

ISO

= 5V, V

= 3.3V

ISO

= 5V

0.30

0.25

0.20

0.15

0.10

V

= 3.3V, V

= 3.3V

CC

ISO

= 3.3V

= 5V, V

ISO

= 5V

0.25

0.20

0.15

0.10

–40 –30 –20 –10

0

10 20 30 40 50 60 70 80 90 100

TEMPERATURE (°C)

0

100

200

300

400

500

FREQUENCY (kHz)

Figure 14. V_CCSupply Current vs. Temperature at 500 kbps, 54 Ω Load,

500 kbps Models (ADM2561E and ADM2563E)

Figure 17. V_CCSupply Current vs. Frequency, T_A= 25°C, 54 Ω Load,

500 kbps Models (ADM2561E and ADM2563E)

Rev. B | Page 14 of 28

Data Sheet

ADM2561E/ADM2563E/ADM2565E/ADM2567E

0.20

0.16

V

= 3.3V, V

= 3.3V

CC

ISO

V

= 3.3V, V

= 3.3V

CC

ISO

= 3.3V

= 5V, V

= 3.3V

ISO

= 5V, V

ISO

= 5V

0.14

0.12

0.10

0.08

0.06

0.04

0.02

0

= 5V

0.18

0.16

0.14

0.12

0.10

0.08

0.06

–40 –30 –20 –10

0

10 20 30 40 50 60 70 80 90 100

TEMPERATURE (°C)

0

5

10

15

20

25

FREQUENCY (Mbps)

Figure 18. V_CCSupply Current vs. Temperature at 25 Mbps, No Load,

25 Mbps Models (ADM2565E and ADM2567E)

Figure 21. V_CCSupply Current vs. Frequency, T_A= 25°C, No Load,

25 Mbps Models (ADM2565E and ADM2567E)

0.30

0.24

V

= 3.3V, V

= 3.3V

CC

ISO

= 3.3V

V

= 3.3V, V

= 3.3V

CC

ISO

= 5V, V

ISO

= 5V, V

= 3.3V

ISO

0.22

0.20

0.18

0.16

0.14

0.12

0.10

0.08

0.06

= 5V

0.25

0.20

0.15

0.10

–40 –30 –20 –10

0

10 20 30 40 50 60 70 80 90 100

TEMPERATURE (°C)

0

5

10

15

20

25

FREQUENCY (Mbps)

Figure 19. V_CCSupply Current vs. Temperature at 25 Mbps, 120 Ω Load,

25 Mbps Models (ADM2565E and ADM2567E)

Figure 22. V_CCSupply Current vs. Frequency, T_A= 25°C, 120 Ω Load,

25 Mbps Models (ADM2565E and ADM2567E)

0.40

0.30

V

= 3.3V, V

= 3.3V

CC

ISO

V

= 3.3V, V

= 3.3V

CC

ISO

= 3.3V

= 5V, V

= 3.3V

ISO

= 5V, V

ISO

= 5V

0.35

0.30

0.25

0.20

0.15

0.10

0.25

0.20

0.15

0.10

–40 –30 –20 –10

0

10 20 30 40 50 60 70 80 90 100

TEMPERATURE (°C)

0

5

10

15

20

25

FREQUENCY (Mbps)

Figure 20. V_CCSupply Current vs. Temperature at 25 Mbps, 54 Ω Load,

25 Mbps Models (ADM2565E and ADM2567E)

Figure 23. V_CCSupply Current vs. Frequency, T_A= 25°C, 54 Ω Load,

25 Mbps Models (ADM2565E and ADM2567E)

Rev. B | Page 15 of 28

ADM2561E/ADM2563E/ADM2565E/ADM2567E

Data Sheet

5.5

0

–20

V

= 1.8V

= 2.5V

= 3.3V

= 5V

IO

V

= 3.3V

= 5V

ISO

5.3

5.1

4.9

4.7

4.5

4.3

4.1

3.9

–40

–60

–80

–100

–120

100

1k

10k

100k

1M

10M

100M

–8

–6

–4

–2

0

DATA RATE (bps)

DRIVER OUTPUT HIGH VOLTAGE (V)

Figure 24. V_IOSupply Current vs. Data Rate

Figure 27. Driver Output Current vs. Driver Output High Voltage

120

100

80

60

40

20

0

140

V

= 3.3V

= 5V

ISO

V

= 3.3V

= 5V

ISO

120

100

80

60

40

20

0

1

2

3

4

5

6

0

2

4

6

8

10

12

DRIVER DIFFERENTIAL OUTPUT VOLTAGE (V)

DRIVER OUTPUT LOW VOLTAGE (V)

Figure 25. Driver Output Current vs. Driver Differential Output Voltage

Figure 28. Driver Output Current vs. Driver Output Low Voltage

220

t_DPLH(V

t_DPHL(V

= 3.3V)

= 5V)

= 3.3V)

= 5V)

ISO

3.8

R

= 100Ω, V

= 3.3V

= 5V

= 3.3V

= 5V

L

ISO

200

180

160

140

120

= 54Ω, V

ISO

3.3

2.8

2.3

1.8

–60

–40

–20

0

20

40

60

80

100

120

–50

0

50

TEMPERATURE (°C)

100

150

TEMPERATURE (°C)

Figure 26. Driver Differential Output Voltage vs. Temperature

Figure 29. Driver Differential Propagation Delay vs. Temperature,

500 kbps Models (ADM2561E and ADM2563E)

Rev. B | Page 16 of 28

Data Sheet

ADM2561E/ADM2563E/ADM2565E/ADM2567E

22

6

t_DPLH(V

= 3.3V)

= 5V)

= 3.3V)

= 5V)

V

= 5V

ISO

IO

= 3.3V

= 2.5V

= 1.8V

t_DPLH(V

t_DPHL(V

20

18

16

14

12

10

5

4

3

2

1

0

–60

–40

–20

0

20

40

60

80

100

120

–0.015

–0.010

–0.005

0

TEMPERATURE (°C)

RECEIVER OUTPUT CURRENT (A)

Figure 30. Driver Differential Propagation Delay vs. Temperature,

25 Mbps Models (ADM2565E and ADM2567E)

Figure 33. Receiver Output High Voltage vs. Receiver Output Current

1.0

V

= 5V

CHANNEL 1 (TxD)

IO

= 3.3V

= 2.5V

= 1.8V

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

1

CHANNEL 2 (V

)

OD

2

CH1 1.0V

CH2 1.0V

2µs/DIV

0

5

10

15

RECEIVER OUTPUT CURRENT (mA)

Figure 31. Transmitter Switching at 500 kbps,

500 kbps Models (ADM2561E and ADM2563E)

Figure 34. Receiver Output Low Voltage vs. Receiver Output Current

25.5

CHANNEL 1 (TxD)

V

= 3.6V, 2mA LOAD

= 2.7V, 1mA LOAD

= 1.95V, 0.5mA LOAD

IO

25.0

24.5

24.0

23.5

23.0

22.5

22.0

21.5

21.0

1

CHANNEL 2 (V

)

OD

2

CH1 1.0V

CH2 1.0V

50ns/DIV

–60

–40

–20

0

20

40

60

80

100

120

TEMPERATURE (°C)

Figure 32. Transmitter Switching at 25 Mbps,

25 Mbps Models (ADM2565E and ADM2567E)

Figure 35. Receiver Output Low Voltage vs. Temperature

Rev. B | Page 17 of 28

ADM2561E/ADM2563E/ADM2565E/ADM2567E

Data Sheet

3.0

CHANNEL 1 (V

)

ID

2.8

1

V

= 3.0V, –2mA LOAD

= 2.3V, –1mA LOAD

= 1.7V, –0.5mA LOAD

IO

2.6

2.4

2.2

2.0

1.8

1.6

CHANNEL 2 (RxD)

2

CH1 1.0V

CH2 1.0V

50ns/DIV

–60

–40

–20

0

20

40

60

80

100

120

TEMPERATURE (°C)

Figure 38. Receiver Switching at 25 Mbps

Figure 36. Receiver Output High Voltage vs. Temperature

38

36

34

32

30

28

26

CHANNEL 1 (V )

ID

t_RPLH(V

t_RPHL(V

t_RPLH(V

= 3.3V)

= 5V)

= 3.3V)

= 5V)

ISO

1

CHANNEL 2 (RxD)

2

CH1 1.0V

CH2 1.0V

2µs/DIV

–60

–40

–20

0

20

40

60

80

100

120

TEMPERATURE (°C)

Figure 37. Receiver Propagation Delay vs. Temperature

Figure 39. Receiver Switching at 500 kbps

Rev. B | Page 18 of 28

Data Sheet

ADM2561E/ADM2563E/ADM2565E/ADM2567E

TEST CIRCUITS

+1.5V

A/Y

R

L

V

IO

2

S1

V

TxD

OD2

R

L

R

–1.5V

S2

V

RE

OC

2

C

B/Z

L

RE IN

Figure 45. Receiver Enable or Disable Time Measurement

Figure 40. Driver Voltage Measurement

375Ω

V

ISOIN

IO CC

ISOOUT

A/Y

ISOLATED

DC-TO-DC

CONVERTER

V

CM

TxD

OD3

60Ω

A

RxD

TxD

B/Z

R

120Ω

375Ω

15pF

B

Z

GND

1

Figure 41. Driver Voltage Measurement over Common-Mode Range

V

IO

D

Y

A/Y

GND

1

C

L

GND

2

1

DE = V

TxD

R

IO

L

ISOLATION

BARRIER

RE = GND

1

L

B/Z

Figure 42. Driver Propagation Delay Measurement

Figure 46. CMTI Test Diagram, Full Duplex

V

ISOIN

V

ISOIN

O

IO CC

ISOOUT

A/Y

B/Z

R

110Ω

L

ISOLATED

DC-TO-DC

CONVERTER

TxD

DE

S2

S1

C

L

50pF

RxD

TxD

R

A

B

15pF

GND

Figure 43. Driver Enable or Disable Time Measurement

120Ω

1

V

IO

D

A

GND

1

V

O

GND

2

1

RE

B

DE = V

IO

ISOLATION

BARRIER

C

L

RE = GND

1

Figure 44. Receiver Propagation Delay Time Measurement

Figure 47. CMTI Test Diagram, Half Duplex

Rev. B | Page 19 of 28

ADM2561E/ADM2563E/ADM2565E/ADM2567E

Data Sheet

THEORY OF OPERATION

LOW EMI INTEGRATED DC-TO-DC CONVERTER

ROBUST LOW POWER DIGITAL ISOLATOR

The ADM2561E/ADM2563E/ADM2565E/ADM2567E include

a flexible integrated dc-to-dc converter optimized for low

radiated emissions (EMI). The isolated dc-to-dc converter is

constructed of a set of chip scale coplanar coils separated by an

insulating material. By exciting the upper coil with an ac signal,

power is magnetically coupled across the isolation barrier

where it is rectified and regulated. Because no direct electrical

connection exists between the top and bottom coil, the primary

and secondary side of the device remain galvanically isolated.

The ADM2561E/ADM2563E/ADM2565E/ADM2567E feature

a low power digital isolator to galvanically isolate the primary

and secondary side of the device. The use of coplanar transformer

coils with an on and off keying modulation scheme allows high

data throughput across the isolation barrier while minimizing

radiation emissions. This architecture provides a robust digital

isolator with immunity to common-mode transients of greater

than 250 kV/µs across the full temperature and supply range of

the device.

This isolated dc-to-dc converter features a regulated output of

either 3.3 V or 5 V, selectable via the V_SELlogic pin, which

allows the user to optimize the supply rail of the RS-485

transceiver. For lower power applications, a 3.3 V supply can be

chosen. For applications requiring a large differential output

voltage, such as PROFIBUS®, the isolated dc-to-dc converter

can be operated with a 5 V output. Table 14 shows the

supported supply configurations for the isolated dc-to-dc

converter.

CHANNEL 1 (TxD)

1

CHANNEL 2 (V

)

CM

2

3

CHANNEL 3 (RxD)

Table 14. Isolated DC-to-DC Converter Supply Configuration

V_ISOOutput

Supply Voltage

Supported V_CC

Supply Range

V_SELPin

CH1 2.0V CH2 1kV

CH3 2.0V

100ns/DIV

Connected to GND_ISO

Connected to V_ISOOUT

3.3 V

5 V

3 V to 5.5 V

4.5 V to 5.5 V

Figure 49. Switching Correctly in the Presence of >250 kV/µs

Common-Mode Transients

The integrated dc-to-dc converter is optimized to minimize

radiated EMI, and allows designers to meet the CISPR32 and

EN 55032 Class B requirements on a 2-layer PCB with the

addition of two low cost, surface-mount device (SMD) ferrites.

Follow layout recommendations during PCB design to minimize

these emissions. See the PCB Layout and Electromagnetic

Interference (EMI) section for more details.

HIGH DRIVER DIFFERENTIAL OUTPUT VOLTAGE

The ADM2561E/ADM2563E/ADM2565E/ADM2567E feature

a proprietary transmitter architecture with a low driver output

impedance, resulting in an increased driver differential output

voltage. This architecture is particularly useful when operating the

device over long cable runs, where the dc resistance of the

transmission line dominates signal attenuation. In these

applications, the increased differential voltage improves noise

margin and allows transmission over longer cable lengths. In

addition, when operated as a 5 V transceiver (V_SEL= V_ISO), the

ADM2561E/ADM2563E/ADM2565E/ADM2567E meet or

exceed the PROFIBUS requirement of a minimum 2.1 V

differential output voltage.

80

70

60

50

CLASS A

40

CLASS B

30

20

10

0

IEC61000-4-2 ESD PROTECTION

ESD is the sudden transfer of electrostatic charge between bodies

at different potentials caused by near contact or induced by an

electric field. ESD has the characteristics of high current in a

short time period. The primary purpose of the IEC 61000-4-2

test is to determine the immunity of systems to external ESD

events outside the system during operation. IEC 61000-4-2

describes testing using two coupling methods: contact

30

100

FREQUENCY (MHz)

1000

Figure 48. Low Radiated Emissions DC-to-DC Converter Meets EN55022

Class B with Margin on a 2-Layer PCB

discharge and air discharge. Contact discharge implies a direct

contact between the discharge gun and the equipment under

test (EUT). During air discharge testing, the charged electrode

of the discharge gun is moved toward the EUT until a discharge

occurs as an arc across the air gap. The discharge gun does not

Rev. B | Page 20 of 28

Data Sheet

ADM2561E/ADM2563E/ADM2565E/ADM2567E

I

PEAK

make direct contact with the EUT. A number of factors affect

the results and repeatability of the air discharge test, including

humidity, temperature, barometric pressure, distance, and rate

of approach to the EUT. Air discharge testing is a more accurate

representation of an actual ESD event than contact discharge but is

not as repeatable. Therefore, contact discharge is the preferred test

method. During testing, the data port is subjected to at least

10 positive and 10 negative single discharges. Selection of the test

voltage is dependent on the system end environment. Figure 50

shows the 8 kV contact discharge current waveform as described

in the IEC 61000-4-2 specification. Some of the key waveform

parameters are rise times of less than 1 ns and pulse widths of

approximately 60 ns.

30A

90%

IEC 61000-4-2 ESD 8kV

16A

8A

I

30ns

60ns

HBM ESD 8kV

5.33A

10%

TIME

10ns

t_R= 0.7ns TO 1ns

30ns

60ns

Figure 51. IEC61000-4-2 ESD 8 kV Waveform Compared to HBM ESD 8 kV

Waveform

I

PEAK

30A

90%

TRUTH TABLES

Table 16 and Table 17 use the abbreviations shown in Table 15.

RE

V

_IOsupplies the DE, TxD, , RxD, INVR, and INVD pins

only.

16A

I

30ns

60ns

Table 15. Truth Table Abbreviations

Letter

8A

Description

H

I

L

X

Z

High level

Indeterminate

Low level

Any state

High impedance (off)

10%

TIME

60ns

30ns

t_R= 0.7ns TO 1ns

Figure 50. IEC61000-4-2 ESD Waveform (8 kV)

Figure 51 shows the 8 kV contact discharge current waveform

from the IEC 61000-4-2 standard compared to the HBM ESD

8 kV waveform. Figure 51 shows that the two standards specify

a different waveform shape and peak current (I_PEAK). The peak

current associated with an IEC 61000-4-2 8 kV pulse is 30 A,

whereas the corresponding peak current for HBM ESD is more

than five times less, at 5.33 A. The other difference is the rise

time of the initial voltage spike, with the IEC 61000-4-2 ESD

waveform having a much faster rise time of 1 ns, compared to

the 10 ns associated with the HBM ESD waveform. The amount

of power associated with an IEC ESD waveform is much greater

than that of an HBM ESD waveform. The HBM ESD standard

requires the EUT to be subjected to three positive and three

negative discharges, whereas in comparison, the IEC ESD

standard requires 10 positive and 10 negative discharge tests.

Table 16. Transmitting Truth Table

Supply Status Inputs

Outputs

V_CC

V_IO

On

Off

X

DE

H

L

TxD

H

L

X

INVD

Y

H

L

Z

L

H

L

Z

On

Off

L

H

L

H

X

L

H

Z

X

Table 17. Receiving Truth Table

Supply Status Inputs

Output

INVR RE

V_CC

On

X

V_IO

On

Off

On

A − B

RxD

≥−0.03 V

≤0.03 V

≤−0.2 V

≥0.2 V

−0.2 V < A – B < −0.03 V

0.03 V < A – B < 0.2 V

Inputs open/shorted

X

L

H

L

H

L

H

X

L

H

X

L

H

L

I

The ADM2561E/ADM2563E/ADM2565E/ADM2567E are

rated to 12 kV contact and 15 kV air ESD protection to the

IEC61000-4-2 standard between the RS-485 bus pins (A, B, Y

and Z) and GND₂. The isolation barrier provides 8 kV contact

protection between the bus pins and GND₁. These devices with

IEC 61000-4-2 ESD ratings are better suited for operation in harsh

environments when compared to other RS-485 transceivers that

state varying levels of HBM ESD protection.

I

H

Z

I

X

Off

I

Rev. B | Page 21 of 28

ADM2561E/ADM2563E/ADM2565E/ADM2567E

Data Sheet

pin to correct receiver functionality when A and B are wired

with the incorrect polarity. The ADM2561E/ADM2565E are

half-duplex devices that have a single inversion pin, INV, to

correct both transmitter and receiver polarity. When the

receiver is inverted, the device maintains a Logic 1 receiver

output with a 30 mV noise margin when inputs are shorted

together or open circuit. Figure 52 shows the receiver output in

both inverted and noninverted cases.

RECEIVER FAIL-SAFE

The ADM2561E/ADM2563E/ADM2565E/ADM2567E

guarantee a logic high receiver output when the receiver inputs

are shorted, open, or connected to a terminated transmission line

with all drivers disabled. When the receiver inversion feature is

disabled (INV/INVR = 0 V), a fail-safe logic high output is

achieved by setting the receiver input threshold between −30 mV

and −200 mV. If the differential receiver input voltage (A − B) is

greater than or equal to −30 mV, the RxD pin is logic high. If the

A − B input is less than or equal to −200 mV, RxD is logic low.

Fail-safe is preserved when the receiver inversion feature is

enabled (INVR = V_IO) by setting the inverted receiver input

threshold between 30 mV and 200 mV. In the case of a shorted

or terminated bus with all transmitters disabled, the receiver

differential input voltage is pulled to 0 V by the termination

resistor, resulting in a logic high with a 30 mV minimum noise

margin. This feature eliminates the need for external biasing

components usually required to implement fail-safe.

A – B

PHASE INVERTED RS-485

INVR = H

RS-485

INVR = L

0

+200mV

+30mV

IN

1

FAIL SAFE

–30mV

1

–200mV

0

These features are fully compatible with external fail-safe

biasing configurations, which can be used in applications with

legacy devices that lack fail-safe support, or in applications

where additional noise margin is desired. See the AN-960

Application Note, RS-485/RS-422 Circuit Implementation

Guide, for details on external fail-safe biasing.

Figure 52. RS-485 and Phase Inverted RS-485 Comparison

HOT SWAP INPUTS

When a circuit board is inserted in a powered (or hot)

backplane, parasitic coupling from supply and ground rails to

digital inputs may occur. The ADM2561E/ADM2563E/

ADM2565E/ADM2567E contain circuitry to ensure that the

Y and Z outputs remain in a high impedance state during

power-up, and then default to the correct states. For example,

DRIVER AND RECEIVER CABLE INVERSION

The ADM2561E/ADM2563E/ADM2565E/ADM2567E feature

cable inversion functionality to correct errors during installa-

tion. This adjustment can be implemented in software on the

controller driving the RS485 transceiver and helps avoid

additional installation costs to fix wiring errors. The ADM2563E/

ADM2567E feature separate digital logic pins, INVD and INVR,

to correct cases where the driver, receiver, or both are wired in

reverse. Use the INVD pin to correct driver functionality when

Y and Z are wired with the incorrect polarity. Use the INVR

RE

when V_IOand V_CCpower up at the same time and the

pin is

pulled low, with the DE and TxD pins pulled high, the Y and Z

outputs remain in high impedance until settling at an expected

default high state for the Y pin and expected default low state

for the Z pin.

Table 18. Product Description Table

Isolation

Maximum

Device

Withstand Duplex Data Rate Cable Inversion Feature

Package(s) Available

ADM2561E 3 kV

ADM2563E 3 kV

ADM2565E 3 kV

ADM2567E 3 kV

Half

Full

Half

Full

500 kbps¹Inversion pin (INV)

500 kbps¹Separate driver (INVD) and receiver (INVR) inversion

28-lead SOIC_W with finer pitch

25 Mbps

Inversion pin (INV)

Separate driver (INVD) and receiver (INVR) inversion

¹Driver outputs are slew rate limited to minimize common-mode emissions over long cable runs.

Rev. B | Page 22 of 28

Data Sheet

ADM2561E/ADM2563E/ADM2565E/ADM2567E

192 TRANSCEIVERS ON THE BUS

1.7 V TO 5.5 V V_IOLOGIC SUPPLY

The standard RS-485 receiver input impedance is 12 kΩ (1 unit

load), and the standard driver can drive up to 32 unit loads.

The ADM2561E/ADM2563E/ADM2565E/ADM2567E

transceiver has a 1/6 unit load receiver input resistance

(equivalent to 72 kΩ), allowing up to 192 transceivers to be

connected in parallel on one communication line. Any

combination of these devices and other RS-485 transceivers

with a total of 32 unit loads or fewer can be connected to the line.

The ADM2561E/ADM2563E/ADM2565E/ADM2567E feature

a V_IOlogic supply pin to allow a flexible digital interface

operational to voltages as low as 1.7 V. The V_IOpin powers the

primary side of the signal isolation, the logic inputs, and the

RxD output. These input and output pins interface with logic

devices such as universal asynchronous receiver/transmitters

(UARTs), application specific integrated circuits (ASICs), and

microcontrollers. For applications where these devices use I/Os

operating at voltages other than the ADM2561E/ADM2563E/

ADM2565E/ADM2567E V_CCsupply voltage, the V_IOsupply can

be powered from the same supply rail as the logic device. The

DRIVER OUTPUT PROTECTION

The ADM2561E/ADM2563E/ADM2565E/ADM2567E feature

two methods to prevent excessive output current and power

dissipation caused by faults or by bus contention. Current-limit

protection on the output stage provides immediate protection

against short circuits over the entire common-mode voltage

range. In addition, a thermal shutdown circuit forces the driver

outputs to a high impedance state if the die temperature rises

excessively. This circuitry is designed to disable the driver

outputs when a die temperature greater than 150°C is reached.

As the device cools, the drivers are reenabled at a temperature

of 140°C.

V_IOsupply accepts a supply voltage between 1.7 V and 5.5 V,

allowing communication with 1.8 V, 2.5 V, 3.3 V, and 5 V

devices.

Rev. B | Page 23 of 28

ADM2561E/ADM2563E/ADM2565E/ADM2567E

Data Sheet

APPLICATIONS INFORMATION

PCB LAYOUT AND ELECTROMAGNETIC

INTERFERENCE (EMI)

The ADM2561E/ADM2563E/ADM2565E/ADM2567E can

dissipate over 500 mW of power when fully loaded. Because it

is not possible to apply a heat sink to an isolation device, the

devices primarily depend on heat dissipation to the PCB through

the GND_xpins. If the devices are used at high ambient

temperatures, provide a thermal path from the GND_xpins to the

PCB ground plane. The use of a solid GND₁and GND₂plane is

recommended. Implementing a low thermal impedance between

the top ground layers and internal ground layers reduce the

temperature inside the chip significantly.

The ADM2561E/ADM2563E/ADM2565E/ADM2567E meet

EN 55032 Class B/CISPR32 radiated emissions requirements.

Two external surface-mount technology (SMT) ferrite beads

are used to pass the Class B limits with margin. No additional

mitigation techniques, such as stitching capacitance, are

needed, allowing system designers to create a compliant design

on a 2-layer PCB, without the need for complex and area

intensive layouts.

The ADM2561E/ADM2563E/ADM2565E/ADM2567E feature

an internal split paddle lead frame on the bus side. For optimal

noise suppression, filter the V_ISOOUTsignal (Pin 25) and GND_ISO

signal (Pin 24, Pin 26, and Pin 28) for high frequency currents

before routing power to the RS-485 transceiver and other

circuitry. Two SMT ferrite beads, L1 and L2, are recommended

to achieve this filtering. The size of the V_ISOOUTand GND_ISOnet

must also be kept to a minimum. See Figure 53 for the

recommended PCB layout.

DEVICE POWER-UP

The integrated isoPower isolated dc-to-dc converter requires

10 ms to power up to the setpoint of 3.3 V or 5 V. During this

start-up time, it is not recommended to assert the DE driver

enable signal.

In applications where the isolated dc-to-dc converter is

operated with a 3.3 V output voltage (V_SELpin connected to

GND_ISO), the V_CCsupply rail must be greater than 3.135 V

during the power-up sequence. After the 10 ms power-up

duration, the V_CCsupply rail can operate across the full 3 V to

5.5 V range.

METAL KEEP OUT

10µF

L1

10µF

GND

V

GND

1

ISO

1

2

28

27

26

25

24

23

22

21

20

19

18

17

16

15

V

SEL

0.1µF

L2

GND

V

ISO

3

0.1µF

CC

MAXIMUM DATA RATE vs. AMBIENT

TEMPERATURE

ISOOUT

4

GND

1

ISO

5

GND

V

ISOIN

6

0.1µF

GND

A

IO

2

ADM2567E

Under a large current load or when operating at high frequency

operation, self heating effects within the isoPower dc-to-dc

converter can limit the maximum ambient temperature achievable

while retaining a silicon junction temperature below 150°C.

This internal power dissipation is related to application conditions

such as supply voltage configuration, switching frequency,

effective load on the RS-485 bus, and the amount of time the

transceiver is in transmit mode. Thermal performance also

depends on the PCB design and thermal characteristics of a

system.

7

TOP VIEW

RxD

8

(Not to Scale)

RE

DE

9

B

10

11

12

13

14

TxD

Z

INVD

INVR

GND

Y

GND

2

GND

1

Figure 53. Recommended PCB Layout

The isoPower® integrated dc-to-dc converter contains switching

frequencies between 180 MHz and 400 MHz. To effectively

filter these frequencies, the impedance of the ferrite bead is

chosen to be about 2 kΩ between the 100 MHz and 1 GHz

frequency range. Some recommended SMT ferrites are shown

in Table 19. Although these ferrite beads are required to

achieve compliance to EN 55032 Class B, they are not needed for

system functionality. The ADM2561E/ADM2563E/ADM2565E/

ADM2567E have been fully characterized with the recommended

BLM15HD182SN1 ferrite beads.

In applications with a fully loaded RS-485 bus (equivalent to

54 Ω bus resistance) operating with V_ISO= 5 V, it is recommended

to keep the V_CCinput supply greater than 4.75 V. If this is not

possible for the ADM2565E/ADM2567E, limit either the

maximum ambient temperature to 85°C or the maximum

operating data rate to 6 Mbps. If this is not possible for the

ADM2561E/ADM2563E, limit the maximum ambient

temperature to 85°C.

Table 19. Examples of Surface-Mount Ferrite Beads

Manufacturer

Murata Electronics

Taiyo Yuden

Device No.

BLM15HD182SN1

BKH1005LM182-T

Rev. B | Page 24 of 28

Data Sheet

ADM2561E/ADM2563E/ADM2565E/ADM2567E

Table 20. Recommended Components for ESD, EFT, and

Surge Protection

Recommended Components Part Number

ISOLATED PROFIBUS SOLUTION

The ADM2565E features a driver that is well suited for meeting

the requirements of an isolated PROFIBUS node. When operating

the ADM2565E as a PROFIBUS transceiver, connect the V_SELpin

to the V_ISOOUTpin to operate the transceiver with a 5 V isolated

supply voltage. The ADM2565E features the following characteris-

tics that make it ideally suited for use in PROFIBUS applications:

TVS

CDSOT23-SM712

10 Ω Pulse Proof Resistors

CRCW060310R0FKEAHP

Table 21. Protection Levels with Recommended Circuit

EMC Standard

Protection Level (kV)

≥ 30 (exceeds Level 4)

≥ 4 (exceeds Level 4)

≥ 1 (Level 2)

•

5 V isolated transceiver power supply. The 5 V V_ISOoutput

supply provides the required current for the RS-485

transceiver at up to 12 Mbps and the additional 5 mA

required for the PROFIBUS termination network.

The output driver meets or exceeds the PROFIBUS

differential output requirements. To ensure the transmitter

differential output does not exceed 7 V p-p over all

conditions, place 10 Ω resistors in series with the A and B

transmitter outputs.

ESD—Contact (IEC61000-4-2)

ESD—Air (IEC61000-4-2)

EFT (IEC61000-4-4)

Surge (IEC61000-4-5)

•

INSULATION LIFETIME

All insulation structures eventually break down when subjected

to voltage stress over a sufficiently long period of time. The rate

of insulation degradation is dependent on the characteristics of

the voltage waveform applied across the insulation, as well as

on the materials and material interfaces.

•

High speed timing to operate at 12 Mbps with low

propagation delay and less than 10% transmitter and

receiver skew.

The two types of insulation degradation of primary interest are

breakdown along surfaces exposed to the air and insulation wear

out. Surface breakdown is the phenomenon of surface tracking and

is the primary determinant of surface creepage requirements in

system level standards. Insulation wear out is the phenomenon

where charge injection or displacement currents inside the

insulation material cause long-term insulation degradation.

•

Low bus pin capacitance of 28 pF.

Class I (no loss of data) immunity to IEC 61000-4-4 EFT

to 1 kV can be achieved using a PROFIBUS shielded

cable. At data rates of ≤500 kbps, IEC 61000-4-4 Class I to

3 kV can be achieved with the addition of a 470 pF

capacitor to GND₁on the RxD output pin.

EMC, EFT, AND SURGE

Surface Tracking

In applications where additional levels of protection against

IEC61000-4-4 EFT or IEC61000-4-5 surge events are required,

external protection circuits can be added to further enhance the

EMC robustness of these devices. See Figure 54 for a recom-

mended protection circuit, which uses a series of SM712 transient

voltage suppressor (TVS) and 10 Ω pulse proof resistors to

achieve in excess of Level 4 IEC61000-4-2 ESD and IEC61000-4-4

EFT protection, and Level 2 IEC61000-4-5 surge protection.

Table 20 and Table 21 describe the recommended components

for protection and the protection levels.

Surface tracking is addressed in electrical safety standards by

setting a minimum surface creepage based on the working

voltage, the environmental conditions, and the properties of the

insulation material. Safety agencies perform characterization

testing on the surface insulation of components, allowing the

components to be categorized in different material groups.

Lower material group ratings are more resistant to surface

tracking and can therefore provide adequate lifetime with

smaller creepage. The minimum creepage for a given working

voltage and material group is in each system level standard and

is based on the total rms voltage across the isolation, pollution

degree, and material group. See Table 6 for the material group

and creepage information for the ADM2561E/ADM2563E/

ADM2565E/ADM2567E isolated RS-485 transceiver.

V

CC

IO

10Ω

A

B

R

RxD

TxD

120Ω

10Ω

SM712

TVS

Insulation Wear Out

Z

Y

D

The lifetime of insulation caused by wear out is determined by

the thickness, material properties, and the voltage stress applied

across the insulation. It is important to verify that the product

lifetime is adequate at the application working voltage. The

working voltage supported by an isolator for wear out may not

be the same as the working voltage supported for tracking. The

working voltage applicable to tracking is specified in most

standards.

10Ω

SM712

TVS

GND

2

1

ISOLATION

BARRIER

Figure 54. Isolated RS-485 Solution with ESD, EFT, and Surge Protection

Rev. B | Page 25 of 28

ADM2561E/ADM2563E/ADM2565E/ADM2567E

Data Sheet

Testing and modeling show that the primary driver of long-term

degradation is displacement current in the polyimide insulation,

causing incremental damage. The stress on the insulation can be

divided into broad categories, such as dc stress and ac component

time varying voltage stress. DC stress causes little wear out because

there is no displacement current, whereas ac component time

varying voltage stress causes wear out.

The working voltage across the barrier from Equation 1 is

2

V_RMS= V_{AC RMS}²−V_DC

V_RMS

_RMS= 466 V

=

240²− 400²

V

This V_RMSvalue is the working voltage used together with the

material group and pollution degree when determining the

creepage required by a system standard.

The ratings in certification documents are typically based on

60 Hz sinusoidal stress to reflect isolation from the line voltage.

However, many practical applications have combinations of

60 Hz ac and dc across the barrier, as shown in Equation 1.

Because only the ac portion of the stress causes wear out, the

equation can be rearranged to solve for the ac rms voltage, as

shown in Equation 2. For insulation wear out with the

polyimide materials used in these products, the ac rms voltage

determines the product lifetime.

To determine if the lifetime is adequate, obtain the time varying

portion of the working voltage. To obtain the ac rms voltage,

use Equation 2.

2

V_{AC RMS}= V_RMS²−V_DC

V_{AC RMS}

=

466²− 400²

2

V_RMS= V_{AC RMS}²−V_DC

(1)

V

_{AC RMS}= 240 V rms

In this case, the ac rms voltage is simply the line voltage of

240 V rms. This calculation is more relevant when the waveform is

not sinusoidal. The value is compared to the limits for working

voltage in Table 10 for the expected lifetime, which is less than

a 60 Hz sine wave, and it is well within the limit for a 50-year

service life.

or

2

V_{AC RMS}= V_RMS²−V_DC

(2)

where:

V

_RMSis the total rms working voltage.

_{AC RMS}is the time varying portion of the working voltage.

_DCis the dc offset of the working voltage.

The dc working voltage limit is set by the creepage of the

package as specified in IEC 60664-1. This value can differ for

specific system level standards.

Calculation and Use of Parameters Example

The following example frequently arises in power conversion

applications. Assume that the line voltage on one side of the

TYPICAL APPLICATIONS

An example circuit using the ADM2567E as a full duplex

RS-485 node is shown in Figure 56. Placement of the termina-

tion resistor, R_T, is dependent on the location of the node and

the network topology. Refer to the AN-960 Application Note,

RS-485/RS-422 Circuit Implementation Guide, for guidance on

termination. Up to 192 transceivers can be connected to the

bus. To minimize reflections, terminate the line at the receiving

end in its characteristic impedance and keep stub lengths off

the main line as short as possible. For half-duplex operation,

this means that both ends of the line must be terminated

because either end can be the receiving end.

isolation is 240 V ac rms and a 400 V dc bus voltage is present

on the other side of the isolation barrier. The isolator material

is polyimide. To establish the critical voltages in determining

the creepage, clearance, and lifetime of a device, see Figure 55

and the following equations.

V

AC RMS

V

DC

PEAK

RMS

TIME

Figure 55. Critical Voltage Example

Rev. B | Page 26 of 28

Data Sheet

ADM2561E/ADM2563E/ADM2565E/ADM2567E

LOW VOLTAGE

1.8V/2.5V SUPPLY

3.3V/5V POWER

SUPPLY

100nF

10µF

100nF

GND

ISO

V

ISOIN

CC

SEL

ISOOUT

10uF

100nF

LOW RADIATED EMISSIONS DC-TO-DC

V

OSCILLATOR

RECTIFIER

IO

V

CC

REGULATOR

DIGITAL ISOLATION

iCoupler

RS-485 TRANSCEIVER

RE

A

B

RxD

CABLE

INVERT

DECODE

ENCODE

R

T

INVR

ENCODE

DECODE

MICROCONTROLLER

Y

Z

AND

TxD

UART

D

INVD

DE

ENCODE

DECODE

ADM2567E

GND

2

GND

1

GND

1

ISO

ISOLATION

BARRIER

Figure 56. Example Circuit Diagram Using the ADM2567E

Rev. B | Page 27 of 28

ADM2561E/ADM2563E/ADM2565E/ADM2567E

OUTLINE DIMENSIONS

Data Sheet

10.45

10.15

28

15

7.60

7.40

10.55

10.05

14

1

PIN 1

INDICATOR

TOP VIEW

0.65 BSC

0.40

0.25

0.75

0.25

× 45°

2.40

2.25

2.65

2.35

END VIEW

SIDE VIEW

0.32

0.23

8°

0°

0.25

0.10

0.25 BSC

SEATING

PLANE

(GAUGE PLANE)

1.40

REF

1.27

0.40

COPLANARITY

0.10

Figure 57. 28-Lead Standard Small Outline, Wide Body, with Finer Pitch [SOIC_W_FP]

(RN-28-1)

Dimensions shown in millimeters

ORDERING GUIDE

Model¹

Isolation (kV) Data Rate (Mbps) Duplex Temperature Range Package Description

Package Option

RN-28-1

ADM2561EBRNZ

3

0.5

25

Half

Full

Half

Full

−40°C to +105°C

28-Lead SOIC_W_FP

ADM2561EBRNZ-RL7 3

ADM2563EBRNZ

ADM2563EBRNZ-RL7 3

ADM2565EBRNZ

ADM2565EBRNZ-RL7 3

ADM2567EBRNZ

3

28-Lead SOIC_W_FP

RN-28-1

3

28-Lead SOIC_W_FP

RN-28-1

25

3

25

28-Lead SOIC_W_FP

RN-28-1

ADM2567EBRNZ-RL7 3

EVAL-ADM2561EEBZ

EVAL-ADM2563EEBZ

EVAL-ADM2565EEBZ

EVAL-ADM2567EEBZ

Half Duplex Evaluation Board

Full Duplex Evaluation Board

Half Duplex Evaluation Board

Full Duplex Evaluation Board

¹Z = RoHS Compliant Part.

registered trademarks are the property of their respective owners.

D22764-8/20(B)

Rev. B | Page 28 of 28


型号：	ADM2563EBRNZ-RL7
厂家：	ADI
描述：	3 kV RMS Signal and Power Isolated RS-485 Transceiver with Â±15 kV IEC ESD
文件：	总28页 (文件大小：562K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADM2563EBRNZ-RL7 [ADI]

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