ADM3061EBRMZ [ADI]
IEC ESD Protected, 500 kbps/50 Mbps RS-485 Transceivers;
| 型号： | ADM3061EBRMZ |
| 厂家： | 
ADI |
| 描述： | IEC ESD Protected, 500 kbps/50 Mbps RS-485 Transceivers |
| 文件： | 总28页 (文件大小：683K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
3.0 V to 5.5 V, ±12 kV IEC ESD Protected,
500 kbps/50 Mbps RS-485 Transceivers
Data Sheet ADM3061E/ADM3062E/ADM3063E/ADM3065E/ADM3066E/ADM3067E/ADM3068E
FEATURES
FUNCTIONAL BLOCK DIAGRAMS
V
CC
TIA/EIA RS-485 compliant over full supply range
3.0 V to 5.5 V operating voltage range on VCC
1.62 V to 5.5 V VIO logic supply option available
ESD protection on the bus pins
IEC 61000-4-2 12 kV contact discharge
IEC 61000-4-2 ≥ 12 kV air discharge
R
RO
RE
A
B
DE
DI
HBM: ≥ 30 kV
D
Full hot swap support (glitch free power-up/power-down)
High speed 50 Mbps data rate (ADM3065E/ADM3066E/
ADM3067E/ADM3068E)
Low speed 500 kbps data rate for long cables (ADM3061E/
ADM3062E/ADM3063E)
ADM3061E/ADM3065E
GND
Figure 1. ADM3061E/ADM3065E Functional Block Diagram
V
CC
Full receiver short-circuit, open circuit, and bus idle fail-safe
Extended temperature range up to 125°C
PROFIBUS compliant at VCC ≥ 4.5 V
Half duplex and full duplex models available
Allows connection of up to 128 transceivers onto the bus
Space-saving package options
A
B
R
RO
RE
DE
DI
Z
Y
D
10-lead, 3 mm × 3 mm LFCSP
8-lead and 10-lead, 3 mm × 3 mm MSOP
8-lead and 14-lead, narrow body SOIC
ADM3063E/ADM3067E
GND
APPLICATIONS
Figure 2. ADM3063E/ADM3067E Functional Block Diagram
Industrial fieldbuses
V
CC
Process control
V
IO
Building automation
PROFIBUS networks
Motor control servo drives and encoders
R
RO
RE
A
B
LEVEL
TRANSLATOR
DE
DI
D
ADM3062E/ADM3066E
GND
Figure 3. ADM3062E/ADM3066E Functional Block Diagram
V
CC
V
IO
A
B
R
RO
RE
LEVEL
TRANSLATOR
DE
DI
Y
Z
D
ADM3068E
GND
Figure 4. ADM3068E Functional Block Diagram
Rev. F
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ADM3061E/ADM3062E/ADM3063E/ADM3065E/ADM3066E/ADM3067E/ADM3068E Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagrams............................................................. 1
Revision History ............................................................................... 2
General Description......................................................................... 4
Specifications..................................................................................... 5
Timing Specifications .................................................................. 7
Absolute Maximum Ratings.......................................................... 11
Thermal Resistance .................................................................... 11
ESD Caution................................................................................ 11
Pin Configurations and Function Descriptions ......................... 12
Typical Performance Characteristics ........................................... 16
Test Circuits..................................................................................... 20
Theory of Operation ...................................................................... 21
REVISION HISTORY
IEC ESD Protected RS-485 ....................................................... 21
High Driver Differential Output Voltage................................ 21
IEC 61000-4-2 ESD Protection ................................................ 21
Truth Tables................................................................................. 22
Receiver Fail-Safe ....................................................................... 22
Hot Swap Capability................................................................... 22
128 Transceivers on the Bus...................................................... 22
Driver Output Protection.......................................................... 22
Applications Information.............................................................. 23
Isolated High Speed RS-485 Node........................................... 24
Outline Dimensions....................................................................... 25
Ordering Guide .......................................................................... 27
6/2019—Rev. E to Rev. F
Changes to Figure 14, Figure 15, Figure 16, and Figure 18
Captions........................................................................................... 14
Changes to Figure 19, Figure 20, Figure 23, and Figure 24
Captions........................................................................................... 15
Change to Figure 25 Caption........................................................ 14
Changes to Figure 39...................................................................... 18
Changes to IEC ESD Protected RS-485 Section......................... 19
Changes to Truth Tables Section, Table 11, Table 12, and
Receiver Fail-Safe Section ............................................................. 20
Added Table 10; Renumbered Sequentially................................ 20
Changes to Isolated High Speed RS-485 Node Section and
Figure 47 .......................................................................................... 22
Changes to Ordering Guide...................................................................25
Added ADM3068E.............................................................Universal
Added Figure 2; Renumbered Sequentially .................................. 1
Changes to Features Section and Figure 4..................................... 1
Changes to Table 1 Title................................................................... 4
Changes to Table 2............................................................................ 5
Changes to ADM3061E/ADM3062E/ADM3063E Section and
Table 3 ................................................................................................ 7
Changes to ADM3065E/ADM3066E/ADM3067E/ADM3068E
Section and Table 4........................................................................... 8
Changes to Figure 5 and Figure 7................................................... 9
Changes to Figure 8........................................................................ 10
RE
Added Endnote 1 to Digital Input and Output Voltage (DE,
,
DI, and RO) Parameter, Table 5.................................................... 11
3/2019—Rev. C to Rev. D
RE
Changes to Digital Input and Output Voltage (DE, , DI, and
Added ADM3067E and 14-Lead SOIC_N, R-14 ...........Universal
Changes to Feature Section......................................................................1
Added Figure 3; Renumbered Sequentially ..........................................1
Moved Table 1 to........................................................................................4
Changes to Table 2.....................................................................................5
Changes to ADM3065E/ADM3066E/ADM3067E Section..............7
Change to Pin 3, Description Column, Table 7 .................................11
Changes to Figure 10, Figure 11, and Table 8.....................................12
Added Figure 12 and Table 9; Renumbered Sequentially ................13
Changes to Figure 14...............................................................................14
Moved Test Circuits to ............................................................................18
Changes to Table 10 and Table 11.........................................................20
Updated Outline Dimensions................................................................26
Changes to Ordering Guide...................................................................27
RO) Parameter, Table 5.................................................................. 11
Changes to Table 8.......................................................................... 13
Added Figure 14 and Table 10; Renumbered Sequentially ....... 15
Changes to Figure 19 Caption....................................................... 16
Changes to Figure 43 and Figure 44............................................. 20
Changes to Isolated High Speed RS-485 Node Section............. 24
Changes to Ordering Guide .......................................................... 27
4/2019—Rev. D to Rev. E
Added ADM3063E.............................................................Universal
Change to Features Section ............................................................. 1
Changes to Figure 3.......................................................................... 1
Changes to Table 1............................................................................ 4
Changes to Table 2............................................................................ 5
Added Endnote 1, Table 2; Renumbered Sequentially ................ 5
Change to Table 7 ........................................................................... 11
Changes to Table 8.......................................................................... 12
Changes to Figure 12 and Table 9................................................. 13
1/2018—Rev. B to Rev. C
Added ADM3062E.............................................................Universal
Changes to Figure 2 and Table 1 .............................................................1
Rev. F | Page 2 of 28
Data Sheet ADM3061E/ADM3062E/ADM3063E/ADM3065E/ADM3066E/ADM3067E/ADM3068E
Changes to ADM3061E/ADM3062E Timing Specifications
Section and Figure 3...................................................................................6
Changes to Figure 5 and Figure 6..............................................................7
Changes to Figure 9 and Figure 10........................................................ 11
Changes to Figure 16 and Figure 17...................................................... 12
Changes to Figure 44................................................................................. 21
Changes to Figure 45................................................................................. 22
Changes to Ordering Guide .................................................................... 25
Changed High Speed IEC ESD Protected RS-485 Section to IEC
ESD Protected RS-485 Section................................................................17
Changes to IEC ESD Protected RS-485 Section .................................17
Added Endnote 4, Table 9.........................................................................18
Changes to Table 10 ...................................................................................18
Changes to Figure 44 .................................................................................21
Changes to Figure 45 .................................................................................22
Changes to Ordering Guide...........................................................25
12/2017—Rev. A to Rev. B
5/2017—Rev. 0 to Rev. A
Added ADM3061E.............................................................Universal
Changes to Product Title, Features Section, Figure 1, and Table 1...1
Changes to General Description Section.......................................3
Changes to Table 2 ............................................................................4
Added ADM3061E Timing Specification Section and Table 3;
Renumbered Sequentially ................................................................6
Moved Figure 3..................................................................................6
Moved Figure 4, Figure 5, and Figure 6..........................................7
Changes to ADM3065E/ADM3066E Timing Specification
Section Title .......................................................................................8
Added 10-Lead MSOP Parameter and 10-Lead LFCSP Parameter,
Table 5 ..................................................................................................9
Changes to Operating Temperature Range Parameter, Table 5
and Table 6 .........................................................................................9
Changes to Figure 7, Figure 8, and Table 7.....................................10
Changes to Table 8 ..........................................................................11
Changes to Figure 11 ......................................................................12
Added Figure 23; Renumbered Sequentially...............................13
Added Figure 24, Figure 25, Figure 26, Figure 27, and Figure 28 .. 14
Added ADM3066E............................................................. Universal
Changes to Features Section, Figure 1, and Table 1......................1
Added Figure 2; Renumbered Sequentially...................................1
Moved General Description Section ..............................................3
Changes to General Description Section.......................................3
Changes to Specifications Section and Table 2 .............................4
Changes to Timing Specifications Section and Figure 3 .............5
Changes to Figure 4, Figure 5, and Figure 6..................................6
Added VIO to GND Parameter, Table 4 ..........................................7
Changes to Thermal Resistance Section and Table 5...................7
Added Figure 8 ..................................................................................8
Changes to Table 6 ............................................................................8
Added Figure 9 and Figure 10.........................................................9
Added Table 7; Renumbered Sequentially.....................................9
Changes to Figure 14, Figure 16, and Figure 17..........................10
Changes to Table 8 and Table 9 .....................................................15
Added Figure 42 and Figure 43.....................................................20
Changes to Ordering Guide...........................................................21
3/2017—Revision 0: Initial Version
Rev. F | Page 3 of 28
ADM3061E/ADM3062E/ADM3063E/ADM3065E/ADM3066E/ADM3067E/ADM3068E Data Sheet
GENERAL DESCRIPTION
The ADM3061E/ADM3062E/ADM3063E/ADM3065E/
ADM3066E/ADM3067E/ADM3068E are 3.0 V to 5.5 V, IEC
electrostatic discharge (ESD) protected RS-485 transceivers,
allowing the devices to withstand 12 kV contact discharges on
the transceiver bus pins without latch-up or damage. The
ADM3062E/ADM3066E/ADM3068E feature a VIO logic supply
pin that allow a flexible digital interface capable of operating as
low as 1.62 V.
The RS-485 transceivers are available in a number of space-
saving packages, such as the 10-lead, 3 mm × 3 mm lead frame
chip-scale package (LFCSP), the 8-lead or 10-lead, 3 mm × 3 mm
mini small outline package (MSOP), and the 8-lead or 14-lead,
narrow body standard small outline packages (SOIC_N).
Models with operating temperature ranges of −40°C to +125°C
and −40°C to +85°C are available.
Excessive power dissipation caused by bus contention or by
output shorting is prevented by a thermal shutdown circuit. If a
significant temperature increase is detected in the internal driver
circuitry during fault conditions, this feature forces the driver
output into a high impedance state.
The ADM3065E/ADM3066E/ADM3067E/ADM3068E are
suitable for high speed, 50 Mbps, bidirectional data commu-
nication on multipoint bus transmission lines. The ADM3061E/
ADM3062E/ADM3063E/ADM3065E/ADM3066E/ADM3067E/
ADM3068E feature a 1/4 unit load input impedance that allows
up to 128 transceivers on a bus. The ADM3061E/ADM3062E/
ADM3063E models offer all of the same features as the
ADM3065E/ADM3066E/ADM3067E/ADM3068E models at a
low 500 kbps data rate that is suitable for operation over long
cable runs.
The ADM3061E/ADM3062E/ADM3063E/ADM3065E/
ADM3066E/ADM3067E/ADM3068E guarantee a logic high
receiver output when the receiver inputs are shorted, open, or
connected to a terminated transmission line with all drivers
disabled.
Table 1 presents an overview of the ADM3061E/ADM3062E/
ADM3063E/ADM3065E/ADM3066E/ADM3067E/ADM3068E
data rate capability across temperature, power supply, and package
options. Refer to the Ordering Guide for model numbering.
The ADM3061E/ADM3062E/ADM3065E/ADM3066E are half-
duplex RS-485 transceivers, fully compliant to the PROFIBUS®
standard with increased 2.1 V bus differential voltage at VCC
≥
4.5 V. The ADM3063E/ADM3067E/ADM3068E are full duplex
RS-485 transceiver options.
Table 1. Summary of the ADM3061E/ADM3062E/ADM3063E/ADM3065E/ADM3066E/ADM3067E/ADM3068E Operating
Conditions—Data Rate Capability Across Temperature, Power Supply, and Package
Maximum Data Rate1
50 Mbps
50 Mbps
50 Mbps
Maximum VCC (V) Maximum Temperature Package Description
5.5
5.5
3.6
5.5
−40°C to +125°C
−40°C to +105°C
−40°C to +125°C
−40°C to +125°C
10-lead LFCSP
8-lead SOIC_N, 8-lead MSOP, 10-lead MSOP, and 14-lead SOIC_N
8-lead SOIC_N, 8-lead MSOP, 10-lead MSOP, and 14-lead SOIC_N
8-lead SOIC_N, 8-lead MSOP, 10-lead MSOP, 10-lead LFCSP, and
14-lead SOIC_N
500 kbps
1 The ADM3065E/ADM3066E/ADM3067E/ADM3068E data input (DI) is transmitting 50 Mbps (or 500 kbps for the ADM3061E/ADM3062E/ADM3063E) clock data, and the
ADM3061E/ADM3062E/ADM3063E/ADM3065E/ADM3066E/ADM3067E/ADM3068E driver enable (DE) is enabled for 50% of the DI transmit time
Rev. F | Page 4 of 28
Data Sheet ADM3061E/ADM3062E/ADM3063E/ADM3065E/ADM3066E/ADM3067E/ADM3068E
SPECIFICATIONS
VCC = 3.0 V to 5.5 V, VIO = 1.62 V to VCC (ADM3062E/ADM3066E/ADM3068E), TA = TMIN (−40°C) to TMAX (+125°C), unless otherwise
noted. All typical specifications are at TA = 25°C, VIO = VCC = 3.3 V, unless otherwise noted.
Table 2.
Parameter
Symbol Min
Typ Max
Unit Test Conditions/Comments
POWER SUPPLY
No Load Supply Current
1
ICC
3.5
3.5
3
7.5
7.5
4.5
172
mA DE = VIO
,
RE
= 0 V
mA DE = V , = V
RE
IO
IO
mA DE = 0 V, = 0 V
RE
ADM3065E/ADM3066E/ADM3067E/
ADM3068E Supply Current,
Data Rate = 50 Mbps
ICC
107
mA Load resistance (RL) = 54 Ω, DE = VIO,
RE = 0V (VCC ≥ 4.5 V)
67
75
mA R = 54 Ω, DE = V , = 0 V (V = 3.0 V)
RE
L
IO
CC
ADM3061E/ADM3062E/ADM3063E
Supply Current, Data Rate = 500 kbps
ICC
100
165
mA R = 54 Ω, DE = V , = 0 V (V ≥ 4.5 V)
RE
L
IO
CC
56
210
1
74
mA R = 54 Ω, DE = V , = 0 V (VCC = 3.0 V)
RE
L
IO
Supply Current in Shutdown Mode
VIO Shutdown Current2
ISHDN
450
50
µA
µA
RE
DE = 0 V, = V
IO
IO
IIOSHDN
RE
DE = 0 V, = V
DRIVER
Differential Outputs
Output Voltage, Loaded
|VOD2
|VOD2
|VOD2
|VOD2
|VOD3
|
|
|
|
|
2.0
1.5
2.1
2.1
1.5
2.5
2.1
3.5
3
VCC
VCC
VCC
VCC
VCC
V
V
V
V
V
VCC ≥ 3.0 V, RL = 50 Ω, see Figure 38
VCC ≥ 3.0 V, RL = 27 Ω (RS-485), see Figure 38
VCC ≥ 4.5 V, RL = 50 Ω, see Figure 38
VCC ≥ 4.5 V, RL = 27 Ω (RS-485), see Figure 38
VCC ≥ 3.0 V, −7 V ≤ common-mode voltage
(VCM) ≤ +12 V, see Figure 39
2.1
|VOD3
∆|VOD|
|
2.1
3
VCC
0.2
V
V
VCC ≥ 4.5 V, −7 V ≤ VCM ≤ +12 V, see Figure 39
RL = 27 Ω or 50 Ω, see Figure 38
Change in Differential Input Voltage for
Complementary Output States
Common-Mode Output Voltage
Change in Common Mode Voltage for
Complementary Output States
VOC
∆|VOC|
1.6
3.0
0.2
V
V
RL = 27 Ω or 50 Ω, see Figure 38
RL = 27 Ω or 50 Ω, see Figure 38
Output Short-Circuit Current
ADM3063E/ADM3067E Output
Leakage (Y, Z)
IOS
IO
−250
−100
+250
+100
mA −7 V < output voltage (VOUT) < +12 V
µA
DE = 0 V, RE = 0 V, VCC = 0 V or 3.6 V,
input voltage (VIN) = 12 V
µA
RE
DE = 0 V, = 0 V, VCC = 0 V or 3.6 V, VIN = −7 V
Logic Inputs (DE, RE, DI)
Input Voltage
Low
VIL
VIH
II
0.33 × VIO
+2
V
RE
DE, , DI, 1.62 V ≤ V ≤ 5.5 V
IO
High
0.67 × VIO
−2
V
RE
DE, , DI, 1.62 V ≤ V ≤ 5.5 V
IO
Input Current
µA
RE
DE, , DI, 1.62 V ≤ V ≤ 5.5 V, 0 V ≤ V ≤ V
IO
IN
IO
Rev. F | Page 5 of 28
ADM3061E/ADM3062E/ADM3063E/ADM3065E/ADM3066E/ADM3067E/ADM3068E Data Sheet
Parameter
Symbol Min
Typ Max
Unit Test Conditions/Comments
RECEIVER
Differential Inputs
Differential Input Threshold Voltage
Input Voltage Hysteresis
Input Current (A, B)
VTH
VHYS
II
−200
−125 −30
30
mV −7 V < VCM < +12 V
mV −7 V < VCM < +12 V
mA DE = 0 V, VCC = powered/unpowered, VIN = 12 V
mA DE = 0 V, VCC = powered/unpowered, VIN = −7 V
0.1
0.25
−0.20
48
−0.1
96
Line Input Resistance
Logic Outputs
Output Voltage
Low
RIN
kΩ
−7 V ≤ VCM ≤ +12 V
VOL
0.4
V
VIO = 3.6 V, output current (IOUT) = 2 mA,
VID3 ≤ −0.2 V
0.4
0.2
V
V
V
V
V
VIO = 2.7 V, IOUT = 1 mA, VID ≤ −0.2 V2
VIO = 1.95 V, IOUT = +500 µA, VID ≤ −0.2 V2
VIO = 3.0 V, IOUT = −2 mA, VID ≥ −0.03 V
VIO = 2.3 V, IOUT = −1 mA, VID ≥ −0.03 V2
VIO = 1.65 V, IOUT = −500 µA, VID ≥ −0.03 V2
High
VOH
2.4
2.0
VIO − 0.2
Short-Circuit Current
Three-State Output Leakage
85
2
mA VOUT = GND or VIO
µA RO pin = 0 V or VIO
IOZR
1 VIO = VCC for ADM3061E/ADM3063E/ADM3065E/ADM3067E.
2 ADM3062E/ADM3066E/ADM3068E only.
3 VID is the receiver input differential voltage.
Rev. F | Page 6 of 28
Data Sheet ADM3061E/ADM3062E/ADM3063E/ADM3065E/ADM3066E/ADM3067E/ADM3068E
TIMING SPECIFICATIONS
ADM3061E/ADM3062E/ADM3063E
VCC = 3.0 V to 5.5 V, VIO = 1.62 V to VCC (ADM3062E), TA = TMIN (−40°C) to TMAX (+125°C), unless otherwise noted. All typical
specifications are at TA = 25°C, VIO = VCC = 3.3 V, unless otherwise noted.
Table 3.
Parameter
Symbol
Min Typ Max Unit Test Conditions/Comments
DRIVER
Maximum Data Rate1
Propagation Delay
500
kbps
ns
tDPLH, tDPHL
tDSKEW
220 800
100
120 300 800
RLDIFF capacitor = 54 Ω, CL1 capacitor = CL2 capacitor =
100 pF, see Figure 5 and Figure 40
RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, see Figure 5 and
Figure 40
RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, see Figure 5 and
Figure 40
Skew
5
ns
ns
Rise/Fall Times
tDR, tDF
Enable to Output High
Enable to Output Low
Disable Time from Low
Disable Time from High
Enable Time from Shutdown to High
Enable Time from Shutdown to Low
RECEIVER
tDZH
tDZL
tDLZ
tDHZ
tDZH(SHDN)
tDZL(SHDN)
100 1000 ns
RL = 110 Ω, CL = 50 pF, see Figure 6 and Figure 41
RL = 110 Ω, CL = 50 pF, see Figure 6 and Figure 41
RL = 110 Ω, CL = 50 pF, see Figure 6 and Figure 41
RL = 110 Ω, CL = 50 pF, see Figure 6 and Figure 41
RL = 110 Ω, CL = 50 pF, see Figure 6 and Figure 41
RL = 110 Ω, CL = 50 pF, see Figure 6 and Figure 41
100 1000 ns
350 2000 ns
600 2000 ns
550 2000 ns
550 2000 ns
2
2
Maximum Data Rate
Propagation Delay
500
kbps
ns
tRPLH, tRPHL
tRSKEW
tRZH
200
50
50
50
50
50
CL = 15 pF, |VID| ≥ 1.5 V, VCM = 1.5 V, see Figure 7 and
Figure 42
CL = 15 pF, |VID| ≥ 1.5 V, VCM = 1.5 V, see Figure 7 and
Figure 42
RL = 1 kΩ, CL = 15 pF, |VID| ≥ 1.5 V, DE high, see Figure 8
and Figure 44
RL = 1 kΩ, CL = 15 pF, |VID| ≥ 1.5 V, DE high, see Figure 8
and Figure 44
RL = 1 kΩ, CL = 15 pF, |VID| ≥ 1.5 V, see Figure 8 and
Figure 44
RL = 1 kΩ, CL = 15 pF, |VID| ≥ 1.5 V, see Figure 8 and
Figure 44
RL = 1 kΩ, CL = 15 pF, |VID| ≥ 1.5 V, see Figure 8 and
Figure 43
Skew/Pulse Width Distortion
Enable to Output High
ns
ns
ns
ns
ns
10
10
10
10
Enable to Output Low
tRZL
Disable Time from Low
tRLZ
Disable Time from High
Enable from Shutdown to High
Enable from Shutdown to Low
TIME TO SHUTDOWN
tRHZ
3
tRZH(SHDN)
2000 ns
2000 ns
ns
3
tRZL(SHDN)
RL = 1 kΩ, CL = 15 pF, |VID| ≥ 1.5 V, see Figure 8 and
Figure 43
4
tSHDN
40
1 Maximum data rate assumes a ratio of tDR:tBIT:tDF equal to 1:0.5:1.
2
RE
tDZH(SHDN) and tDZL(SHDN) refer to the time for the device to enable when DE changes from 0 V to VCC. = VCC for this condition.
3
4
RE
tRZH(SHDN) and tRZL(SHDN) refer to the time for the device to enable when changes from VCC to 0 V. DE = 0 V for this condition.
Minimum time required to put the device into shutdown: DE and must be disabled for more than 40 ns for the device to go into shutdown.
RE
Rev. F | Page 7 of 28
ADM3061E/ADM3062E/ADM3063E/ADM3065E/ADM3066E/ADM3067E/ADM3068E Data Sheet
ADM3065E/ADM3066E/ADM3067E/ADM3068E
VCC = 3.0 V to 5.5 V, VIO = 1.62 V to VCC (ADM3066E/ADM3068E), TA = TMIN (−40°C) to TMAX (+125°C), unless otherwise noted. All
typical specifications are at TA = 25°C, VIO = VCC = 3.3 V, unless otherwise noted.
Table 4.
Parameter
Symbol
Min Typ Max Unit
Test Conditions/Comments
DRIVER
Maximum Data Rate1
Propagation Delay
50
Mbps
ns
tDPLH, tDPHL
tDSKEW
9
1
4
15
2
RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, see Figure 5 and
Figure 40
RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, see Figure 5 and
Figure 40
RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, see Figure 5 and
Figure 40
Skew
ns
ns
Rise/Fall Times
tDR, tDF
6.7
Enable to Output High
Enable to Output Low
Disable Time from Low
Disable Time from High
Enable Time from Shutdown to High
Enable Time from Shutdown to Low
RECEIVER
tDZH
tDZL
tDLZ
tDHZ
tDZH(SHDN)
tDZL(SHDN)
10
10
10
10
30
30
30
30
ns
ns
ns
ns
RL = 110 Ω, CL = 50 pF, see Figure 6 and Figure 41
RL = 110 Ω, CL = 50 pF, see Figure 6 and Figure 41
RL = 110 Ω, CL = 50 pF, see Figure 6 and Figure 41
RL = 110 Ω, CL = 50 pF, see Figure 6 and Figure 41
RL = 110 Ω, CL = 50 pF, see Figure 6 and Figure 41
RL = 110 Ω, CL = 50 pF, see Figure 6 and Figure 41
2
550 2000 ns
550 2000 ns
2
Maximum Data Rate
Propagation Delay
50
Mbps
ns
tRPLH, tRPHL
tRSKEW
tRZH
20
1
35
3
CL = 15 pF, |VID| ≥ 1.5 V, VCM = 1.5 V, see Figure 7 and
Figure 42
CL = 15 pF, |VID| ≥ 1.5 V, VCM = 1.5 V, see Figure 7 and
Figure 42
RL = 1 kΩ, CL = 15 pF, |VID| ≥ 1.5 V, DE high,
see Figure 8 and Figure 44
RL = 1 kΩ, CL = 15 pF, |VID| ≥ 1.5 V, DE high,
see Figure 8 and Figure 44
RL = 1 kΩ, CL = 15 pF, |VID| ≥ 1.5 V, see Figure 8 and
Figure 44
RL = 1 kΩ, CL = 15 pF, |VID| ≥ 1.5 V, see Figure 8 and
Figure 44
RL = 1 kΩ, CL = 15 pF, |VID| ≥ 1.5 V, see Figure 8 and
Figure 43
RL = 1 kΩ, CL = 15 pF, |VID| ≥ 1.5 V, see Figure 8 and
Figure 43
Skew/Pulse Width Distortion
Enable to Output High
ns
ns
ns
ns
ns
10
10
10
10
35
35
35
35
Enable to Output Low
tRZL
Disable Time from Low
tRLZ
Disable Time from High
Enable from Shutdown to High
Enable from Shutdown to Low
TIME TO SHUTDOWN
tRHZ
3
tRZH(SHDN)
450 2000 ns
450 2000 ns
ns
3
tRZL(SHDN)
4
tSHDN
40
1 Maximum data rate assumes a ratio of tDR:tBIT:tDF equal to 1:1:1.
2
RE
tDZH(SHDN) and tDZL(SHDN) refer to the time for the device to enable when DE changes from 0 V to VCC. = VCC for this condition.
3
4
RE
tRZH(SHDN) and tRZL(SHDN) refer to the time for the device to enable when changes from VCC to 0 V. DE = 0 V for this condition.
Minimum time required to put the device into shutdown: DE and must be disabled for more than 40 ns for the device to go into shutdown.
RE
Rev. F | Page 8 of 28
Data Sheet ADM3061E/ADM3062E/ADM3063E/ADM3065E/ADM3066E/ADM3067E/ADM3068E
Timing Diagrams
V
CC
1/2V
1/2V
CC
CC
tSKEW
= tDPLH – tDPHL
0V
tDPLH
tDPHL
B, Z
1/2V
OD
V
OD
Y, A
+V
OD
90% POINT
10% POINT
90% POINT
V
= V – V
(A) (B)
OD
V
OD
10% POINT
–V
OD
tDF
tDR
NOTES
1. V IS THE DIFFERENCE BETWEEN A AND B,
OD
WITH +V BEING THE MAXIMUM POINT OF V
,
OD
OD
AND –V
BEING THE MINIMUM POINT OF V
.
OD
OD
2. V = V FOR ADM3062E/ADM3066E/ADM3068E.
CC
IO
Figure 5. Driver Propagation Delay Rise and Fall Timing Diagram
V
IO
1/2V
tDLZ
DE
IO
1/2V
IO
0V
tDZL
V
CC
1/2 (V
+ V
)
CC
OL
A OR B
V
+ 0.5V
– 0.5V
OL
V
V
OL
OH
tDZH
tDHZ
V
A OR B
NOTES
OH
1/2V
OH
0V
1. V = V FOR ADM3061E/ADM3063E/ADM3065E/ADM3067E
IO
CC
2. A = Y, B = Z FOR ADM3063E/ADM3067E/ADM3068E
Figure 6. Driver Enable and Disable Timing Diagram
A – B
0V
0V
tRPLH
tRPHL
V
V
OH
1/2V
1/2V
CC
CC
RO
tRSKEW
= |tRPLH – tRPHL|
OL
NOTES
1. V = V FOR ADM3062E/ADM3066E/ADM3068E.
CC
IO
Figure 7. Receiver Propagation Delay Timing Diagram
Rev. F | Page 9 of 28
ADM3061E/ADM3062E/ADM3063E/ADM3065E/ADM3066E/ADM3067E/ADM3068E Data Sheet
V
CC
RE
1/2V
tRZL
1/2V
CC
CC
0V
tRLZ
V
CC
1/2V
1/2V
CC
RO
V
V
+ 0.5V
OL
OUTPUT LOW
V
V
OL
tRHZ
tRZH
OUTPUT HIGH
CC
OH
– 0.5V
RO
OH
0V
NOTES
1. V = V FOR ADM3062E/ADM3066E/ADM3068E.
CC
IO
Figure 8. Receiver Enable and Disable Timing Diagram
Rev. F | Page 10 of 28
Data Sheet ADM3061E/ADM3062E/ADM3063E/ADM3065E/ADM3066E/ADM3067E/ADM3068E
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 5.
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Careful attention to
PCB thermal design is required.
Parameter
Rating
VCC to GND
VIO to GND
6 V
−0.3 V to +6 V
Digital Input and Output Voltage (DE, RE, DI,
and RO)
Driver Output and Receiver Input Voltage
Operating Temperature Ranges
−0.3 V to
θJA is the natural convection junction to ambient thermal
resistance measured in a one cubic foot sealed enclosure.
VIO1 + 0.3 V
−9 V to +14 V
θJC is the junction to case thermal resistance.
−40°C to +85°C
−40°C to +125°C
−65°C to +150°C
Table 6. Thermal Resistance
Storage Temperature Range
Continuous Total Power Dissipation
8-Lead SOIC_N
8-Lead MSOP
10-Lead MSOP
10-Lead LFCSP
14-Lead SOIC_N
Maximum Junction Temperature (TJ)
Lead Temperature
1
1
Package Type
θJA
θJC
Unit
°C/W
°C/W
°C/W
°C/W
°C/W
R-8
RM-8
RM-10
R-14
CP-10-9
110.88
165.69
165.69
104.5
58.63
49.61
49.61
42.90
33.22
0.225 W
0.151 W
0.151 W
0.450 W
0.239 W
150°C
55.65
1 Thermal impedance simulated values are based on JEDEC 2S2P thermal test
board with no bias. See JEDEC JESD-51.
ESD CAUTION
Soldering (10 sec)
Vapor Phase (60 sec)
Infrared (15 sec)
300°C
215°C
220°C
ESD on the Bus Pins (A, B, Y, Z)
IEC 61000-4-2 Contact Discharge
IEC 61000-4-2 Air Discharge
12 kV
10 Positive and 10 Negative
Discharges
Three Positive or Three Negative
Discharges
12 kV
15 kV
ESD Human Body Model (HBM)
On the Bus Pins (A, B, Y, Z)
All Other Pins
≥ 30 kV
8 kV
1 VIO = VCC on the ADM3061E/ADM3063E/ADM3065E/ADM3067E.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Rev. F | Page 11 of 28
ADM3061E/ADM3062E/ADM3063E/ADM3065E/ADM3066E/ADM3067E/ADM3068E Data Sheet
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
RO
RE
DE
DI
1
2
3
4
8
7
6
5
V
CC
RO
RE
DE
DI
1
2
3
4
8
7
6
5
V
CC
ADM3061E/
ADM3065E
B
ADM3061E/
ADM3065E
B
A
TOP VIEW
A
TOP VIEW
(Not to Scale)
GND
(Not to Scale)
GND
Figure 10. ADM3061E/ADM3065E 8-Lead MSOP Pin Configuration
Figure 9. ADM3061E/ADM3065E 8-Lead Narrow Body SOIC_N Pin
Configuration
Table 7. ADM3061E/ADM3065E Pin Function Descriptions
Pin No. Mnemonic Description
1
2
3
RO
Receiver Output Data. This output is high when (A − B) ≥ −30 mV and low when (A − B) ≤ −200 mV. This output is
tristated when the receiver is disabled; that is, when RE is driven high.
Receiver Enable Input. This is an active low input. Driving this input low enables the receiver and driving it high
disables the receiver.
Driver Enable. A high level on this pin enables the driver differential outputs, A and B. A low level places the driver
output into a high impedance state.
RE
DE
4
5
6
DI
GND
A
Transmit Data Input. Data to be transmitted by the driver is applied to this input.
Ground.
Noninverting Driver Output and Receiver Input. When the driver is disabled, or when VCC is powered down, Pin A is
put into a high impedance state to avoid overloading the bus.
7
8
B
Inverting Driver Output and Receiver Input. When the driver is disabled, or when VCC is powered down, Pin B is put
into a high impedance state to avoid overloading the bus.
3.0 V to 5.5 V Power Supply. Adding a 0.1 µF decoupling capacitor between the VCC pin and the GND pin is recommended.
VCC
Rev. F | Page 12 of 28
Data Sheet ADM3061E/ADM3062E/ADM3063E/ADM3065E/ADM3066E/ADM3067E/ADM3068E
V
1
2
3
4
5
10
9
V
CC
IO
V
1
10 V
IO
CC
RO
DE
RE
DI
B
ADM3062E/
ADM3066E
RO 2
DE 3
RE 4
DI 5
9
8
7
6
B
ADM3062E/
ADM3066E
8
A
A
7
NIC
GND
TOP VIEW
(Not to Scale)
TOP VIEW
NIC
GND
(Not to Scale)
6
1. NIC = NO INTERNAL CONNECTION. THIS
PIN IS NOT INTERNALLY CONNECTED.
NOTES
1. NIC = NO INTERNAL CONNECTION. THIS
PIN IS NOT INTERNALLY CONNECTED.
2. EXPOSED PAD. THE EXPOSED PAD
MUST BE CONNECTED TO GROUND.
Figure 11. ADM3062E/ADM3066E 10-Lead LFCSP Pin Configuration
Figure 12. ADM3062E/ADM3066E 10-Lead MSOP Pin Configuration
Table 8. ADM3066E/ADM3062E Pin Function Descriptions
Pin No. Mnemonic Description
1
2
3
4
VIO
RO
DE
RE
1.62 V to 5.5 V Logic Supply. Adding a 0.1 μF decoupling capacitor between the VIO pin and the GND pin is
recommended.
Receiver Output Data. This output is high when (A − B) ≥ −30 mV and is low when (A − B) ≤ −200 mV. This output is
tristated when the receiver is disabled; that is, when RE is driven high.
Driver Enable. A high level on this pin enables the driver differential outputs, A and B. A low level places the driver
output into a high impedance state.
Receiver Enable Input. This is an active low input. Driving this input low enables the receiver, and driving it high
disables the receiver.
5
6
7
8
DI
Transmit Data Input. Data to be transmitted by the driver is applied to this input.
Ground.
No Internal Connection. This pin is not internally connected.
Noninverting Driver Output and Receiver Input. When the driver is disabled, or when VCC is powered down, Pin A is
put into a high impedance state to avoid overloading the bus.
GND
NIC
A
9
B
Inverting Driver Output and Receiver Input. When the driver is disabled, or when VCC is powered down, Pin B is put
into a high impedance state to avoid overloading the bus.
10
VCC
EPAD
3.0 V to 5.5 V Power Supply. Adding a 0.1 μF decoupling capacitor between the VCC pin and the GND pin is recommended.
Exposed Pad. The exposed pad must be connected to ground.
Rev. F | Page 13 of 28
ADM3061E/ADM3062E/ADM3063E/ADM3065E/ADM3066E/ADM3067E/ADM3068E Data Sheet
NIC
RO
1
2
3
4
5
6
7
14
13
12
11
10
9
V
V
CC
CC
RE
A
ADM3063E/
ADM3067E
DE
B
TOP VIEW
DI
Z
(Not to Scale)
GND
GND
Y
8
NIC
NIC = NO INTERNAL CONNECTION. THIS
PIN IS NOT INTERNALLY CONNECTED.
Figure 13. ADM3063E/ADM3067E 14-Lead SOIC Pin Configuration
Table 9. ADM3063E/ADM3067E Pin Function Descriptions
Pin No. Mnemonic Description
1, 8
2
NIC
RO
No Internal Connection. This pin is not internally connected.
Receiver Output Data. This output is high when (A − B) ≥ −30 mV and is low when (A − B) ≤ −200 mV. This output is
tristated when the receiver is disabled; that is, when RE is driven high.
3
4
Receiver Enable Input. This is an active low input. Driving this input low enables the receiver and driving it high
disables the receiver.
Driver Enable. A high level on this pin enables the driver differential outputs, Y and Z. A low level places the driver
output into a high impedance state.
RE
DE
5
6, 7
9
DI
GND
Y
Transmit Data Input. Data to be transmitted by the driver is applied to this input.
Ground.
Driver Noninverting Output. When the driver is disabled, or when VCC is powered down, Pin Y is put into a high
impedance state to avoid overloading the bus.
10
Z
Driver Inverting Output. When the driver is disabled, or when VCC is powered down, Pin Z is put into a high
impedance state to avoid overloading the bus.
11
B
Inverting Receiver Input.
12
A
Noninverting Receiver Input.
13, 14
VCC
3.0 V to 5.5 V Power Supply. Adding a 0.1 µF decoupling capacitor between the VCC pin and the GND pin is
recommended.
Rev. F | Page 14 of 28
Data Sheet ADM3061E/ADM3062E/ADM3063E/ADM3065E/ADM3066E/ADM3067E/ADM3068E
V
1
2
3
4
5
6
7
14 V
IO
CC
RO
DE
13 NIC
12
11
10
9
A
ADM3068E
RE
B
TOP VIEW
(Not to Scale)
DI
Z
GND
NIC
Y
8
GND
NIC = NO INTERNAL CONNECTION. THIS
PIN IS NOT INTERNALLY CONNECTED.
Figure 14. ADM3068E 14-Lead SOIC Pin Configuration
Table 10. ADM3068E Pin Function Descriptions
Pin No. Mnemonic Description
1
2
3
4
VIO
RO
DE
RE
1.62 V to 5.5 V Logic Supply. Adding a 0.1 µF decoupling capacitor between the VIO pin and the GND pin is
recommended.
Receiver Output Data. This output is high when (A − B) ≥ −30 mV and is low when (A − B) ≤ −200 mV. This output is
tristated when the receiver is disabled; that is, when RE is driven high.
Driver Enable. A high level on this pin enables the driver differential outputs, Y and Z. A low level places the driver
output into a high impedance state.
Receiver Enable Input. This is an active low input. Driving this input low enables the receiver and driving it high
disables the receiver.
5
DI
Transmit Data Input. Data to be transmitted by the driver is applied to this input.
Ground.
No Internal Connection. This pin is not internally connected.
Driver Noninverting Output. When the driver is disabled, or when VCC is powered down, Pin Y is put into a high
impedance state to avoid overloading the bus.
6, 8
7, 13
9
GND
NIC
Y
10
Z
Driver Inverting Output. When the driver is disabled, or when VCC is powered down, Pin Z is put into a high
impedance state to avoid overloading the bus.
11
12
14
B
A
VCC
Inverting Receiver Input.
Noninverting Receiver Input.
3.0 V to 5.5 V Power Supply. Adding a 0.1 µF decoupling capacitor between the VCC pin and the GND pin is
recommended.
Rev. F | Page 15 of 28
ADM3061E/ADM3062E/ADM3063E/ADM3065E/ADM3066E/ADM3067E/ADM3068E Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
400
350
300
250
200
150
100
50
0.12
0.10
0.08
0.06
0.04
0.02
0
V
V
V
= 5.5V
= 4.5V
= 3.3V
CC
CC
CC
V
= 5.5V
CC
V
= 5.0V
CC
V
= 3.3V
CC
0
–40 –25 –10
5
20
35
50
65
80 95 110 125
0
5
10
15
20
25
30
35
40
45
50
TEMPERATURE (°C)
DATA RATE (Mbps)
Figure 18. Supply Current (ICC) vs. Data Rate with 54 Ω Load Resistance,
50 Mbps Models
Figure 15. Shutdown Current (ISHDN) vs. Temperature
0.08
0.07
0.06
0.05
0.04
0.03
0.02
0.01
0
0.08
0.07
0.06
0.05
R
= 54Ω
L
R
= 120Ω
L
V
= 5.5V
CC
NO LOAD
0.04
0.03
0.02
0.01
0
V
= 5.0V
CC
V
= 3.3V
CC
–40 –25 –10
5
20
35
50
65
80 95 110 125
0
5
10
15
20
25
30
35
40
45
50
TEMPERATURE (°C)
DATA RATE (Mbps)
Figure 19. Supply Current (ICC) vs. Data Rate with No Load Resistance,
50 Mbps Models
Figure 16. Supply Current (ICC) vs. Temperature, Data Rate = 50 Mbps,
50 Mbps Models, VCC = 3.3 V
0.12
0.10
V
V
V
V
= 3.3V, NO LOAD
= 3.3V, 54Ω LOAD
= 5V, NO LOAD
= 5V, 54Ω LOAD
CC
CC
CC
CC
R
= 54Ω
L
0.10
0.08
0.06
0.04
0.02
0
0.08
0.06
0.04
0.02
0
R
= 120Ω
L
NO LOAD
0
50
100 150 200 250 300 350 400 450 500
DATA RATE (kbps)
–55
–35
–15
5
25
45
65
85
105
125
TEMPERATURE (°C)
Figure 20. Supply Current (ICC) vs. Data Rate with 54 Ω Load Resistance and
No Load Resistance, 500 kbps Models
Figure 17. Supply Current (ICC) vs. Temperature, Data Rate = 50 Mbps,
50 Mbps Models, VCC = 5.0 V
Rev. F | Page 16 of 28
Data Sheet ADM3061E/ADM3062E/ADM3063E/ADM3065E/ADM3066E/ADM3067E/ADM3068E
60
50
V
ID
1
40
30
20
10
0
R
OUT
2
B
B
W
–55
–35
–15
5
25
45
65
85
105
125
CH1 1.0V
A CH1
0V
CH2 1.0V
W
TEMPERATURE (°C)
Figure 24. Receiver Propagation Delay (Oscilloscope Plot),
Data Rate = 500 kbps, VID ≥ 1.5 V
Figure 21. Supply Current (ICC) vs. Temperature, Data Rate = 500 kbps,
500 kbps Models, VCC = 3.0 V
140
120
100
80
DI
1
A
B
60
2
40
M1
V
OD
20
0
B
B
B
W
CH1 3.0V
CH3 2.0V
CH2 2.0V
M1 2.5V
A CH1
1.98V
W
W
–60 –40 –20
0
20
40
60
80
100 120 140
TEMPERATURE (°C)
Figure 25. Driver Propagation Delay (Oscilloscope Plot),
Data Rate = 500 kbps, 500 kbps Models
Figure 22. Supply Current (ICC) vs. Temperature, Data Rate = 500 kbps,
500 kbps Models, VCC = 5.5 V
12
300
tDPLH AT 5.5V
tDPHL AT 5.5V
11
10
9
280
tDPLH AT 3.0V
tDPHL AT 3.0V
260
240
220
200
180
160
140
8
7
tDPHL
tDPLH
tDPHL
tDPLH
V
V
V
V
= 3.0V
= 3.0V
= 5.5V
= 5.5V
,
,
,
,
CC
CC
CC
CC
6
5
4
–60 –40 –20
0
20
40
60
80
100 120 140
–40 –25 –10
5
20
35
50
65
80 95 110 125
TEMPERATURE (°C)
TEMPERATURE (⁰C)
Figure 26. Driver Differential Propagation Delay vs. Temperature, 50 Mbps
Models
Figure 23. Driver Differential Propagation Delay vs. Temperature,
500 kbps Models
Rev. F | Page 17 of 28
ADM3061E/ADM3062E/ADM3063E/ADM3065E/ADM3066E/ADM3067E/ADM3068E Data Sheet
0.04
V
= V = 3.3 V
CC
IO
DI
0.02
0
1
–0.02
–0.04
–0.06
–0.08
–0.10
V
OD
2
B
B
C1 1.0V/DIV
C2 2.0V/DIV
50Ω
50Ω
: 1.5G
: 1.5G
20ns/DIV
5.0GS/s
200ps/pt
A C1 1.34V
W
W
–7 –6 –5 –4 –3 –2 –1
0
1
2
3
4
5
DRIVER OUTPUT HIGH VOLTAGE (V)
Figure 27. Driver Propagation Delay (Oscilloscope Plot),
Data Rate = 50 Mbps, 50 Mbps models
Figure 30. Driver Output Current vs. Driver Output High Voltage
0.10
0.04
0.02
V
= V = 3.3 V
IO CC
0.09
0.08
0.07
0.06
0.05
0.04
0.03
0.02
0.01
0
0
–0.02
–0.04
–0.06
–0.08
–0.10
–0.12
V
V
V
= 5.5V
= 4.5V
= 3.0V
CC
CC
CC
0
2
4
6
8
10
12
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0
DRIVER DIFFERENTIAL OUTPUT VOLTAGE (V)
DRIVER OUTPUT LOW VOLTAGE (V)
Figure 28. Driver Output Current vs. Driver Differential Output Voltage
Figure 31. Driver Output Current vs. Driver Output Low Voltage
3.2
3.0
V
ID
V
= 4.5V
CC
2.8
2.6
2.4
2.2
2.0
1.8
1.6
1.4
1
RO
V
= 3.0V
CC
2
B
B
C1 1.0V/DIV
C2 1.0V/DIV
50Ω
50Ω
: 1.5G
20ns/DIV
5.0GS/s
200ps/pt
A C1 0.0V
W
W
–40 –25 –10
5
20
35
50
65
80 95 110 125
: 1.5G
TEMPERATURE (°C)
Figure 29. Driver Differential Output Voltage vs. Temperature
Figure 32. Receiver Propagation Delay at 50 Mbps, |VID| ≥ 1.5 V
Rev. F | Page 18 of 28
Data Sheet ADM3061E/ADM3062E/ADM3063E/ADM3065E/ADM3066E/ADM3067E/ADM3068E
6.0
5.8
5.6
5.4
5.2
5.0
28
26
24
22
20
18
16
tRPHL
tRPLH
–40 –25 –10
5
20
35
50
65
80 95 110 125
–40 –25 –10
5
20
35
50
65
80 95 110 125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 33. Receiver Propagation Delay vs. Temperature, 50 Mbps
Figure 36. Receiver Output High Voltage vs. Temperature
0.035
0.25
0.20
0.15
0.10
0.05
0
V
= 3.3V
CC
0.030
0.025
0.020
0.015
0.010
0.005
0
–40 –25 –10
5
20
35
50
65
80 95 110 125
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
TEMPERATURE (°C)
RECEIVER OUTPUT LOW VOLTAGE (V)
Figure 34. Receiver Output Current vs. Receiver Output Low Voltage
(VCC = 3.3 V)
Figure 37. Receiver Output Low Voltage vs. Temperature
0
V
= 3.3V
CC
–0.005
–0.010
–0.015
–0.020
–0.025
–0.030
–0.035
–0.040
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
RECEIVER OUTPUT HIGH VOLTAGE (V)
Figure 35. Receiver Output Current vs. Receiver Output High Voltage
(VCC = 3.3 V)
Rev. F | Page 19 of 28
ADM3061E/ADM3062E/ADM3063E/ADM3065E/ADM3066E/ADM3067E/ADM3068E Data Sheet
TEST CIRCUITS
A
R
R
L
INPUT
GENERATOR
V
V
V
OUT
DI
OD2
IN
RE
C
L
V
L
B
OC
RE = 0V
Figure 38. Driver Voltage Measurements
Figure 42. Receiver Propagation Delay/Skew
+1.5V
–1.5V
375Ω
V
CC
S1
R
V
L
V
CM
DI
OD3
60Ω
S2
RE
C
V
OUT
L
375Ω
RE IN
NOTES
1. V = V FOR ADM3062E/ADM3066E/ADM3068E.
CC IO
Figure 39. Driver Voltage Measurements over Common-Mode Range
Figure 43. Receiver Enable/Disable from Shutdown
V
CC
V
CC
C
L1
DE
DI
R
LDIFF
DI
S1
D
C
L2
V
CC
A
B
Figure 40. Driver Propagation Delay
V
OUT
R
L
S2
R
V
CC
C
L
RE
R
L
0V OR V
S2
S1
IO
RE IN
NOTES
DE
C
L
DE IN
NOTES
1. V = V FOR ADM3062E/ADM3066E/ADM3068E.
CC
IO
1. V = V FOR ADM3061E/ADM3063E/ADM3065E/ADM3067E.
IO
CC
Figure 44. Receiver Enable/Disable
Figure 41. Driver Enable/Disable
Rev. F | Page 20 of 28
Data Sheet ADM3061E/ADM3062E/ADM3063E/ADM3065E/ADM3066E/ADM3067E/ADM3068E
THEORY OF OPERATION
I
PEAK
IEC ESD PROTECTED RS-485
30A
90%
The ADM3065E/ADM3066E/ADM3067E/ADM3068E are 3.0 V
to 5.5 V, 50 Mbps RS-485 transceivers with IEC 61000-4-2 Level 4
ESD protection on the bus pins. The ADM3061E/ADM3062E/
ADM3063E/ADM3065E/ADM3066E/ADM3067E/ADM3068E
can withstand up to 12 kV contact discharge on transceiver
bus pins (A, B, Y, and Z) without latch-up or damage. The
ADM3061E/ADM3062E/ADM3063E has the same robust IEC
61000-4-2 ESD protection as the ADM3065E/ADM3066E/
ADM3067E/ADM3068E models and operate at a lower,
500 kbps data rate.
16A
I
I
30ns
60ns
8A
10%
TIME
60ns
30ns
HIGH DRIVER DIFFERENTIAL OUTPUT VOLTAGE
tR = 0.7ns TO 1ns
The ADM3061E/ADM3062E/ADM3063E/ADM3065E/
ADM3066E/ADM3067E/ADM3068E have characteristics that
are optimized for use in PROFIBUS applications. When powered at
Figure 45. IEC 61000-4-2 ESD Waveform (8 kV)
Figure 46 shows the 8 kV contact discharge current waveform
from the IEC 61000-4-2 standard compared to the HBM ESD
8 kV waveform. Figure 46 shows that the two standards specify a
different waveform shape and peak current. The peak current
associated with an IEC 61000-4-2 8 kV pulse is 30 A, whereas
the corresponding peak current for HBM ESD is more than five
times less, at 5.33 A. The other difference is the rise time of the
initial voltage spike, with the IEC 61000-4-2 ESD waveform having
a much faster rise time of 1 ns, compared to the 10 ns associated
with the HBM ESD waveform. The amount of power associated
with an IEC ESD waveform is much greater than that of an
HBM ESD waveform. The HBM ESD standard requires the
EUT to be subjected to three positive and three negative
discharges, whereas the IEC ESD standard requires 10 positive
and 10 negative discharge tests.
V
CC ≥ 4.5 V, the ADM3061E/ADM3062E/ADM3063E/
ADM3065E/ADM3066E/ADM3067E/ADM3068E driver output
differential voltage meets or exceeds the PROFIBUS requirements
of 2.1 V with a 54 Ω load.
IEC 61000-4-2 ESD PROTECTION
ESD is the sudden transfer of electrostatic charge between bodies at
different potentials caused either by near contact or induced by
an electric field. It has the characteristics of high current in a
short time period. The primary purpose of the IEC 61000-4-2
test is to determine the immunity of systems to external ESD
events outside the system during operation. IEC 61000-4-2
describes testing using two coupling methods: contact discharge
and air discharge. Contact discharge implies a direct contact
between the discharge gun and the equipment under test (EUT).
During air discharge testing, the charged electrode of the
discharge gun is moved toward the EUT until a discharge
occurs as an arc across the air gap. The discharge gun does not
make direct contact with the EUT. A number of factors affect
the results and repeatability of the air discharge test, including
humidity, temperature, barometric pressure, distance, and rate
of approach to the EUT. This method is a more accurate
representation of an actual ESD event but is not as repeatable.
Therefore, contact discharge is the preferred test method.
The ADM3061E/ADM3062E/ADM3063E/ADM3065E/
ADM3066E/ADM3067E/ADM3068E with IEC 61000-4-2 ESD
ratings is better suited for operation in harsh environments
compared to other RS-485 transceivers that state varying levels
of HBM ESD protection.
I
PEAK
30A
90%
During testing, the data port is subjected to at least 10 positive
and 10 negative single discharges. Selection of the test voltage is
dependent on the system end environment.
IEC 61000-4-2 ESD 8kV
16A
8A
I
I
30ns
60ns
Figure 45 shows the 8 kV contact discharge current waveform
as described in the IEC 61000-4-2 specification. Some of the
key waveform parameters are rise times of less than 1 ns and
pulse widths of approximately 60 ns.
5.33A
HBM ESD 8kV
10%
TIME
60ns
10ns
tR = 0.7ns TO 1ns
30ns
Figure 46. IEC 61000-4-2 ESD Waveform 8 kV Compared to HBM ESD
Waveform 8 kV
Rev. F | Page 21 of 28
ADM3061E/ADM3062E/ADM3063E/ADM3065E/ADM3066E/ADM3067E/ADM3068E Data Sheet
If the (A − B) input is less than or equal to −200 mV, RO is logic
low. In the case of a shorted, open circuit or terminated bus with all
transmitters disabled, the receiver differential input voltage is
pulled to 0 V, resulting in a logic high with a 30 mV minimum
noise margin.
TRUTH TABLES
Table 12 and Table 13 use the abbreviations shown in Table 11.
Table 11. Truth Table Abbreviations
Letter
Description
H
I
L
X
Z
High level
Indeterminate
Low level
Any state
High impedance (off)
HOT SWAP CAPABILITY
When a circuit board is inserted into a powered (or hot)
backplane, differential disturbances to the data bus can lead to
data errors. During this period, processor logic output drivers
RE
are high impedance and are unable to drive the DE and
inputs of the RS-485 transceivers to a defined logic level. Leakage
currents up to 10 µA from the high impedance state of the
processor logic drivers can cause standard complementary
metal-oxide semiconductor (CMOS) enable inputs of a
transceiver to drift to an incorrect logic level. Additionally,
parasitic circuit board capacitance can cause coupling of VCC
or GND to the enable inputs. Without the hot swap capability,
these factors can improperly enable the driver or receiver of
the transceiver. When VCC or VIO rises, an internal pull-down
Table 12. Transmitting Truth Table
Supply Status
Inputs
Outputs
B/Z
1
VIO
VCC
RE
X
X
X
X
DE
DI
A/Y
On
On
On
Off
On
Off
On
On
On
On
Off
Off
H
H
L
X
X
X
H
L
X
X
X
X
H
L
Z
I
Z
Z
L
H
Z
I
Z
Z
X
X
RE
circuit holds DE low and
high. After the initial power-up
1 For the ADM3061E, ADM3063E, ADM3065E, and ADM3067E, the VIO pin is
not applicable.
sequence, the pull-down circuit becomes transparent, resetting
the hot swap tolerable input.
Table 13. Receiving Truth Table
128 TRANSCEIVERS ON THE BUS
Supply Status
Inputs
Outputs
RE DE RO
The standard RS-485 receiver input impedance is 12 kΩ
(one unit load), and the standard driver can drive up to 32 unit
loads. The ADM3061E/ADM3062E/ADM3063E/ADM3065E/
ADM3066E/ADM3067E/ADM3068E transceivers have a one
fourth unit load receiver input impedance (48 kΩ), allowing up to
128 transceivers to be connected in parallel on one communication
line. Any combination of these devices and other RS-485
transceivers with a total of 32 unit loads or fewer can be
connected to the line.
1
VIO
VCC
A − B
On
On
On
On
On
On
>−0.03 V
<−0.2 V
−0.2 V ≤ A – B ≤
−0.03 V
L
L
L
X
X
X
H
L
I
On
On
On
On
Off
Off
On
On
Off
Off
On
Off
Inputs open/shorted
L
H
L
H
L
X
X
X
X
X
X
X
H
Z
I
Z
I
X
X
X
X
X
DRIVER OUTPUT PROTECTION
I
The ADM3061E/ADM3062E/ADM3063E/ADM3065E/
ADM3066E/ADM3067E/ADM3068E feature two methods to
prevent excessive output current and power dissipation caused
by faults or by bus contention. Current-limit protection on the
output stage provides immediate protection against short circuits
over the whole common-mode voltage range. In addition, a
thermal shutdown circuit forces the driver outputs into a high
impedance state if the die temperature rises excessively. This
circuitry is designed to disable the driver outputs when a die
temperature of 150°C is reached. As the device cools, the drivers
are reenabled at a temperature of 140°C.
1 For the ADM3061E, ADM3063E, ADM3065E, and ADM3067E, the VIO pin is
not applicable.
RECEIVER FAIL-SAFE
The ADM3061E/ADM3062E/ADM3063E/ADM3065E/
ADM3066E/ADM3067E/ADM3068E guarantee a logic high
receiver output when the receiver inputs are shorted, open, or
connected to a terminated transmission line with all drivers
disabled. This receiver output is achieved by setting the receiver
input threshold between −30 mV and −200 mV. If the differential
receiver input voltage (A − B) is greater than or equal to
−30 mV, the RO pin is logic high.
Rev. F | Page 22 of 28
Data Sheet ADM3061E/ADM3062E/ADM3063E/ADM3065E/ADM3066E/ADM3067E/ADM3068E
APPLICATIONS INFORMATION
The ADM3061E/ADM3065E transceiver is designed for
bidirectional data communications on multipoint bus
transmission lines. Figure 47 shows a typical network
applications circuit.
To minimize reflections, terminate the line at both ends with a
termination resistor (the value of the termination resistor must
be equal to the characteristic impedance of the cable used) and
keep stub lengths off the main line as short as possible.
V
V
CC
CC
ADM3061E/
ADM3065E
ADM3061E/
ADM3065E
R
R
RO
RE
RO
RE
A
A
R
R
T
T
DE
DI
DE
DI
B
B
D
D
GND
GND
V
V
CC
CC
ADM3061E/
ADM3065E
ADM3061E/
ADM3065E
R
R
RO
RE
RO
RE
A
B
A
B
DE
DI
DE
DI
D
D
GND
GND
NOTES
1. THE MAXIMUM NUMBER OF NODES IS 128.
2. R IS EQUAL TO THE CHARACTERISTIC IMPEDANCE OF THE CABLE USED.
T
Figure 47. ADM3061E/ADM3065E Typical Half-Duplex RS-485 Communications Network
Rev. F | Page 23 of 28
ADM3061E/ADM3062E/ADM3063E/ADM3065E/ADM3066E/ADM3067E/ADM3068E Data Sheet
switching elements to transfer power through the transformers.
Take care during PCB layout to meet emissions standards. See the
AN-0971 Application Note for PCB layout recommendations.
ISOLATED HIGH SPEED RS-485 NODE
Galvanic isolation, with reinforced insulation and 5 kV rms
transient withstand voltage, can be added to the ADM3065E
using Analog Devices, Inc., iCoupler® and isoPower® technology.
The ADuM6401 provides the required quad channels of 5 kV rms
signal isolation, operating at rates up to 25 Mbps, together with
an integrated dc-to-dc converter. The ADuM6401 combines with
the ADM3065E (shown in Figure 48) with the VISO pin configured
for 3.3 V by connecting the VSEL pin to GNDISO and a 5 V supply
connected to VDD1. Operation at 3.3 V ensures the ADM3065E
remains within the load capability of ADuM6401 even at 25 Mbps.
Galvanic isolation of the ADM3065E at the full data rate, up to
50 Mbps, can be implemented using the ADuM241D quad-
channel digital isolator and the ADuM6028 isolated dc-to-dc
converter, as shown in Figure 49. The ADuM6028 is an 8-pin
device that contains a 300 mW dc-to-dc converter optimized to
meet emissions standards on a 2-layer PCB using two ferrite
beads. The ADuM241D operates at a data rate up to 150 Mbps,
and offers the precise timing required to fully support the
ADM3065E at 50 Mbps.
The dc-to-dc converter in the ADuM6401 isoPower device
provides regulated, isolated power to the ADM3065E (and the
ADuM241D). These isoPower devices use high frequency
V
CC
5V
10nF
0.1µF
ADM3065E
V
V
ISO
DD1
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
0.1µF
GND
GND
1
ISO
RO
RE
R
V
FERRITE
BEAD
OA
V
IA
IB
IC
A
B
V
OB
V
V
4-CHANNEL iCOUPLER CORE
V
V
ADuM6401
OC
DE
DI
5V
ID
V
OD
D
V
V
SEL
DDL
0.1µF
GND
GND
ISO
1
GND
Figure 48. Signal and Power Isolated 25 Mbps RS-485 Solution (Simplified Diagram—All Connections Not Shown)
ADuM6028
V
PDIS
SEL
8
7
6
5
1
2
3
4
PCS
GND
V
GND
1
ISO
+5V
FERRITE BEAD
V
DDP
ISO
OSC
RECT
REG
10nF
10μF
0.1µF
GND
GND
1
ISO
FERRITE BEAD
+5V
V
CC
0.1µF
V
V
DD2
DD1
ADuM241D
GND
GND
2
1
0.1µF
RO
R
V
V
OA
OB
V
V
V
IA
IB
IC
ENCODE
ENCODE
ENCODE
DECODE
DECODE
DECODE
DECODE
ENCODE
A
B
RE
DE
V
V
OC
ID
V
OD
D
DISABLE , VE
1
DISABLE , VE
2 2
GND
DI
1
1
GND
2
ADM3065E
GND
Figure 49. Signal and Power Isolated 50 Mbps RS-485 Solution (Simplified Diagram—All Connections Not Shown)
Rev. F | Page 24 of 28
Data Sheet ADM3061E/ADM3062E/ADM3063E/ADM3065E/ADM3066E/ADM3067E/ADM3068E
OUTLINE DIMENSIONS
5.00 (0.1968)
4.80 (0.1890)
8
1
5
4
6.20 (0.2441)
5.80 (0.2284)
4.00 (0.1574)
3.80 (0.1497)
0.50 (0.0196)
0.25 (0.0099)
1.27 (0.0500)
BSC
45°
1.75 (0.0688)
1.35 (0.0532)
0.25 (0.0098)
0.10 (0.0040)
8°
0°
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
1.27 (0.0500)
0.40 (0.0157)
0.25 (0.0098)
0.17 (0.0067)
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MS-012-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 50. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
3.20
3.00
2.80
8
1
5
4
5.15
4.90
4.65
3.20
3.00
2.80
PIN 1
IDENTIFIER
0.65 BSC
0.95
0.85
0.75
15° MAX
1.10 MAX
0.80
0.55
0.40
0.15
0.05
0.23
0.09
6°
0°
0.40
0.25
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187-AA
Figure 51. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
Rev. F | Page 25 of 28
ADM3061E/ADM3062E/ADM3063E/ADM3065E/ADM3066E/ADM3067E/ADM3068E Data Sheet
3.10
3.00
2.90
10
1
6
5
5.15
4.90
4.65
3.10
3.00
2.90
PIN 1
IDENTIFIER
0.50 BSC
0.95
0.85
0.75
15° MAX
1.10 MAX
0.70
0.55
0.40
0.15
0.05
0.23
0.13
6°
0°
0.30
0.15
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187-BA
Figure 52. 10-Lead Mini Small Outline Package [MSOP]
(RM-10)
Dimensions shown in millimeters
DETAIL A
(JEDEC 95)
2.48
2.38
2.23
3.10
3.00 SQ
0.50 BSC
2.90
10
6
PIN 1 INDEX
AREA
EXPOSED
PAD
1.74
1.64
1.49
0.50
0.40
0.30
0.20 MIN
PIN 1
INDIC ATOR AREA OPTIONS
(SEE DETAIL A)
1
5
BOTTOM VIEW
TOP VIEW
SIDE VIEW
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.80
0.75
0.70
0.05 MAX
0.02 NOM
COPLANARITY
0.08
SECTION OF THIS DATA SHEET.
SEATING
PLANE
0.30
0.25
0.20
0.20 REF
Figure 53. 10-Lead Lead Frame Chip Scale Package [LFCSP]
3 mm × 3 mm Body and 0.75 mm Package Height
(CP-10-9)
Dimensions shown in millimeters
Rev. F | Page 26 of 28
Data Sheet ADM3061E/ADM3062E/ADM3063E/ADM3065E/ADM3066E/ADM3067E/ADM3068E
8.75 (0.3445)
8.55 (0.3366)
8
7
14
1
6.20 (0.2441)
5.80 (0.2283)
4.00 (0.1575)
3.80 (0.1496)
1.27 (0.0500)
0.50 (0.0197)
0.25 (0.0098)
45°
BSC
1.75 (0.0689)
1.35 (0.0531)
0.25 (0.0098)
0.10 (0.0039)
8°
0°
COPLANARITY
0.10
SEATING
PLANE
1.27 (0.0500)
0.40 (0.0157)
0.51 (0.0201)
0.31 (0.0122)
0.25 (0.0098)
0.17 (0.0067)
COMPLIANT TO JEDEC STANDARDS MS-012-AB
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 54. 14-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-14)
Dimensions shown in millimeters and (inches)
ORDERING GUIDE
Model1
Temperature Range Package Description
Package Option Marking Code
ADM3061EARZ
ADM3061EARZ-R7
ADM3061EBRZ
−40°C to +85°C
−40°C to +85°C
−40°C to +125°C
−40°C to +125°C
−40°C to +85°C
−40°C to +85°C
−40°C to +125°C
−40°C to +125°C
−40°C to +85°C
−40°C to +85°C
−40°C to +125°C
−40°C to +125°C
−40°C to +85°C
−40°C to +85°C
−40°C to +125°C
−40°C to +125°C
−40°C to +85°C
−40°C to +85°C
−40°C to +125°C
−40°C to +125°C
−40°C to +85°C
−40°C to +85°C
−40°C to +125°C
−40°C to +125°C
−40°C to +85°C
−40°C to +85°C
−40°C to +125°C
−40°C to +125°C
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Mini Small Outline Package [MSOP]
8-Lead Mini Small Outline Package [MSOP]
8-Lead Mini Small Outline Package [MSOP]
8-Lead Mini Small Outline Package [MSOP]
10-Lead Lead Frame Chip Scale Package [LFCSP]
10-Lead Lead Frame Chip Scale Package [LFCSP]
10-Lead Lead Frame Chip Scale Package [LFCSP]
10-Lead Lead Frame Chip Scale Package [LFCSP]
10-Lead Mini Small Outline Package [MSOP]
10-Lead Mini Small Outline Package [MSOP]
10-Lead Mini Small Outline Package [MSOP]
10-Lead Mini Small Outline Package [MSOP]
14-Lead Standard Small Outline Package [SOIC_N]
14-Lead Standard Small Outline Package [SOIC_N]
14-Lead Standard Small Outline Package [SOIC_N]
14-Lead Standard Small Outline Package [SOIC_N]
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Mini Small Outline Package [MSOP]
8-Lead Mini Small Outline Package [MSOP]
8-Lead Mini Small Outline Package [MSOP]
8-Lead Mini Small Outline Package [MSOP]
R-8
R-8
R-8
R-8
ADM3061EBRZ-R7
ADM3061EARMZ
ADM3061EARMZ-R7
ADM3061EBRMZ
ADM3061EBRMZ-R7
ADM3062EACPZ
ADM3062EACPZ-R7
ADM3062EBCPZ
ADM3062EBCPZ-R7
ADM3062EARMZ
ADM3062EARMZ-R7
ADM3062EBRMZ
ADM3062EBRMZ-R7
ADM3063EARZ
ADM3063EARZ-R7
ADM3063EBRZ
ADM3063EBRZ-R7
ADM3065EARZ
ADM3065EARZ-R7
ADM3065EBRZ
RM-8
RM-8
RM-8
RM-8
CP-10-9
CP-10-9
CP-10-9
CP-10-9
RM-10
RM-10
RM-10
RM-10
R-14
MBY
MBY
MC0
MC0
MCC
MCC
MCD
MCD
MC7
MC7
MC8
MC8
R-14
R-14
R-14
R-8
R-8
R-8
R-8
RM-8
RM-8
RM-8
RM-8
ADM3065EBRZ-R7
ADM3065EARMZ
ADM3065EARMZ-R7
ADM3065EBRMZ
ADM3065EBRMZ-R7
MC1
MC1
MC2
MC2
Rev. F | Page 27 of 28
ADM3061E/ADM3062E/ADM3063E/ADM3065E/ADM3066E/ADM3067E/ADM3068E Data Sheet
Model1
Temperature Range Package Description
Package Option Marking Code
ADM3066EACPZ
ADM3066EACPZ-R7
ADM3066EBCPZ
ADM3066EBCPZ-R7
ADM3066EARMZ
ADM3066EARMZ-R7
ADM3066EBRMZ
ADM3066EBRMZ-R7
ADM3067EARZ
ADM3067EARZ-R7
ADM3067EBRZ
ADM3067EBRZ-R7
ADM3068EARZ
ADM3068EARZ-R7
ADM3068EBRZ
ADM3068EBRZ-R7
EVAL-ADM3061EEBZ
EVAL-ADM3061EEB1Z
EVAL-ADM3062EEBZ
EVAL-ADM3062EEB1Z
EVAL-ADM3063EEBZ
EVAL-ADM3065EEBZ
EVAL-ADM3065EEB1Z
EVAL-ADM3066EEBZ
EVAL-ADM3066EEB1Z
EVAL-ADM3067EEBZ
EVAL-ADM3068EEBZ
−40°C to +85°C
−40°C to +85°C
−40°C to +125°C
−40°C to +125°C
−40°C to +85°C
−40°C to +85°C
−40°C to +125°C
−40°C to +125°C
−40°C to +85°C
−40°C to +85°C
−40°C to +125°C
−40°C to +125°C
−40°C to +85°C
−40°C to +85°C
−40°C to +125°C
−40°C to +125°C
10-Lead Lead Frame Chip Scale Package [LFCSP]
CP-10-9
CP-10-9
CP-10-9
CP-10-9
RM-10
RM-10
RM-10
RM-10
R-14
MC9
MC9
MCA
MCA
MC4
MC4
MC5
MC5
10-Lead Lead Frame Chip Scale Package [LFCSP]
10-Lead Lead Frame Chip Scale Package [LFCSP]
10-Lead Lead Frame Chip Scale Package [LFCSP]
10-Lead Mini Small Outline Package [MSOP]
10-Lead Mini Small Outline Package [MSOP]
10-Lead Mini Small Outline Package [MSOP]
10-Lead Mini Small Outline Package [MSOP]
14-Lead Standard Small Outline Package [SOIC_N]
14-Lead Standard Small Outline Package [SOIC_N]
14-Lead Standard Small Outline Package [SOIC_N]
14-Lead Standard Small Outline Package [SOIC_N]
14-Lead Standard Small Outline Package [SOIC_N]
14-Lead Standard Small Outline Package [SOIC_N]
14-Lead Standard Small Outline Package [SOIC_N]
14-Lead Standard Small Outline Package [SOIC_N]
8-Lead SOIC_N Evaluation Board
8-Lead MSOP Evaluation Board
10-Lead MSOP Evaluation Board
10-Lead LFCSP Evaluation Board
14-Lead SOIC_N Evaluation Board
8-Lead SOIC_N Evaluation Board
8-Lead MSOP Evaluation Board
10-Lead MSOP Evaluation Board
10-Lead LFCSP Evaluation Board
R-14
R-14
R-14
R-14
R-14
R-14
R-14
14-Lead SOIC_N Evaluation Board
14-Lead SOIC_N Evaluation Board
1 Z = RoHS Compliant Part.
©2017–2019 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D14666-0-6/19(F)
Rev. F | Page 28 of 28
相关型号：
ADM3062EACPZ-R7
3.0 V to 5.5 V with VIO, ±12 kV IEC ESD Protected, Half Duplex 500 kbps RS-485 Transceiver
ADI
ADM3062EARMZ
3.0 V to 5.5 V with VIO, ±12 kV IEC ESD Protected, Half Duplex 500 kbps RS-485 Transceiver
ADI
ADM3062EARMZ-R7
3.0 V to 5.5 V with VIO, ±12 kV IEC ESD Protected, Half Duplex 500 kbps RS-485 Transceiver
ADI
ADM3062EBCPZ-R7
3.0 V to 5.5 V with VIO, ±12 kV IEC ESD Protected, Half Duplex 500 kbps RS-485 Transceiver
ADI
ADM3062EBRMZ
3.0 V to 5.5 V with VIO, ±12 kV IEC ESD Protected, Half Duplex 500 kbps RS-485 Transceiver
ADI
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