ADM3251E_VE [ADI]
Isolated, Single-Channel RS-232 Line Driver/Receiver; 隔离，单通道RS - 232线路驱动器/接收器
| 型号： | ADM3251E_VE |
| 厂家： | 
ADI |
| 描述： | Isolated, Single-Channel RS-232 Line Driver/Receiver |
| 文件： | 总16页 (文件大小：261K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Isolated, Single-Channel
RS-232 Line Driver/Receiver
ADM3251E
FEATURES
FUNCTIONAL BLOCK DIAGRAM
C1
0.1µF
16V
C3
0.1µF
10V
C2
0.1µF
16V
C4
0.1µF
16V
2.5 kV fully isolated (power and data) RS-232 transceiver
isoPower integrated, isolated dc-to-dc converter
460 kbps data rate
0.1µF
V
1 Tx and 1 Rx
V+
ISO
C1+ C1–
C2+
V–
C2–
VOLTAGE
DOUBLER
VOLTAGE
INVERTER
ADM3251E
Meets EIA/TIA-232E specifications
ESD protection on RIN and TOUT pins
8 kV: contact discharge
V
CC
RECT
REG
OSC
15 kV: air gap discharge
0.1 μF charge pump capacitors
High common-mode transient immunity: >25 kV/μs
Safety and regulatory approvals
UL recognition
0.1µF
DECODE
ENCODE
ENCODE
DECODE
R
T
*
IN
R
T
R
OUT
OUT
T
IN
2500 V rms for 1 minute per UL 1577
VDE Certificate of Conformity
GND
GND
ISO
*INTERNAL 5kΩ PULL-DOWN RESISTOR ON THE RS-232 INPUT.
DIN EN 60747-5-2 (VDE 0884 Teil 2): 2003-01
CSA Component Acceptance Notice #5A
Operating temperature range: −40°C to +85°C
Wide body, 20-lead SOIC package
Figure 1.
APPLICATIONS
High noise data communications
Industrial communications
General-purpose RS-232 data links
Industrial/telecommunications diagnostic ports
Medical equipment
GENERAL DESCRIPTION
transformer. Special care must be taken during printed circuit
board (PCB) layout to meet emissions standards. Refer to
Application Note AN-0971, Control of Radiated Emissions with
isoPower Devices, for details on board layout considerations.
The ADM3251E is a high speed, 2.5 kV fully isolated, single-
channel RS-232/V.28 transceiver device that operates from a
single 5 V power supply. Due to the high ESD protection on the
RIN and TOUT pins, the device is ideally suited for operation in
electrically harsh environments or where RS-232 cables are
frequently being plugged and unplugged.
The ADM3251E conforms to the EIA/TIA-232E and ITU-T V. 28
specifications and operates at data rates up to 460 kbps.
The ADM3251E incorporates dual-channel digital isolators with
isoPower™ integrated, isolated power. There is no requirement
to use a separate isolated dc-to-dc converter. Chip-scale trans-
former iCoupler® technology from Analog Devices, Inc., is used
both for the isolation of the logic signals as well as for the inte-
grated dc-to-dc converter. The result is a total isolation solution.
Four external 0.1 μF charge pump capacitors are used for the
voltage doubler/inverter, permitting operation from a single
5 V supply.
The ADM3251E is available in a 20-lead, wide body SOIC package
and is specified over the −40°C to +85°C temperature range.
The ADM3251E contains isoPower technology that uses high
frequency switching elements to transfer power through the
Rev. E
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2008–2010 Analog Devices, Inc. All rights reserved.
ADM3251E
TABLE OF CONTENTS
Features .............................................................................................. 1
Theory of Operation ...................................................................... 11
Isolation of Power and Data...................................................... 11
Charge Pump Voltage Converter ............................................. 12
5.0 V Logic to EIA/TIA-232E Transmitter.............................. 12
EIA/TIA-232E to 5 V Logic Receiver ...................................... 12
High Baud Rate........................................................................... 12
Thermal Analysis ....................................................................... 12
Insulation Lifetime..................................................................... 12
Applications Information.............................................................. 13
PCB Layout ................................................................................. 13
Example PCB for Reduced EMI............................................... 13
Isolated Power Supply Circuit .................................................. 14
Outline Dimensions....................................................................... 15
Ordering Guide .......................................................................... 15
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Package Characteristics ............................................................... 5
Regulatory Information............................................................... 5
Insulation and Safety-Related Specifications............................ 5
DIN EN 60747-5-2 (VDE 0884 Teil 2): 2003-01 Insulation
Characteristics .............................................................................. 6
Absolute Maximum Ratings............................................................ 7
ESD Caution.................................................................................. 7
Pin Configuration and Function Descriptions............................. 8
Typical Performance Characteristics ............................................. 9
REVISION HISTORY
5/10—Rev. D to Rev. E
11/09—Rev. A to Rev. B
Changes to Features Section............................................................ 1
Changes to Table 4............................................................................ 5
Changes to Figure 1...........................................................................1
Changed to Primary Side Supply Input Current, ICC(DISABLE)
Maximum Limit to 2.5 mA ..............................................................4
Changes to Table 4.............................................................................5
Changes to Figure 13...................................................................... 11
3/10—Rev. C to Rev. D
Changes to Features and General Description Sections.............. 1
Changes to Table 4 and Table 5....................................................... 5
Changed DIN V VDE V 0884-10 (VDE V 0884-10):2006-12
Insulation Characteristics (Pending) Heading to DIN EN
60747-5-2 (VDE 0884 Teil 2): 2003-01 Insulation
Characteristics................................................................................... 6
Changes to Pollution Degree and Input–to-Output Test
Voltage Parameters, Table 6............................................................. 6
Added Applications Information Section and Example PCB
for Reduced EMI Section .............................................................. 13
Added Table 9 and Table 10; Renumbered Sequentially ........... 13
Changes to PCB Layout Section................................................... 13
Added Isolated Power Supply Circuit Section............................ 14
Added Figure 22; Renumbered Sequentially .............................. 14
9/08—Rev. 0 to Rev. A
Changes to Timing Parameters in Table 1 .....................................3
Changes to Timing Parameters in Table 2 .....................................4
Changes to Ordering Guide.......................................................... 14
7/08—Revision 0: Initial Version
1/10—Rev. B to Rev. C
Changes to Table 4............................................................................ 5
Rev. E | Page 2 of 16
ADM3251E
SPECIFICATIONS
All voltages are relative to their respective ground; all minimum/maximum specifications apply over the entire recommended operating
range; TA = 25°C and VCC = 5.0 V (dc-to-dc converter enabled), unless otherwise noted.
Table 1.
Parameter
Min
Typ
Max
5.5
Unit
Test Conditions/Comments
DC CHARACTERISTICS
VCC Operating Voltage Range
DC-to-DC Converter Enable Threshold, VCC(ENABLE)
4.5
4.5
V
V
V
1
1
3.7
DC-to-DC Converter Disable Threshold, VCC(DISABLE)
DC-to-DC Converter Enabled
Input Supply Current, ICC(ENABLE)
110
145
mA
mA
V
VCC = 5.5 V, no load
VCC = 5.5 V, RL = 3 kΩ
IISO = 0 μA
VISO Output2
5.0
LOGIC
Transmitter Input, TIN
Logic Input Current, ITIN
−10
+0.01
+10
μA
V
Logic Low Input Threshold, VTINL
Logic High Input Threshold, VTINH
Receiver Output, ROUT
0.3 VCC
0.7 VCC
V
Logic High Output, VROUTH
VCC − 0.1
VCC − 0.5
VCC
V
V
V
V
IROUTH = −20 μA
IROUTH = −4 mA
IROUTH = 20 μA
IROUTH = 4 mA
VCC − 0.3
0.0
Logic Low Output, VROUTL
0.1
0.4
0.3
RS-232
Receiver, RIN
EIA-232 Input Voltage Range3
EIA-232 Input Threshold Low
EIA-232 Input Threshold High
EIA-232 Input Hysteresis
EIA-232 Input Resistance
Transmitter, TOUT
−30
0.6
+30
2.4
7
V
2.0
2.1
0.1
5
V
V
V
3
kΩ
Output Voltage Swing (RS-232)
Transmitter Output Resistance
Output Short-Circuit Current (RS-232)
TIMING CHARACTERISTICS
Maximum Data Rate
5
5.7
12
V
RL = 3 kΩ to GND
VISO = 0 V
300
Ω
mA
460
kbps
RL = 3 kΩ to 7 kΩ, CL = 50 pF to 1000 pF
RL = 3 kΩ, CL = 1000 pF
Receiver Propagation Delay
tPHL
190
135
650
80
ns
tPLH
ns
Transmitter Propagation Delay
Transmitter Skew
ns
ns
Receiver Skew
70
ns
Transition Region Slew Rate3
5.5
10
30
V/μs
+3 V to −3 V or −3 V to +3 V, VCC = +3.3 V,
RL = 3 kΩ, CL = 1000 pF, TA = 25°C
AC SPECIFICATIONS
Output Rise/Fall Time, tR/tF (10% to 90%)
2.3
ns
CL = 15 pF, CMOS signal levels
Common-Mode Transient Immunity at Logic High Output4
Common-Mode Transient Immunity at Logic Low Output4
ESD PROTECTION (RIN And TOUT PINS)
25
25
kV/μs
kV/μs
VCM = 1 kV, transient magnitude = 800 V
VCM = 1 kV, transient magnitude = 800 V
15
8
kV
kV
Human body model air discharge
Human body model contact discharge
1 Enable/disable threshold is the VCC voltage at which the internal dc-to-dc converter is enabled/disabled.
2 To maintain data sheet specifications, do not draw current from VISO
3 Guaranteed by design.
.
4 VCM is the maximum common-mode voltage slew rate that can be sustained while maintaining specification-compliant operation. VCM is the common-mode potential
difference between the logic and bus sides. The transient magnitude is the range over which the common mode is slewed. The common-mode voltage slew rates
apply to both rising and falling common-mode voltage edges.
Rev. E | Page 3 of 16
ADM3251E
All voltages are relative to their respective ground; all minimum/maximum specifications apply over the entire recommended operating
range; TA = 25°C, VCC = 3.3 V (dc-to-dc converter disabled), and the secondary side is powered externally by VISO = 3.3 V, unless
otherwise noted.
Table 2.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
DC CHARACTERISTICS
VCC Operating Voltage Range
DC-to-DC Converter Disable Threshold, VCC(DISABLE)
DC-to-DC Converter Disabled
3.0
3.7
3.7
V
V
1
2
VISO
3.0
5.5
2.5
12
V
Primary Side Supply Input Current, ICC(DISABLE)
mA
mA
mA
No load
Secondary Side Supply Input Current, IISO(DISABLE)
Secondary Side Supply Input Current, IISO(DISABLE)
VISO = 5.5 V, RL = 3 kΩ
RL = 3 kΩ
6.2
LOGIC
Transmitter Input, TIN
Logic Input Current, ITIN
−10
+0.01
+10
μA
V
Logic Low Input Threshold, VTINL
Logic High Input Threshold, VTINH
Receiver Output, ROUT
0.3 VCC
0.7 VCC
V
Logic High Output, VROUTH
VCC − 0.1
VCC − 0.5
VCC
V
V
V
V
IROUTH = −20 μA
IROUTH = −4 mA
IROUTH = 20 μA
IROUTH = 4 mA
VCC − 0.3
0.0
Logic Low Output, VROUTL
0.1
0.4
0.3
RS-232
Receiver, RIN
EIA-232 Input Voltage Range3
EIA-232 Input Threshold Low
EIA-232 Input Threshold High
EIA-232 Input Hysteresis
EIA-232 Input Resistance
Transmitter, TOUT
−30
0.6
+30
2.4
7
V
1.3
1.6
0.3
5
V
V
V
3
kΩ
Output Voltage Swing (RS-232)
Transmitter Output Resistance
Output Short-Circuit Current (RS-232)
TIMING CHARACTERISTICS
Maximum Data Rate
5
5.7
11
V
RL = 3 kΩ to GND
VISO = 0 V
300
Ω
mA
460
kbps
RL = 3 kΩ to 7 kΩ, CL = 50 pF to 1000 pF
RL = 3 kΩ, CL = 1000 pF
Receiver Propagation Delay
tPHL
190
135
650
80
ns
tPLH
ns
Transmitter Propagation Delay
Transmitter Skew
ns
ns
Receiver Skew
55
ns
Transition Region Slew Rate3
5.5
10
30
V/μs
+3 V to −3 V or −3 V to +3 V, VCC = 3.3 V,
RL = 3 kΩ, CL = 1000 pF, TA = 25°C
AC SPECIFICATIONS
Output Rise/Fall Time, tR/tF (10% to 90%)
Common-Mode Transient Immunity at Logic High Output4
Common-Mode Transient Immunity at Logic Low Output4
ESD PROTECTION (RIN AND TOUT PINS)
2.3
ns
CL = 15 pF, CMOS signal levels
25
25
kV/μs
kV/μs
kV
VCM = 1 kV, transient magnitude = 800 V
VCM = 1 kV, transient magnitude = 800 V
Human body model air discharge
Human body model contact discharge
15
8
kV
1 Enable/disable threshold is the VCC voltage at which the internal dc-to-dc converter is enabled/disabled.
2 To maintain data sheet specifications, do not draw current from VISO
3 Guaranteed by design.
.
4 VCM is the maximum common-mode voltage slew rate that can be sustained while maintaining specification-compliant operation. VCM is the common-mode potential
difference between the logic and bus sides. The transient magnitude is the range over which the common mode is slewed. The common-mode voltage slew rates
apply to both rising and falling common-mode voltage edges.
Rev. E | Page 4 of 16
ADM3251E
PACKAGE CHARACTERISTICS
Table 3.
Parameter
Symbol
RI-O
CI-O
Min
Typ
1012
2.2
Max
Unit
Ω
pF
Test Conditions
f = 1 MHz
Resistance (Input-to-Output)
Capacitance (Input-to-Output)
Input Capacitance
CI
4.0
pF
IC Junction-to-Air Thermal Resistance
θJA
47.05
°C/W
REGULATORY INFORMATION
Table 4.
UL1
VDE2
CSA
Recognized under 1577 Component Certified according to DIN EN 60747-5-2 (VDE
Approved under CSA Component Acceptance
Notice #5A
Recognition Program
0884 Teil 2):2003-01
File E214100
File 2471900-4880-0001/123328
Basic Insulation per CSA 60950-1-07 and IEC
60950-1, 400 V rms (566 V peak) maximum
working voltage
File 2268268
1 In accordance with UL 1577, each ADM3251E is proof-tested by applying an insulation test voltage ≥3000 V rms for 1 sec (current leakage detection limit = 5 μA).
2 Each ADM3251E is proof tested by applying an insulation test voltage ≥4000 V peak for 1 sec (partial discharge detection limit = 5 pC).
INSULATION AND SAFETY-RELATED SPECIFICATIONS
Table 5.
Parameter
Symbol Value Unit
Conditions
Rated Dielectric Insulation Voltage
Minimum External Air Gap (Clearance)
2500
7.7
V rms
mm
1 minute duration
Measured from input terminals to output terminals,
shortest distance through air
Measured from input terminals to output terminals,
shortest distance path along body
L(I01)
L(I02)
Minimum External Tracking (Creepage)
4.16
mm
Minimum Internal Gap (Internal Clearance)
Tracking Resistance (Comparative Tracking Index)
Isolation Group
0.017
>175
IIIa
mm
V
Distance through insulation
DIN IEC 112/VDE 0303 Part 1
CTI
Maximum Working Voltage Compatible with
50-Year Service Life
VIORM
425
V peak
Continuous peak voltage across the isolation barrier
Rev. E | Page 5 of 16
ADM3251E
DIN EN 60747-5-2 (VDE 0884 TEIL 2): 2003-01 INSULATION CHARACTERISTICS
This isolator is suitable for reinforced isolation only within the safety limit data. Maintenance of the safety data is ensured by
protective circuits.
Table 6.
Description
Conditions
Symbol
Characteristic Unit
Installation Classification per DIN VDE 0110
For Rated Mains Voltage ≤ 150 V rms
For Rated Mains Voltage ≤ 300 V rms
Climatic Classification
I to IV
I to III
40/105/21
2
Pollution Degree
Maximum Working Insulation Voltage
Input-to-Output Test Voltage
Method b1
VIORM
424
V peak
VIORM × 1.875 = VPR, 100% production test, tm = 1 sec, VPR
partial discharge < 5 pC
795
V peak
V peak
Highest Allowable Overvoltage
Safety-Limiting Values
Case Temperature
Supply Current
Insulation Resistance at TS
Transient overvoltage, tTR = 10 sec
Maximum value allowed in the event of a failure
VTR
4000
TS
IS1
RS
150
531
>109
°C
mA
Ω
VIO = 500 V
Rev. E | Page 6 of 16
ADM3251E
ABSOLUTE MAXIMUM RATINGS
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Table 7.
Parameter
Rating
VCC, VISO
V+
V−
−0.3 V to +6 V
(VCC − 0.3 V) to +13 V
–13 V to +0.3 V
Input Voltages
TIN
RIN
−0.3 V to (VCC + 0.3 V)
30 V
ESD CAUTION
Output Voltages
TOUT
15 V
ROUT
−0.3 V to (VCC + 0.3 V)
Short-Circuit Duration
TOUT
Power Dissipation
θJA, Thermal Impedance
Operating Temperature Range
Industrial
Continuous
47.05°C/W
−40°C to +85°C
−65°C to +150°C
Storage Temperature Range
Pb-Free Temperature (Soldering, 30 sec) 260°C
Rev. E | Page 7 of 16
ADM3251E
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
NC
1
2
3
4
5
6
7
8
9
20 V
ISO
V
19 V+
CC
CC
V
18 C1+
17 C1–
GND
GND
GND
GND
ADM3251E
16
15
T
OUT
TOP VIEW
(Not to Scale)
R
IN
14 C2+
13 C2–
12 V–
R
OUT
T
IN
GND 10
11 GND
ISO
NC = NO CONNECT
Figure 2. Pin Configuration
Table 8. Pin Function Descriptions
Pin No.
Mnemonic Description
1
2, 3
NC
VCC
No Connect. This pin should always remain unconnected.
Power Supply Input. A 0.1 μF decoupling capacitor is required between VCC and ground. When a voltage
between 4.5 V and 5.5 V is applied to the VCC pin, the integrated dc-to-dc converter is enabled. If this voltage is
lowered to between 3.0 V and 3.7 V, the integrated dc-to-dc converter is disabled.
4, 5, 6, 7, 10 GND
Ground.
8
9
ROUT
TIN
GNDISO
V−
C2−, C2+
Receiver Output. This pin outputs CMOS logic levels.
Transmitter (Driver) Input. This pin accepts TTL/CMOS levels.
Ground Reference for Isolator Primary Side.
Internally Generated Negative Supply.
Positive and Negative Connections for Charge Pump Capacitors. External Capacitor C2 is connected between
these pins; a 0.1 μF capacitor is recommended, but larger capacitors up to 10 μF can be used.
11
12
13, 14
15
RIN
Receiver Input. This input accepts RS-232 signal levels.
16
TOUT
Transmitter (Driver) Output. This outputs RS-232 signal levels.
17, 18
C1−, C1+
Positive and Negative Connections for Charge Pump Capacitors. External Capacitor C1 is connected between
these pins; a 0.1 μF capacitor is recommended, but larger capacitors up to 10 μF can be used.
19
20
V+
VISO
Internally Generated Positive Supply.
Isolated Supply Voltage for Isolator Secondary Side. A 0.1 μF decoupling capacitor is required between VISO and
ground. When the integrated dc-to-dc converter is enabled, the VISO pin should not be used to power external
circuitry. If the integrated dc-to-dc converter is disabled, power the secondary side by applying a voltage in the
range of 3.0 V to 5.5 V to this pin.
Rev. E | Page 8 of 16
ADM3251E
TYPICAL PERFORMANCE CHARACTERISTICS
12
12
10
8
Tx HIGH (V = 5V)
CC
Tx OUTPUT HIGH (V = 5V)
CC
8
4
0
Tx HIGH (V
ISO
= 3.3V)
6
Tx OUTPUT HIGH (V
ISO
= 3.3V)
4
2
0
–2
–4
–6
–4
–8
Tx LOW (V
ISO
= 3.3V)
Tx OUTPUT LOW (V
ISO
= 3.3V)
–8
–10
–12
Tx LOW (V = 5V)
CC
Tx OUTPUT LOW (V = 5V)
CC
–12
0
200
400
600
800
1000
0
1
2
3
4
LOAD CAPACITANCE (pF)
LOAD CURRENT (mA)
Figure 3. Transmitter Output Voltage High/Low vs. Load
Capacitance at 460 kbps
Figure 6. Transmitter Output Voltage High/Low vs. Load Current
12
10
15
Tx OUTPUT HIGH
V+ (V = 5V)
CC
10
5
8
6
V+ (V
= 3.3V)
= 3.3V)
ISO
ISO
4
2
0
0
–2
–4
–6
V– (V
–5
–10
–15
V– (V = 5V)
CC
Tx OUTPUT LOW
–8
–10
4.5
4.7
4.9
5.1
5.3
5.5
0
1
2
3
4
V
(V)
LOAD CURRENT (mA)
CC
Figure 7. Charge Pump V+, V− vs. Load Current
Figure 4. Transmitter Output Voltage High/Low vs. VCC, RL = 3 kΩ
400
12
V–
10
Tx OUTPUT HIGH
350
300
250
200
8
6
4
2
V+
0
–2
–4
150
100
50
Tx OUTPUT LOW
–6
–8
–10
–12
0
4.50
4.75
5.00
(V)
5.25
5.50
3.0
3.5
4.0
4.5
5.0
5.5
V
V
(V)
CC
ISO
Figure 8. Charge Pump Impedance vs. VCC
Figure 5. Transmitter Output Voltage High/Low vs. VISO, RL = 3 kΩ
Rev. E | Page 9 of 16
ADM3251E
400
350
300
250
200
V–
V+
1
150
100
50
2
5
CC
LOAD = 3kΩ AND 1nF
0
3.00 3.25 3.50 3.75 4.00 4.25 4.50 4.75 5.00 5.25 5.50
V
(V)
ISO
TIME (500ns/DIV)
Figure 9. Charge Pump Impedance vs. VISO
Figure 11. 460 kbps Data Transmission
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
200
180
160
140
120
100
80
V
= 5.5V
CC
HIGH THRESHOLD
LOW THRESHOLD
V
= 5V
CC
V
= 4.5V
CC
60
40
20
0
4.50
4.75
5.00
(V)
5.25
5.50
0
46
92
138 184 230 276 322 368 414 460
DATA RATE (kbps)
V
CC
Figure 10. Primary Supply Current vs. Data Rate
Figure 12. TIN Voltage Threshold vs. VCC
Rev. E | Page 10 of 16
ADM3251E
THEORY OF OPERATION
The ADM3251E is a high speed, 2.5 kV fully isolated, single-
channel RS-232 transceiver device that operates from a single
power supply.
The TIN pin accepts TTL/CMOS input levels. The driver input
signal that is applied to the TIN pin is referenced to logic ground
(GND). It is coupled across the isolation barrier, inverted, and
then appears at the transceiver section, referenced to isolated
ground (GNDISO). Similarly, the receiver input (RIN) accepts
RS-232 signal levels that are referenced to isolated ground.
The RIN input is inverted and coupled across the isolation
barrier to appear at the ROUT pin, referenced to logic ground.
The internal circuitry consists of the following main sections:
•
•
•
•
Isolation of power and data
A charge pump voltage converter
A 5.0 V logic to EIA/TIA-232E transmitter
A EIA/TIA-232E to 5.0 V logic receiver
The digital signals are transmitted across the isolation barrier
using iCoupler technology. Chip-scale transformer windings
couple the digital signals magnetically from one side of the
barrier to the other. Digital inputs are encoded into waveforms
that are capable of exciting the primary transformer of the winding.
At the secondary winding, the induced waveforms are decoded
into the binary value that was originally transmitted.
C1
0.1µF
16V
C3
0.1µF
10V
C2
0.1µF
16V
C4
0.1µF
16V
0.1µF
V
V+
ISO
C1+ C1–
C2+
V–
C2–
VOLTAGE
DOUBLER
VOLTAGE
INVERTER
ADM3251E
V
CC
RECT
REG
There is hysteresis in the VCC input voltage detect circuit.
Once the dc-to-dc converter is active, the input voltage
must be decreased below the turn-on threshold to disable
the converter. This feature ensures that the converter does
not go into oscillation due to noisy input power.
OSC
0.1µF
DECODE
ENCODE
ENCODE
DECODE
R
T
*
IN
R
T
R
OUT
OUT
T
IN
V
ISO
+
C3
0.1µF
10V
GND
GND
ISO
0.1µF
4.5V TO 5.5V
0.1µF
+
+
V+
V
*INTERNAL 5kΩ PULL-DOWN RESISTOR ON THE RS-232 INPUT.
CC
ADM3251E
C1+
C1–
C1
0.1µF
16V
Figure 13. Functional Block Diagram
ISOLATION OF POWER AND DATA
EIA/TIA-232E OUTPUT
EIA/TIA-232E INPUT
T
OUT
R
T
CMOS OUTPUT
CMOS INPUT
OUT
The ADM3251E incorporates a dc-to-dc converter section,
which works on principles that are common to most modern
power supply designs. VCC power is supplied to an oscillating
circuit that switches current into a chip-scale air core transformer.
Power is transferred to the secondary side, where it is rectified
to a high dc voltage. The power is then linearly regulated to
about 5.0 V and supplied to the secondary side data section
and to the VISO pin. The VISO pin should not be used to power
external circuitry.
R
IN
IN
C2+
C2
+
0.1µF
16V
C2–
V–
C4
+ 0.1µF
16V
ISOLATION
BARRIER
GND
GND
ISO
Figure 14. Typical Operating Circuit with the DC-to-DC Converter Enabled
(VCC = 4.5 V to 5.5 V)
Because the oscillator runs at a constant high frequency
independent of the load, excess power is internally dissipated
in the output voltage regulation process. Limited space for
transformer coils and components also adds to internal power
dissipation. This results in low power conversion efficiency.
3.0V TO 5.5V
ISOLATED SUPPLY
V
ISO
+
C3
0.1µF
10V
3.0V TO 3.7V
0.1µF
0.1µF
+
+
V+
V
CC
ADM3251E
C1+
C1–
C1
0.1µF
16V
The ADM3251E can be operated with the dc-to-dc converter
enabled or disabled. The internal dc-to-dc converter state of the
ADM3251E is controlled by the input VCC voltage. In normal
operating mode, VCC is set between 4.5 V and 5.5 V and the
internal dc-to-dc converter is enabled. To disable the dc-to-dc
converter, lower VCC to a value between 3.0 V and 3.7 V. In this
mode, the user must externally supply isolated power to the
EIA/TIA-232E OUTPUT
EIA/TIA-232E INPUT
T
OUT
R
T
CMOS OUTPUT
CMOS INPUT
OUT
R
IN
IN
C2+
C2
+
0.1µF
16V
C2–
V–
C4
+ 0.1µF
16V
ISOLATION
BARRIER
VISO pin. An isolated secondary side voltage of between 3.0 V
and 5.5 V and a secondary side input current, IISO, of 12 mA
(maximum) is required on the VISO pin. The signal channels of
the ADM3251E then continue to operate normally.
GND
GND
ISO
Figure 15. Typical Operating Circuit with the DC-to-DC Converter Disabled
(VCC = 3.0 V to 3.7 V)
Rev. E | Page 11 of 16
ADM3251E
CHARGE PUMP VOLTAGE CONVERTER
THERMAL ANALYSIS
The charge pump voltage converter consists of a 200 kHz
oscillator and a switching matrix. The converter generates a
10.0 V supply from the input 5.0 V level. This is done in two
stages by using a switched capacitor technique as illustrated in
Figure 16 and Figure 17. First, the 5.0 V input supply is doubled
to 10.0 V by using C1 as the charge storage element. The +10.0 V
level is then inverted to generate −10.0 V using C2 as the storage
element. C3 is shown connected between V+ and VISO, but is
Each ADM3251E device consists of three internal die, attached
to a split-paddle lead frame. For the purposes of thermal analysis,
it is treated as a thermal unit with the highest junction temper-
ature reflected in the θJA value from Table 7. The value of θJA is
based on measurements taken with the part mounted on a JEDEC
standard 4-layer PCB with fine-width traces in still air. Follow-
ing the recommendations in the PCB Layout section decreases
the thermal resistance to the PCB, allowing increased thermal
margin at high ambient temperatures.
equally effective if connected between V+ and GNDISO
.
Capacitor C3 and Capacitor C4 are used to reduce the output
ripple. Their values are not critical and can be increased, if
desired. Larger capacitors (up to 10 ꢀF) can be used in place
of C1, C2, C3, and C4.
INSULATION LIFETIME
All insulation structures eventually break down when subjected
to voltage stress over a sufficiently long period. The rate of insula-
tion degradation is dependent on the characteristics of the
voltage waveform applied across the insulation. In addition
to the testing performed by the regulatory agencies, Analog
Devices carries out an extensive set of evaluations to determine
the lifetime of the insulation structure within the ADM3251E.
5.0 V LOGIC TO EIA/TIA-232E TRANSMITTER
The transmitter driver converts the 5.0 V logic input levels
into RS-232 output levels. When driving an RS-232 load with
VCC = 5.0 V, the output voltage swing is typically 10 V.
The insulation lifetime of the ADM3251E depends on the
voltage waveform type imposed across the isolation barrier.
The iCoupler insulation structure degrades at different rates
depending on whether the waveform is bipolar ac, unipolar ac,
or dc. Figure 18, Figure 19, and Figure 20 illustrate these
different isolation voltage waveforms.
S1
S2
S3
S4
V
V+ = 2V
ISO
ISO
+
+
C1
C3
V
GND
ISO
INTERNAL
OSCILLATOR
Bipolar ac voltage is the most stringent environment. In the
case of unipolar ac or dc voltage, the stress on the insulation is
significantly lower.
Figure 16. Charge Pump Voltage Doubler
RATED PEAK VOLTAGE
S1
S2
S3
S4
V+
GND
ISO
FROM
VOLTAGE
DOUBLER
+
+
0V
C2
C4
V– = –(V+)
GND
ISO
Figure 18. Bipolar AC Waveform
INTERNAL
OSCILLATOR
RATED PEAK VOLTAGE
Figure 17. Charge Pump Voltage Inverter
EIA/TIA-232E TO 5 V LOGIC RECEIVER
0V
The receiver is an inverting level-shifter that accepts the RS-232
input level and translates it into a 5.0 V logic output level. The
input has an internal 5 kΩ pull-down resistor to ground and is
also protected against overvoltages of up to 30 V. An uncon-
nected input is pulled to 0 V by the internal 5 kΩ pull-down
resistor. This, therefore, results in a Logic 1 output level for an
unconnected input or for an input connected to GND. The
receiver has a Schmitt-trigger input with a hysteresis level of
0.1 V. This ensures error-free reception for both a noisy input
and for an input with slow transition times.
Figure 19. Unipolar AC Waveform
RATED PEAK VOLTAGE
0V
Figure 20. DC Waveform Outline Dimensions
HIGH BAUD RATE
The ADM3251E offers high slew rates, permitting data trans-
mission at rates well in excess of the EIA/TIA-232E specifications.
The RS-232 voltage levels are maintained at data rates up to
460 kbps.
Rev. E | Page 12 of 16
ADM3251E
APPLICATIONS INFORMATION
PCB LAYOUT
EXAMPLE PCB FOR REDUCED EMI
The choice of how aggressively EMI must be addressed for a design
to pass emissions levels depends on the requirements of the design
as well as cost and performance trade-offs.
The ADM3251E requires no external circuitry for its logic
interfaces. Power supply bypassing is required at the input
and output supply pins (see Figure 21). Bypass capacitors are
conveniently connected between Pin 3 and Pin 4 for VCC and
between Pin 19 and Pin 20 for VISO. The capacitor value should
be between 0.01 ꢀF and 0.1 ꢀF. The total lead length between
both ends of the capacitor and the input power supply pin
should not exceed 20 mm.
The starting point for this example is a 2-layer PCB. EMI reduc-
tions are relative to the emissions and noise from this board.
To conform to FCC Class B levels, the emissions at these two
frequencies must be less than 46 dBꢀV/m, normalized to 3 m
antenna distance. As expected, EMI testing confirmed that the
largest emissions peaks occur at the tank frequency and rectifier
frequency.
Because it is not possible to apply a heat sink to an isolation
device, the device primarily depends on heat dissipating into
the PCB through the ground pins. If the device is used at high
ambient temperatures, care should be taken to provide a
thermal path from the ground pins to the PCB ground plane.
The board layout in Figure 21 shows enlarged pads for Pin 4,
Pin 5, Pin 6, Pin 7, Pin 10, and Pin 11. Multiple vias should be
implemented from each of the pads to the ground plane,
which significantly reduce the temperatures inside the chip.
The dimensions of the expanded pads are left to the discretion
of the designer and the available board space.
A 6-layer PCB that employs edge guarding and buried capacitive
bypassing, which are EMI mitigation techniques described in
detail in Application Note AN-0971, was manufactured. The
stackup of the 6-layer test PCB is shown in Table 9. PCB layout
Gerber files are available upon request.
Table 9. PCB Layers
Layer
Description
Top
Components and ground planes
VCC planes
All tracks
Inner Layer 1
Inner Layer 2
Inner Layer 3
Inner Layer 4
Bottom
VIA TO GND
ISO
0.1µF
V
NC
Blank
ISO
C3
Buried capacitive plane
Ground planes
V
V+
CC
ADM3251E
V
C1+
CC
0.1µF
C1
EMI testing was repeated on the optimized board. The resulting
reduction in radiated emissions is shown in Table 10. This
board meets FCC Class B standards with no external shielding
by utilizing buried stitching capacitors and edge fencing.
GND
GND
GND
GND
C1–
T
OUT
R
IN
C2+
C2–
C2
C4
Table 10. EMI Test Results
R
OUT
EMI Test Results
300 MHz
48 dB
36 dB
600 MHz
53 dB
32 dB
T
V–
IN
2-Layer PCB Emissions
6-Layer PCB Emissions
Achieved EMI Reduction
GND
GND
ISO
12 dB
21 dB
NC = NO CONNECT
Figure 21. Recommended Printed Circuit Board Layout
In applications involving high common-mode transients,
care should be taken to ensure that board coupling across the
isolation barrier is minimized. Furthermore, the board layout
should be designed such that any coupling that does occur
equally affects all pins on a given component side.
The power supply section of the ADM3251E uses a 300 MHz
oscillator frequency to pass power through its chip-scale trans-
formers. Operation at these high frequencies may raise concerns
about radiated emissions and conducted noise. PCB layout and
construction is a very important tool for controlling radiated
emissions. Refer to Application Note AN-0971, Control of
Radiated Emissions with isoPower Devices, for extensive guidance
on radiation mechanisms and board layout considerations.
Rev. E | Page 13 of 16
ADM3251E
ISOLATION
BARRIER
ISOLATED POWER SUPPLY CIRCUIT
V
CC
SD103C
To operate the ADM3251E with its internal dc-to-dc converter
disabled, connect a voltage of between 3.0 V and 3.7 V to the
5V
IN
OUT
ADP3330
+
+
22µF
10µF
SD
ERR
NR
V
CC pin and apply an isolated power of between 3.0 V and 5.5 V
V
TRANSFORMER
DRIVER
CC
to the VISO pin, referenced to GNDISO
.
GND
A transformer driver circuit with a center-tapped transformer
and LDO can be used to generate the isolated supply, as shown
in Figure 22. The center-tapped transformer provides electrical
isolation of the 5 V power supply. The primary winding of the
transformer is excited with a pair of square waveforms that are
180° out of phase with each other. A pair of Schottky diodes and
a smoothing capacitor are used to create a rectified signal from
the secondary winding. The ADP3330 linear voltage regulator
provides a regulated power supply to the bus side circuitry
(VISO) of the ADM3251E.
78253
SD103C
V
V
CC
CC
V
ISO
ADM3251E
GND
GND
ISO
Figure 22. Isolated Power Supply Circuit
Rev. E | Page 14 of 16
ADM3251E
OUTLINE DIMENSIONS
13.00 (0.5118)
12.60 (0.4961)
20
1
11
10
7.60 (0.2992)
7.40 (0.2913)
10.65 (0.4193)
10.00 (0.3937)
0.75 (0.0295)
0.2
5 (0.0098)
⋅
45°
2.65 (0.1043)
2.35 (0.0925)
0.30 (0.0118)
0.10 (0.0039)
8°
0°
COPLANARITY
0.10
SEATING
PLANE
0.51 (0.0201)
0.31 (0.0122)
1.27 (0.0500)
0.40 (0.0157)
1.27
(0.0500)
BSC
0.33 (0.0130)
0.20 (0.0079)
COMPLIANT TO JEDEC STANDARDS MS-013-AC
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 23. 20-Lead Standard Small Outline Package [SOIC_W]
Wide Body
(RW-20)
Dimensions shown in millimeters and (inches)
ORDERING GUIDE
Model1
ADM3251EARWZ
ADM3251EARWZ-REEL
EVAL-ADM3251EEBZ
Temperature Range
−40°C to +85°C
−40°C to +85°C
Package Description
Package Option
RW-20
RW-20
20-Lead Standard Small Outline Package [SOIC_W]
20-Lead Standard Small Outline Package [SOIC_W]
Evaluation Board
1 Z = RoHS Compliant Part.
Rev. E | Page 15 of 16
ADM3251E
NOTES
©2008–2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07388-0-5/10(E)
Rev. E | Page 16 of 16
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