ADM3485AR [ADI]
IC LINE TRANSCEIVER, PDSO8, SOIC-8, Line Driver or Receiver;
| 型号： | ADM3485AR |
| 厂家： | 
ADI |
| 描述： | IC LINE TRANSCEIVER, PDSO8, SOIC-8, Line Driver or Receiver 驱动 光电二极管 接口集成电路 驱动器 |
| 文件： | 总14页 (文件大小：526K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
3.3V Slew Rate Limited,
Half and Full Duplex
Preliminary Technical Data
ADM3483/ADM3485/ADM3488/ADM3490
logic-high output if both inputs are open circuit. The ADM3488
and ADM3490 feature full duplex communication, while the
ADM3483 and ADM3485 are designed for half-duplex
communication.
The driver outputs are slew rate limited in order to reduce EMI
and data errors caused by reflections from improperly
terminated buses. Excessive power dissipation caused by bus
contention or by output shorting is prevented with a thermal
shutdown circuit.
FEATURES
EIA RS-485/RS-422 Compliant
Data Rate Options
ADM3483, ADM3488 – 250kbps
ADM3485, ADM3490 – 10Mbps
Half and Full Duplex Options
Reduced Slew Rates for Low EMI
2nA Supply Current in Shutdown Mode
(ADM3483,ADM3485)
Up to 32 Transceivers on a bus
-7V to +12V Bus Common Mode Range
Specified over –40°C to +85°C Temperature Range
Available in 8-Lead SOIC
The parts are fully specified over the commercial and industrial
temperature ranges and all are available in 8-lead SOIC and the
ADM3483 and the ADM3485 are also available in an 8-lead
LFCSP packages.
ADM3483/85 available in an 8-Lead LFCSP Package
APPLICATIONS
Low-Power RS-485 Applications
EMI Sensitive Systems
DTE-DCE Interfaces
Industrial Control
Packet Switching
Local Area Networks
Level Translators
FUNCTIONAL BLOCK DIAGRAMS
V
CC
V
CC
ADM3483/ADM3485
R
ADM3488/ADM3490
R
A
B
RO
RO
DI
A
B
RE
DE
DI
GENERAL DESCRIPTION
The ADM3483, ADM3485, ADM3488 and ADM3490 are 3.3V,
low-power transceivers for RS-485 and RS-422 communication.
Each part contains one driver and one receiver. The ADM3483
and ADM3488 feature slew-rate-limited drivers that minimize
EMI and reduce reflections caused by improperly terminated
cables, allowing error-free data transmission at data rates up to
250kbps. The partially slew-rate-limited MAX3486 transmits up
to 2.5Mbps. The ADM3485 and ADM3490 transmit at up to
10Mbps.
Z
Y
D
D
GND
GND
The drivers are short-circuit current limited and are protected
against excessive power dissipation by thermal shutdown
circuitry that places the driver outputs into a high-impedance
state. The receiver input has a fail-safe feature that guarantees a
Part No.
Guaranteed
Data Rate
(Mpbs)
0.25
Supply
Voltage
Half/Full
Duplex
Slew-Rate
Limited
Driver/
Reciever
Enable
Yes
Shutdown
Current
Pin
Count
(V)
(nA)
2
Yes
No
Yes
No
ADM3483
ADM3485
ADM3488
ADM3490
Half
Half
Full
Full
8
8
8
8
2
-
10
Yes
3.0 to 3.6
0.25
No
-
10
No
Table 1. Selection Table
Rev. PrD
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703
www.analog.com
© 2005 Analog Devices, Inc. All rights reserved.
ADM3483/ADM3485/ADM3488/ADM3490
Preliminary Technical Data
ADM3483/ADM3485/ADM3488/ADM3490— SPECIFICATIONS
(VCC=3.3V 0.3ꢀ, TA= TMIN to TMAX, unless otherwise noted.)
Parameter
Min
Typ
Max
Units
Test Conditions/Comments
DRIVER
Differential Output Voltage, VOD
2.0
V
R=100Ω (RS-422), Figure 3
Vcc = 3.3V 5ꢀ
1.5
1.5
V
V
R=54Ω (RS-485), Figure 3
R=60Ω (RS-485), Vcc = 3.3V,
Figure 4
0.2
3
V
V
V
∆ |VOD| for Complementary Output States
Common Mode Output Voltage, VOC
∆ |VOC| for Complementary Output States
DRIVER INPUT LOGIC
R=54Ω or 100Ω, Figure 3
R=54Ω or 100Ω, Figure 3
R=54Ω or 100Ω, Figure 3
0.2
CMOS Input Logic Threshold Low, VIH
CMOS Input Logic Threshold High, VIL
CMOS Logic Input Current, IN1
0.8
V
DE,DI,RE
DE,DI,RE
DE,DI,RE
VIN = 12V DE = 0V
VIN = -7V
VIN = 12V
VIN = -7V
VIN = 12V
VIN = -7V
2.0
2
V
µA
mA
mA
µA
µA
µA
µA
Input Current (A,B), IN2
1.0
-0.8
20
VCC = 0V or 3.6V
DE = 0V, RE = 0V
VCC = 0V or 3.6V
DE = 0V, RE = 0V
VCC = 0V or 3.6V
Output Leakage (Y,Z), IO
-20
Output Leakage (Y,Z) in Shudown Mode, IO
1
-1
RECEIVER
Differential Input Threshold Voltage, VTH
Input Hysteresis, ∆ VTH
CMOS Output Voltage High, VOH
-0.2
0.2
V
mV
V
-7V<VCM<+12V
VCM=0V
50
Vcc – 0.4
IOUT= -1.5mA VID = 200mV,
Figure 5
CMOS Output Voltage Low, VOL
0.4
1
V
IOUT= 2.5mA, VID = 200mV,
Figure 5
Three-State Output Leakage Current, IOZR
Input Resistance , RIN
µA
Vcc = 3.6V, 0V ≤ VOUT ≤ Vcc
-7V<VCM<+12V
12
kΩ
POWER SUPPLY CURRENT
DE = VCC
1.1
2.2
1.9
mA
mA
RE = 0V or VCC No Load,
DE = VCC
Supply Current
DI = 0V or VCC
0.95
RE = 0V
Supply Current in Shutdown Mode, ISHDN
Driver Short-Circuit Output Current, IOSD
Receiver Short-Circuit Output Current, IOSR
0.002
1
µA
mA
mA
mA
DE = 0V, RE = VCC, DI = VCC or 0V
VOUT = -7V
VOUT = 12V
-250
250
60
8
0V < VRO < VCC
Rev.PrD | Page 2 of 14
Preliminary Technical Data
ADM3483/ADM3485/ADM3488/ADM3490
TIMING SPECIFICATIONS-ADM3485/ADM3490 (VCC=3.3V, TA= 25°)
Parameter
Min
Typ
Max
Units Test Conditions/Comments
DRIVER
Differential Output Delay, tDD
1
3
7
7
22
8
35
25
35
35
8
ns
ns
ns
ns
ns
RL = 60Ω, Figure 6
RL = 60Ω, Figure 6
RL = 27Ω, Figure 7
RL = 27Ω, Figure 7
RL = 27Ω, Figure 7
Differential Output Transition Time, tTD
Propagation Delay, Low-to-High Level, tPLH
Propagation Delay, High-to-Low Level, tPHL
22
22
|tPLH – tPHL| Propagation Delay Skew (Note 2),
tPDS
DRIVER OUTPUT ENABLE/DISABLE TIMES
(ADM3485 ONLY)
Output Enable Time Low Level, tPZL
Output Enable Time High Level, tPZH
Output Enable Time from High Level, tPHZ
Output Enable Time from Low Level, tPLZ
45
45
90
90
ns
ns
ns
ns
ns
RL = 110Ω, Figure 8
RL = 110Ω, Figure 8
RL = 110Ω, Figure 8
RL = 110Ω, Figure 9
RL = 110Ω, Figure 9
40
80
40
80
Output Enable Time from Shutdown to Low
Level, tPSL
650
900
Output Enable Time from Shutdown to
High Level, tPSH
650
900
ns
RL = 110Ω, Figure 8
TIMING SPECIFICATIONS-ADM3483/ADM3488 (VCC=3.3V, TA= 25°)
Parameter
Min
Typ
Max
Units Test Conditions/Comments
DRIVER
Differential Output Delay, tDD
600
400
700
700
900
700
1400
1200
1500
1500
ns
ns
ns
ns
ns
RL = 60Ω, Figure 6
RL = 60Ω, Figure 6
RL = 27Ω, Figure 7
RL = 27Ω, Figure 7
RL = 27Ω, Figure 7
Differential Output Transition Time, tTD
Propagation Delay, Low-to-High Level, tPLH
Propagation Delay, High-to-Low Level, tPHL
1000
1000
100
|tPLH – tPHL| Propagation Delay Skew (Note 2),
tPDS
DRIVER OUTPUT ENABLE/DISABLE TIMES
(ADM3485 ONLY)
Output Enable Time Low Level, tPZL
Output Enable Time High Level, tPZH
Output Enable Time from High Level, tPHZ
Output Enable Time from Low Level, tPLZ
900
600
50
1300
800
80
ns
ns
ns
ns
ns
RL = 110Ω, Figure 9
RL = 110Ω, Figure 8
RL = 110Ω, Figure 8
RL = 110Ω, Figure 9
RL = 110Ω, Figure 9
50
80
Output Enable Time from Shutdown to Low
Level, tPSL
1.9
2.7
Output Enable Time from Shutdown to
High Level, tPSH
2.2
3.0
ns
RL = 110Ω, Figure 8
Rev.PrD | Page 3 of 14
ADM3483/ADM3485/ADM3488/ADM3490
Preliminary Technical Data
TIMING SPECIFICATIONS (VCC=3.3V, TA= 25°)
Parameter
Min
Typ
Max
Units Test Conditions/Comments
RECEIVER
Time to Shutdown, tSHDN
80
25
25
25
25
190
65
300
90
ns
ns
ns
ns
ns
ns
ns
ns
ADM3483/ADM3485 only, Note 3
VID = 0V to 3.0V, CL = 15pF, Figure 10
ADM3483/ADM3488 only.
Propagation Delay, Low-to-High Level, tRPLH
Propagation Delay, High-to-Low Level, tRPHL
|tPLH – tPHL| Propagation Delay Skew, tRPDS
75
65
120
90
VID = 0V to 3.0V, CL = 15pF, Figure 10
ADM3483/ADM3488 only.
75
120
10
VID = 0V to 3.0V, CL = 15pF, Figure 10
ADM3483/ADM3488 only.
20
25
25
50
CL = 15pF, Figure 11, ADM3483/ADM3485
only
Output Enable Time to Low Level, tPRZL
Output Enable Time to High Level, tPRZH
Ouput Disable Time from High Level, tPRHZ
Ouput Disable Time from Low Level, tPRLZ
50
45
ns
ns
ns
ns
ns
CL = 15pF, Figure 11, ADM3483/ADM3485
only
25
CL = 15pF, Figure 116, ADM3483/ADM3485
only
25
45
CL = 15pF, Figure 11, ADM3483/ADM3485
only
Output Enable Time from Shutdown to
Low Level, tPRSL
720
720
1400
1400
CL = 15pF, Figure 11, ADM3483/ADM3485
only
Output Enable Time from Shutdown to
High Level, tPRSH
CL = 15pF, Figure 11, ADM3483/ADM3485
only
Note1: ∆VOD and ∆VOC are the changes in VOD and VOC, respectively, when DI input changes state.
Note 2: Measured on |tPLH (Y) - tPHL (Y) | and |tPLH (Z) - tPHL (Z) |.
Note 3: The transceivers are put into shutdown by bringing RE high and DE low. If the inputs are in this state for less than 80ns, the parts are guaranteed not to enter
shutdown. If the inputs are in this state for at least 300ns, the part are guaranteed to have entered shutdown.
Rev.PrD | Page 4 of 14
Preliminary Technical Data
ADM3483/ADM3485/ADM3488/ADM3490
AB1SOLUTE MAXIMUM RATINGS
Table 2. (TA = 25°C unless otherwise noted)
Parameter
Rating
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or
any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
VCC to GND
TBD
TBD
RE
Digital I/O Voltage (DE, , DI, ROUT)
Driver Output/Receiver Input Voltage
Operating Temperature Range
Storage Temperature Range
TBD
-40°C to +85°C
-65°C to +125°C
θJA Thermal Impedance
SOIC
LFCSP
110°C/W
62°C/W
Lead Temperature
Soldering (10 sec)
Vapour Phase (60 sec)
Infrared (15 sec)
300°C
215°C
220°C
Rev.PrD | Page 5 of 14
ADM3483/ADM3485/ADM3488/ADM3490
Preliminary Technical Data
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
8
7
6
5
8
7
6
5
RO
RE
DE
DI
V
V
A
B
Z
1
2
3
4
1
2
3
4
CC
CC
ADM3483
ADM3485
TOP VIEW
(Not to Scale)
ADM3488
ADM3490
TOP VIEW
(Not to Scale)
B
RO
DI
A
GND
GND
Y
Table 3. ADM3483/ADM3485 Pin Descriptions
Pin No.
Mnemonic
Description
1
RO
Receiver Output. When enabled, if A > B by 200 mV, then RO = high.
If A < B by 200 mV, then RO = low.
2
RE
Receiver Output Enable.
A low level enables the receiver output, RO.
A high level places it in a high impedance state.
3
4
DE
DI
Driver Output Enable. A high level enables the driver differential inputs A and B.
A low level places it in a high impedance state.
Driver Input. When the driver is enabled, a logic low on DI forces A low and B high
while a logic high on DI forces A high and B low.
5
6
7
8
GND
A
B
Ground.
Noninverting Receiver Input A/Driver Output A.
Inverting Receiver Input B/Driver Output B.
5 V Power Supply.
VCC
Table 4. ADM34884/ADM3490 Pin Descriptions
Pin No.
Mnemonic
Description
1
2
VCC
RO
5 V Power Supply.
Receiver Output. When enabled, if A > B by 200 mV, then RO = high.
If A < B by 200 mV, then RO = low.
3
DI
Driver Input. When the driver is enabled, a logic low on DI forces A low and B high
while a logic high on DI forces A high and B low.
4
5
6
7
8
GND
Ground.
Y
Z
B
A
Driver Noninverting Output.
Driver Inverting Output.
Receiver Inverting Input.
Receiver Noninverting Input.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev.PrD | Page 6 of 14
Preliminary Technical Data
ADM3483/ADM3485/ADM3488/ADM3490
TEST CIRCUITS AND SWITCHING CHARACTERISTICS
C
Y
L
OUT
D
R =
L
RL/2
60⍀
GENERATOR
(NOTE 4)
50⍀
V
OD
V
CC
C
V
OC
RL/2
L
= 15pF (NOTE 5)
C
L
Z
3V
0
Figure 3. Driver VOD and VOC
IN
1.5V
1.5V
375⍀
t
t
DD
DD
2.0V
90%
90%
50%
10%
50%
V
=
CM
-7V to +12V
OUT
10%
R
V
L
OD
-2.0V
D
t
t
TD
TD
V
375⍀
CC
Figure 6. Driver Differential Output Delay and Transition Times
V
OM
Figure 4. Driver VOD with Varying Common-Mode Voltage
= 27⍀
R
L
S1
OUT
D
GENERATOR
(NOTE 4)
V
R
ID
50⍀
= 15pF
C
L
(NOTE 5)
V
CC
0
V
OH
+V
OL
V
V
OL
OH
I
OL
(+)
I
OH
(-)
1.5V
V
=
OM
2
3V
0V
Figure 5. Receiver VOH and VOL
IN
1.5V
1.5V
t
t
PHL
PLH
V
OH
Y
OUT
V
OM
V
OM
V
OL
t
t
PLH
PHL
V
OH
Z
OUT
V
OM
V
OM
V
OL
Figure 7. Driver Propagation Delays
Rev.PrD | Page 7 of 14
ADM3483/ADM3485/ADM3488/ADM3490
Preliminary Technical Data
S1
OUT
OUT
0 OR 3V
D
V
ID
R
GENERATOR
(NOTE 4)
50⍀
= 15pF
L
C
R
= 110⍀
L
= 50pF
C
L
(NOTE 5)
(NOTE 5)
GENERATOR
(NOTE 4)
50⍀
1.5V
0
V
OH
+V
2
OL
1.5V
V
=
V
OM
CC
V
=
OM
2
3V
0
3.0V
IN
1.5V
1.5V
IN
1.5V
1.5V
0
t
t
PHZ
PZH
t
RPHL
t
RPLH
V
OH
0.25V
V
CC
OUT
V
OM
V
OM
V
OM
OUT
0
0
Figure 8. Driver Enable and Disable Times (tPZH, tPSH, tPHZ
)
Figure 10. Receiver Propagation Delay
V
CC
= 110⍀
R
L
S1
0 OR 3V
OUT
D
= 50pF
C
L
(NOTE 5)
GENERATOR
(NOTE 4)
50⍀
3V
IN
1.5V
1.5V
0
t
t
PLZ
PSL
V
CC
OUT
V
OM
0.25V
V
OL
Figure 9. Driver Enable and Disable Times (tPZL, tPSL, tPLZ
)
Rev.PrD | Page 8 of 14
Preliminary Technical Data
ADM3483/ADM3485/ADM3488/ADM3490
S1
S3
1.5V
1k⍀
V
CC
-1.5V
V
ID
R
S2
C
L
(NOTE 5)
GENERATOR
(NOTE 4)
50⍀
3V
3V
S1 OPEN
S2 CLOSED
S3 = 1.5V
S1 CLOSED
S2 OPEN
IN
1.5V
IN
1.5V
S3 = -1.5V
0
0
t
t
t
PRZH
PRSH
PRZL
t
PRSL
V
V
OH
CC
OUT
OUT
1.5V
1.5V
0
V
OL
3V
3V
S1 OPEN
S2 CLOSED
S3 = 1.5V
S1 CLOSED
S2 OPEN
IN
1.5V
IN
1.5V
S3 = -1.5V
0
0
t
PRHZ
t
PRLZ
V
V
OH
CC
OUT
0.25V
OUT
0.25V
0
V
OL
Figure 11. Receiver Enable and Disable Times
Rev.PrD | Page 9 of 14
ADM3483/ADM3485/ADM3488/ADM3490
Preliminary Technical Data
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 1. Output Current vs. Receiver Output Low Voltage
Figure 2. Output Current vs. Receiver Output High Voltage
Figure 3. Receiver Output High Voltage vs. Temperature
Figure 4. Receiver Output Low Voltage vs. Temperature
Figure 5. Driver Output Current vs. Differential Output Voltage
Figure 6. Driver Differential Output Voltage vs. Temperature
Rev.PrD | Page 10 of 14
Preliminary Technical Data
ADM3483/ADM3485/ADM3488/ADM3490
Figure 7. Output Current vs. Driver Output Low Voltage
Figure 10. Shutdown Current vs. Temperature
Figure 8. Output Current vs. Driver Output High Voltage
Figure 11. TBD
Figure 9.Supply Current vs. Temperature
Figure 12. TBD
Rev.PrD | Page 11 of 14
ADM3483/ADM3485/ADM3488/ADM3490
Preliminary Technical Data
REDUCED EMI AND REFLECTIONS
CIRCUIT DESCRIPTION
(ADM3483/ ADM3488)
The ADM3483/ADM3485/ADM 3488/ADM3490 are low-
power transceivers for RS-485 and RS-422 communications.
The ADM3483 and ADM3488 can transmit and receive at data
rates up to 250kbps, and the ADM3485/ ADM3490 at up to
10Mbps. The ADM3488/ ADM3490 are full-duplex
transceivers, while the ADM3483/ADM3485 are half-duplex.
Driver Enable (DE) and Receiver Enable (RE) pins are included
on the ADM3483/ADM3485. When disabled, the driver and
receiver outputs are high impedance.
The ADM3483/ADM3488 are slew-rate limited, minimizing
EMI and reducing reflections caused by improperly terminated
cables.
LOW-POWER SHUTDOWN MODE
(ADM3483/ADM3485)
A low-power shutdown mode is initiated by bringing both RE
high and DE low. The devices will not shut down unless both
the driver and receiver are disabled (high impedance). In
shutdown, the devices typically draw only 2nA of supply
current. For these devices, the tPSH and tPSL enable times assume
the part was in the low-power shutdown mode; the tPZH and tPZL
enable times assume the receiver or driver was disabled, but the
part was not shut down.
DEVICES WITH RECEIVER/DRIVER ENABLES
(ADM3483/ADM2485)
Inputs
Outputs
Mode
DE
1
DI
1
B*
A*
RE
X
0
1
0
Normal
Normal
Normal
X
1
0
1
DRIVER OUTPUT PROTECTION
0
0
X
High-Z
High-Z
High-Z
Excessive output current and power dissipation caused by faults
or by bus contention are prevented by two methods. A foldback
current limit on the output stage provides immediate protection
against short circuits over the whole common-mode voltage
range (see Typical Performance Characteristics). In addition, a
thermal shutdown circuit forces the driver outputs into a high-
impedance state if the die temperature rises excessively.
1
0
X
High-Z Shutdown
Table x. Transmitting Truth Table
Outputs
Inputs
Mode
DE
0*
0*
0*
0
A,B
≥+0.2V
≤-0.2V
Inputs Open
x
RO
RE
0
1
Normal
Normal
PROPAGATION DELAY
Skew time is simply the difference between the low-to-high and
high-to-low propagation delay. Small driver/receiver skew times
help maintain a symmetrical mark-space ratio (50% duty cycle).
The receiver skew time, |tPRLH - tPRHL|, is under 10ns (20ns
for the ADM3483/ADM3488). The driver skew times are 8ns
for the ADM485/ADM3490, and typically under 100ns for the
ADM3483/ADM3488.
0
0
1
0
Normal
1
High-Z
Shutdown
Table x. Receiving Truth Table
DEVICES WITHOUT RECEIVER/DRIVER ENABLES
(ADM3488/ADM2490)
LINE LENGTH VS. DATA RATE
The RS-485/RS-422 standard covers line lengths up to 4000 feet.
For line lengths greater than 4000 feet, see Figure 13.
Input
Outputs
DI
1
Z
0
1
Y
1
0
0
TYPICAL APPLICATIONS
Table x. Transmitting Truth Table
The ADM3483, ADM3485, ADM3488 and ADM3490
transceivers are designed for bidirectional data communications
on multipoint bus transmission lines. Figures 11 and 12 show
typical network applications circuits. These parts can also be
used as line repeaters, with cable lengths longer than 4000 feet,
as shown in Figure 13. To minimize reflections, the line should
be terminated at both ends in its characteristic impedance, and
stub lengths off the main line should be kept as short as
possible. The slew-rate-limited ADM3483/ADM3488 are more
tolerant of imperfect termination.
Input
A,B
Outputs
RO
0
≥+0.2
1
≤ -0.2
Inputs Open
1
Table x. Receiving Truth Table
Rev.PrD | Page 12 of 14
Preliminary Technical Data
ADM3483/ADM3485/ADM3488/ADM3490
MAXIMUM NUMBER OF TRANSCEIVERS ON BUS: 32
ADM3483/ADM3485
ADM3483/ADM3485
RO
R
RO
RE
DE
DI
R
A
B
A
B
RE
DE
DI
D
D
Figure 11. ADM3483/ADM3485 Typical RS-485 Network
MASTER
SLAVE
MAXIMUM NUMBER OF NODES: 32
ADM3488/ADM3490
ADM3488/ADM3490
DE
DI
A
B
Y
Z
D
RO
RE
DE
R
Z
Y
B
A
DI
D
R
RO
RE
A
B
Z
Y
A
B
Z
Y
R
R
SLAVE
SLAVE
D
D
RO
DE DI
RO
DE DI
RE
RE
Figure 12. ADM3488/ADM3490 Full Duplex RS-485 Network
ADM3488/ADM3490
A
RO
R
DATA IN
RE
B
DE
DI
Z
Y
D
DATA OUT
Figure 13. Line Repeater for ADM3488/ADM3490
Rev.PrD | Page 13 of 14
ADM3483/ADM3485/ADM3488/ADM3490
OUTLINE DIMENSIONS
Preliminary Technical Data
5.00 (0.1968)
4.80 (0.1890)
8
1
5
6.20 (0.2440)
5.80 (0.2284)
4.00 (0.1574)
3.80 (0.1497)
4
0.50 (0.0196)
0.25 (0.0099)
1.27 (0.0500)
BSC
× 45°
1.75 (0.0688)
1.35 (0.0532)
0.25 (0.0098)
0.10 (0.0040)
8°
0.51 (0.0201)
0.31 (0.0122)
0° 1.27 (0.0500)
COPLANARITY
0.10
0.25 (0.0098)
0.17 (0.0067)
SEATING
PLANE
0.40 (0.0157)
Figure 6. 8-Lead Standard Small Outline Package [SOIC]
Figure 7. 8-Lead Lead Frame Chip Scale Package [LFCSP]
(CP-8)
(R-8)
Dimensions shown in millimeters
Dimensions shown in millimeters
ORDERING GUIDE
Model
Temperature Range
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
Package Type
Branding
ADM3483AR
ADM3483ACP
ADM3485AR
ADM3485ACP
ADM3488AR
ADM3490AR
R-8
CP-8
R-8
CP-8
R-8
R-8
© 2004 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective companies.
Printed in the U.S.A.
PR05524-0-4/05(PrD)
Rev.PrD | Page 14 of 14
相关型号：
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