ADM485JR-REEL [ADI]
Meets EIA RS-485 standard; 符合EIA RS- 485标准
| 型号： | ADM485JR-REEL |
| 厂家： | 
ADI |
| 描述： | Meets EIA RS-485 standard |
| 文件： | 总16页 (文件大小：607K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
5 V Low Power
EIA RS-485 Transceiver
ADM485
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Meets EIA RS-485 standard
5 Mbps data rate
ADM485
1
8
Single 5 V supply
RO
RE
V
CC
R
–7 V to +12 V bus common-mode range
High speed, low power BiCMOS
Thermal shutdown protection
Short-circuit protection
Driver propagation delay: 10 ns typical
Receiver propagation delay: 15 ns typical
High-Z outputs with power off
Superior upgrade for LTC485
2
3
4
7
6
5
B
DE
DI
A
GND
D
Figure 1.
APPLICATIONS
Low power RS-485 systems
DTE/DCE interface
Packet switching
Local area networks (LNAs)
Data concentration
Data multiplexers
Integrated services digital network (ISDN)
GENERAL DESCRIPTION
The ADM485 is a differential line transceiver suitable for high
speed bidirectional data communication on multipoint bus
transmission lines. It is designed for balanced data transmission
and complies with EIA standards RS-485 and RS-422. The part
contains a differential line driver and a differential line receiver.
Both the driver and the receiver can be enabled independently.
When disabled, the outputs are three-stated.
The receiver contains a fail-safe feature that results in a logic
high output state if the inputs are unconnected (floating).
The ADM485 is fabricated on BiCMOS, an advanced mixed
technology process combining low power CMOS with fast
switching bipolar technology. All inputs and outputs contain
protection against ESD; all driver outputs feature high source
and sink current capability. An epitaxial layer is used to guard
against latch-up.
The ADM485 operates from a single 5 V power supply.
Excessive power dissipation caused by bus contention or by
output shorting is prevented by a thermal shutdown circuit. If
during fault conditions, a significant temperature increase is
detected in the internal driver circuitry, this feature forces the
driver output into a high impedance state.
The ADM485 features extremely fast switching speeds. Minimal
driver propagation delays permit transmission at data rates up
to 5 Mbps while low skew minimizes EMI interference.
The part is fully specified over the commercial and industrial
temperature range and is available in 8-lead PDIP, 8-lead SOIC,
and small footprint, 8-lead MSOP packages.
Up to 32 transceivers can be connected simultaneously on a
bus, but only one driver should be enabled at any time. It is
important, therefore, that the remaining disabled drivers do not
load the bus. To ensure this, the ADM485 driver features high
output impedance when disabled and when powered down,
which minimizes the loading effect when the transceiver is not
being used. The high impedance driver output is maintained
over the common-mode voltage range of −7 V to +12 V.
Rev. F
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©1993–2008 Analog Devices, Inc. All rights reserved.
ADM485
TABLE OF CONTENTS
Features .............................................................................................. 1
Test Circuits..................................................................................... 10
Switching Characteristics .............................................................. 11
Applications Information.............................................................. 12
Differential Data Transmission ................................................ 12
Cable and Data Rate................................................................... 12
Thermal Shutdown .................................................................... 12
Propagation Delay...................................................................... 12
Receiver Open Circuit, Fail-Safe.............................................. 12
Outline Dimensions....................................................................... 13
Ordering Guide .......................................................................... 14
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Specifications .................................................................. 4
Absolute Maximum Ratings............................................................ 5
ESD Caution.................................................................................. 5
Pin Configuration and Function Descriptions............................. 6
Typical Performance Characteristics ............................................. 7
REVISION HISTORY
04/08—Rev. E to Rev. F
1/03—Rev. B to Rev. C.
Updated Format..................................................................Universal
Changes to Table 2............................................................................ 4
Updated Outline Dimension......................................................... 13
Changes to Ordering Guide .......................................................... 14
Change to Specifications ..................................................................2
Change to Ordering Guide...............................................................3
12/02—Rev. A to Rev. B.
Deleted Q-8 Package..........................................................Universal
Edits to Features.................................................................................1
Edits to General Description ...........................................................1
Edits, additions to Specifications.....................................................2
Edits, additions to Absolute Maximum Ratings............................3
Additions to Ordering Guide...........................................................3
TPCs Updated and Reformatted .....................................................5
Addition of 8-Lead MSOP Package ................................................9
Update to Outline Dimensions........................................................9
10/03—Rev. D to Rev. E
Changes to Timing Specifications.................................................. 2
Updated Ordering Guide................................................................. 3
7/03—Rev. C to Rev. D
Changes to Absolute Maximum Ratings....................................... 3
Changes to Ordering Guide ............................................................ 3
Update to Outline Dimensions....................................................... 9
Rev. F | Page 2 of 16
ADM485
SPECIFICATIONS
VCC = 5 V 5ꢀ, all specifications TMIN to TMAX, unless otherwise noted.
Table 1.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
DRIVER
Differential Output Voltage, VOD
5.0
5.0
5.0
5.0
0.2
3
0.2
250
250
0.8
V
V
V
V
V
V
V
mA
mA
V
V
μA
R = ∞, see Figure 20
2.0
1.5
1.5
VCC = 5 V, R = 50 Ω (RS-422), see Figure 20
R = 27 Ω (RS-485), see Figure 20
VTST = −7 V to +12 V, see Figure 21
R = 27 Ω or 50 Ω, see Figure 20
R = 27 Ω or 50 Ω, see Figure 20
R = 27 Ω or 50 Ω
VOD3
Δ|VOD| for Complementary Output States
Common-Mode Output Voltage, VOC
Δ|VOD| for Complementary Output States
Output Short-Circuit Current, VOUT = High
Output Short-Circuit Current, VOUT = Low
CMOS Input Logic Threshold Low, VINL
CMOS Input Logic Threshold High, VINH
Logic Input Current (DE, DI)
35
35
−7 V ≤ VO ≤ +12 V
−7 V ≤ VO ≤ +12 V
2.0
1.0
RECEIVER
Differential Input Threshold Voltage, VTH
Input Voltage Hysteresis, ΔVTH
Input Resistance
−0.2
12
+0.2
V
−7 V ≤ VCM ≤ +12 V
VCM = 0 V
−7 V ≤ VCM ≤ +12 V
VIN = 12 V
70
mV
kΩ
mA
mA
V
Input Current (A, B)
1
–0.8
0.8
VIN = −7 V
CMOS Input Logic Threshold Low, VINL
CMOS Input Logic Threshold High, VINH
Logic Enable Input Current (RE)
CMOS Output Voltage Low, VOL
CMOS Output Voltage High, VOH
Short-Circuit Output Current
Three-State Output Leakage Current
POWER SUPPLY CURRENT
2.0
V
1
μA
V
V
mA
μA
0.4
IOUT = 4.0 mA
IOUT = −4.0 mA
VOUT = GND or VCC
0.4 V ≤ VOUT ≤ 2.4 V
4.0
7
85
1.0
ICC, Outputs Enabled
1.0
0.6
2.2
1
mA
mA
Digital inputs = GND or VCC
Digital inputs = GND or VCC
ICC, Outputs Disabled
Rev. F | Page 3 of 16
ADM485
TIMING SPECIFICATIONS
VCC = 5 V 5ꢀ, all specifications TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter
Min Typ Max Unit Test Conditions/Comments
DRIVER
Propagation Delay Input to Output, tPLH, tPHL
Driver Output to OUTPUT, tSKEW
Driver Rise/Fall Time, tR, tF
Driver Enable to Output Valid
Driver Disable Timing
Matched Enable Switching |tZH − tZL|
Matched Disable Switching |tHZ − tLZ|
RECEIVER
2
10
1
15
5
ns
ns
ns
ns
ns
ns
ns
RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, see Figure 22
RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, see Figure 22
RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, see Figure 22
RL = 110 Ω, CL = 50 pF, see Figure 23
RL = 110 Ω, CL = 50 pF, see Figure 23
RL = 110 Ω, CL = 50 pF, see Figure 231
RL = 110 Ω, CL = 50 pF, see Figure 231
8
15
25
25
2
10
10
0
0
2
Propagation Delay Input to Output, tPLH, tPHL
8
15
30
5
20
20
ns
ns
ns
ns
ns
ns
CL = 15 pF, see Figure 24
CL = 15 pF, see Figure 24
CL = 15 pF, RL = 1 kΩ, see Figure 25
CL = 15 pF, RL = 1 kΩ, see Figure 25
Skew |tPLH − tPHL
|
Receiver Enable, tZH, tZL
Receiver Disable, tHZ, tLZ
Tx Pulse Width Distortion
Rx Pulse Width Distortion
5
5
1
1
1 Guaranteed by characterization.
Rev. F | Page 4 of 16
ADM485
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 4. Transmitting
Inputs
Outputs
Table 3.
Parameter
DE
DI
B
A
Rating
1
1
0
1
0
X1
0
1
Z2
1
0
Z2
VCC
Inputs
Driver Input (DI)
Control Inputs (DE, RE)
Receiver Inputs (A, B)
Outputs
−0.3 V to +7 V
−0.3 V to VCC + 0.3 V
−0.3 V to VCC + 0.3 V
−9 V to +14 V
1 X = don’t care.
2 Z = high impedance.
Table 5. Receiving
Driver Outputs (A, B)
Receiver Output
−9 V to +14 V
−0.5 V to VCC + 0.5 V
900 mW
206°C/W
500 mW
130°C/W
450 mW
170°C/W
RE
Input A − Input B
Output RO
0
0
0
1
≥ +0.2 V
≤ −0.2 V
Inputs open
X1
1
0
1
Z2
Power Dissipation 8-Lead MSOP
θJA, Thermal Impedance
Power Dissipation 8-Lead PDIP
θJA, Thermal Impedance
Power Dissipation 8-Lead SOIC
θJA, Thermal Impedance
Operating Temperature Range
Commercial Range (J Version)
Industrial Range (A Version)
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
Vapor Phase (60 sec)
Infrared (15 sec)
1 X = don’t care.
2 Z = high impedance.
0°C to 70°C
−40°C to +85°C
−65°C to +150°C
300°C
215°C
220°C
ESD CAUTION
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. F | Page 5 of 16
ADM485
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
RO
RE
DE
DI
1
2
3
4
8
7
6
5
V
CC
B
ADM485
TOP VIEW
(Not to Scale)
A
GND
Figure 2. Pin Configuration
Table 6. Pin Function Descriptions
Pin No. Mnemonic Function
1
2
3
RO
RE
Receiver Output. When enabled, if A is greater than B by 200 mV, RO is high. If A is less than B by 200 mV, RO is low.
Receiver Output Enable. A low level enables the receiver output, RO. A high level places it in a high impedance state.
DE
Driver Output Enable. A high level enables the driver differential outputs, A and B. A low level places it in a high
impedance state.
4
DI
Driver Input. When the driver is enabled, a logic low on DI forces A low and B high, while a logic high on DI forces
A high and B low.
5
6
7
8
GND
A
B
Ground Connection, 0 V.
Noninverting Receiver Input A/Driver Output A.
Inverting Receiver Input B/Driver Output B.
Power Supply, 5 V 5ꢀ.
VCC
Rev. F | Page 6 of 16
ADM485
TYPICAL PERFORMANCE CHARACTERISTICS
50
45
40
35
30
25
20
15
10
5
0.40
0.35
0.30
0.25
0.20
0.15
I = 8mA
0
0
0.25
0.50
0.75
1.00
1.25
1.50
1.75
2.00
–50
–25
0
25
50
75
100
125
RECEIVER OUTPUT LOW VOLTAGE (V)
TEMPERATURE (°C)
Figure 6. Receiver Output Low Voltage vs. Temperature
Figure 3. Output Current vs. Receiver Output Low Voltage
90
80
70
60
50
40
30
20
10
0
–2
–4
–6
–8
–10
–12
–14
–16
–18
0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
3.50
3.75
4.00
4.25
4.50
4.75
5.00
DRIVER DIFFERENTIAL OUTPUT VOLTAGE (V)
RECEIVER OUTPUT HIGH VOLTAGE (V)
Figure 4. Output Current vs. Receiver Output High Voltage
Figure 7. Output Current vs. Driver Differential Output Voltage
4.55
2.15
I = 8mA
R
= 26.8Ω
L
4.50
4.45
4.40
4.35
4.30
4.25
4.20
4.15
2.10
2.05
2.00
1.95
1.90
–50
–25
0
25
50
75
100
125
–50
–25
0
25
50
75
100
125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 5. Receiver Output High Voltage vs. Temperature
Figure 8. Driver Differential Output Voltage vs. Temperature
Rev. F | Page 7 of 16
ADM485
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
100
90
80
70
60
50
40
30
20
10
|
tPLH – tPHL |
0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
–50
–25
0
25
50
75
100
125
DRIVER OUTPUT LOW VOLTAGE (V)
TEMPERATURE (°C)
Figure 9. Output Current vs. Driver Output Low Voltage
Figure 12. Receiver Skew vs. Temperature
0
6
5
4
3
2
1
–10
–20
–30
–40
–50
–60
–70
| tPHLA – tPHLB
|
|
–80
–90
–100
–110
–120
| tPLHA – tPLHB
0
–50
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
–25
0
25
50
75
100
125
DRIVER OUTPUT HIGH VOLTAGE (V)
TEMPERATURE (°C)
Figure 10. Output Current vs. Driver Output High Voltage
Figure 13. Driver Skew vs. Temperature
1.1
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
1.0
0.9
0.8
0.7
0.6
0.5
DRIVER ENABLED
|
tPLH – tPHL |
DRIVER DISABLED
–50
–25
0
25
50
75
100
125
–50
–25
0
25
50
75
100
125
150
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 11. Supply Current vs. Temperature
Figure 14. Driver Pulse Width Distortion (PWD) vs. Temperature
Rev. F | Page 8 of 16
ADM485
T
DI
A
4
T
A
B
B
1,2
3
1,2
RO
B
B
B
W
CH1 1.00VΩ
CH3 5.00VΩ
CH2 1.00VΩ
CH4 2.00VΩ
M10.00ns
CH4
2.76V
W
B
B
W
B
CH1 1.00VΩ
CH2 1.00VΩ
M5.00ns
CH3
2.64V
W
W
W
Figure 15. Unloaded Driver Differential Outputs
Figure 18. Driver/Receiver Propagation Delays, High to Low
A
A
B
B
1,2
1,2
B
B
W
CH1 1.00VΩ
CH2 500mVΩ
M5.00ns
CH3
2.74V
W
CH1 500mVΩ
CH2 500mVΩ
M10.00ns
CH4
2.76V
Figure 16. Loaded Driver Differential Outputs
Figure 19. Driver Output at 30 Mbps
DI
A
T
4
B
RO
1,2
3
B
B
B
W
CH1 1.00VΩ
CH3 5.00VΩ
CH2 1.00VΩ
CH4 2.00VΩ
M10.0ns
CH4
400mV
W
B
W
W
Figure 17. Driver/Receiver Propagation Delays, Low to High
Rev. F | Page 9 of 16
ADM485
TEST CIRCUITS
V
R
R
CC
A
B
V
OD
R
L
0V OR 3V
DE IN
S1
S2
DE
V
OC
C
V
OUT
L
Figure 20. Driver Voltage Measurement
Figure 23. Driver Enable/Disable
375Ω
A
B
V
V
60Ω
TST
V
OD3
OUT
RE
C
L
375Ω
Figure 21. Driver Voltage Measurement
Figure 24. Receiver Propagation Delay
V
CC
+1.5V
A
B
C
C
S1
L1
L2
R
L
S2
R
–1.5V
RE
LDIFF
C
V
OUT
L
RE
IN
Figure 22. Driver Propagation Delay
Figure 25. Receiver Enable/Disable
Rev. F | Page 10 of 16
ADM485
SWITCHING CHARACTERISTICS
3V
1.5V
tPLH
1.5V
0V
B
tPHL
A, B
0V
0V
1/2V
O
V
O
tPLH
tPHL
A
tSKEW
= tPLH – tPHL
V
V
OH
OL
+V
0V
O
90% POINT
90% POINT
RO
1.5V
1.5V
tSKEW
= tPLH – tPHL
10% POINT
10% POINT
–V
O
tR
tF
Figure 28. Receiver Propagation Delay
Figure 26. Driver Propagation Delay, Rise/Fall Timing
3V
0V
3V
1.5V
1.5V
tZL
RE
DE
1.5V
tZL
1.5V
0V
tLZ
tLZ
1.5V
1.5V
RO
V
+ 0.5V
– 0.5V
2.3V
2.3V
OL
A, B
A, B
OUTPUT LOW
OUTPUT HIGH
V
V
+ 0.5V
OL
OH
V
OL
V
OL
tZH
tHZ
tZH
tHZ
V
V
OH
OH
– 0.5V
V
RO
0V
OH
0V
Figure 27. Driver Enable/Disable Timing
Figure 29. Receiver Enable/Disable Timing
Rev. F | Page 11 of 16
ADM485
APPLICATIONS INFORMATION
DIFFERENTIAL DATA TRANSMISSION
RT
RT
Differential data transmission is used to reliably transmit data at
high rates over long distances and through noisy environments.
Differential transmission nullifies the effects of ground shifts
and noise signals that appear as common-mode voltages on the
line. There are two main standards approved by the EIA that
specify the electrical characteristics of transceivers used in
differential data transmission.
D
D
R
R
The RS-422 standard specifies data rates up to 10 MBaud and
line lengths up to 4000 ft. A single driver can drive a transmission
line with up to 10 receivers.
R
R
D
D
To cater to true multipoint communications, the RS-485
standard was defined. This standard meets or exceeds all the
requirements of RS-422 but also allows for up to 32 drivers and
32 receivers to be connected to a single bus. An extended common-
mode range of −7 V to +12 V is defined. The most significant
difference between the RS-422 standard and the RS-485 standard is
the fact that the drivers can be disabled, thereby allowing more
than one (32 in fact) to be connected to a single line. Only one
driver should be enabled at a time, but the RS-485 standard
contains additional specifications to guarantee device safety in
the event of line contention.
Figure 30. Typical RS-485 Network
As with any transmission line, it is important that reflections be
minimized. This can be achieved by terminating the extreme ends
of the line using resistors equal to the characteristic impedance of
the line. Stub lengths of the main line should also be kept as
short as possible. A properly terminated transmission line appears
purely resistive to the driver.
THERMAL SHUTDOWN
The ADM485 contains thermal shutdown circuitry that protects
the part from excessive power dissipation during fault conditions.
Shorting the driver outputs to a low impedance source can result
in high driver currents. The thermal sensing circuitry detects
the increase in die temperature and disables the driver outputs.
The thermal sensing circuitry is designed to disable the driver
outputs when a die temperature of 150°C is reached. As the
device cools, the drivers are re-enabled at 140°C.
Table 7. Comparison of RS-422 and RS-485 Interface Standards
Specification
RS-422
Differential
4000 ft.
2 V
100 Ω
4 kΩ min
200 mV
RS-485
Differential
4000 ft.
1.5 V
54 Ω
12 kΩ min
200 mV
Transmission Type
Maximum Cable Length
Minimum Driver Output Voltage
Driver Load Impedance
Receiver Input Resistance
Receiver Input Sensitivity
Receiver Input Voltage Range
No. of Drivers/Receivers per Line
PROPAGATION DELAY
The ADM485 features very low propagation delay, ensuring
maximum baud rate operation. The driver is well balanced,
ensuring distortion free transmission.
−7 V to +7 V −7 V to +12 V
1/10 32/32
CABLE AND DATA RATE
Another important specification is a measure of the skew
between the complementary outputs. Excessive skew impairs
the noise immunity of the system and increases the amount of
electromagnetic interference (EMI).
The transmission line of choice for RS-485 communications is
a twisted pair. Twisted pair cable tends to cancel common-mode
noise and causes cancellation of the magnetic fields generated
by the current flowing through each wire, thereby reducing the
effective inductance of the pair.
RECEIVER OPEN CIRCUIT, FAIL-SAFE
The receiver input includes a fail-safe feature that guarantees a
logic high on the receiver when the inputs are open circuit or
floating.
The ADM485 is designed for bidirectional data communications
on multipoint transmission lines. A typical application showing
a multipoint transmission network is illustrated in Figure 30.
An RS-485 transmission line can have as many as 32 transceivers
on the bus. Only one driver can transmit at a particular time,
but multiple receivers can be enabled simultaneously.
Rev. F | Page 12 of 16
ADM485
OUTLINE DIMENSIONS
5.00 (0.1968)
4.80 (0.1890)
8
1
5
4
6.20 (0.2441)
5.80 (0.2284)
4.00 (0.1574)
3.80 (0.1497)
0.50 (0.0196)
0.25 (0.0099)
1.27 (0.0500)
BSC
45°
1.75 (0.0688)
1.35 (0.0532)
0.25 (0.0098)
0.10 (0.0040)
8°
0°
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
1.27 (0.0500)
0.40 (0.0157)
0.25 (0.0098)
0.17 (0.0067)
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MS-012-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 31. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body (R-8)
Dimensions shown in millimeters and (inches)
3.20
3.00
2.80
8
1
5
4
5.15
4.90
4.65
3.20
3.00
2.80
PIN 1
0.65 BSC
0.95
0.85
0.75
1.10 MAX
0.80
0.60
0.40
8°
0°
0.15
0.00
0.38
0.22
0.23
0.08
SEATING
PLANE
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187-AA
Figure 32. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
Rev. F | Page 13 of 16
ADM485
0.400 (10.16)
0.365 (9.27)
0.355 (9.02)
8
1
5
4
0.280 (7.11)
0.250 (6.35)
0.240 (6.10)
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
0.100 (2.54)
BSC
0.060 (1.52)
MAX
0.195 (4.95)
0.130 (3.30)
0.115 (2.92)
0.210 (5.33)
MAX
0.015
(0.38)
MIN
0.150 (3.81)
0.130 (3.30)
0.115 (2.92)
0.015 (0.38)
GAUGE
0.014 (0.36)
0.010 (0.25)
0.008 (0.20)
PLANE
SEATING
PLANE
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
0.430 (10.92)
MAX
0.005 (0.13)
MIN
0.070 (1.78)
0.060 (1.52)
0.045 (1.14)
COMPLIANT TO JEDEC STANDARDS MS-001
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.
Figure 33. 8-Lead Plastic Dual In-Line Package [PDIP]
Narrow Body (N-8)
Dimensions shown in inches and (millimeters)
ORDERING GUIDE
Model
ADM485AN
ADM485ANZ1
Temperature Range
Package Description
8-Lead PDIP
8-Lead PDIP
Package Option
N-8
N-8
R-8
R-8
Branding
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
0°C to 70°C
ADM485AR
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead PDIP
ADM485AR-REEL
ADM485ARZ1
ADM485ARZ-REEL1
R-8
R-8
ADM485ARM
RM-8
RM-8
RM-8
RM-8
RM-8
RM-8
N-8
M41
M41
M41
M41#
M41#
M41#
ADM485ARM-REEL
ADM485ARM-REEL7
ADM485ARMZ1
ADM485ARMZ-REEL1
ADM485ARMZ-REEL71
ADM485JN
ADM485JNZ1
0°C to 70°C
8-Lead PDIP
N-8
ADM485JR
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
R-8
R-8
R-8
R-8
R-8
R-8
ADM485JR-REEL
ADM485JR-REEL7
ADM485JRZ1
ADM485JRZ-REEL1
ADM485JRZ-REEL71
1 Z = RoHS Compliant Part, # denotes RoHS compliant product may be top or bottom marked.
Rev. F | Page 14 of 16
ADM485
NOTES
Rev. F | Page 15 of 16
ADM485
NOTES
©1993–2008 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D00078-0-4/08(F)
Rev. F | Page 16 of 16
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