ADM6825YYRJZ-RL7_技术文档

Low Voltage Supervisory Circuits with

Watchdog and Manual Reset in 5-Lead SOT-23

Data Sheet

ADM6823/ADM6824/ADM6825

FEATURES

FUNCTIONAL BLOCK DIAGRAM

Precision low voltage monitoring

9 reset threshold options: 1.58 V to 4.63 V

140 ms (minimum) reset timeout

Watchdog timer with 1.6 sec timeout

Manual reset input

ADM6823

V

CC

V

CC

RESET

GENERATOR

RESET

V

REF

Reset output stages

Push-pull active-low

DEBOUNCE

MR

WATCHDOG

DETECTOR

Open-drain active-low

Push-pull active-high

Low power consumption: 7 µA

Guaranteed reset output valid to V_CC= 1 V

Power supply glitch immunity

Specified from −40°C to +125°C

5-lead SOT-23 package

GND

WDI

Figure 1.

APPLICATIONS

Microprocessor systems

Computers

Controllers

Intelligent instruments

Portable equipment

GENERAL DESCRIPTION

The ADM6823/ADM6824/ADM6825 are supervisory circuits

that monitor power supply voltage levels and code execution

integrity in microprocessor-based systems. As well as providing

power-on reset signals, an on-chip watchdog timer can reset

the microprocessor if it fails to strobe within a preset timeout

period. A reset signal can also be asserted by means of an

external push-button through a manual reset input. The parts

feature different combinations of watchdog input and manual

reset input and output stage configurations, as shown in Table 1.

The ADM6823/ADM6824/ADM6825 are available in 5-lead

SOT-23 packages and typically consume only 7 µA, making

them suitable for use in low power, portable applications.

Table 1. Selection Table

Output Stage

Watchdog Manual

RESET

Part No.

Timer

Reset

RESET

ADM6823 Yes

ADM6824 Yes

ADM6825

Yes

Push-Pull

Yes

Each part is available in nine reset threshold options, ranging

from 1.58 V to 4.63 V. The reset and watchdog timeout periods

are fixed at 140 ms (minimum) and 1.6 sec (typical),

respectively.

Rev. B

Document Feedback

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rightsof third parties that may result fromits use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks andregisteredtrademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Technical Support

www.analog.com

ADM6823/ADM6824/ADM6825

Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Reset Output ..................................................................................9

Manual Reset Input.......................................................................9

Watchdog Input .............................................................................9

Application Information................................................................ 10

Watchdog Input Current ........................................................... 10

Negative-Going V_CCTransients ................................................ 10

Ensuring Reset Valid to V_CC= 0 V........................................... 10

Watchdog Software Considerations......................................... 10

Outline Dimensions....................................................................... 11

Ordering Guide .......................................................................... 12

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Absolute Maximum Ratings............................................................ 5

ESD Caution.................................................................................. 5

Pin Configuration and Function Descriptions............................. 6

Typical Performance Characteristics ............................................. 7

Theory of Operation ........................................................................ 9

REVISION HISTORY

2/13—Rev. A to Rev. B

Updated Outline Dimensions ...................................................... 11

Changes to Ordering Guide .......................................................... 12

Deleted Automotive Products Section......................................... 12

9/12—Rev. 0 to Rev. A

Removed ADM6821/ADM6822 (Throughout) ........................... 1

Updated Outline Dimensions....................................................... 11

Changes to Ordering Guide .......................................................... 11

Added Automotive Products Section........................................... 11

6/05—Revision 0: Initial Version

Rev. B | Page 2 of 12

Data Sheet

ADM6823/ADM6824/ADM6825

SPECIFICATIONS

V_CC= 4.5 V to 5.5 V for ADM682xL/ADM682xM; V_CC= 2.7 V to 3.6 V for ADM682xT/ADM682xS/ADM682xR; V_CC= 2.1 V to 2.75 V

for ADM682xZ/ADM682xY; V_CC= 1.53 V to 2.0 V for ADM682xW/ADM682xV; T_A= –40°C to +125°C, unless otherwise noted.

Table 2.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

SUPPLY

V_CCOperating Voltage Range

Supply Current

1

5.5

20

16

V

µA

10

7

WDI and MR unconnected, V_CC= 5.5 V

WDI and MR unconnected, V_CC= 3.6 V

RESET THRESHOLD VOLTAGE

ADM682xL

ADM682xM

ADM682xT

ADM682xS

ADM682xR

ADM682xZ

ADM682xY

ADM682xW

4.50

4.25

3.00

2.85

2.55

2.25

2.12

1.62

1.52

4.63

4.38

3.08

2.93

2.63

2.32

2.19

1.67

1.58

60

4.75

4.50

3.15

3.00

2.70

2.38

2.25

1.71

1.62

V

ADM682xV

V

RESET THRESHOLD TEMPERATURE COEFFICIENT

RESET THRESHOLD HYSTERESIS

V_CCTO RESET DELAY

ppm/°C

mV

2 × V_TH

20

µs

V_TH− V_CC= 100 mV

RESET TIMEOUT PERIOD

RESET OUTPUT VOLTAGE

V_OL(Push-Pull or Open-Drain)

140

200

280

ms

0.3

0.4

V

V_CC≥ 1 V, I_SINK= 50 µA

V_CC≥ 1.2 V, I_SINK= 100 µA

V_CC≥ 2.55 V, I_SINK= 1.2 mA

V_CC≥ 4.25 V, I_SINK= 3.2 mA

V_CC≥ 1.8 V, I_SOURCE= 200 µA

V_CC≥ 3.15 V, I_SOURCE= 500 µA

V_CC≥ 4.75 V, I_SOURCE= 800 µA

V_OH(Push-Pull Only)

0.8 × V_CC

RESET OUTPUT LEAKAGE CURRENT (OPEN-

DRAIN ONLY)

1

µA

RESET not asserted

RESET OUTPUT VOLTAGE (PUSH-PULL ONLY)

V_OH

0.8 × V_CC

V

V_CC≥ 1 V, I_SOURCE= 1 µA

V_CC≥ 1.5 V, I_SOURCE= 100 µA

V_CC≥ 2.55 V, I_SOURCE= 500 µA

V_CC≥ 4.25 V, I_SOURCE= 800 µA

V_CC≥ 1.8 V, I_SINK= 500 µA

V_CC≥ 3.15 V, I_SINK= 1.2 mA

V_CC≥ 4.75 V, I_SINK= 3.2 mA

V_OL

0.3

0.4

MANUAL RESET INPUT (ADM6823/ADM6825)

MR Input Threshold

V_IL

0.3 × V_CC

V

V_IH

0.7 × V_CC

1

V

MR Input Pulse Width

MR Glitch Rejection

MR to Reset Delay

MR Pull-Up Resistance

µs

ns

kΩ

100

200

50

25

75

Rev. B | Page 3 of 12

ADM6823/ADM6824/ADM6825

Data Sheet

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

WATCHDOG INPUT (ADM6823/ADM6824)

Watchdog Timeout Period

WDI Pulse Width

WDI Input Threshold

V_IL

1.12

50

1.6

2.40

sec

ns

0.3 × V_CC

160

V

µA

V_IH

0.7 × V_CC

WDI Input Current

120

V_WDI= V_CC

V_WDI= 0

−20

−15

Rev. B | Page 4 of 12

Data Sheet

ADM6823/ADM6824/ADM6825

ABSOLUTE MAXIMUM RATINGS

T_A= 25°C, unless otherwise noted.

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

Table 3.

Parameter

Rating

V_CC

−0.3 V to +6 V

20 mA

Output Current (RESET, RESET)

Operating Temperature Range

−40°C to +125°C

−65°C to +150°C

170°C/W

Storage Temperature Range

θ_JAThermal Impedance

Soldering Temperature

Sn/Pb

ESD CAUTION

240°C, 30 sec

260°C, 40 sec

RoHS Compliant

Rev. B | Page 5 of 12

ADM6823/ADM6824/ADM6825

Data Sheet

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

RESET

GND

MR

1

2

3

5

V

CC

RESET

GND

1

2

3

5

4

V

CC

ADM6823

TOP VIEW

(Not to Scale)

ADM6824

TOP VIEW

(Not to Scale)

4

WDI

RESET

WDI

Figure 2. ADM6823 Pin Configuration

Figure 3. ADM6824 Pin Configuration

RESET

GND

1

2

3

5

4

V

CC

ADM6825

TOP VIEW

(Not to Scale)

RESET

MR

Figure 4. ADM6825 Pin Configuration

Table 4. Pin Function Descriptions

Pin No

ADM6823 ADM6824 ADM6825 Mnemonic Description

1

RESET

Active-Low Reset Output. Asserted whenever V_CCis below the reset threshold, V_TH.

Push-Pull Output Stage for the ADM6823/ADM6824/ADM6825.

Ground.

Manual Reset Input. This is an active-low input, which, when forced low for at least

1 µs, generates a reset. It features a 50 kΩ internal pull-up.

2

3

2

GND

MR

3

4

3

RESET

WDI

Active-High Push-Pull Reset Output.

4

5

Watchdog Input. Generates a reset if the voltage on the pin remains low or high for

the duration of the watchdog timeout. The timer is cleared if a logic transition occurs

on this pin or if a reset is generated.

4

5

MR

V_CC

Manual Reset Input.

5

Power Supply Voltage Being Monitored.

Rev. B | Page 6 of 12

Data Sheet

ADM6823/ADM6824/ADM6825

TYPICAL PERFORMANCE CHARACTERISTICS

10.0

9.5

1.20

1.15

1.10

1.05

1.00

0.95

0.90

9.0

8.5

8.0

7.5

7.0

6.5

6.0

5.5

5.0

4.5

4.0

3.5

V

= 5V

CC

V

= 3.3V

CC

V

= 1.5V

CC

–40

–20

0

20

40

60

80

100

120

–40

–20

0

20

40

60

80

100

120

TEMPERATURE (°C)

Figure 5. Supply Current vs. Temperature

Figure 8. Normalized Watchdog Timeout Period vs. Temperature

1.20

1.15

1.10

1.05

1.00

0.95

0.90

0.85

0.80

1.05

1.04

1.03

1.02

1.01

1.00

0.99

0.98

0.97

0.96

0.95

–40

–20

0

20

40

60

80

100

120

–40

–20

0

20

40

60

80

100

120

TEMPERATURE (°C)

Figure 6. Normalized RESET Timeout Period vs. Temperature

Figure 9. Normalized RESET Threshold vs. Temperature

160

140

120

100

80

100

90

80

70

60

50

40

30

20

10

0

60

40

V

= 4.63V

CC

V

= 2.93V

20

CC

0

10

100

RESET THRESHOLD OVERDRIVE (mV)

1000

–40

–20

0

20

40

60

80

100

120

TEMPERATURE (°C)

Figure 7. V_CCto RESET Output Delay vs. Temperature

Figure 10. Maximum V_CCTransient Duration vs. RESET Threshold Overdrive

Rev. B | Page 7 of 12

ADM6823/ADM6824/ADM6825

Data Sheet

0.20

2.92

2.90

2.88

2.86

2.84

2.82

V

= 2.9V

V

= 2.9V

CC

0.15

0.10

0.05

0

1

2

3

4

5

6

7

0

0.2

0.4

0.6

(mA)

0.8

1.0

I

(mA)

I

SOURCE

SINK

Figure 11. Voltage Output Low vs. I_SINK

Figure 12. Voltage Output High vs. I_SOURCE

Rev. B | Page 8 of 12

Data Sheet

ADM6823/ADM6824/ADM6825

THEORY OF OPERATION

The ADM6823/ADM6824/ADM6825 provide microprocessor

supply voltage supervision by controlling the microprocessor’s

reset input. Code execution errors are avoided during power-

up, power-down, and brownout conditions by asserting a reset

signal when the supply voltage is below a preset threshold. In

addition, the ADM6823/ADM6824/ADM6825 allow supply

voltage stabilization with a fixed timeout before the reset

deasserts after the supply voltage rises above the threshold.

MANUAL RESET INPUT

MR

),

The ADM6823/ADM6825 feature a manual reset input (

MR

which, when driven low, asserts the reset output. When

transitions from low to high, reset remains asserted for the

duration of the reset active timeout period before deasserting.

MR

The

is always high when unconnected. An external push-button

MR

input has a 50 kΩ internal pull-up so that the input

switch can be connected between

and ground so that the

Problems with microprocessor code execution can be moni-

tored and corrected with a watchdog timer (ADM6823/

ADM6824). When watchdog strobe instructions are included

in microprocessor code, a watchdog timer detects if the micro-

processor code breaks down or becomes stuck in an infinite

loop. If this happens, the watchdog timer asserts a reset pulse,

which restarts the microprocessor in a known state.

user can generate a reset. Debounce circuitry is integrated

on-chip for this purpose. Noise immunity is provided on the

MR

input, and fast, negative-going transients of up to 100 ns

MR

(typical) are ignored. A 0.1 μF capacitor between

ground provides additional noise immunity.

and

WATCHDOG INPUT

The ADM6823/ADM6824 feature a watchdog timer, which

monitors microprocessor activity. A timer circuit is cleared

with every low-to-high or high-to-low logic transition on the

watchdog input pin (WDI), which detects pulses as short as

50 ns. If the timer counts through the preset watchdog timeout

period (t_WD), reset is asserted. The microprocessor is required

to toggle the WDI pin to avoid being reset. Failure of the

microprocessor to toggle WDI within the timeout period

therefore indicates a code execution error, and the reset pulse

generated restarts the microprocessor in a known state.

If the user detects a problem with the system’s operation, a

manual reset input is available (ADM6823/ADM6825) to reset

the microprocessor by means of an external push-button, for

example.

RESET OUTPUT

The ADM6823 features an active-low push-pull output. The

ADM6824/ADM6825 feature dual active-low and active-high

push-pull reset outputs. For active-low and active-high outputs,

the reset signal is guaranteed to be logic low and logic high,

respectively, for V_CCdown to 1 V.

In addition to logic transitions on WDI, the watchdog timer is

also cleared by a reset assertion due to an undervoltage condi-

The reset output is asserted when V_CCis below the reset

MR

threshold (V_TH), when

is driven low, or when WDI is

MR

tion on V_CCor

being pulled low. When reset is asserted, the

not serviced within the watchdog timeout period (t_WD). Reset

remains asserted for the duration of the reset active timeout

watchdog timer is cleared and does not begin counting again

until reset deassserts. The watchdog timer can be disabled by

leaving WDI floating or by three-stating the WDI driver.

MR

period (t_RP) after V_CCrises above the reset threshold, after

transitions from low to high, or after the watchdog timer times

out. Figure 13 shows the reset outputs.

V

CC

V

TH

V

CC

1V

0V

V

CC

V

TH

CC

TH

V

CC

RESET

WDI

t_RP

t_WD

t_RD

1V

0V

V

CC

V

CC

RESET

t_RP

t_RD

0V

V

Figure 14. Watchdog Timing Diagram

CC

t_RP

1V

0V

t_RD

Figure 13. Reset Timing Diagram

Rev. B | Page 9 of 12

ADM6823/ADM6824/ADM6825

Data Sheet

APPLICATION INFORMATION

WATCHDOG INPUT CURRENT

WATCHDOG SOFTWARE CONSIDERATIONS

To minimize watchdog input current (and minimize overall

power consumption), leave WDI low for the majority of the

watchdog timeout period. When driven high, WDI can draw

as much as 160 µA. Pulsing WDI low-high-low at a low duty

cycle reduces the effect of the large input current. When WDI

is unconnected, a window comparator disconnects the watch-

dog timer from the reset output circuitry so that reset is not

asserted when the watchdog timer times out.

In implementing the microprocessor’s watchdog strobe

code, quickly switching WDI low-high and then high-low

(minimizing WDI high time) is desirable for current

consumption reasons. However, a more effective way of

using the watchdog function can be considered.

A low-high-low WDI pulse within a given subroutine prevents

the watchdog from timing out. However, if the subroutine

becomes stuck in an infinite loop, the watchdog could not

detect this because the subroutine continues to toggle WDI. A

more effective coding scheme for detecting this error involves

using a slightly longer watchdog timeout. In the program that

calls the subroutine, WDI is set high. The subroutine sets WDI

low when it is called. If the program executes without error,

WDI is toggled high and low with every loop of the program.

If the subroutine enters an infinite loop, WDI is kept low, the

watchdog times out, and the microprocessor is reset.

NEGATIVE-GOING V_CCTRANSIENTS

To avoid unnecessary resets caused by fast power supply

transients, the ADM6823/ADM6824/ADM6825 are equipped

with glitch rejection circuitry. The typical performance

characteristic in Figure 10 plots V_CCtransient duration vs.

the transient magnitude. The curves show combinations of

transient magnitude and duration for which a reset is not

generated for the 4.63 V and 2.93 V reset threshold parts.

For example, with the 2.93 V threshold, a transient that goes

100 mV below the threshold and lasts 8 µs typically does not

cause a reset, but if the transient is any bigger in magnitude

or duration, a reset is generated. An optional 0.1 µF bypass

capacitor mounted close to V_CCprovides additional glitch

rejection.

START

SET WDI

HIGH

RESET

PROGRAM

CODE

ENSURING RESET VALID TO V_CC= 0 V

INFINITE LOOP:

WATCHDOG

TIMES OUT

Both active-low and active-high reset outputs are guaranteed

to be valid for V_CCas low as 1 V. However, by using an external

resistor with push-pull configured reset outputs, valid outputs

for V_CCas low as 0 V are possible. For an active-low reset

SUBROUTINE

SET WDI

LOW

RESET

output, a resistor connected between

and ground pulls

the output low when it is unable to sink current. For the active-

high case, a resistor connected between RESET and V_CCpulls

the output high when it is unable to source current. A large

resistance such as 100 kΩ should be used so that it does not

overload the reset output when V_CCis above 1 V.

RETURN

Figure 16. Watchdog Flow Diagram

V

CC

V

CC

V

CC

RESET

100kΩ

ADM6823

MICROPROCESSOR

I/O

ADM6823/

ADM6824/

ADM6825

MR

WDI

ADM6824/

ADM6825

RESET

100kΩ

Figure 17. Typical Application Circuit

GND

Figure 15. Ensuring Reset Valid to V_CC= 0 V

Rev. B | Page 10 of 12

Data Sheet

ADM6823/ADM6824/ADM6825

OUTLINE DIMENSIONS

3.00

2.90

2.80

5

1

4

3

3.00

2.80

2.60

1.70

1.60

1.50

2

0.95 BSC

1.90

BSC

1.30

1.15

0.90

0.20 MAX

0.08 MIN

1.45 MAX

0.95 MIN

0.55

0.45

0.15 MAX

0.05 MIN

10°

5°

0°

SEATING

PLANE

0.60

0.50 MAX

0.35 MIN

0.35

BSC

COMPLIANT TO JEDEC STANDARDS MO-178-AA

Figure 18. 5-Lead Small Outline Transistor Package [SOT-23]

(RJ-5)

Dimensions shown in millimeters

ADM682 x x YRJZ -RL7

GENERIC NUMBER

ORDERING QUANTITY

RL7: 3,000 PIECE REEL

(3 TO 5)

RESET

Z: LEAD-FREE

THRESHOLD

NUMBER

L: 4.63V

M: 4.38V

T: 3.08V

TEMPERATURE RANGE

Y: –40°C TO +125°C

PACKAGE CODE

RJ: 5-LEAD SOT-23

S: 2.93V

R: 2.63V

Z: 2.32V

Y: 2.19V

W: 1.67V

V: 1.58V

Figure 19. Ordering Code Structure

Rev. B | Page 11 of 12

ADM6823/ADM6824/ADM6825

Data Sheet

ORDERING GUIDE

Reset

Threshold (V)

Reset

Temperature

Package

Description

Package

Model^{1, 2}

Timeout (ms) Range

Quantity

Option

RJ-5

Branding

N0Q

N0C

ADM6823RYRJZ-RL7

ADM6823SYRJ-R7

ADM6823SYRJZ-RL7

ADM6823TYRJ-R7

ADM6823TYRJZ-RL7

ADM6823VYRJZ-RL7

ADM6823WYRJZ-RL7

ADM6823ZYRJZ-RL7

ADM6824TYRJZ-R7

ADM6825TYRJZ-R7

2.63

2.93

3.08

1.58

1.67

2.32

3.08

140

3k

5-Lead SOT-23

−40°C to +125°C

N0Q

N0C

N0Q

N0D

RJ-5

N0E

¹Z = RoHS Compliant Part.

²If ordering nonstandard models, complete the ordering code shown in Figure 19 by inserting the part number and reset threshold suffixes. Contact Sales for

availability of nonstandard models.

registered trademarks are the property of their respective owners.

D04535-0-2/13(B)

Rev. B | Page 12 of 12


型号：	ADM6825YYRJZ-RL7
厂家：	ADI
描述：	1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO5, LEAD FREE, SOT-23, 5 PIN 输入元件光电二极管
文件：	总12页 (文件大小：223K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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