ADM706RARZ-REEL7 [ADI]
3 V, Voltage Monitoring Microprocessor Supervisory Circuit;
| 型号： | ADM706RARZ-REEL7 |
| 厂家： | 
ADI |
| 描述： | 3 V, Voltage Monitoring Microprocessor Supervisory Circuit 监控 输入元件 光电二极管 |
| 文件： | 总16页 (文件大小：404K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
3 V, Voltage Monitoring
Microprocessor Supervisory Circuits
Data Sheet ADM706P/ADM706R/ADM706S/ADM706T, ADM708R/ADM708S/ADM708T
FEATURES
FUNCTIONAL BLOCK DIAGRAMS
Precision supply voltage monitor
2.63 V (ADM706P, ADM706R, ADM708R)
2.93 V (ADM706S, ADM708S)
3.08 V (ADM706T, ADM708T)
100 µA quiescent current
WATCHDOG
WATCHDOG
WATCHDOG
INPUT (WDI)
TRANSITION
DETECTOR
WATCHDOG
OUTPUT (WDO)
TIMER
V
RESET AND
WATCHDOG
TIMEBASE
CC
70μA
200 ms reset pulse width
MR
MR
Debounced manual reset input (
Independent watchdog timer
)
RESET,
(P = RESET)
RESET
GENERATOR
V
CC
1.6 sec timeout (ADM706P, ADM706R, ADM706S,
ADM706T)
Reset output
V
*
REF
ADM706P/ADM706R/
ADM706S/ADM706T
POWER-FAIL
INPUT (PFI)
POWER-FAIL
OUTPUT (PFO)
1.25V
Active high (ADM706P)
*
VOLTAGE REFERENCE = 2.63V (P/R), 2.93V (S), 3.08V (T)
Active low (ADM706R, ADM706S, ADM706T)
Both active high and active low (ADM708R, ADM708S,
ADM708T)
Figure 1. ADM706P/ADM706R/ADM706S/ADM706T
V
CC
Voltage monitor for power fail or low battery warning
70μA
RESET
RESET
RESET
Guaranteed
valid with VCC = 1 V
MR
RESET
GENERATOR
Superior upgrade for MAX706P/R/S/T, MAX708R/S/T
V
CC
APPLICATIONS
V
*
REF
ADM708R/ADM708S/
ADM708T
POWER-FAIL
INPUT (PFI)
Microprocessor systems
Computers
POWER-FAIL
OUTPUT (PFO)
1.25V
Controllers
* VOLTAGE REFERENCE = 2.63V (R), 2.93V (S), 3.08V (T)
Intelligent instruments
Critical microprocessor monitoring
Battery operated systems
Portable instruments
Figure 2. ADM708R/ADM708S/ADM708T
GENERAL DESCRIPTION
The ADM706P/ADM706R/ADM706S/ADM706T and the
ADM708R/ADM708S/ADM708T microprocessor supervisory
circuits are suitable for monitoring either 3 V or 3.3 V power
supplies.
The ADM706R, ADM706S, and ADM706T are identical except
for the reset threshold monitor levels, which are 2.63 V, 2.93 V, and
3.08 V, respectively. The ADM706P is identical to the ADM706R
in that the reset threshold is 2.63 V. It differs only in that it has
an active high reset output.
The ADM706P/ADM706R/ADM706S/ADM706T provide
power supply monitoring circuitry that generate a reset output
during power-up, power-down, and brownout conditions. The
reset output remains operational with VCC as low as 1 V.
Independent watchdog monitoring circuitry is also provided. This
activates if the watchdog input does not toggle within 1.6 sec.
The ADM708R/ADM708S/ADM708T provide similar functio-
nality as the ADM706R/ADM706S/ADM706T and only differ
in that a watchdog timer function is not available. Instead, an
active high reset output (RESET) is provided in addition to the
RESET
active low (
) output.
In addition, there is a 1.25 V threshold detector for a power fail
warning, low battery detection, or to monitor an additional
All devices are available in narrow 8-lead PDIP and 8-lead
SOIC packages.
MR
power supply. An active low debounced
included.
input is also
Rev. E
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Technical Support
www.analog.com
ADM706P/ADM706R/ADM706S/ADM706T, ADM708R/ADM708S/ADM708T Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagrams............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 5
ESD Caution.................................................................................. 5
Pin Configurations and Function Descriptions ........................... 6
Typical Performance Characteristics ............................................. 8
Circuit Information........................................................................ 10
Power Fail Reset.......................................................................... 10
Manual Reset............................................................................... 10
Watchdog Timer (ADM706P/ADM706R/
ADM706S/ADM706T).............................................................. 10
Power Fail Comparator.............................................................. 11
Adding Hysteresis to the Power Fail Comparator ................. 11
RESET
Valid
Below 1 V VCC ..................................................... 11
Applications Information.............................................................. 12
Monitoring Additional Supply Levels...................................... 12
RESET
Microprocessors with Bidirectional
........................... 12
Outline Dimensions....................................................................... 13
Ordering Guide .......................................................................... 14
REVISION HISTORY
1/16—Rev. D to Rev. E
5/08—Rev. B to Rev. C
Changes to Table 3............................................................................ 6
Changes to Table 4............................................................................ 7
Changes to Power Fail Comparator Section, Figure 17,
and Figure 18................................................................................... 10
Changes to Figure 20 and Figure 22............................................. 12
Changes to Ordering Guide .......................................................... 14
Changes to Applications Section.....................................................1
Changes to Table 2.............................................................................5
Changes to Table 3.............................................................................6
Changes to Figure 8...........................................................................7
Changes to Figure 16.........................................................................9
2/07—Rev. A to Rev. B
10/14—Rev. C to Rev. D
Updated Format..................................................................Universal
Changes to Table 1.............................................................................3
Updated Outline Dimensions....................................................... 12
Changes to Ordering Guide.......................................................... 13
Changes to Pin 4 Description; Table 3........................................... 6
Changes to Pin 4 Description; Table 4........................................... 7
Changes to Ordering Guide .......................................................... 14
Rev. E | Page 2 of 16
Data Sheet
ADM706P/ADM706R/ADM706S/ADM706T, ADM708R/ADM708S/ADM708T
SPECIFICATIONS
VCC = 2.70 V to 5.5 V (ADM706P/ADM706R/ADM708R), VCC = 3.00 V to 5.5 V (ADM70xS), VCC = 3.15 V to 5.5 V (ADM70xT), TA =
MIN to TMAX unless otherwise noted.
T
Table 1.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
POWER SUPPLY
VCC Operating Voltage Range
Supply Current
1.0
5.5
200
350
V
μA
μA
100
150
VCC < 3.6 V
VCC < 5.5 V
LOGIC OUTPUT
Reset Threshold (VRST
)
2.55
2.85
3.00
2.63
2.93
3.08
20
2.70
3.00
3.15
V
V
V
mV
ms
ms
ADM706P/ADM706R/ADM708R
ADM706S/ADM708S
ADM706T/ADM708T
Reset Threshold Hysteresis
RESET PULSE WIDTH
160
160
200
200
280
280
ADM706P/ADM706R/ADM708R, VCC = 3 V
ADM706S/ADM708S/ADM706T/ADM708T,
V
CC = 3.3 V
200
ms
VCC = 5.0 V
RESET OUTPUT VOLTAGE (ADM706R/ADM708R/
ADM706S/ADM708S/ADM706T/ADM708T)
VOH
VOL
VOH
VOL
VOL
0.8 × VCC
V
V
V
V
V
VRST (max) < VCC < 3.6 V, ISOURCE = 500 μA
VRST (max) < VCC < 3.6 V, ISINK = 1.2 mA
4.5 V < VCC < 5.5 V, ISOURCE = 800 μA
4.5 V < VCC < 5.5 V, ISINK = 3.2 mA
VCC = 1 V, ISINK = 100 μA
0.3
VCC − 1.5 V
0.4
0.3
RESET OUTPUT VOLTAGE (ADM706P)
VOH
VOL
VOH
VOL
VCC − 0.6 V
VCC − 1.5 V
V
V
V
V
VRST (max) < VCC < 3.6 V, ISOURCE = 215 μA
VRST (max) < VCC < 3.6 V, ISINK = 1.2 mA
4.5 V < VCC < 5.5 V, ISOURCE = 800 μA
4.5 V < VCC < 5.5 V, ISINK = 3.2 mA
0.3
0.4
RESET OUTPUT VOLTAGE
(ADM708R/ADM708S/ADM708T)
VOH
VOL
VOH
VOL
0.8 × VCC
V
V
V
V
VRST (max) < VCC < 3.6 V, ISOURCE = 500 μA
VRST (max) < VCC < 3.6 V, ISINK = 500 μA
4.5 V < VCC < 5.5 V, ISOURCE = 800 μA
4.5 V < VCC < 5.5 V, ISINK = 1.2 mA
0.3
0.4
VCC − 1.5 V
WATCHDOG INPUT (ADM706P/ADM706R/
ADM706S/ADM706T)
Watchdog Timeout Period
1.00
1.60
2.25
sec
ADM706P/ADM706R: VCC = 3 V;
ADM706S/ADM706T: VCC = 3.3 V;
VIL = 0.4 V, VIH = VCC × 0.8 V
WDI Pulse Width
100
50
ns
ns
VRST (max) < VCC < 3.6 V
4.5 V < VCC < 5.5 V
WDI Input Threshold
VIL
VIH
VIL
0.6
V
V
V
VRST (max) < VCC < 3.6 V
VRST (max) < VCC < 3.6 V
VCC = 5.0 V
0.7 × VCC
0.8
VIH
3.5
V
VCC = 5.0 V
WDI Input Current
−1.0
+0.02
+1.0
μA
WDI = 0 V or VCC
Rev. E | Page 3 of 16
ADM706P/ADM706R/ADM706S/ADM706T, ADM708R/ADM708S/ADM708T
Data Sheet
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
WDO OUTPUT VOLTAGE
VOH
0.8 × VCC
VCC − 1.5 V
V
V
V
V
VRST (max) < VCC < 3.6 V, ISOURCE = 500 μA
4.5 V < VCC < 5.5 V, ISOURCE = 800 μA
VRST (max) < VCC < 3.6 V, ISINK = 500 μA
4.5 V < VCC < 5.5 V, ISINK = 1.2 mA
VOL
0.3
0.4
MANUAL RESET INPUT
MR Pull-Up Current (MR = 0 V)
25
70
250
600
μA
μA
ns
VRST (max) < VCC < 3.6 V
4.5 V < VCC < 5.5 V
VRST (max) < VCC < 3.6 V
4.5 V < VCC < 5.5 V
100
500
150
250
MR Pulse Width
ns
MR INPUT THRESHOLD
VIL
VIH
VIL
VIH
0.6
0.8
V
V
V
V
VRST (max) < VCC < 3.6 V
VRST (max) < VCC < 3.6 V
4.5 V < VCC < 5.5 V
0.7 × VCC
2.0
4.5 V < VCC < 5.5 V
MR TO RESET OUTPUT DELAY
750
250
ns
ns
VRST (max) < VCC < 3.6 V
4.5 V < VCC < 5.5 V
POWER FAIL INPUT
PFI Input Threshold
1.2
1.25
1.3
V
ADM706P/ADM706R/ADM708R, VCC = 3 V
ADM706S/ADM708S/ADM706T/ADM708T,
VCC = 3.3 V, PFI falling
PFI Input Current
−25
+0.01
+25
nA
PFO OUTPUT VOLTAGE
VOH
VOL
VOH
VOL
0.8 × VCC
V
V
V
V
VRST (max) < VCC < 3.6 V, ISOURCE = 500 μA
VRST (max) < VCC < 3.6 V, ISINK = 1.2 mA
4.5 V < VCC < 5.5 V, ISOURCE = 800 μA
4.5 V < VCC < 5.5 V, ISINK = 3.2 mA
0.3
0.4
VCC − 1.5 V
Rev. E | Page 4 of 16
Data Sheet
ADM706P/ADM706R/ADM706S/ADM706T, ADM708R/ADM708S/ADM708T
ABSOLUTE MAXIMUM RATINGS
TA = 25°C unless otherwise noted.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Table 2.
Parameter
Rating
VCC
−0.3 V to +6 V
All Other Inputs
−0.3 V to VCC + 0.3 V
Input Current
VCC
20 mA
ESD CAUTION
GND
20 mA
20 mA
727 mW
135°C/W
470 mW
110°C/W
Digital Output Current
Power Dissipation, N-8 (PDIP)
θJA Thermal Impedance
Power Dissipation, R-8 (SOIC)
θJA Thermal Impedance
Operating Temperature Range
Industrial (Version A)
Lead Temperature (Soldering, 10 sec)
Vapor Phase (60 sec)
Infrared (15 sec)
−40°C to +85°C
300°C
215°C
220°C
Storage Temperature Range
ESD Rating
−65°C to +150°C
>4.5 kV
Rev. E | Page 5 of 16
ADM706P/ADM706R/ADM706S/ADM706T, ADM708R/ADM708S/ADM708T
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Data Sheet
MR
1
2
3
4
8
7
6
5
WDO
RESET
WDI
MR
1
2
3
4
8
7
6
5
WDO
ADM706R/
ADM706S/
ADM706T
TOP VIEW
V
ADM706P
V
RESET
CC
CC
GND
GND
WDI
PFO
TOP VIEW
(Not to Scale)
PFI
PFI
PFO
(Not to Scale)
Figure 3. ADM706P
Figure 4. ADM706R/ADM706S/ADM706T
Table 3. Pin Function Descriptions ADM706P/ADM706R/ADM706S/ADM706T
Pin No.
Mnemonic Description
1
MR
Manual Reset Input. When taken below 0.6 V, a RESET/RESET is generated. MR can be driven
from TTL, CMOS logic, or from a manual reset switch because it is internally debounced. An
internal 70 μA pull-up current holds the input high when floating.
2
3
4
VCC
GND
PFI
Power Supply Input. Place a 0.1 µF decoupling capacitor between the VCC and GND pins.
Ground. Ground reference for all signals (0 V).
Power Fail Input. PFI is the noninverting input to the power fail comparator. When PFI is less
than 1.25 V, PFO goes low. If unused, PFI connects to GND.
5
6
PFO
WDI
Power Fail Output. PFO is the output from the power fail comparator. It goes low when PFI is
less than 1.25 V.
Watchdog Input. If WDI remains either high or low for longer than the watchdog timeout period, the
watchdog output, WDO, goes low. The timer resets with each transition at the WDI input. Either
a high to low or a low to high transition clears the counter. The internal timer is also cleared
whenever reset is asserted.
7 (ADM706R/ADM706S/
ADM706T Only)
RESET
Logic Output. RESET goes low for 200 ms when triggered. It is triggered either by VCC being
below the reset threshold or by a low signal on the MR input. RESET remains low whenever VCC
is below the reset threshold. It remains low for 200 ms after VCC goes above the reset threshold
or MR goes from low to high. A watchdog timeout does not trigger RESET unless WDO is
connected to MR.
7 (ADM706P Only)
8
RESET
WDO
Logic Output. RESET is an active high output suitable for systems that use active high reset logic. It is
the inverse of RESET.
Watchdog Output. WDO goes low if the internal watchdog timer times out as a result of inactivity on
the WDI input. It remains low until the watchdog timer is cleared. WDO also goes low during
low line conditions. Whenever VCC is below the reset threshold, WDO remains low. As soon as VCC
goes above the reset threshold, WDO goes high immediately.
Rev. E | Page 6 of 16
Data Sheet
ADM706P/ADM706R/ADM706S/ADM706T, ADM708R/ADM708S/ADM708T
MR
1
2
3
4
8
7
6
5
RESET
RESET
NC
ADM708R/
ADM708S/
ADM708T
TOP VIEW
V
CC
GND
PFI
PFO
(Not to Scale)
NC = NO CONNECT
Figure 5. ADM708R/ADM708S/ADM708T
Table 4. Pin Function Descriptions ADM708R/ADM708S/ADM708T
Pin No.
Mnemonic Description
1
MR
Manual Reset Input. When taken below 0.6 V, a RESET/RESET is generated. MR can be driven from TTL, CMOS
logic, or from a manual reset switch because it is internally debounced. An internal 70 μA pull-up current holds
the input high when floating.
2
3
4
VCC
GND
PFI
Power Supply Input. Place a 0.1 µF decoupling capacitor between the VCC and GND pins.
Ground. Ground reference for all signals (0 V).
Power Fail Input. PFI is the noninverting input to the power fail comparator. When PFI is less than 1.25 V, PFO
goes low. If unused, PFI must connect to GND.
5
6
7
PFO
NC
RESET
Power Fail Output. PFO is the output from the power fail comparator. It goes low when PFI is less than 1.25 V.
No Connect.
Logic Output. RESET goes low for 200 ms when triggered. It is triggered either by VCC being below the reset
threshold or by a low signal on the MR input. RESET remains low whenever VCC is below the reset threshold. It
remains low for 200 ms after VCC goes above the reset threshold or MR goes from low to high. A watchdog
timeout does not trigger RESET unless WDO is connected to MR.
8
RESET
Logic Output. RESET is an active high output suitable for systems that use active high reset logic. It is the
inverse of RESET.
Rev. E | Page 7 of 16
ADM706P/ADM706R/ADM706S/ADM706T, ADM708R/ADM708S/ADM708T
TYPICAL PERFORMANCE CHARACTERISTICS
Data Sheet
V
= 3.3V
CC
= 25°C
T
A
1.3V
PFI
V
CC
1.2V
PFO
0V
3V
RESET
400ms/DIV
500ns/DIV
Figure 6. ADM706R/ADM706S/ADM706T and the
Figure 9. PFI Deassertion Response Time
RESET
ADM708R/ADM708S/ADM708T
Output Voltage vs. Supply Voltage
V
= V
RT
CC
= 25°C
T
A
3V
3V
RESET
RESET
V
CC
RESET
0V
0V
100ns/DIV
400ms/DIV
RESET
Figure 10.
, RESET Assertion
Figure 7. RESET Output Voltage vs. Supply Voltage
V
T
= V
RT
V
T
= 3.3V
CC
= 25°C
CC
= 25°C
A
A
1.3V
PFI
3V
0V
3V
0V
1.2V
PFO
0V
RESET
RESET
3V
500ns/DIV
100ns/DIV
Figure 8. PFI Assertion Response Time
RESET
, RESET Deassertion
Figure 11.
Rev. E | Page 8 of 16
Data Sheet
ADM706P/ADM706R/ADM706S/ADM706T, ADM708R/ADM708S/ADM708T
T
= 25°C
A
3V
V
CC
2V
3V
RESET
0V
2µs/DIV
Figure 12. ADM706R/ADM706S/ADM706T and the
RESET
ADM708R/ADM708S/ADM708T
Response Time
Rev. E | Page 9 of 16
ADM706P/ADM706R/ADM706S/ADM706T, ADM708R/ADM708S/ADM708T
CIRCUIT INFORMATION
Data Sheet
MANUAL RESET
WATCHDOG
TRANSITION
DETECTOR
WATCHDOG
INPUT (WDI)
WATCHDOG
TIMER
WATCHDOG
OUTPUT (WDO)
MR
The
input allows other reset sources, such as a manual reset
switch, to generate a processor reset. The input is effectively
MR
V
RESET AND
WATCHDOG
TIMEBASE
CC
debounced by the timeout period (200 ms typical). The
input is TTL-/CMOS-compatible; it can also be driven by any
70μA
MR
logic reset output. If unused, the
left floating.
input can be tied high or
MR
RESET,
(P = RESET)
RESET
GENERATOR
V
CC
V
V
RT
V
V
*
RT
CC
REF
ADM706P/ADM706R/
ADM706S/ADM706T
POWER-FAIL
INPUT (PFI)
tRS
tRS
POWER-FAIL
OUTPUT (PFO)
1.25V
RESET
MR
*
VOLTAGE REFERENCE = 2.63V (P/R), 2.93V (S), 3.08V (T)
Figure 13. ADM706P/ADM706R/ADM706S/ADM706T Functional Block
Diagram
MR EXTERNALLY
DRIVEN LOW
V
CC
WDO
70μA
RESET
RESET
NOTES
RESET = COMPLEMENT OF RESET
MR
RESET
GENERATOR
V
CC
RESET MR
, and
WDO
Timing
Figure 15.
,
V
*
REF
ADM708R/ADM708S/
ADM708T
WATCHDOG TIMER (ADM706P/ADM706R/
ADM706S/ADM706T)
POWER-FAIL
INPUT (PFI)
POWER-FAIL
OUTPUT (PFO)
1.25V
The watchdog timer circuit monitors the activity of the
microprocessor to check that it is not stalled in an indefinite loop.
An output line on the processor is used to toggle the watchdog
input (WDI) line. If this line is not toggled within the timeout
* VOLTAGE REFERENCE = 2.63V (R), 2.93V (S), 3.08V (T)
Figure 14. ADM708R/ADM708S/ADM708T Functional Block Diagram
POWER FAIL RESET
WDO
period (1.6 sec), the watchdog output ( ) is driven low. The
RESET
The reset output provides a reset (RESET or
) output
WDO
output is connected to a nonmaskable interrupt (NMI) on
signal to the microprocessor whenever the VCC input is below
the reset threshold. The actual reset threshold voltage is dependent
on whether a P, R, S, or T suffix device is used. An internal timer
holds the reset output active for 200 ms after the voltage on VCC
rises above the threshold. This is intended as a power-on reset
signal for the microprocessor. It allows time for both the power
supply and the microprocessor to stabilize after power-up. If a
power supply brownout or interruption occurs, the reset line is
similarly activated and remains active for 200 ms after the supply
recovers. If another interruption occurs during an active reset
period, the reset timeout period continues for an additional 200 ms.
the processor. Therefore, if the watchdog timer times out, an
interrupt is generated. The interrupt service routine is used to
rectify the problem.
The watchdog timer is cleared either by a high to low or by a
low to high transition on WDI. Pulses as narrow as 50 ns are
detected. The timer is also cleared by RESET/
active. Therefore, the watchdog timeout period begins after
reset goes inactive.
RESET
going
WDO
When VCC falls below the reset threshold,
is forced low
whether or not the watchdog timer has timed out. Normally,
this generates an interrupt, but it is overridden by RESET/
going active.
The reset output is guaranteed to remain valid with VCC as low
as 1 V. This ensures that the microprocessor is held in a stable
shutdown condition as the power supply starts up.
RESET
tWP
tWD
tWD
tWD
The ADM706P provides an active high RESET signal; the
WDI
RESET
ADM706R/ADM706S/ADM706T provide an active low
signal; and the ADM708R/ADM706S/ADM706T provide both
RESET
WDO
RESET and
.
RESET EXTERNALLY
TRIGGERED BY MR
RESET
tRS
Figure 16. Watchdog Timing
Rev. E | Page 10 of 16
Data Sheet
ADM706P/ADM706R/ADM706S/ADM706T, ADM708R/ADM708S/ADM708T
3.3V
INPUT
POWER
POWER FAIL COMPARATOR
ADM663A
The power fail comparator is an independent comparator that
monitors the input power supply. The inverting input of the
comparator internally connects to a 1.25 V reference voltage.
The noninverting input is available at the PFI input. This input
monitors the input power supply via a resistive divider network.
When the voltage on the PFI input drops below 1.25 V, the
V
CC
R1
TO µP NMI
1.25V
–
PFO
+
TO µP RESET
PFI
RESET
R2
ADM706R/ADM706S/
ADM706T/ADM708R/
ADM708S/ADM708T
PFO
comparator output (
) goes low, indicating a power failure.
For early warning of power failure, the comparator monitors the
preregulator input by choosing an appropriate resistive divider
R3
PFO
network. The
output interrupts the processor to implement a
shutdown procedure before the power is lost.
3.3V
PFO
As the voltage on the PFI pin is limited to VCC + 0.3 V, it is
recommended to connect the PFI pin with a Schottky diode to
RESET
the
pin, as shown in Figure 17. This helps with clamping
the PFI pin voltage during device power up and operation.
INPUT
POWER
0V
0V
V
H
V
L
1.25V
R1
R2
PFO
V
IN
POWER-FAIL
OUTPUT
Figure 18. Adding Hysteresis to the Power Fail Comparator
POWER-FAIL PFI
INPUT
RESET
RESET
OUTPUT
R2 + R3
R2 × R3
ADM706R/ADM706S/
ADM706T/ADM708R/
ADM708S/ADM708T
VH = 1.25 1 +
R1
VCC − 1.25
1.25
R2
V = 1.25 + R1
−
L
R3
Figure 17. Power Fail Comparator
R1 + R2
R2
ADDING HYSTERESIS TO THE POWER FAIL
COMPARATOR
VMID = 1.25
VALID RESET BELOW 1 V VCC
For increased noise immunity, hysteresis can be added to the
power fail comparator. Because the comparator circuit is non-
inverting, hysteresis is added simply by connecting a resistor
The ADM706R/ADM706S/ADM706T, ADM708R/ADM708S/
ADM708T are guaranteed to provide a valid reset level with VCC
as low as 1 V. Refer to the Typical Performance Characteristics
section. As VCC drops below 1 V, the internal transistor does not
PFO
between the
output and the PFI input as shown in Figure 18.
is low, Resistor R3 sinks current from the summing
PFO
PFO
When
junction at the PFI pin. When
is high, Resistor R3 sources
RESET
have sufficient drive to hold it on so the voltage on
is no
current into the PFI summing junction. This results in differing
trip levels for the comparator. Further noise immunity is achieved
by connecting a capacitor between PFI and GND.
longer held at 0 V. A pull-down resistor, as shown in Figure 19, can
connect externally to hold the line low if it is required.
ADM706R/ADM706S/
ADM706T/ADM708R/
ADM708S/ADM708T
RESET
GND
R1
RESET
Figure 19.
Valid Below 1 V
Rev. E | Page 11 of 16
ADM706P/ADM706R/ADM706S/ADM706T, ADM708R/ADM708S/ADM708T Data Sheet
APPLICATIONS INFORMATION
A typical operating circuit is shown in Figure 20. The unregulated
dc input supply is monitored using the PFI input via the resistive
divider network. Resistor R1 and Resistor R2 are to be selected
so that when the supply voltage drops below the desired level
(for example, 5 V), the voltage on PFI drops below the 1.25 V
threshold, thereby generating an interrupt to the microprocessor.
Monitoring the preregulator input gives additional time to execute
an orderly shutdown procedure before power is lost.
UNREGULATED
MONITORING ADDITIONAL SUPPLY LEVELS
It is possible to use the power fail comparator to monitor a second
supply as shown in Figure 22. The two sensing resistors, R1 and
R2, are selected such that the voltage on PFI drops below 1.25 V at
PFO
the minimum acceptable input supply. The
output can
MR
connect to the
input so a reset generates when the supply drops
out of tolerance. In this case, if either supply drops out of tolerance,
a reset is generated.
ADM666A
DC
V
+3V/+3.3V
X
IN
OUT
GND
3.3V
V
CC
RESET
RESET
R1
R2
V
V
CC
CC
MR
MICROPROCESSOR
WDI
PFO
ADM706R/
ADM706S/
ADM706T
WDI
I/O LINE
MICROPROCESSOR
ADM706R/
ADM706S/
ADM706T
MANUAL
RESET
PFI
MR
NMI
WDO
PFO
GND
INTERRUPT
PFI
RESET
GND
RESET
GND
Figure 22. Monitoring 3 V/3.3 V and an Additional Supply, VX
MICROPROCESSORS WITH BIDIRECTIONAL RESET
Figure 20. Typical Application Circuit
To prevent contention for microprocessors with a bidirectional
reset line, a current limiting resistor is to be inserted between
the ADM706R/ADM706S/ADM706T, ADM708R/ADM708S/
Microprocessor activity is monitored using the WDI input. This
is driven using an output line from the processor. The software
routines toggle this line at least once every 1.6 sec. If a problem
RESET
ADM708T
output pin and the microprocessor reset pin.
WDO
occurs and this line is not toggled,
goes low and a nonmask-
This limits the current to a safe level if there are conflicting output
reset levels. A suitable resistor value is 4.7 kΩ. If the reset output is
required for other uses, it must be buffered as shown in Figure 23.
able interrupt is generated. This interrupt routine is to be used
to clear the problem.
If, in the event of inactivity on the WDI line, a system reset is
BUFFERED
+3V/+3.3V
RESET
WDO
required, the
shown in Figure 21.
output is to be connected to the input as
V
CC
ADM706R/ADM706S/
ADM706T/ADM708R/
ADM708S/ADM708T
RESET
RESET
MICROPROCESSOR
ADM706R/
ADM706S/
ADM706T
RESET
I/O LINE
RESET
GND
WDI
PFI
MR
GND
MICROPROCESSOR
WDO
GND
RESET
Figure 23. Bidirectional Input/Output
WDO
from
RESET
Figure 21.
Rev. E | Page 12 of 16
Data Sheet
ADM706P/ADM706R/ADM706S/ADM706T, ADM708R/ADM708S/ADM708T
OUTLINE DIMENSIONS
0.400 (10.16)
0.365 (9.27)
0.355 (9.02)
8
1
5
4
0.280 (7.11)
0.250 (6.35)
0.240 (6.10)
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
0.100 (2.54)
BSC
0.060 (1.52)
MAX
0.195 (4.95)
0.130 (3.30)
0.115 (2.92)
0.210 (5.33)
MAX
0.015
(0.38)
MIN
0.150 (3.81)
0.130 (3.30)
0.115 (2.92)
0.015 (0.38)
GAUGE
0.014 (0.36)
0.010 (0.25)
0.008 (0.20)
PLANE
SEATING
PLANE
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
0.430 (10.92)
MAX
0.005 (0.13)
MIN
0.070 (1.78)
0.060 (1.52)
0.045 (1.14)
COMPLIANT TO JEDEC STANDARDS MS-001
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.
Figure 24. 8-Lead Plastic Dual In-Line Package [PDIP]
Narrow Body
(N-8)
Dimension shown in inches and (millimeters)
5.00 (0.1968)
4.80 (0.1890)
8
1
5
4
6.20 (0.2441)
5.80 (0.2284)
4.00 (0.1574)
3.80 (0.1497)
0.50 (0.0196)
0.25 (0.0099)
1.27 (0.0500)
BSC
45°
1.75 (0.0688)
1.35 (0.0532)
0.25 (0.0098)
0.10 (0.0040)
8°
0°
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
1.27 (0.0500)
0.40 (0.0157)
0.25 (0.0098)
0.17 (0.0067)
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MS-012-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 25. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
Rev. E | Page 13 of 16
ADM706P/ADM706R/ADM706S/ADM706T, ADM708R/ADM708S/ADM708T
Data Sheet
ORDERING GUIDE
Model1
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
Package Option
ADM706PANZ
ADM706PARZ
ADM706PARZ-REEL
ADM706RANZ
ADM706RAR
ADM706RARZ
ADM706RARZ-REEL
ADM706RARZ-REEL7
ADM706SANZ
ADM706SAR
ADM706SAR-REEL
ADM706SARZ
ADM706SARZ-REEL
ADM706TANZ
ADM706TAR
ADM706TAR-REEL
ADM706TARZ
ADM706TARZ-REEL
ADM708RANZ
ADM708RAR
ADM708RAR-REEL
ADM708RARZ
ADM708RARZ-REEL
ADM708SANZ
ADM708SAR
ADM708SAR-REEL
ADM708SARZ
ADM708SARZ-REEL
ADM708TANZ
ADM708TAR
8-Lead Plastic Dual In-Line Package [PDIP]
8-Lead Small Outline Package [SOIC_N]
8-Lead Small Outline Package [SOIC_N]
8-Lead Plastic Dual In-Line Package [PDIP]
8-Lead Small Outline Package [SOIC_N]
8-Lead Small Outline Package [SOIC_N]
8-Lead Small Outline Package [SOIC_N]
8-Lead Small Outline Package [SOIC_N]
8-Lead Plastic Dual In-Line Package [PDIP]
8-Lead Small Outline Package [SOIC_N]
8-Lead Small Outline Package [SOIC_N]
8-Lead Small Outline Package [SOIC_N]
8-Lead Small Outline Package [SOIC_N]
8-Lead Plastic Dual In-Line Package [PDIP]
8-Lead Small Outline Package [SOIC_N]
8-Lead Small Outline Package [SOIC_N]
8-Lead Small Outline Package [SOIC_N]
8-Lead Small Outline Package [SOIC_N]
8-Lead Plastic Dual In-Line Package [PDIP]
8-Lead Small Outline Package [SOIC_N]
8-Lead Small Outline Package [SOIC_N]
8-Lead Small Outline Package [SOIC_N]
8-Lead Small Outline Package [SOIC_N]
8-Lead Plastic Dual In-Line Package [PDIP]
8-Lead Small Outline Package [SOIC_N]
8-Lead Small Outline Package [SOIC_N]
8-Lead Small Outline Package [SOIC_N]
8-Lead Small Outline Package [SOIC_N]
8-Lead Plastic Dual In-Line Package [PDIP]
8-Lead Small Outline Package [SOIC_N]
8-Lead Small Outline Package [SOIC_N]
8-Lead Small Outline Package [SOIC_N]
N-8
R-8
R-8
N-8
R-8
R-8
R-8
R-8
N-8
R-8
R-8
R-8
R-8
N-8
R-8
R-8
R-8
R-8
N-8
R-8
R-8
R-8
R-8
N-8
R-8
R-8
R-8
R-8
N-8
R-8
R-8
R-8
ADM708TARZ
ADM708TARZ-REEL
1 Z = RoHS Compliant Part.
Rev. E | Page 14 of 16
Data Sheet
NOTES
ADM706P/ADM706R/ADM706S/ADM706T, ADM708R/ADM708S/ADM708T
Rev. E | Page 15 of 16
ADM706P/ADM706R/ADM706S/ADM706T, ADM708R/ADM708S/ADM708T
NOTES
Data Sheet
©2007–2016 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D00089-0-1/16(E)
Rev. E | Page 16 of 16
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