ADM706SAN [ADI]
+3 V, Voltage Monitoring uP Supervisory Circuits; +3 V ，电压监控多达监控电路
| 型号： | ADM706SAN |
| 厂家： | 
ADI |
| 描述： | +3 V, Voltage Monitoring uP Supervisory Circuits |
| 文件： | 总8页 (文件大小：128K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
+3 V, Voltage Monitoring
a
P Supervisory Circuits
ADM706P/R/S/T, ADM708R/S/T
FUNCTIONAL BLOCK DIAGRAMS
FEATURES
Precision Supply-Voltage Monitor
+2.63 V (ADM706P/R, ADM708R)
+2.93 V (ADM706S, ADM708S)
+3.08 V (ADM706T, ADM708T)
100 A Quiescent Current
WATCHDOG
WATCHDOG
WATCHDOG
OUTPUT(WDO)
WATCHDOG
TIMER
INPUT (WDI)
TRANSITION
DETECTOR
RESET &
WATCHDOG
TIMEBASE
200 ms Reset Pulsewidth
V
CC
Debounced Manual Reset Input (MR)
Independent Watchdog Timer—1.6 sec Timeout
(ADM706x)
70A
MR
RESET
GENERATOR
RESET,
(P = RESET)
Reset Output
Active High (ADM706P)
Active Low (ADM706R/S/T)
V
CC
V
*
Both Active High and Active Low (ADM708R/S/T)
Voltage Monitor for Power-Fail or Low Battery Warning
Guaranteed RESET Valid with VCC = 1 V
Superior Upgrade for MAX706P/R/S/T, MAX708R/S/T
REF
ADM706
POWER FAIL
INPUT (PFI)
POWER FAIL
OUTPUT (PFO)
1.25V
*VOLTAGE REFERENCE = 2.63V (P/R), 2.93V (S), 3.08V (T)
APPLICATIONS
Microprocessor Systems
Computers
V
CC
Controllers
RESET
Intelligent Instruments
Critical P Monitoring
Automotive Systems
Battery Operated Systems
Portable Instruments
70A
MR
RESET
GENERATOR
RESET
V
CC
V
*
REF
ADM708
GENERAL DESCRIPTION
POWER FAIL
INPUT (PFI)
The ADM706P/R/S/T and the ADM708R/S/T microprocessor
supervisory circuits are suitable for monitoring either 3 V or 3.3 V
power supplies.
POWER FAIL
OUTPUT (PFO)
1.25V
*VOLTAGE REFERENCE = 2.63V (R), 2.93V (S), 3.08V (T)
The ADM706P/R/S/T provide the following functions:
1. Power-supply monitoring circuitry which generates a Reset
output during power-up, power-down and brownout condi-
tions. The reset output remains operational with VCC as low
as 1 V.
The ADM708R/S/T provide the same functionality as the
ADM706R/S/T and only differ in that:
1. A watchdog timer function is not available.
2. Independent watchdog monitoring circuitry which is acti-
vated if the watchdog input has not been toggled within
1.6 seconds.
2. An active high reset output (RESET) in addition to the
active low (RESET) output is available.
All parts are available in 8-lead DIP and narrow SOIC packages.
3. A 1.25 V threshold detector for power fail warning, low bat-
tery detection, or to monitor an additional power supply.
4. An active low debounced manual reset input (MR).
The ADM706R, ADM706S, ADM706T are identical except for
the reset threshold monitor levels which are 2.63 V, 2.93 V, and
3.08 V respectively. The ADM706P is identical to the ADM706R
in that the reset threshold is 2.63 V. It differs only in that it has
an active high reset output.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 1999
(V = 2.70 V to 5.5 V (ADM70_P/R),
ADM706P/R/S/T, ADM708R/S/T–SPECIFICATIONS
CC
VCC = 3.00 V to 5.5 V (ADM70_S), VCC = 3.15 V to 5.5 V (ADM70_T), TA = TMIN to TMAX unless otherwise noted.)
Parameter
Min
Typ
Max
Units
Test Conditions/Comments
V
CC Operating Voltage Range
1.0
5.5
200
350
V
µA
µA
Supply Current
100
150
VCC < 3.6 V
VCC < 5.5 V
Reset Threshold (VRST
)
2.55
2.85
3.00
2.63
2.93
3.08
20
2.70
3.00
3.15
V
V
V
mV
ADM70_P/R
ADM70_S
ADM70_T
Reset Threshold Hysteresis
Reset Pulsewidth
160
160
200
200
200
280
280
ms
ms
ms
ADM70_P/R, VCC = 3 V
ADM70_S/T, VCC = 3.3 V
VCC = 5.0 V
RESET Output Voltage
ADM70_R/S/T
VOH
VOL
VOH
VOL
VOL
0.8 × VCC
V
V
V
V
V
VRST (max) < VCC < 3.6 V, ISOURCE = 500 µA
VRST (max) < VCC < 3.6 V, ISINK = 1.2 mA
4.5 V < VCC < 5.5 V, ISOURCE = 800 µA
4.5 V < VCC < 5.5 V, ISINK = 3.2 mA
VCC = 1 V, ISINK = 100 µA
0.3
VCC–1.5 V
0.4
0.3
RESET Output Voltage
ADM706P
VOH
VOL
VOH
VOL
VCC–0.6 V
VCC–1.5 V
V
V
V
V
VRST (max) < VCC < 3.6 V, ISOURCE = 215 µA
VRST (max) < VCC < 3.6 V, ISINK = 1.2 mA
4.5 V < VCC < 5.5 V, ISOURCE = 800 µA
4.5 V < VCC < 5.5 V, ISINK = 3.2 mA
0.3
0.4
RESET Output Voltage
ADM708_
VOH
VOL
VOH
VOL
0.8 × VCC
V
V
V
V
VRST (max) < VCC < 3.6 V, ISOURCE = 500 µA
VRST (max) < VCC < 3.6 V, ISINK = 500 µA
4.5 V < VCC < 5.5 V, ISOURCE = 800 µA
4.5 V < VCC < 5.5 V, ISINK = 1.2 mA
0.3
VCC–1.5 V
0.4
Watchdog Timeout Period
1.00
1.60
2.25
sec
ADM70_P/R; VCC = 3 V. ADM70_S/T,
VCC = 3.3 V
WDI Pulsewidth
VIL = 0.4 V, VIH = (VCC) × (0.8)
VRST (max) < VCC < 3.6 V
4.5 V < VCC < 5.5 V
ADM706_
100
50
ns
ns
WDI Input Threshold
VIL
VIH
VIL
VIH
0.6
0.8
1.0
V
V
V
V
VRST (max) < VCC < 3.6 V
VRST (max) < VCC < 3.6 V
VCC = 5.0 V
VCC = 5.0 V
WDI = 0 V or VCC
0.7 × VCC
3.5
–1.0
WDI Input Current
0.02
µA
WDO Output Voltage
VOH
VOL
VOH
VOL
0.8 × VCC
V
V
V
V
VRST (max) < VCC < 3.6 V, ISOURCE = 500 µA
VRST (max) < VCC < 3.6 V, ISINK = 500 µA
4.5 V < VCC < 5.5 V, ISOURCE = 800 µA
4.5 V < VCC < 5.5 V, ISINK = 1.2 mA
0.3
0.4
VCC–1.5 V
MR Pull Up Current
MR = 0 V
VRST (max) < VCC < 3.6 V
4.5 V < VCC < 5.5 V
25
100
70
250
250
600
µA
µA
MR Pulsewidth
500
150
ns
ns
VRST (max) < VCC < 3.6 V
4.5 V < VCC < 5.5 V
MR Input Threshold
VIL
VIH
VIL
VIH
0.6
0.8
V
V
V
V
VRST (max) < VCC < 3.6 V
VRST (max) < VCC < 3.6 V
4.5 V < VCC < 5.5 V
0.7 × VCC
2.0
4.5 V < VCC < 5.5 V
–2–
REV. A
ADM706P/R/S/T, ADM708R/S/T
Parameter
Min
Typ
Max
Units
Test Conditions/Comments
MR to Reset Output Delay
750
250
ns
ns
VRST (max) < VCC < 3.6 V
4.5 V < VCC < 5.5 V
PFI Input Threshold
PFI Input Current
1.2
1.25
0.01
1.3
V
ADM70_P/R; VCC = 3 V. ADM70_S/T,
VCC = 3.3 V, PFI falling
–25
25
nA
PFO Output Voltage
VOH
VOL
VOH
VOL
0.8 × VCC
V
V
V
V
VRST (max) < VCC < 3.6 V, ISOURCE = 500 µA
VRST (max) < VCC < 3.6 V, ISINK = 1.2 mA
4.5 V < VCC < 5.5 V, ISOURCE = 800 µA
4.5 V < VCC < 5.5 V, ISINK = 3.2 mA
0.3
0.4
VCC–1.5 V
ORDERING GUIDE
ABSOLUTE MAXIMUM RATINGS*
(TA = +25°C unless otherwise noted)
Temperature
Range
Package
Options
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V
All Other Inputs . . . . . . . . . . . . . . . . . . –0.3 V to VCC + 0.3 V
Input Current
Model
ADM706PAN
ADM706PAR
ADM706RAN
ADM706RAR
ADM706SAN
ADM706SAR
ADM706TAN
ADM706TAR
ADM708RAN
ADM708RAR
ADM708SAN
ADM708SAR
ADM708TAN
ADM708TAR
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
N-8
SO-8
N-8
SO-8
N-8
SO-8
N-8
SO-8
N-8
SO-8
N-8
SO-8
N-8
SO-8
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Power Dissipation, N-8 DIP . . . . . . . . . . . . . . . . . . . . 727 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 135°C/W
Power Dissipation, SO-8 SOIC . . . . . . . . . . . . . . . . . . 470 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 110°C/W
Operating Temperature Range
Industrial (A Version) . . . . . . . . . . . . . . . . . –40°C to +85°C
Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . . +300°C
Vapor Phase (60 secs) . . . . . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 secs) . . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C
Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C
ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>5 kV
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum
ratings for extended periods of time may affect device reliability.
REV. A
–3–
ADM706P/R/S/T, ADM708R/S/T
PIN FUNCTION DESCRIPTIONS
Pin No.
Mnemonic ADM706
Pin No.
ADM708
Function
MR
1
1
Manual Reset Input. When taken below 0.6 V a RESET is generated. MR can be
driven from TTL, CMOS logic or from a manual reset switch as it is internally
debounced. An internal 70 µA pull-up current holds the input high when floating.
VCC
GND
PFI
2
3
4
2
3
4
Power Supply Input.
0 V. Ground reference for all signals.
Power Fail Input. PFI is the noninverting input to the Power Fail Comparator.
When PFI is less than 1.25 V, PFO goes low. If unused, PFI should be connected
to GND.
PFO
5
6
5
Power Fail Output. PFO is the output from the Power Fail Comparator. It goes
low when PFI is less than 1.25 V.
WDI
N/A
Watchdog Input. WDI is a three level input. If WDI remains either high or low
for longer than the watchdog timeout period, the watchdog output WDO goes
low. The timer resets with each transition at the WDI input. Either a high-to-low
or a low-to-high transition will clear the counter. The internal timer is also
cleared whenever reset is asserted. The Watchdog Timer is disabled when WDI is
left floating or connected to a three-state buffer.
NC
RESET
N/A
7 (R/S/T Only)
6
7
No Connect.
Logic Output. RESET goes low for 200 ms when triggered. It can be triggered
either by VCC being below the reset threshold or by a low signal on the manual
reset (MR) input. RESET will remain low whenever VCC is below the reset
threshold. It remains low for 200 ms after VCC goes above the reset threshold or
MR goes from low to high. A watchdog timeout will not trigger RESET unless
WDO is connected to MR.
RESET
7 (P Only)
8
8
Logic Output. RESET is an active high output suitable for systems which use
active high RESET logic. It is the inverse of RESET.
Logic Output. The Watchdog Output, WDO, goes low if the internal watchdog
timer times out as a result of inactivity on the WDI input. It remains low until
the watchdog timer is cleared. WDO also goes low during low line conditions.
Whenever VCC is below the reset threshold, WDO remains low. As soon as VCC
goes above the reset threshold, WDO goes high immediately.
WDO
N/A
PIN CONFIGURATIONS
1
8
7
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
RESET
RESET
NC
MR
WDO
MR
MR
WDO
RESET
WDI
2
3
4
V
V
V
RESET
CC
CC
GND
PFI
CC
ADM706
ADM706
R/S/T
ADM708
R/S/T
P
6
5
GND
GND
PFI
WDI
TOP VIEW
(Not to Scale)
TOP VIEW
(Not to Scale)
TOP VIEW
(Not to Scale)
PFI
PFO
PFO
PFO
NC = NO CONNECT
–4–
REV. A
ADM706P/R/S/T, ADM708R/S/T
Manual Reset
The manual reset input (MR) allows other reset sources such as
a manual reset switch to generate a processor reset. The input is
effectively debounced by the timeout period (200 ms typical).
The MR input is TTL/CMOS compatible so it may also be
driven by any logic reset output. If unused, the MR input may
be tied high or left floating.
WATCHDOG
INPUT (WDI)
WATCHDOG
TRANSITION
DETECTOR
WATCHDOG
OUTPUT(WDO)
WATCHDOG
TIMER
RESET &
WATCHDOG
TIMEBASE
V
CC
70A
VRT
VRT
MR
RESET
GENERATOR
RESET,
(P = RESET)
V
CC
tRS
tRS
V
CC
RESET
V
*
REF
ADM706
POWER FAIL
INPUT (PFI)
POWER FAIL
MR
MR EXTERNALLY
1.25V
OUTPUT (PFO)
DRIVEN LOW
*VOLTAGE REFERENCE = 2.63V (P/R), 2.93V (S), 3.08V (T)
WDO
Figure 1. ADM706 Functional Block Diagram
NOTE: RESET = COMPLEMENT OF RESET
V
CC
RESET
Figure 3. RESET, MR and WDO Timing
70A
Watchdog Timer (ADM706)
MR
RESET
GENERATOR
RESET
The watchdog timer circuit may be used to monitor the activity
of the microprocessor in order to check that it is not stalled in
an indefinite loop. An output line on the processor is used to
toggle the Watchdog Input (WDI) line. If this line is not toggled
within the timeout period (1.6 sec), the watchdog output
(WDO) is driven low. The WDO output may be connected to a
nonmaskable interrupt (NMI) on the processor. Therefore, if
the watchdog timer times out, an interrupt is generated. The in-
terrupt service routine should then be used to rectify the
problem.
V
CC
V
*
REF
ADM708
POWER FAIL
INPUT (PFI)
POWER FAIL
OUTPUT (PFO)
1.25V
*VOLTAGE REFERENCE = 2.63V (R), 2.93V (S), 3.08V (T)
Figure 2. ADM708 Functional Block Diagram
CIRCUIT INFORMATION
The watchdog timer is cleared by either a high-to-low or by a
low-to-high transition on WDI. Pulses as narrow as 50 ns are
detected. The timer is also cleared by RESET/RESET going
active. Therefore the watchdog timeout period begins after reset
goes inactive.
Power Fail Reset
The reset output provides a reset (RESET or RESET) output
signal to the Microprocessor whenever the VCC input is below
the reset threshold. The actual reset threshold voltage is depen-
dent on whether a P/R, S, or T suffix device is used. An internal
timer holds the reset output active for 200 ms after the voltage
on VCC rises above the threshold. This is intended as a power-on
reset signal for the microprocessor. It allows time for both the
power supply and the microprocessor to stabilize after power-
up. If a power supply brownout or interruption occurs, the reset
line is similarly activated and remains active for 200 ms after the
supply recovers. If another interruption occurs during an active
reset period, then the reset timeout period continues for an ad-
ditional 200 ms.
When VCC falls below the reset threshold, WDO is forced low
whether or not the watchdog timer has timed out. Normally
this would generate an interrupt but it is overridden by RESET/
RESET going active.
The watchdog monitor can be deactivated by floating the
Watchdog Input (WDI). The WDO output can now be used as
a low line output since it will only go low when VCC falls below
the reset threshold.
tWD
tWD
tWD
tWP
WDI
The reset output is guaranteed to remain valid with VCC as low
as 1 V. This ensures that the microprocessor is held in a stable
shutdown condition as the power supply starts up.
WDO
The ADM706P provides an active high reset (RESET) signal;
the ADM706R/S/T provides an active low (RESET) signal;
while the ADM708R/S/T provides both RESET and RESET.
RESET
RESET EXTERNALLY
TRIGGERED BY MR
tRS
Figure 4. Watchdog Timing
REV. A
–5–
ADM706P/R/S/T, ADM708R/S/T
Power-Fail Comparator
1. 25 VCC – 1.25
VL = 1. 25 + R1
–
The power-fail comparator is an independent comparator which
may be used to monitor the input power supply. The compara-
tor’s inverting input is internally connected to a 1.25 V reference
voltage. The noninverting input is available at the PFI input.
This input may be used to monitor the input power supply via a
resistive divider network. When the voltage on the PFI input drops
below 1.25 V, the comparator output (PFO) goes low indicating
a power failure. For early warning of power failure the compara-
tor may be used to monitor the preregulator input simply by
choosing an appropriate resistive divider network. The PFO output
can be used to interrupt the processor so that a shutdown proce-
dure is implemented before the power is lost.
R2
R3
R1 + R2
V
MID 1. 25
R2
Valid RESET Below 1 V VCC
The ADM70x family of products are guaranteed to provide a
valid reset level with VCC as low as 1 V. Please refer to the Typi-
cal Performance Characteristics. As VCC drops below 1 V, the
internal transistor will not have sufficient drive to hold it ON so
the voltage on RESET will no longer be held at 0 V. A pull-
down resistor as shown in Figure 7 may be connected externally
to hold the line low if it is required.
INPUT
POWER
R1
PFO
1.25V
PFI
ADM70x
POWER-FAIL
OUTPUT
POWER-FAIL
INPUT
ADM70x
RESET
R2
R1
GND
Figure 5. Power-Fail Comparator
Adding Hysteresis to the Power-Fail Comparator
Figure 7. RESET Valid Below 1 V
For increased noise immunity, hysteresis may be added to the
power-fail comparator. Since the comparator circuit is nonin-
verting, hysteresis can be added simply by connecting a resistor
between the PFO output and the PFI input as shown in Figure
6. When PFO is low, resistor R3 sinks current from the sum-
ming junction at the PFI pin. When PFO is high, resistor R3
sources current into the PFI summing junction. This results in
differing trip levels for the comparator. Further noise immunity
may be achieved by connecting a capacitor between PFI and GND.
Typical Performance Characteristics
V
CC
+3.3V
ADM663A
INPUT
POWER
V
CC
R1
R2
TO P NMI
PFO
1.25V
PFI
RESET
ADM70x
400ms/DIV
Figure 8. ADM706/ADM708 RESET Output Voltage vs.
R3
Supply Voltage
3.3V
PFO
0V
0V
V
V
H
L
V
CC
V
IN
Figure 6. Adding Hysteresis to the Power-Fail
Comparator
RESET
R2 + R3
VH = 1.25 1 +
R1
R2 × R3
400ms/DIV
Figure 9. RESET Output Voltage vs. Supply Voltage
–6–
REV. A
ADM706P/R/S/T, ADM708R/S/T
V
T
= V
RT
= +25؇C
V
T
= +5V
CC
CC
= +25؇C
A
A
1.3V
PFI
+3V
+1.2V
+3V
RESET
RESET
+3V
PFO
0V
0V
0V
100ns/DIV
500ns/DIV
Figure 13. RESET, RESET Deassertion
Figure 10. PFI Assertion Response Time
T
= +25؇C
A
V
T
= +5V
CC
+3V
= +25؇C
A
V
CC
+1.3V
PFI
+2V
1.2V
+3V
+3V
RESET
PFO
0V
0V
2s/DIV
500ns/DIV
Figure 11. PFI Deassertion Response Time
Figure 14. ADM706/ADM708 RESET Response Time
APPLICATIONS
V
T
= V
RT
= +25؇C
CC
A typical operating Circuit is shown in Figure 15. The unregu-
lated dc input supply is monitored using the PFI input via the
resistive divider network. Resistors R1 and R2 should be selected
such that when the supply voltage drops below the desired level
(e.g., 5 V) the voltage on PFI drops below the 1.25 V threshold
thereby generating an interrupt to the µP. Monitoring the
preregulator input gives additional time to execute an orderly
shutdown procedure before power is lost.
A
+3V
+3V
RESET
RESET
0V
0V
ADM666A
UNREGULATED
IN
OUT
DC
+3.3V
GND
100ns/DIV
V
V
CC
CC
Figure 12. RESET, RESET Assertion
RESET
I/O LINE
RESET
WDI
ADM706
P
PFI
NMI
WDO
MR
PFO
INTERRUPT
GND
GND
MANUAL
RESET
Figure 15. Typical Application Circuit
REV. A
–7–
ADM706P/R/S/T, ADM708R/S/T
V
+3V/+3.3V
Microprocessor activity is monitored using the WDI input. This
is driven using an output line from the processor. The software
routines should toggle this line at least once every 1.6 seconds.
If a problem occurs and this line is not toggled, then WDO goes
low and a nonmaskable interrupt is generated. This interrupt
routine may be used to clear the problem.
X
V
CC
RESET
RESET
WDI
R1
R2
P
ADM706
PFI
MR
PFO
GND
If, in the event of inactivity on the WDI line, a system reset is
required, then the WDO output should be connected to the
input as shown in Figure 16.
Figure 17. Monitoring 3 V/3.3 V and an Additional
Supply, VX
RESET
RESET
Ps with Bidirectional RESET
P
ADM706
In order to prevent contention for microprocessors with a bidi-
rectional reset line, a current limiting resistor should be inserted
between the ADM70x RESET output pin and the µP reset pin.
This will limit the current to a safe level if there are conflicting
output reset levels. A suitable resistor value is 4.7 kΩ. If the re-
set output is required for other uses, then it should be buffered
as shown in Figure 18.
I/O LINE
WDI
PFI
WDO
MR
GND
Figure 16. RESET from WDO
Monitoring Additional Supply Levels
BUFFERED
+3V/+3.3V
RESET
It is possible to use the power-fail comparator to monitor a
second supply as shown in Figure 17. The two sensing resistors
R1 and R2 are selected such that the voltage on PFI drops below
1.25 V at the minimum acceptable input supply. The PFO output
may be connected to the MR input so that a RESET is gener-
ated when the supply drops out of tolerance. In this case if
either supply drops out of tolerance, a RESET will be generated.
V
CC
P
ADM70x
RESET
GND
RESET
GND
Figure 18. Bidirectional I-O RESET
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
8-Lead Plastic DIP
(N-8)
8-Lead SOIC
(SO-8)
0.430 (10.92)
0.348 (8.84)
0.1968 (5.00)
0.1890 (4.80)
8
5
8
1
5
4
0.280 (7.11)
0.240 (6.10)
0.2440 (6.20)
0.2284 (5.80)
0.1574 (4.00)
0.1497 (3.80)
1
4
0.325 (8.25)
0.300 (7.62)
PIN 1
PIN 1
0.100 (2.54)
BSC
0.0196 (0.50)
0.0099 (0.25)
0.0500 (1.27)
BSC
؋
45؇ 0.060 (1.52)
0.015 (0.38)
0.210
(5.33)
MAX
0.195 (4.95)
0.115 (2.93)
0.0688 (1.75)
0.0532 (1.35)
0.0098 (0.25)
0.0040 (0.10)
0.130
(3.30)
MIN
8؇
0؇
0.0500 (1.27)
0.0160 (0.41)
0.0192 (0.49)
0.0138 (0.35)
0.160 (4.06)
0.115 (2.93)
0.0098 (0.25)
0.0075 (0.19)
SEATING
PLANE
0.015 (0.381)
0.008 (0.204)
0.022 (0.558) 0.070 (1.77) SEATING
0.014 (0.356) 0.045 (1.15)
PLANE
–8–
REV. A
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