ADM7150ACPZ-1.8-R7_技术文档

800 mA Ultralow Noise,

High PSRR, RF Linear Regulator

ADM7150

Data Sheet

FEATURES

TYPICAL APPLICATION CIRCUIT

ADM7150

Input voltage range: 4.5 V to 16 V

Maximum output current: 800 mA

Low noise

V

= 6.2V

V

C

= 5.0V

IN

OUT

VIN

VOUT

C

IN

10µF

OUT

10µF

ON

1.0 µV rms total integrated noise from 100 Hz to 100 kHz

1.6 µV rms total integrated noise from 10 Hz to 100 kHz

Noise spectral density: 1.7 nV√Hz typical from 10 kHz to 1 MHz

Power supply rejection ratio (PSRR) at 400 mA load

>90 dB from 1 kHz to 100 kHz, V_OUT= 5 V

>60 dB at 1 MHz, V_OUT= 5 V

EN

REF

REF_SENSE

GND

C

REF

1µF

OFF

BYP

C

1µF

BYP

VREG

C

REG

10µF

Figure 1. 5 V Output Circuit

Dropout voltage: 0.6 V at V_OUT= 5 V, 800 mA load

Initial voltage accuracy: ±1%

Voltage accuracy over line, load and temperature: ±±%

Quiescent current (I_GND): 4.3 mA at no load

Low shutdown current: 0.1 µA

Stable with a 10 µF ceramic output capacitor

Fixed output voltage options: 1.8 V, ±.8 V, 3.0 V, 3.3 V, 4.5 V,

4.8 V, and 5.0 V (16 outputs between 1.5 V and 5.0 V are

available)

Exposed pad 8-lead LFCSP and 8-lead SOIC packages

APPLICATIONS

Regulated power noise sensitive applications

RF mixers, phase-locked loops (PLLs), voltage-controlled

oscillators (VCOs), and PLLs with integrated VCOs

Communications and infrastructure

Cable digital-to-analog converter (DAC) drivers

Backhaul and microwave links

GENERAL DESCRIPTION

The ADM7150 is a low dropout (LDO) linear regulator that

operates from 4.5 V to 16 V and provides up to 800 mA of

output current. Using an advanced proprietary architecture, it

provides high power supply rejection (>90 dB from 1 kHz to 1 MHz),

ultralow output noise (<1.7 nV√Hz), and achieves excellent line and

load transient response with a 10 µF ceramic output capacitor.

footprint. See the ADM7151 adjustable LDO to generate additional

output voltages.

100k

C

= 1µF

BYP

= 10µF

= 100µF

= 1mF

10k

1k

100

10

1

The ADM7150 is available in 1.8 V, 2.8 V, 3.0 V, 3.3 V, 4.5 V,

4.8 V, and 5.0 V fixed outputs. In addition, 16 fixed output

voltages between 1.5 V and 5.0 V are available upon request.

The ADM7150 regulator typical output noise is 1.0 µV rms

from 100 Hz to 100 kHz for fixed output voltage options, and

the noise spectral density is 1.7 nV/√Hz from 10 kHz to 1 MHz.

The ADM7150 is available in 8-lead, 3 mm × 3 mm LFCSP and

8-lead SOIC packages, making it not only a very compact solution

but also providing excellent thermal performance for applications

requiring up to 800 mA of output current in a small, low profile

0.1

1

10

100

1k

10k

100k

1M

FREQUENCY (Hz)

Figure 2. Noise Spectral Density (NSD) vs. Frequency for Various C_BYP

Rev. 0

Document Feedback

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rightsof third parties that may result fromits use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks andregisteredtrademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 0±06±-9106, U.S.A.

Tel: 781.3±9.4700

Technical Support

www.analog.com

ADM7150* PRODUCT PAGE QUICK LINKS

Last Content Update: 11/29/2017

COMPARABLE PARTS

View a parametric search of comparable parts.

DESIGN RESOURCES

• ADM7150 Material Declaration

• PCN-PDN Information

EVALUATION KITS

• AD-FMCOMMS6-EBZ Evaluation Board

• Quality And Reliability

• Symbols and Footprints

• ADM7150 and ADM7151 Evaluation Board

DISCUSSIONS

View all ADM7150 EngineerZone Discussions.

DOCUMENTATION

Data Sheet

SAMPLE AND BUY

Visit the product page to see pricing options.

• ADM7150: 800 mA Ultralow Noise, High PSRR, RF Linear

Regulator Data Sheet

TOOLS AND SIMULATIONS

• ADI Linear Regulator Design Tool and Parametric Search

TECHNICAL SUPPORT

Submit a technical question or find your regional support

number.

• ADIsimPower™ Voltage Regulator Design Tool

REFERENCE DESIGNS

DOCUMENT FEEDBACK

• CN0369

Submit feedback for this data sheet.

REFERENCE MATERIALS

Press

• Ultra-Low-Noise RF Low-Dropout Regulators Reduce

Phase Noise in Wideband Communication Systems

Solutions Bulletins & Brochures

• Ultralow Noise, High Rejection Low Dropout Regulators

Technical Articles

• Replacing YIG-Tuned Oscillators with Silicon by Using an

Ultrawideband PLL/VCO with Precise Phase Control

This page is dynamically generated by Analog Devices, Inc., and inserted into this data sheet. A dynamic change to the content on this page will not

trigger a change to either the revision number or the content of the product data sheet. This dynamic page may be frequently modified.

ADM7150

Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Typical Performance Characteristics ..............................................7

Theory of Operation ...................................................................... 15

Applications Information .............................................................. 16

Capacitor Selection .................................................................... 16

Enable (EN) and Undervoltage Lockout (UVLO)................. 17

Start-Up Time ............................................................................. 18

REF, BYP, and, VREG pins........................................................ 18

Current-Limit and Thermal Overload Protection................. 19

Thermal Considerations............................................................ 19

Printed Circuit Board Layout Considerations........................ 21

Outline Dimensions....................................................................... 22

Ordering Guide .......................................................................... 22

Applications....................................................................................... 1

Typical Application Circuit ............................................................. 1

General Description......................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Input and Output Capacitor Recommended Specifications... 4

Absolute Maximum Ratings............................................................ 5

Thermal Data ................................................................................ 5

Thermal Resistance ...................................................................... 5

ESD Caution.................................................................................. 5

Pin Configurations and Function Descriptions ........................... 6

REVISION HISTORY

9/13—Revision 0: Initial Version

Rev. 0 | Page 2 of 24

Data Sheet

ADM7150

SPECIFICATIONS

V_IN= V_OUT+ 1.2 V or V_IN= 4.5 V, whichever is greater, V_EN= V_IN, I_OUT= 10 mA, C_IN= C_OUT= C_REG= 10 µF, C_REF= C_BYP= 1 µF. T_A= 25°C

for typical specifications. T_J= −40°C to +125°C for minimum/maximum specifications, unless otherwise noted.

Table 1.

Parameter

Symbol

V_IN

Test Conditions/Comments

Min

Typ Max

Unit

V

INPUT VOLTAGE RANGE

OPERATING SUPPLY CURRENT

4.5

16

I_GND

I_OUT= 0 µA

I_OUT= 800 mA

4.3

8.6

0.1

1.6

1.0

1.7

86

54

95

62

94

62

95

68

7.0

12

3

mA

µA

SHUTDOWN CURRENT

OUTPUT NOISE

I_IN-SD

V_EN= 0 V

OUT_NOISE

10 Hz to 100 kHz, independent of output voltage

100 Hz to 100 kHz, independent of output voltage

10 kHz to 1 MHz, independent of output voltage

1 kHz to 100 kHz, V_IN= 6.2 V, V_OUT= 5 V at 800 mA

1 MHz, V_IN= 6.2 V, V_OUT= 5 V at 800 mA

1 kHz to 100 kHz, V_IN= 6.2 V, V_OUT= 5 V at 400 mA

1 MHz, V_IN= 6.2 V, V_OUT= 5 V at 400 mA

1 kHz to 100 kHz, V_IN= 5 V, V_OUT= 3.3 V at 800 mA

1 MHz, V_IN= 5 V, V_OUT= 3.3 V at 800 mA

1 kHz to 100 kHz, V_IN= 5 V, V_OUT= 3.3 V at 400 mA

1 MHz, V_IN= 5 V, V_OUT= 3.3 V at 400 mA

V_OUT= V_REF

µV rms

nV/√Hz

dB

NOISE SPECTRAL DENSITY

NSD

POWER SUPPLY REJECTION RATIO

PSRR

dB

V_OUTVOLTAGE ACCURACY

Voltage Accuracy

V_OUT

I_OUT= 10 mA, T_J= 25°C

1 mA < I_OUT< 800 mA, over line, load and

temperature

−1

−2

+1

+2

%

V_OUTREGULATION

Line Regulation

ΔV_OUT/ΔV_IN

V_IN= V_OUT+ 1.2 V or V_OUT+ 4.5 V, whichever is

greater, to 16 V

I_OUT= 1 mA to 800 mA

−0.01

1.0

+0.01 %/V

Load Regulation¹

V_OUTCURRENT-LIMIT THRESHOLD²

DROPOUT VOLTAGE³

ΔV_OUT/ΔI_OUT

I_LIMIT

0.4

1.2

0.3

0.6

1.0

1.6

0.5

1.0

%/A

A

V_DROPOUT

I_OUT= 400 mA, V_OUT= 5 V

I_OUT= 800 mA, V_OUT= 5 V

V

PULL-DOWN RESISTANCE

V_OUTPull-Down Resistance

V_REGPull-Down Resistance

V_REFPull-Down Resistance

V_BYPPull-Down Resistance

START-UP TIME⁴

V_OUT-PULL

V_REG-PULL

V_REF-PULL

V_BYP-PULL

V_EN= 0 V, V_OUT= 1 V

V_EN= 0 V, V_REG= 1 V

V_EN= 0 V, V_REF= 1 V

V_EN= 0 V, V_BYP= 1 V

V_OUT= 5 V

600

34

800

500

Ω

kΩ

Ω

V_OUTStart-Up Time

V_REGStart-Up Time

V_REFStart-Up Time

t_START-UP

t_REG-START-UP

t_REF-START-UP

2.8

1.0

1.8

ms

THERMAL SHUTDOWN

Thermal Shutdown Threshold

Thermal Shutdown Hysteresis

UNDERVOLTAGE THRESHOLDs

Input Voltage Rising

Input Voltage Falling

Hysteresis

V_REG⁵UNDERVOLTAGE THRESHOLDS

V_REGRise

V_REGFall

Hysteresis

TS_SD

TS_SD-HYS

T_Jrising

155

15

°C

UVLO_RISE

UVLO_FALL

UVLO_HYS

4.49

3.1

V

mV

3.85

2.55

240

210

VREGUVLO_RISE

VREGUVLO_FALL

VREGUVLO_HYS

V

mV

Rev. 0 | Page 3 of 24

ADM7150

Data Sheet

Parameter

Symbol

Test Conditions/Comments

Min

Typ Max

Unit

EN INPUT

4.5 V ≤ V_IN≤ 16 V

EN Input Logic High

EN Input Logic Low

EN Input Logic Hysteresis

EN Input Leakage Current

EN_HIGH

EN_LOW

EN_HYS

I_EN-LKG

3.2

V

mV

µA

0.8

1.0

V_IN= 5 V

V_EN= V_INor GND

225

0.1

¹Based on an end-point calculation using 1 mA and 800 mA loads. See Figure 7, Figure 16, and Figure 22 for typical load regulation performance for loads less than 1 mA.

²Current-limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 5.0 V

output voltage is defined as the current that causes the output voltage to drop to 90% of 5.0 V, or 4.5 V.

³Dropout voltage is defined as the input-to-output voltage differential when the input voltage is set to achieve the nominal output voltage. Dropout applies only for

output voltages above 4.5 V.

⁴Start-up time is defined as the time between the rising edge of V_ENto V_OUT, V_REG, or V_REFbeing at 90% of its nominal value.

⁵The output voltage is turned off until the V_REGUVLO rise threshold is crossed. The V_REGoutput is turned off until the input voltage UVLO rise threshold is crossed.

INPUT AND OUTPUT CAPACITOR RECOMMENDED SPECIFICATIONS

Table 2.

Parameter

Symbol

Test Conditions/Comments

Min

Typ

Max

Unit

CAPACITANCE

Minimum Input¹

T_A= −40°C to +125°C

C_IN

7.0

0.1

0.7

µF

Minimum Regulator¹

Minimum Output¹

Minimum Bypass

Minimum Reference

CAPACITOR Equivalent Series Resistance (ESR)

C_REG, C_OUT, C_IN, C_REF

C_BYP

C_REG

C_OUT

C_BYP

C_REF

R_ESR

T_A= −40°C to +125°C

0.001

0.2

2.0

Ω

¹The minimum input, regulator, and output capacitance must be greater than 7.0 μF over the full range of operating conditions. The full range of operating conditions

in the application must be considered during device selection to ensure that the minimum capacitance specification is met. X7R and X5R type capacitors are

recommended; however, Y5V and Z5U capacitors are not recommended for use with any LDO.

Rev. 0 | Page 4 of 24

Data Sheet

ADM7150

ABSOLUTE MAXIMUM RATINGS

Table 3.

Junction to ambient thermal resistance (θ_JA) of the package is

based on modeling and calculation using a 4-layer board. The

junction to ambient thermal resistance is highly dependent on

the application and board layout. In applications where high

maximum power dissipation exists, close attention to thermal

board design is required. The value of θ_JAmay vary, depending

on PCB material, layout, and environmental conditions. The

specified values of θ_JAare based on a 4-layer, 4 in. × 3 in. circuit

board. See JESD51-7 and JESD51-9 for detailed information

on the board construction.

Parameter

VIN to GND

VREG to GND

Rating

−0.3 V to +18 V

−0.3 V to VIN, or +6 V

(whichever is less)

VOUT to GND

−0.3 V to VREG, or +6 V

(whichever is less)

VOUT to BYP

EN to GND

0.3 V

−0.3 V to +18 V

BYP to GND

−0.3 V to VREG, or +6 V

(whichever is less)

Ψ_JBis the junction to board thermal characterization parameter

REF to GND

−0.3 V to VREG, or +6 V

(whichever is less)

−0.3 V to +6 V

−65°C to +150°C

150°C

with units of °C/W. Ψ_JBof the package is based on modeling and the

calculation using a 4-layer board. The JESD51-12, Guidelines for

Reporting and Using Electronic Package Thermal Information,

states that thermal characterization parameters are not the same

as thermal resistances. Ψ_JBmeasures the component power

flowing through multiple thermal paths rather than a single

path as in thermal resistance (θ_JB). Therefore, Ψ_JBthermal paths

include convection from the top of the package as well as

radiation from the package, factors that make Ψ_JBmore useful

in real-world applications. Maximum junction temperature (T_J)

is calculated from the board temperature (T_B) and power

dissipation (P_D) using the formula

REF_SENSE to GND

Storage Temperature Range

Junction Temperature

Operating Ambient Temperature Range

Soldering Conditions

−40°C to +125°C

JEDEC J-STD-020

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

T_J= T_B+ (P_D× Ψ_JB)

See JESD51-8 and JESD51-12 for more detailed information

about Ψ_JB.

THERMAL DATA

Absolute maximum ratings apply individually only, not in

combination. The ADM7150 can be damaged when the

junction temperature limits are exceeded. Monitoring ambient

temperature does not guarantee that T_Jis within the specified

temperature limits. In applications with high power dissipation

and poor thermal resistance, the maximum ambient temperature

may have to be derated.

THERMAL RESISTANCE

θ_JA, θ_JC, and Ψ_JBare specified for the worst-case conditions, that is,

a device soldered in a circuit board for surface-mount packages.

Table 4. Thermal Resistance

Package Type

8-Lead LFCSP

8-Lead SOIC

θ_JA

θ_JC

Ψ_JB

Unit

°C/W

36.7

36.9

23.5

27.1

13.3

18.6

In applications with moderate power dissipation and low

printed circuit board (PCB) thermal resistance, the maximum

ambient temperature can exceed the maximum limit as long as

the junction temperature is within specification limits. The

junction temperature (T_J) of the device is dependent on the

ambient temperature (T_A), the power dissipation of the device

(P_D), and the junction to ambient thermal resistance of the

package (θ_JA).

ESD CAUTION

Maximum junction temperature (T_J) is calculated from the

ambient temperature (T_A) and power dissipation (P_D) using the

formula

T_J= T_A+ (P_D× θ_JA)

Rev. 0 | Page 5 of 24

ADM7150

Data Sheet

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

VREG

VOUT

BYP

1

2

3

4

8

7

6

5

VIN

VREG

VOUT

BYP

1

2

3

4

8

7

6

5

VIN

EN

ADM7150

EN

TOP VIEW

ADM7150

REF

(Not to Scale)

TOP VIEW

REF

(Not to Scale)

GND

REF_SENSE

GND

REF_SENSE

NOTES

1. EXPOSED PAD ON THE BOTTOM OF THE PACKAGE.

EXPOSED PAD ENHANCES THERMAL PERFORMANCE AND IS

ELECTRICALLY CONNECTED TO GND INSIDE THE PACKAGE.

CONNECT THE EXPOSED PAD TO THE GROUND PLANE ON

THE BOARD TO ENSURE PROPER OPERATION.

1. EXPOSED PAD ON THE BOTTOM OF THE PACKAGE.

EXPOSED PAD ENHANCES THERMAL PERFORMANCE AND IS

ELECTRICALLY CONNECTED TO GND INSIDE THE PACKAGE.

CONNECT THE EXPOSED PAD TO THE GROUND PLANE ON

THE BOARD TO ENSURE PROPER OPERATION.

Figure 3. 8-Lead LFCSP Pin Configuration

Figure 4. 8-Lead SOIC Pin Configuration

Table 5. Pin Function Descriptions

Pin No.

Mnemonic

Description

1

VREG

Regulated Input Supply to LDO Amplifier. Bypass VREG to GND with a 10 µF or greater capacitor. Do not connect

a load to ground.

2

3

4

5

6

VOUT

BYP

GND

REF_SENSE

REF

Regulated Output Voltage. Bypass VOUT to GND with a 10 µF or greater capacitor.

Low Noise Bypass Capacitor. Connect a 1 µF capacitor to GND to reduce noise. Do not connect a load to ground.

Ground Connection.

REF_SENSE must be connected to the REF pin for proper operation. Do not connect to VOUT or GND.

Low Noise Reference Voltage Output. Bypass REF to GND with a 1 µF capacitor. Short REF_SENSE to REF for fixed

output voltages. Do not connect a load to ground.

7

8

EN

Enable. Drive EN high to turn on the regulator and drive EN low to turn off the regulator. For automatic startup,

connect EN to VIN.

Regulator Input Supply. Bypass VIN to GND with a 10 µF or greater capacitor.

VIN

EPAD

Exposed Pad on the Bottom of the Package. The exposed pad enhances thermal performance and is electrically

connected to GND inside the package. Connect the exposed pad to the ground plane on the board to ensure

proper operation.

Rev. 0 | Page 6 of 24

Data Sheet

ADM7150

TYPICAL PERFORMANCE CHARACTERISTICS

V_IN= V_OUT+ 1.2 V, or V_IN= 4.5 V, whichever is greater, V_EN= V_IN, I_OUT= 10 mA, C_IN= C_OUT= C_REG= 10 µF, C_REF= C_BYP= 1 µF, T_A= 25°C,

unless otherwise noted.

1.1

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

5.05

5.04

5.03

5.02

5.01

5.00

4.99

4.98

4.97

4.96

4.95

V

= 6.2V

= 6.5V

= 7V

= 10V

= 16V

IN

LOAD = 1mA

LOAD = 10mA

LOAD = 100mA

LOAD = 200mA

LOAD = 400mA

LOAD = 800mA

–0.1

–50

–25

0

25

50

75

100

125

6

8

10

12

14

16

TEMPERATURE (°C)

V

(V)

IN

Figure 5. Shutdown Current vs. Temperature at

Various Input Voltages, V_OUT= 5 V

Figure 8. Output Voltage (V_OUT) vs. Input Voltage (V_IN), V_OUT= 5 V

5.05

5.04

5.03

5.02

5.01

5.00

4.99

4.98

4.97

4.96

4.95

20

LOAD = 1mA

LOAD = 10mA

18

LOAD = 100mA

16

14

12

10

8

LOAD = 200mA

LOAD = 400mA

LOAD = 800mA

LOAD = 1mA

6

LOAD = 10mA

LOAD = 100mA

LOAD = 200mA

LOAD = 400mA

LOAD = 800mA

4

2

0

–40

–5

25

85

125

–40

–5

25

85

125

JUNCTION TEMPERATURE (°C)

Figure 6. Output Voltage (V_OUT) vs. Junction Temperature (T_J), V_OUT= 5 V

Figure 9. Ground Current vs. Junction Temperature (T_J), V_OUT= 5 V

5.05

5.04

5.03

5.02

5.01

5.00

4.99

4.98

4.97

4.96

4.95

10

9

8

7

6

5

4

3

2

1

0

1

10

100

1000

1

10

100

1000

I

(mA)

I

(mA)

LOAD

Figure 7. Output Voltage (V_OUT) vs. Load Current (I_LOAD), V_OUT= 5 V

Figure 10. Ground Current vs. Load Current (I_LOAD), V_OUT= 5 V

Rev. 0 | Page 7 of 24

ADM7150

Data Sheet

12

10

8

10

9

8

7

6

5

4

3

2

1

0

6

4

LOAD = 1mA

I

= 5mA

GND

LOAD = 10mA

LOAD = 100mA

LOAD = 200mA

LOAD = 400mA

LOAD = 800mA

= 10mA

= 100mA

= 200mA

= 400mA

= 800mA

2

0

4.6

5

6

7

8

9

10

V

11

(V)

12

13

14

15

16

4.8

5.0

5.2

5.4

(V)

5.6

5.8

6.0

V

IN

Figure 11. Ground Current vs. Input Voltage (V_IN), V_OUT= 5 V

Figure 14. Ground Current vs. Input Voltage (V_IN) in Dropout, V_OUT= 5 V

700

3.32

3.31

3.30

3.29

600

500

400

300

200

100

0

3.28

LOAD = 1mA

LOAD = 10mA

LOAD = 100mA

LOAD = 200mA

LOAD = 400mA

3.27

LOAD = 800mA

3.26

1

10

100

1000

–40

–5

25

85

125

I

(mA)

JUNCTION TEMPERATURE (°C)

LOAD

Figure 15. Output Voltage (V_OUT) vs. Junction Temperature (T_J), V_OUT= 3.3 V

Figure 12. Dropout Voltage vs. Load Current (I_LOAD), V_OUT= 5 V

3.32

3.31

3.30

3.29

3.28

3.27

3.26

5.2

5.0

4.8

4.6

4.4

V

= 5mA

DROPOUT

= 10mA

= 100mA

= 200mA

= 400mA

= 800mA

4.2

4.0

1

10

100

1000

4.6

4.8

5.0

5.2

5.4

(V)

5.6

5.8

6.0

I

(mA)

V

LOAD

IN

Figure 16. Output Voltage (V_OUT) vs. Load Current (I_LOAD), V_OUT= 3.3 V

Figure 13. Output Voltage (V_OUT) vs. Input Voltage (V_IN) in Dropout, V_OUT= 5 V

Rev. 0 | Page 8 of 24

Data Sheet

ADM7150

3.32

3.31

3.30

3.29

3.28

10

9

8

7

6

5

4

3

2

1

0

LOAD = 1mA

LOAD = 10mA

LOAD = 100mA

LOAD = 200mA

LOAD = 400mA

LOAD = 800mA

LOAD = 10mA

LOAD = 100mA

LOAD = 200mA

LOAD = 400mA

LOAD = 800mA

3.27

3.26

4

6

8

10

(V)

12

14

16

4

6

8

10

(V)

12

14

16

V

IN

Figure 17. Output Voltage (V_OUT) vs. Input Voltage (V_IN), V_OUT= 3.3 V

Figure 20. Ground Current vs. Input Voltage (V_IN), V_OUT= 3.3 V

10

9

1.820

LOAD = 1mA

LOAD = 10mA

LOAD = 100mA

1.815

8

LOAD = 200mA

1.810

1.805

1.800

1.795

1.790

1.785

1.780

LOAD = 400mA

LOAD = 800mA

7

6

5

4

LOAD = 1mA

3

2

1

0

LOAD = 10mA

LOAD = 100mA

LOAD = 200mA

LOAD = 400mA

LOAD = 800mA

–40

–5

25

85

125

–40

–5

25

85

125

JUNCTION TEMPERATURE (°C)

Figure 18. Ground Current vs. Junction Temperature (T_J), V_OUT= 3.3 V

Figure 21. Output Voltage (V_OUT) vs. Junction Temperature (T_J), V_OUT= 1.8 V

1.820

1.815

1.810

1.805

1.800

1.795

1.790

1.785

1.780

10

9

8

7

6

5

4

3

2

1

0

1

10

100

1000

1

10

100

1000

I

(mA)

I

(mA)

LOAD

Figure 19. Ground Current vs. Load Current (I_LOAD), V_OUT= 3.3 V

Figure 22. Output Voltage (V_OUT) vs. Load Current (I_LOAD), V_OUT= 1.8 V

Rev. 0 | Page 9 of 24

ADM7150

Data Sheet

1.820

1.815

1.810

1.805

1.800

1.795

1.790

1.785

10

9

8

7

6

5

4

3

2

1

0

LOAD = 1mA

LOAD = 10mA

LOAD = 100mA

LOAD = 200mA

LOAD = 400mA

LOAD = 800mA

LOAD = 1mA

LOAD = 10mA

LOAD = 100mA

LOAD = 200mA

LOAD = 400mA

LOAD = 800mA

1.780

4

6

8

10

(V)

12

14

16

6

8

10

(V)

12

14

16

V

IN

Figure 26. Ground Current vs. Input Voltage (V_IN), V_OUT= 1.8 V

Figure 23. Output Voltage (V_OUT) vs. Input Voltage (V_IN), V_OUT= 1.8 V

10

9

0

LOAD = 800mA

LOAD = 400mA

LOAD = 200mA

LOAD = 100mA

LOAD = 10mA

–20

8

7

–40

–60

6

5

4

–80

LOAD = 1mA

3

2

1

0

LOAD = 10mA

LOAD = 100mA

LOAD = 200mA

LOAD = 400mA

LOAD = 800mA

–100

–120

–40

–5

25

85

125

1

10

100

1k

10k

100k

1M

10M

JUNCTION TEMPERATURE (°C)

FREQUENCY (Hz)

Figure 24. Ground Current vs. Junction Temperature (T_J), V_OUT=1.8 V

Figure 27. Power Supply Rejection Ratio (PSRR) vs. Frequency,

_OUT= 5 V, V_IN= 6.2 V

V

10

9

8

7

6

5

4

3

2

1

0

400mV

500mV

600mV

700mV

800mV

900mV

1.0V

1.1V

1.2V

1.3V

1.4V

1.5V

–20

–40

–60

–80

–100

–120

1

10

100

1000

1

10

100

1k

10k

100k

1M

10M

I

(mA)

FREQUENCY (Hz)

LOAD

Figure 28. Power Supply Rejection Ratio (PSRR) vs. Frequency for Various

Headroom Voltage, V_OUT= 5 V, 400 mA Load

Figure 25. Ground Current vs. Load Current (I_LOAD), V_OUT= 1.8 V

Rev. 0 | Page 10 of 24

Data Sheet

ADM7150

0

–20

10Hz

100Hz

1kHz

10kHz

100kHz

1MHz

10MHz

LOAD = 800mA

LOAD = 400mA

LOAD = 200mA

LOAD = 100mA

LOAD = 10mA

–20

–40

–60

–80

–100

–120

–100

–120

1

10

100

1k

10k

100k

1M

10M

0.3

0.5

0.7

0.9

1.1

1.3

1.5

FREQUENCY (Hz)

HEADROOM (V)

Figure 29. Power Supply Rejection Ratio (PSRR) vs. Frequency,

_OUT= 3.3 V, V_IN= 5 V

Figure 32. Power Supply Rejection Ratio (PSRR) vs. Headroom Voltage,

400 mA Load, V_OUT= 5 V

V

0

10Hz

100Hz

1kHz

10kHz

100kHz

1MHz

LOAD = 800mA

LOAD = 400mA

LOAD = 200mA

LOAD = 100mA

LOAD = 10mA

–20

–40

10MHz

–40

–60

–80

–100

–120

–100

–120

1

10

100

1k

10k

100k

1M

10M

0.6

0.7

0.8

0.9

1.0

1.1

1.2

1.3

1.4

1.5

1.6

FREQUENCY (Hz)

HEADROOM (V)

Figure 30. Power Supply Rejection Ratio (PSRR) vs. Frequency,

Figure 33. Power Supply Rejection Ratio (PSRR) vs. Headroom Voltage,

800 mA Load, V_OUT= 5 V

V_OUT= 1.8 V, V_IN= 5 V

0

–20

0

10Hz

100Hz

1kHz

10kHz

100kHz

1MHz

10Hz

100Hz

1kHz

10kHz

100kHz

1MHz

10MHz

–10

–20

–40

–30

–40

–50

–60

–70

–60

–80

–100

–120

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

1.1

1.2

1

10

100

1000

HEADROOM (V)

CAPACITANCE (µF)

Figure 31. Power Supply Rejection Ratio (PSRR) vs. Headroom Voltage,

100 mA Load, V_OUT= 5 V

Figure 34. Power Supply Rejection Ratio (PSRR) vs. C_BYP

,

400 mA Load, 400 mV Headroom, V_OUT= 5 V

Rev. 0 | Page 11 of 24

ADM7150

Data Sheet

–40

10

10Hz

100Hz

1kHz

10kHz

100kHz

1MHz

–50

–60

–70

–80

1

–90

–100

–110

–120

1

0.1

1k

10

100

1000

10k

100k

1M

10M

CAPACITANCE (µF)

FREQUENCY (Hz)

Figure 35. Power Supply Rejection Ratio (PSRR) vs. Capacitance (C_BYP),

400 mA Load, 1.2 V Headroom, V_OUT= 5 V

Figure 38. Output Noise Spectral Density,

1 kHz to 10 MHz, I_LOAD= 10 mA

2.0

1.8

1.6

1.4

100k

10k

1k

10Hz TO 100kHz

1.2

1.0

0.8

0.6

0.4

0.2

0

100

10

1

10

100

1000

0.1

1

10

100

1k

10k

100k

LOAD CURRENT (mA)

FREQUENCY (Hz)

Figure 36. RMS Output Noise vs. Load Current (I_LOAD), 10 Hz to 100 kHz

Figure 39. Output Noise Spectral Density,

0.1 Hz to 100 kHz, I_LOAD= 10 mA

2.0

1.8

1.6

1.4

1.2

1k

LOAD = 10mA

LOAD = 100mA

LOAD = 200mA

LOAD = 400mA

LOAD = 800mA

100

10

1

1.0

0.8

0.6

0.4

0.2

0

100Hz TO 100kHz

0.1

10

100

1000

1k

10k

100k

1M

10M

LOAD CURRENT (mA)

FREQUENCY (Hz)

Figure 37. RMS Output Noise vs. Load Current (I_LOAD), 100 Hz to 100 kHz

Figure 40. Output Noise Spectral Density at Different Load Currents,

1 kHz to 10 MHz

Rev. 0 | Page 12 of 24

Data Sheet

ADM7150

100k

10k

1k

T

LOAD = 10mA

LOAD = 100mA

LOAD = 200mA

LOAD = 400mA

LOAD = 800mA

1

100

10

2

1

0.1

B

W

CH1 500mA Ω

CH2 10mV

M4µs

A CH1

200mA

W

1

10

100

1k

10k

100k

T

11.0%

FREQUENCY (Hz)

Figure 44. Load Transient Response, I_LOAD= 10 mA to 800 mA,

_OUT= 5 V, V_IN= 6.2 V, CH1 = I_OUT, CH2 = V_OUT

Figure 41. Output Noise Spectral Density at Different Load Currents,

0.1 Hz to 100 kHz

V

100k

T

C

= 1µF

BYP

= 4.7µF

= 10µF

= 22µF

= 47µF

= 100µF

= 470µF

= 1mF

10k

1k

100

10

1

2

B

W

CH1 200mA Ω

CH2 10mV

M2µs

A CH1

460mA

W

0.1

1

10

100

1k

10k

100k

1M

T

11.0%

FREQUENCY (Hz)

Figure 45. Load Transient Response, I_LOAD= 100 mA to 600 mA,

_OUT= 5 V, V_IN= 6.2 V, CH1 = I_OUT, CH2 = V_OUT

Figure 42. Output Noise Spectral Density at Different C_BYP

,

V

Load Current = 10 mA

T

1

2

1

2

B

W

B

W

CH1 50.0mA Ω

CH2 2.0mV

M4µs

A CH1

50.0mA

CH1 500mA Ω

CH2 20mV

M20µs

A CH1

200mA

W

T

10.0%

T

10.40%

Figure 46. Load Transient Response, I_LOAD= 1 mA to100 mA,

_OUT= 5 V, V_IN= 6.2 V, CH1 = I_OUT, CH2 = V_OUT

Figure 43. Load Transient Response, I_LOAD= 1 mA to 800 mA,

_OUT= 5 V, V_IN= 6.2 V, CH1 = I_OUT, CH2 = V_OUT

V

Rev. 0 | Page 13 of 24

ADM7150

Data Sheet

T

1

2

B

CH2 2.0mV Ω

W

CH1 1.0V

CH2 2.0mV Ω

M10µs

10.0%

A CH1

1.14V

CH1 1.0V

M10µs

10.0%

A CH3

1.14V

W

T

Figure 47. Line Transient Response, 2 V Input Step, I_LOAD= 800 mA,

_OUT= 1.8 V, V_IN= 4.5 V, CH1 = V_IN, CH2 = V_OUT

Figure 49. Line Transient Response, 2 V Input Step, I_LOAD= 800 mA,

V

V_OUT= 5 V, V_IN= 6.2 V, CH1 = V_IN, CH2 = V_OUT

5.5

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

T

1

2

V

EN

REG

REF

OUT

–0.5

B

W

CH1 1.0V

CH2 2.0mV Ω

M10µs

10.0%

A CH3

1.14V

W

0

1

2

3

4

5

6

7

8

9

10

T

TIME (ms)

Figure 50. V_OUT, V_REF, V_REGStart-Up Time After V_ENRising, V_OUT= 3.3 V, V_IN= 5 V

Figure 48. Line Transient Response, 2 V Input Step, I_LOAD= 800 mA,

_OUT= 3.3 V, V_IN= 4.5 V, CH1 = V_IN, CH2 = V_OUT

V

Rev. 0 | Page 14 of 24

Data Sheet

ADM7150

THEORY OF OPERATION

The ADM7150 is an ultralow noise, high power supply rejection

ratio (PSRR) linear regulator targeting radio frequency (RF)

applications. The input voltage range is 4.5 V to 16 V, and it can

deliver up to 800 mA of output current. Typical shutdown current

consumption is 0.1 µA at room temperature.

By heavily filtering the reference voltage, the ADM7150 is able

to achieve 1.7 nV/√Hz output typical from 10 kHz to 1 MHz.

Because the error amplifier is always in unity gain, the output

noise is independent of the output voltage.

To maintain very high PSRR over a wide frequency range, the

ADM7150 architecture uses an internal active ripple filter. This

stage isolates the low output noise LDO from noise on VIN.

The result is that the PSRR of the ADM7150 is significantly

higher over a wider frequency range than any single stage LDO.

Optimized for use with 10 µF ceramic capacitors, the ADM7150

provides excellent transient performance.

ACTIVE

RIPPLE

FILTER

VIN

VOUT

SHORT CIRCUIT,

THERMAL

The ADM7150 uses the EN pin to enable and disable the VOUT

pin under normal operating conditions. When EN is high, VOUT

turns on, and when EN is low, VOUT turns off. For automatic

startup, EN can be tied to VIN.

VREG

BYP

PROTECT

GND

OTA

REFERENCE

E/A

VIN

18V

REF_SENSE

REF

VREG

SHUTDOWN

EN

6V

REF

Figure 51. Simplified Internal Block Diagram

REF_SENSE

BYP

6V

Internally, the ADM7150 consists of a reference, an error amplifier,

and a P-channel MOSFET pass transistor. Output current is

delivered via the PMOS pass device, which is controlled by the

error amplifier. The error amplifier compares the reference

voltage with the feedback voltage from the output and amplifies

the difference. If the feedback voltage is lower than the reference

voltage, the gate of the PMOS device is pulled lower, allowing

more current to pass and increasing the output voltage. If the

feedback voltage is higher than the reference voltage, the gate of

the PMOS device is pulled higher, allowing less current to pass

and decreasing the output voltage.

6V

OUT

EN

18V

6V

18V

GND

Figure 52. Simplified ESD Protection Block Diagram

The ESD protection devices are shown in the block diagram as

Zener diodes (see Figure 52).

Rev. 0 | Page 15 of 24

ADM7150

Data Sheet

APPLICATIONS INFORMATION

CAPACITOR SELECTION

BYP Capacitor

The BYP capacitor is necessary to filter the reference buffer. A

1 µF capacitor is typically connected between BYP and GND.

Capacitors as small as 0.1 µF can be used; however, the output

noise voltage of the LDO increases as a result.

Output Capacitor

The ADM7150 is designed for operation with ceramic capacitors

but functions with most commonly used capacitors as long as

care is taken with regard to the effective series resistance (ESR)

value. The ESR of the output capacitor affects the stability of the

LDO control loop. A minimum of 10 µF capacitance with an

ESR of 0.2 Ω or less is recommended to ensure the stability of the

ADM7150. Output capacitance also affects transient response to

changes in load current. Using a larger value of output capacitance

improves the transient response of the ADM7150 to large changes

in load current. Figure 53 shows the transient responses for an

output capacitance value of 10 µF.

In addition, the BYP capacitor value can be increased to reduce

the noise below 1 kHz at the expense of increasing the start-up

time of the LDO. Very large values of C_BYPsignificantly reduce

the noise below 10 Hz. Tantalum capacitors are recommended for

capacitors larger than approximately 33 µF. A 1 μF ceramic

capacitor in parallel with the larger tantalum capacitor is required

to retain good noise performance at higher frequencies. Solid

tantalum capacitors are less prone to microphonic noise issues.

100k

C

= 1µF

T

BYP

= 4.7µF

= 10µF

= 22µF

= 47µF

= 100µF

= 470µF

= 1mF

10k

1k

100

10

1

2

B

W

CH1 500mA Ω

CH2 10mV

M4µs

11.0%

A CH1

200mA

W

0.1

1

10

100

1k

10k

100k

1M

T

FREQUENCY (Hz)

Figure 53. Output Transient Response, V_OUT= 5 V, C_OUT= 10 µF,

CH1 = Load Current, CH2 = V_OUT

Figure 54. Noise Spectral Density vs. Frequency, C_BYP= 1 µF to 1 mF

10k

1Hz

3Hz

Input and VREG Capacitor

10Hz

100Hz

400Hz

30Hz

300Hz

1kHz

Connecting a 10 µF capacitor from VIN to GND reduces the

circuit sensitivity to PCB layout, especially when long input

traces or high source impedance are encountered.

1k

100

10

To maintain the best possible stability and PSRR performance,

connect a 10 µF capacitor from VREG to GND. When more

than 10 µF of output capacitance is required, increase the input

and VREG capacitors to match it.

REF Capacitor

The REF capacitor is necessary to stabilize the reference amplifier.

Connect at least a 1 µF capacitor between REF and GND.

1

10

100

1000

C

(µF)

BYP

Figure 55. Noise Spectral Density vs. Capacitance (C_BYP) for

Different Frequencies

Rev. 0 | Page 16 of 24

Data Sheet

ADM7150

Capacitor Properties

Substituting these values in Equation 1 yields

_EFF= 9.72 µF × (1 − 0.15) × (1 − 0.1) = 7.44 µF

Any good quality ceramic capacitors can be used with the

ADM7150 as long as they meet the minimum capacitance

and maximum ESR requirements. Ceramic capacitors are

manufactured with a variety of dielectrics, each with different

behavior over temperature and applied voltage. Capacitors must

have a dielectric adequate to ensure the minimum capacitance

over the necessary temperature range and dc bias conditions.

X5R or X7R dielectrics with a voltage rating of 6.3 V to 50 V

are recommended. However, Y5V and Z5U dielectrics are

not recommended due to their poor temperature and dc bias

characteristics.

C

Therefore, the capacitor chosen in this example meets the

minimum capacitance requirement of the LDO over

temperature and tolerance at the chosen output voltage.

To guarantee the performance of the ADM7150, it is imperative

that the effects of dc bias, temperature, and tolerances on the

behavior of the capacitors be evaluated for each application.

ENABLE (EN) AND UNDERVOLTAGE LOCKOUT

(UVLO)

The ADM7150 uses the EN pin to enable and disable the VOUT

pin under normal operating conditions. As shown in Figure 57,

when a rising voltage on EN crosses the upper threshold, VOUT

turns on. When a falling voltage on EN crosses the lower threshold,

VOUT turns off. The hysteresis varies as a function of the input

voltage. For example, the EN hysteresis is approximately 200 mV

with an input voltage of 4.5 V.

Figure 56 depicts the capacitance vs. dc bias voltage of a 1206,

10 µF, 10 V, X5R capacitor. The voltage stability of a capacitor is

strongly influenced by the capacitor size and voltage rating. In

general, a capacitor in a larger package or higher voltage rating

exhibits better stability. The temperature variation of the X5R

dielectric is ~ 15% over the −40°C to +85°C temperature range

and is not a function of package or voltage rating.

12

3.5

3.0

2.5

10

8

2.0

VOUT_EN_FALL

1.5

6

VOUT_EN_RISE

1.0

4

0.5

2

0

1.0

1.1

1.2

1.3

(V)

1.4

1.5

1.6

0

V

0

2

4

6

8

10

EN

DC BIAS VOLTAGE (V)

Figure 57. Typical V_OUTResponse to EN Pin Operation, V_OUT= 3.3 V, V_IN= 5 V

Figure 56. Capacitance vs. DC Bias Voltage

3.2

Use Equation 1 to determine the worst-case capacitance

accounting for capacitor variation over temperature,

component tolerance, and voltage.

3.0

2.8

2.6

C

_EFF= C_BIAS× (1 − TEMPCO) × (1 − TOL)

where:

_BIASis the effective capacitance at the operating voltage.

(1)

–40°C

2.4

2.2

2.0

+125°C

+25°C

C

TEMPCO is the worst-case capacitor temperature coefficient.

TOL is the worst-case component tolerance.

1.8

1.6

1.4

In this example, the worst-case temperature coefficient

(TEMPCO) over −40°C to +85°C is assumed to be 15% for an

X5R dielectric. The tolerance of the capacitor (TOL) is assumed

to be 10%, and C_BIASis 9.72 µF at 5 V, as shown in Figure 56.

6

8

10

12

14

16

V

(V)

IN

Figure 58. Typical EN Rise Threshold vs. Input Voltage (V_IN) for Various

Temperatures

Rev. 0 | Page 17 of 24

ADM7150

Data Sheet

2.4

2.2

2.0

1.8

1.6

1.4

1.2

START-UP TIME

The ADM7150 uses an internal soft start to limit the inrush

current when the output is enabled. The start-up time for a 5 V

output is approximately 3 ms from the time the EN active threshold

is crossed to when the output reaches 90% of its final value.

–40°C

The rise time of the output voltage (10% to 90%) is approximately

0.0012 × C_BYPseconds

+25°C

+125°C

where C_BYPis in microfarads.

6

ENABLE

C

= 1µF

= 4.7µF

= 10µF

BYP

5

4

3

2

1

0

1.0

6

8

10

12

14

16

V

(V)

IN

Figure 59. Typical EN Fall Threshold vs. Input Voltage (V_IN) for Various

Temperatures

The ADM7150 also incorporates an internal undervoltage

lockout circuit to disable the output voltage when the input

voltage is less than the minimum input voltage rating of the

regulator. The upper and lower thresholds are internally fixed

with about 300 mV of hysteresis.

3.5

0

0.002 0.004 0.006 0.008 0.010 0.012 0.014 0.016 0.018 0.020

TIME (Seconds)

3.0

Figure 61. Typical Start-Up Behavior with C_BYP= 1 µF to 10 µF

2.5

6

VOUT_VIN_FALL

2.0

5

4

3

2

1.5

VOUT_VIN_RISE

1.0

0.5

0

4.0

4.1

4.2

4.3

4.4

4.5

V

(V)

1

0

ENABLE

IN

C

= 10µF

= 47µF

= 330µF

BYP

Figure 60. Typical UVLO Hysteresis, V_OUT= 3.3 V

0

0.02 0.04 0.06 0.08 0.10 0.12 0.14 0.16 0.18 0.20

TIME (Seconds)

Figure 60 shows the typical hysteresis of the UVLO function.

This hysteresis prevents on/off oscillations that can occur due to

noise on the input voltage as it passes through the threshold

points.

Figure 62. Typical Start-Up Behavior with C_BYP= 10 µF to 330 µF

REF, BYP, AND, VREG PINS

REF, BYP, and VREG are internally generated voltages that

require external bypass capacitors for proper operation. Do not,

under any circumstances, connect any loads to these pins because

doing so compromises the noise and PSRR performance of the

ADM7150. Using larger values of C_BYP, C_REF, and C_REGis acceptable

but can increase the start-up time as described in the Start-Up

Time section.

Rev. 0 | Page 18 of 24

Data Sheet

ADM7150

between the junction and ambient air (θ_JA). The θ_JAnumber is

dependent on the package assembly compounds that are used

and the amount of copper used to solder the package GND pin

and exposed pad to the PCB.

CURRENT-LIMIT AND THERMAL OVERLOAD

PROTECTION

The ADM7150 is protected against damage due to excessive

power dissipation by current and thermal overload protection

circuits. The ADM7150 is designed to current-limit when the

output load reaches 1.2 A (typical). When the output load

exceeds 1.2 A, the output voltage is reduced to maintain a

constant current limit.

Table 6 shows typical θ_JAvalues of the 8-lead SOIC and 8-lead

LFCSP packages for various PCB copper sizes.

Table 7 shows the typical Ψ_JBvalues of the 8-lead SOIC and

8-lead LFCSP.

Thermal overload protection is included, which limits the

junction temperature to a maximum of 155°C (typical). Under

extreme conditions (that is, high ambient temperature and/or

high power dissipation) when the junction temperature starts to

rise above 155°C, the output is turned off, reducing the output

current to zero. When the junction temperature drops below

140°C, the output is turned on again, and output current is

restored to its operating value.

Table 6. Typical θ_JAValues

θ_JA(°C/W)

Copper Size (mm^±)

25¹

8-Lead LFCSP

165.1

8-Lead SOIC

165

126.4

69.8

57.8

43.6

100

125.8

500

68.1

1000

6400

56.4

42.1

Consider the case where a hard short from VOUT to GND occurs.

At first, the ADM7150 current limits, so that only 1.2 A is

conducted into the short. If self heating of the junction is great

enough to cause its temperature to rise above 155°C, thermal

shutdown activates, turning off the output and reducing the

output current to zero. As the junction temperature cools and

drops below 140°C, the output turns on and conducts 1.2 A into

the short, again causing the junction temperature to rise above

155°C. This thermal oscillation between 140°C and 155°C

causes a current oscillation between 1.2 A and 0 mA that

continues as long as the short remains at the output.

¹Device soldered to minimum size pin traces.

Table 7. Typical Ψ_JBValues

Package

Ψ_JB(°C/W)

8-Lead LFCSP

8-Lead SOIC

15.1

17.9

The junction temperature of the ADM7150 is calculated from

the following equation:

T_J= T_A+ (P_D× θ_JA)

(2)

where:

T_Ais the ambient temperature.

P_Dis the power dissipation in the die, given by

Current-limit and thermal limit protections are intended to

protect the device against accidental overload conditions. For

reliable operation, device power dissipation must be externally

limited so that the junction temperature does not exceed 150°C.

P_D= [(V_IN− V_OUT) × I_LOAD] + (V_IN× I_GND

where:

_INand V_OUTare the input and output voltages, respectively.

)

(3)

V

THERMAL CONSIDERATIONS

I_LOADis the load current.

In applications with low input to output voltage differential, the

ADM7150 does not dissipate much heat. However, in applications

with high ambient temperature and/or high input voltage, the

heat dissipated in the package may become large enough that it

causes the junction temperature of the die to exceed the maximum

junction temperature of 150°C.

I_GNDis the ground current.

Power dissipation due to ground current is quite small and can

be ignored. Therefore, the junction temperature equation simplifies

to the following:

T_J= T_A+ {[(V_IN− V_OUT) × I_LOAD] × θ_JA}

(4)

When the junction temperature exceeds 155°C, the converter

enters thermal shutdown. It recovers only after the junction

temperature decreases below 140°C to prevent any permanent

damage. Therefore, thermal analysis for the chosen application

is important to guarantee reliable performance over all conditions.

The junction temperature of the die is the sum of the ambient

temperature of the environment and the temperature rise of the

package due to the power dissipation, as shown in Equation 2.

As shown in Equation 4, for a given ambient temperature, input

to output voltage differential, and continuous load current, there

exists a minimum copper size requirement for the PCB to ensure

that the junction temperature does not rise above 150°C.

The heat dissipation from the package can be improved by

increasing the amount of copper attached to the pins and

exposed pad of the ADM7150. Adding thermal planes under

the package also improves thermal performance. However, as

listed in Table 6, a point of diminishing returns is eventually

reached, beyond which an increase in the copper area does not

yield significant reduction in the junction to ambient thermal

resistance.

To guarantee reliable operation, the junction temperature of the

ADM7150 must not exceed 150°C. To ensure that the junction

temperature stays below this maximum value, the user must be

aware of the parameters that contribute to junction temperature

changes. These parameters include ambient temperature, power

dissipation in the power device, and thermal resistances

Rev. 0 | Page 19 of 24

ADM7150

Data Sheet

155

145

135

125

115

102

95

Figure 63 to Figure 68 show junction temperature calculations for

different ambient temperatures, power dissipation, and areas of

PCB copper.

155

145

135

125

115

105

95

85

75

65

55

2

6400mm

85

2

45

500mm

75

2

25mm

35

T

MAX

65

J

25

55

45

35

25

0

0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0

TOTAL POWER DISSIPATION (W)

2

6400mm

2

500mm

2

25mm

Figure 66. Junction Temperature vs. Total Power Dissipation for

the 8-Lead SOIC, T_A= 25°C

T

MAX

J

0

0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0

TOTAL POWER DISSIPATION (W)

160

150

140

130

120

110

100

90

Figure 63. Junction Temperature vs. Total Power Dissipation for

the 8-Lead LFCSP, T_A= 25°C

160

150

140

130

120

110

100

90

80

2

6400mm

70

2

500mm

2

25mm

60

50

T

MAX

J

80

0

0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4

TOTAL POWER DISSIPATION (W)

2

6400mm

70

2

500mm

2

25mm

60

50

Figure 67. Junction Temperature vs. Total Power Dissipation for

the 8-Lead SOIC, T_A= 50°C

T

MAX

J

0

0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4

TOTAL POWER DISSIPATION (W)

155

145

135

125

115

105

95

Figure 64. Junction Temperature vs. Total Power Dissipation for

the 8-Lead LFCSP, T_A= 50°C

155

145

135

125

115

105

95

85

75

65

2

6400mm

2

500mm

2

25mm

T

MAX

1.8

J

0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

2.0

85

75

65

2

6400mm

TOTAL POWER DISSIPATION (W)

2

500mm

2

25mm

Figure 68. Junction Temperature vs. Total Power Dissipation for

the 8-Lead SOIC, T_A= 85°C

T

MAX

J

0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5

TOTAL POWER DISSIPATION (W)

Figure 65. Junction Temperature vs. Total Power Dissipation for

the 8-Lead LFCSP, T_A= 85°C

Rev. 0 | Page 20 of 24

Data Sheet

ADM7150

Thermal Characterization Parameter (Ψ_JB)

PRINTED CIRCUIT BOARD LAYOUT

CONSIDERATIONS

When board temperature is known, use the thermal

characterization parameter, Ψ_JB, to estimate the junction

temperature rise (see Figure 69 and Figure 70). Maximum

junction temperature (T_J) is calculated from the board temperature

(T_B) and power dissipation (P_D) using the following formula:

Place the input capacitor as close as possible to the VIN and GND

pins. Place the output capacitor as close as possible to the VOUT

and GND pins. Place the bypass capacitors for V_REG, V_REF, and

V

_BYPclose to the respective pins and GND. Use of an 0805,

0603, or 0402 size capacitor achieves the smallest possible

footprint solution on boards where area is limited.

T_J= T_B+ (P_D× Ψ_JB)

(5)

The typical value of Ψ_JBis 15.1°C/W for the 8-lead LFCSP

package and 17.9°C/W for the 8-lead SOIC package.

160

140

120

100

80

60

T

= 25°C

= 50°C

= 65°C

= 85°C

MAX

B

J

40

20

0

0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0

TOTAL POWER DISSIPATION (W)

Figure 69. Junction Temperature vs. Total Power Dissipation for

the 8-Lead LFCSP

Figure 71. Example 8-Lead LFCSP PCB Layout

160

140

120

100

80

60

T

= 25°C

= 50°C

= 65°C

= 85°C

MAX

B

J

40

20

0

0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5

TOTAL POWER DISSIPATION (W)

Figure 70. Junction Temperature vs. Total Power Dissipation for

the 8-Lead SOIC

Figure 72. Example 8-Lead SOIC PCB Layout

Rev. 0 | Page 21 of 24

ADM7150

Data Sheet

OUTLINE DIMENSIONS

2.44

2.34

2.24

3.10

3.00 SQ

2.90

0.50 BSC

8

5

PIN 1 INDEX

EXPOSED

PAD

1.70

1.60

1.50

AREA

0.50

0.40

0.30

0.20 MIN

4

1

PIN 1

TOP VIEW

BOTTOM VIEW

INDICATOR

(R 0.15)

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

0.80

0.75

0.70

0.05 MAX

0.02 NOM

COPLANARITY

0.08

SECTION OF THIS DATA SHEET.

SEATING

PLANE

0.30

0.25

0.20

0.203 REF

COMPLIANT TO JEDEC STANDARDS MO-229-WEED

Figure 73. 8-Lead Lead Frame Chip Scale Package [LFCSP_WD]

3 mm × 3 mm Body, Very Very Thin, Dual Lead

(CP-8-11)

Dimensions shown in millimeters

5.00

4.90

4.80

3.098

0.356

5

6.20

6.00

5.80

8

1

4.00

3.90

3.80

2.41

0.457

4

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

BOTTOM VIEW

45°

1.27 BSC

3.81 REF

TOP VIEW

SECTION OF THIS DATA SHEET.

1.65

1.25

1.75

1.35

0.50

0.25

0.17

0.10 MAX

0.05 NOM

SEATING

PLANE

8°

0°

0.51

0.31

1.04 REF

COPLANARITY

0.10

1.27

0.40

COMPLIANT TO JEDEC STANDARDS MS-012-AA

Figure 74. 8-Lead Standard Small Outline Package, with Exposed Pad [SOIC_N_EP]

Narrow Body

(RD-8-2)

Dimensions shown in millimeters

ORDERING GUIDE

Model¹

Temperature Range

−40°C to +125°C

Output Voltage

Package Description

8-Lead LFCSP_WD

Package Option

Branding

LP3

LNA

LNL

LNM

LNB

ADM7150ACPZ-1.8-R2

ADM7150ACPZ-3.3-R2

ADM7150ACPZ-4.5-R2

ADM7150ACPZ-4.8-R2

ADM7150ACPZ-5.0-R2

1.8

3.3

4.5

4.8

5.0

CP-8-11

Rev. 0 | Page 22 of 24

Data Sheet

ADM7150

Model¹

Temperature Range

−40°C to +125°C

Output Voltage

Package Description

8-Lead LFCSP_WD

8-Lead SOIC_N_EP

Evaluation Board

Package Option

CP-8-11

RD-8-2

Branding

LP3

LNA

LNL

LNM

LNB

ADM7150ACPZ-1.8-R7

ADM7150ACPZ-3.3-R7

ADM7150ACPZ-4.5-R7

ADM7150ACPZ-4.8-R7

ADM7150ACPZ-5.0-R7

ADM7150ARDZ-1.8

ADM7150ARDZ-2.8

ADM7150ARDZ-3.0

ADM7150ARDZ-3.3

ADM7150ARDZ-5.0

ADM7150ARDZ-3.0-R7

ADM7150ARDZ-3.3-R7

ADM7150ARDZ-5.0-R7

ADM7150CP-EVALZ

1.8

3.3

4.5

4.8

5.0

1.8

2.8

3.0

3.3

5.0

3.0

3.3

5.0

RD-8-2

¹Z = RoHS Compliant Part.

Rev. 0 | Page 23 of 24

ADM7150

NOTES

Data Sheet

registered trademarks are the property of their respective owners.

D11043-0-9/13(0)

Rev. 0 | Page 24 of 24


型号：	ADM7150ACPZ-1.8-R7
厂家：	ADI
描述：	800 mA, Ultra Low Noise/High PSRR LDO 光电二极管输出元件调节器
文件：	总25页 (文件大小：827K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADM7150ACPZ-1.8-R7 [ADI]

相关型号：

SI9130DB

SI9135LG-T1

SI9135LG-T1-E3

SI9135_11

SI9136_11

SI9130CG-T1-E3

SI9130LG-T1-E3

SI9130_11

SI9137

SI9137DB

SI9137LG

SI9122E