ADM7154ACPZ-1.8-R7_技术文档

600 mA, Ultralow Noise,

High PSRR, RF Linear Regulator

ADM7154

Data Sheet

FEATURES

TYPICAL APPLICATION CIRCUIT

Input voltage range: 2.3 V to 5.5 V

Maximum load current: 600 mA

Low noise

0.9 µV rms total integrated noise from 100 Hz to 100 kHz

1.6 µV rms total integrated noise from 10 Hz to 100 kHz

Noise spectral density: 1.5 nV/√Hz from 10 kHz to 1 MHz

PSRR of 90 dB from 200 Hz to 200 kHz; 58 dB at 1 MHz,

ADM7154

V

= 3.8V

V

= 3.3V

OUT

IN

VIN

VOUT

C

OUT

10µF

IN

10µF

ON

EN

REF

C

REF

OFF

1µF

BYP REF_SENSE

C

BYP

1µF

VREG

GND

C

REG

V

_OUT= 3.3 V, V_IN= 3.8 V

10µF

Dropout voltage: 120 mV typical at V_OUT= 3.3 V, I_OUT= 600 mA

Initial accuracy: 0.5%

Accuracy over line, load, and temperature: −2.0% (minimum),

+1.5% (maximum), from −40°C to +85°C

Quiescent current, I_GND= 4 mA at no load

Low shutdown current: 0.2 μA

Stable with a 10 µF ceramic output capacitor

Adjustable and fixed output voltage options: 1.2 V, 1.8 V, 2.5 V,

2.8 V, 3.0 V, 3.3 V (16 standard voltages between 1.2 V and

3.3 V available)

8-lead LFCSP and 8-lead SOIC packages

Precision enable

Figure 1. Regulated 3.3 V Output from 3.8 V Input

10k

NOISE FLOOR

1.0µF

3.3µF

10µF

1k

100

10

33µF

100µF

330µF

1000µF

Supported by ADIsimPower tool

1

APPLICATIONS

0.1

Regulation to noise sensitive applications: PLLs, VCOs, and

PLLs with integrated VCOs

1

10

100

1k

10k

100k

1M

FREQUENCY (Hz)

Communications and infrastructure

Backhaul and microwave links

Figure 2. Noise Spectral Density for Different Values of C_BYP

GENERAL DESCRIPTION

The ADM7154 is a linear regulator that operates from 2.3 V to

5.5 V and provides up to 600 mA of load current. Using an

advanced proprietary architecture, it provides high power

supply rejection and ultralow noise, achieving excellent line and

load transient response with only a 10 µF ceramic output capacitor.

The ADM7154 is available in 8-lead, 3 mm × 3 mm LFCSP and

8-lead SOIC packages, making it not only a very compact

solution, but also providing excellent thermal performance for

applications requiring up to 600 mA of load current in a small,

low profile footprint.

There are 16 standard output voltages for the ADM7154. The

following voltages are available in stock: 1.2 V, 1.8 V, 2.5 V, 2.8 V,

3.0 V, and 3.3 V. Additional voltages are available by special

order: 1.3 V, 1.5 V, 1.6 V, 2.0 V, 2.2 V, 2.6 V, 2.7 V, 2.9 V, 3.1 V,

and 3.2 V.

Table 1. Related Devices

Input

Voltage

Output

Fixed/

Model

Current Adj¹

Package

ADM7150ACP 4.5 V to 16 V

ADM7150ARD 4.5 V to 16 V

ADM7151ACP 4.5 V to 16 V

ADM7151ARD 4.5 V to 16 V

ADM7155ACP 2.3 V to 5.5 V 600 mA

ADM7155ARD 2.3 V to 5.5 V 600 mA

800 mA

Fixed

Adj

8-Lead LFCSP

8-Lead SOIC

8-Lead LFCSP

8-Lead SOIC

8-Lead LFCSP

8-Lead SOIC

The ADM7154 regulator typical output noise is 0.9 μV rms from

100 Hz to 100 kHz for fixed output voltage options and

1.5 nV/√Hz for noise spectral density from 10 kHz to 1 MHz.

Adj

¹Adj means adjustable.

Rev. B

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ADM7154* PRODUCT PAGE QUICK LINKS

Last Content Update: 11/29/2017

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REFERENCE MATERIALS

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up to 400 MHz

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DOCUMENTATION

Data Sheet

• ADM7154: 600 mA, Ultralow Noise, High PSRR, RF Linear

Regulator Data Sheet

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ADM7154

Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications Information .............................................................. 15

ADIsimPower Design Tool ....................................................... 15

Capacitor Selection .................................................................... 15

Undervoltage Lockout (UVLO) ............................................... 16

Programmable Precision Enable .............................................. 17

Start-Up Time ............................................................................. 17

REF, BYP, and VREG Pins......................................................... 18

Current-Limit and Thermal Overload Protection................. 18

Thermal Considerations............................................................ 18

PCB Layout Considerations.......................................................... 21

Outline Dimensions ....................................................................... 22

Ordering Guide .......................................................................... 23

Applications....................................................................................... 1

Typical Application Circuit ............................................................. 1

General Description......................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Absolute Maximum Ratings............................................................ 5

Thermal Data ................................................................................ 5

Thermal Resistance ...................................................................... 5

ESD Caution.................................................................................. 5

Pin Configurations and Function Descriptions ........................... 6

Typical Performance Characteristics ............................................. 7

Theory of Operation ...................................................................... 14

REVISION HISTORY

8/2016—Rev. A to Rev. B

Changes to Programmable Precision Enable Section and

Figure 52 .......................................................................................... 17

12/2014—Rev. 0 to Rev. A

Changes to Figure 35 to Figure 40................................................ 12

Changes to Figure 44...................................................................... 15

10/2014—Revision 0: Initial Version

Rev. B | Page 2 of 23

Data Sheet

ADM7154

SPECIFICATIONS

V_IN= V_OUT+ 0.5 V or 2.3 V, whichever is greater; EN = V_IN; I_LOAD= 10 mA; C_IN= C_OUT= C_REG= 10 µF; C_REF= C_BYP= 1 µF; T_A= 25°C for

typical specifications; T_J= −40°C to +125°C for minimum/maximum specifications, unless otherwise noted.

Table 2.

Parameter

Symbol

V_IN

Test Conditions/Comments

Min

Typ Max

Unit

V

INPUT VOLTAGE RANGE

LOAD CURRENT

2.3

5.5

I_LOAD

600

mA

µA

OPERATING SUPPLY CURRENT

I_GND

I_LOAD= 0 µA

I_LOAD= 600 mA

EN = GND

4.0

6.5

0.2

7.0

10

2

SHUTDOWN CURRENT

NOISE

I_{IN_SD}

Output Noise

OUT_NOISE

10 Hz to 100 kHz, V_OUT= 1.2 V to 3.3 V

100 Hz to 100 kHz, V_OUT= 1.2 V to 3.3 V

10 kHz to 1 MHz, V_OUT= 1.2 V to 3.3 V

200 Hz to 200 kHz, V_IN= 3.8 V, V_OUT= 3.3 V,

1.6

0.9

1.5

90

µV rms

nV/√Hz

dB

Noise Spectral Density

OUT_NSD

PSRR

POWER SUPPLY REJECTION RATIO

I

_LOAD= 400 mA

1 MHz, V_IN= 3.8 V, V_OUT= 3.3 V, I_LOAD= 400 mA

200 Hz to 200 kHz, V_IN= 2.3 V, V_OUT= 1.8 V,

58

90

dB

I

_LOAD= 400 mA

1 MHz, V_IN= 2.3 V, V_OUT= 1.8 V, I_LOAD= 400 mA

V_OUT= V_REF

I_LOAD= 10 mA, T_J= +25°C

1 mA < I_LOAD< 600 mA, T_J= −40°C to +85°C

1 mA < I_LOAD< 600 mA

63

dB

OUTPUT VOLTAGE ACCURACY

Initial Accuracy

V_OUT

−0.5

−2.0

+0.5

+1.5

+2.0

%

REGULATION

Line

∆V_OUT/∆V_IN

V_IN= V_OUT+ 0.5 V or 2.3 V, whichever is greater,

to 5.5 V

I_OUT= 1 mA to 600 mA

−0.02

+0.02 %/V

Load¹

∆V_OUT/∆I_OUT

I_LIMIT

0.3

1.6

%/A

CURRENT-LIMIT THRESHOLD²

V_REF

V_OUT

22

960

80

mA

mV

700

1200

130

210

DROPOUT VOLTAGE ³

V_DROPOUT

I_OUT= 400 mA, V_OUT= 3.3 V

I_OUT= 600 mA, V_OUT= 3.3 V

120

PULL-DOWN RESISTANCE

VOUT

REG

REF

BYP

V_{OUT_PULL}

V_{REG_PULL}

V_{REF_PULL}

V_{BYP_PULL}

EN = 0 V, V_OUT= 1 V, V_IN= 5.5 V

EN = 0 V, V_REG= 1 V, V_IN= 5.5 V

EN = 0 V, V_REF= 1 V, V_IN= 5.5 V

EN = 0 V, V_BYP= 1 V, V_IN= 5.5 V

550

33

620

400

Ω

kΩ

Ω

START-UP TIME⁴

V_OUT

V_REG

V_REF

t_STARTUP

t_{REG_STARTUP}

t_{REF_STARTUP}

V_OUT= 3.3 V

1.2

0.55

0.44

ms

THERMAL SHUTDOWN

Threshold

Hysteresis

TS_SD

TS_{SD_HYS}

T_Jrising

150

15

°C

UNDERVOLTAGE THRESHOLDS

Input Voltage

Rising

Falling

Hysteresis

UVLO_RISE

UVLO_FALL

UVLO_HYS

2.29

V

mV

1.95

200

Rev. B | Page 3 of 23

ADM7154

Data Sheet

Parameter

Symbol

Test Conditions/Comments

Min

Typ Max

Unit

V_REGTHRESHOLDS⁵

Rising

Falling

Hysteresis

V_{REG_UVLORISE}

V_{REG_UVLOFALL}

V_{REG_UVLOHYS}

1.94

V

mV

1.60

185

PRECISION EN INPUT

Logic High

Logic Low

Logic Hysteresis

Leakage Current

2.3 V ≤ V_IN≤ 5.5 V

EN = V_INor GND

EN_HIGH

EN_LOW

EN_HYS

I_{EN_LKG}

1.13

1.05

1.22 1.31

1.13 1.22

90

V

mV

µA

0.01

1

¹Based on an endpoint calculation using 1 mA and 600 mA loads.

²Current-limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 3.0 V

output voltage is defined as the current that causes the output voltage to drop to 90% of 3.0 V, or 2.7 V.

³Dropout voltage is defined as the input-to-output voltage differential when the input voltage is set to the nominal output voltage. Dropout applies only for output

voltages above 2.3 V.

⁴Start-up time is defined as the time between the rising edge of V_ENto V_OUT, V_REG, or V_REFbeing at 90% of the nominal value.

⁵The output voltage is disabled until the V_REGUVLO rise threshold is crossed. The V_REGoutput is disabled until the input voltage UVLO rising threshold is crossed.

Table 3. Input and Output Capacitors, Recommended Specifications

Parameter

MINIMUM CAPACITANCE

Input¹

Regulator¹

Output¹

Symbol

Test Conditions/Comments

Min

Typ

Max

Unit

C_IN

T_A= −40°C to +125°C

7.0

0.1

0.7

µF

C_REG

C_OUT

C_BYP

C_REF

Bypass

Reference

CAPACITOR ESR

C_REG, C_OUT, C_IN, C_REF

C_BYP

R_ESR

T_A= −40°C to +125°C

0.001

0.2

2.0

Ω

¹The minimum input, regulator, and output capacitances must be greater than 7.0 μF over the full range of operating conditions. The full range of operating conditions

in the application must be considered during device selection to ensure that the minimum capacitance specification is met. X7R and X5R type capacitors are

recommended; Y5V and Z5U capacitors are not recommended for use with any LDO.

Rev. B | Page 4 of 23

Data Sheet

ADM7154

ABSOLUTE MAXIMUM RATINGS

Junction-to-ambient thermal resistance (θ_JA) of the package is

based on modeling and calculation using a 4-layer PCB. The

junction-to-ambient thermal resistance is highly dependent on

the application and PCB layout. In applications where high

maximum power dissipation exists, close attention to thermal

PCB design is required. The value of θ_JAcan vary, depending on

PCB material, layout, and environmental conditions. The

specified values of θ_JAare based on a 4-layer, 4 in. × 3 in. circuit

board. See JESD51-7 and JESD51-9 for detailed information on

the board construction.

Table 4.

Parameter

VIN to GND

VREG to GND

Rating

−0.3 V to +7 V

−0.3 V to VIN, or +4 V

(whichever is less)

VOUT to GND

−0.3 V to VREG, or +4 V

(whichever is less)

BYP to VOUT

EN to GND

BYP to GND

0.3 V

−0.3 V to +7 V

−0.3 V to VREG, or +4 V

(whichever is less)

Ψ_JBis the junction-to-board thermal characterization parameter

REF to GND

−0.3 V to VREG, or +4 V

(whichever is less)

with units of °C/W. Ψ_JBof the package is based on modeling and

calculation using a 4-layer PCB. JESD51-12, Guidelines for

Reporting and Using Electronic Package Thermal Information,

states that thermal characterization parameters are not the same

as thermal resistances. Ψ_JBmeasures the component power

flowing through multiple thermal paths rather than a single

path as in thermal resistance, θ_JB. Therefore, Ψ_JBthermal paths

include convection from the top of the package as well as

radiation from the package, factors that make Ψ_JBmore useful

in real-world applications. Maximum junction temperature (T_J)

is calculated from the PCB temperature (T_B) and power

dissipation (P_D) using the formula

REF_SENSE to GND

Storage Temperature Range

Junction Temperature

−0.3 V to +4 V

−65°C to +150°C

150°C

Operating Ambient Temperature

Range

−40°C to +125°C

Soldering Conditions

JEDEC J-STD-020

Stresses at or above those listed under Absolute Maximum

Ratings may cause permanent damage to the product. This is a

stress rating only; functional operation of the product at these

or any other conditions above those indicated in the operational

section of this specification is not implied. Operation beyond

the maximum operating conditions for extended periods may

affect product reliability.

T_J= T_B+ (P_D× Ψ_JB)

See JESD51-8 and JESD51-12 for more detailed information

about Ψ_JB.

THERMAL DATA

THERMAL RESISTANCE

Absolute maximum ratings apply individually only, not in

combination. The ADM7154 can be damaged when the

junction temperature limits are exceeded. Monitoring ambient

temperature does not guarantee that T_Jis within the specified

temperature limits. In applications with high power dissipation

and poor thermal resistance, the maximum ambient temper-

ature may need to be derated.

θ_JA, θ_JC, and Ψ_JBare specified for the worst case conditions, that

is, a device soldered in a circuit board for surface-mount

packages.

Table 5. Thermal Resistance

Package Type

8-Lead LFCSP

8-Lead SOIC

θ_JA

θ_JC

Ψ_JB

Unit

°C/W

36.7

36.9

23.5

27.1

13.3

18.6

In applications with moderate power dissipation and low

printed circuit board (PCB) thermal resistance, the maximum

ambient temperature can exceed the maximum limit provided

that the junction temperature is within specification limits. The

junction temperature (T_J) of the device is dependent on the

ambient temperature (T_A), the power dissipation of the device

(P_D), and the junction-to-ambient thermal resistance of the

package (θ_JA).

ESD CAUTION

Maximum junction temperature (T_J) is calculated from the

ambient temperature (T_A) and power dissipation (P_D) using the

following formula:

T_J= T_A+ (P_D× θ_JA)

Rev. B | Page 5 of 23

ADM7154

Data Sheet

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

VREG

VOUT

BYP

1

2

3

4

8

7

6

5

VIN

EN

VREG 1

VOUT 2

BYP 3

8

VIN

ADM7154

7

EN

TOP VIEW

ADM7154

REF

(Not to Scale)

TOP VIEW

6 REF

GND

REF_SENSE

(Not to Scale)

5 REF_SENSE

GND 4

NOTES

1. THE EXPOSED PAD IS LOCATED ON THE BOTTOM OF

THE PACKAGE. THE EXPOSED PAD ENHANCES

THERMAL PERFORMANCE, AND IT IS ELECTRICALLY

CONNECTED TO GND INSIDE THE PACKAGE. CONNECT

THE EP TO THE GROUND PLANE ON THE BOARD TO

ENSURE PROPER OPERATION.

NOTES

1. THE EXPOSED PAD IS LOCATED ON THE BOTTOM OF

THE PACKAGE. THE EXPOSED PAD ENHANCES

THERMAL PERFORMANCE, AND IT IS ELECTRICALLY

CONNECTED TO GND INSIDE THE PACKAGE. CONNECT

THE EP TO THE GROUND PLANE ON THE BOARD TO

ENSURE PROPER OPERATION.

Figure 3. 8-Lead LFCSP Pin Configuration

Figure 4. 8-Lead SOIC Pin Configuration

Table 6. Pin Function Descriptions

Pin No.

Mnemonic

Description

1

VREG

Regulated Input Supply Voltage to LDO Amplifier. Bypass VREG to GND with a 10 µF or greater

capacitor.

2

3

VOUT

BYP

Regulated Output Voltage. Bypass VOUT to GND with a 10 µF or greater capacitor.

Low Noise Bypass Capacitor. Connect a 1 µF capacitor from the BYP pin to GND to reduce noise. Do not

connect a load to ground.

4

5

6

GND

REF_SENSE

REF

Ground Connection.

Reference Sense. Connect Pin 5 to the REF pin. Do not connect Pin 5 to VOUT or GND.

Low Noise Reference Voltage Output. Bypass REF to GND with a 1 µF capacitor. Short REF_SENSE to REF

for fixed output voltages. Do not connect a load to ground.

7

8

EN

Enable. Drive EN high to turn on the regulator; drive EN low to turn off the regulator. For automatic

startup, connect EN to VIN.

Regulator Input Supply Voltage. Bypass VIN to GND with a 10 µF or greater capacitor.

Exposed Pad. The exposed pad is located on the bottom of the package. The exposed pad enhances

thermal performance, and it is electrically connected to GND inside the package. Connect the EP to the

ground plane on the board to ensure proper operation.

VIN

EP

Rev. B | Page 6 of 23

Data Sheet

ADM7154

TYPICAL PERFORMANCE CHARACTERISTICS

V_IN= V_OUT+ 0.5 V, or V_IN= 2.3 V, whichever is greater; V_EN= V_IN; I_OUT= 10 mA; C_IN= C_OUT= C_REG= 10 µF; C_REF= C_BYP= 1 µF; T_A= 25°C,

unless otherwise noted.

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

3.33

3.32

3.31

3.30

3.29

3.28

3.27

V

= 2.3V

= 2.4V

= 2.6V

= 3.0V

= 4.0V

= 5.5V

IN

I

= 1mA

LOAD

= 10mA

= 100mA

= 200mA

= 400mA

= 600mA

–50

–25

0

25

50

75

100

125

3.5

4.0

4.5

(V)

5.0

5.5

TEMPERATURE (°C)

V

IN

Figure 5. Shutdown Current vs. Temperature at

Various Input Voltages, V_OUT= 1.8 V

Figure 8. Output Voltage (V_OUT) vs. Input Voltage (V_IN) at Various Loads,

V_OUT= 3.3 V

3.33

3.32

3.31

3.30

3.29

3.28

3.27

10

9

8

7

6

5

4

3

2

1

0

I

= 1mA

LOAD

I

= 1mA

LOAD

= 10mA

= 100mA

= 200mA

= 400mA

= 600mA

= 10mA

= 100mA

= 200mA

= 400mA

= 600mA

–40

–5

25

85

125

–40

–5

25

85

125

JUNCTION TEMPERATURE (°C)

Figure 6. Output Voltage (V_OUT) vs. Junction Temperature at Various Loads,

_OUT= 3.3 V

Figure 9. Ground Current vs. Junction Temperature (T_J) at Various Loads,

_OUT= 3.3 V

V

3.33

3.32

3.31

3.30

3.29

3.28

3.27

10

9

8

7

6

5

4

3

2

1

0

1

10

100

1000

1

10

100

1000

I

(mA)

I

(mA)

LOAD

Figure 7. Output Voltage (V_OUT) vs. Load Current (I_LOAD), V_OUT= 3.3 V

Figure 10. Ground Current vs. Load Current (I_LOAD), V_OUT= 3.3 V

Rev. B | Page 7 of 23

ADM7154

Data Sheet

10

9

10

9

8

7

6

5

4

3

2

1

0

8

7

6

5

4

3

I

= 5mA

= 10mA

= 100mA

= 200mA

= 400mA

= 600mA

I

= 1mA

LOAD

I

= 10mA

= 100mA

= 200mA

= 400mA

= 600mA

LOAD

2

1

0

3.5

4.0

4.5

(V)

5.0

5.5

3.1

3.2

3.3

3.4

3.5

(V)

3.6

3.7

3.8

V

IN

Figure 11. Ground Current vs. Input Voltage (V_IN) at Various Loads,

V_OUT= 3.3 V

Figure 14. Ground Current vs. Input Voltage (V_IN) in Dropout, V_OUT= 3.3 V

160

140

120

100

80

1.820

1.815

1.810

1.805

1.800

1.795

60

I

= 1mA

LOAD

40

1.790

1.785

1.780

= 10mA

= 100mA

= 200mA

= 400mA

= 600mA

20

0

1

10

100

1000

–40

–5

25

85

125

I

(mA)

JUNCTION TEMPERATURE (°C)

LOAD

Figure 12. Dropout Voltage vs. Load Current (I_LOAD), V_OUT= 3.3 V

Figure 15. Output Voltage (V_OUT) vs. Junction Temperature (T_J) at Various

Loads, V_OUT= 1.8 V

3.40

3.35

3.30

3.25

3.20

3.15

1.820

1.815

1.810

1.805

1.800

1.795

1.790

1.785

1.780

I

= 5mA

LOAD

3.10

3.05

3.00

= 10mA

= 100mA

= 200mA

= 400mA

= 600mA

3.1

3.2

3.3

3.4

3.5

(V)

3.6

3.7

3.8

1

10

100

1000

V

I

(mA)

LOAD

IN

Figure 13. Output Voltage (V_OUT) vs. Input Voltage (V_IN) in Dropout,

_OUT= 3.3 V

Figure 16. Output Voltage (V_OUT) vs. Load Current (I_LOAD), V_OUT= 1.8 V

V

Rev. B | Page 8 of 23

Data Sheet

ADM7154

1.820

1.815

1.810

1.805

1.800

1.795

1.790

1.785

1.780

8

7

6

5

4

3

2

1

0

I

= 1mA

LOAD

= 10mA

= 100mA

= 200mA

= 400mA

= 600mA

I

= 1mA

LOAD

= 10mA

= 100mA

= 200mA

= 400mA

= 600mA

2.0

2.5

3.0

3.5

4.0

(V)

4.5

5.0

5.5

2.0

2.5

3.0

3.5

4.0

(V)

4.5

5.0

5.5

V

IN

Figure 17. Output Voltage (V_OUT) vs. Input Voltage (V_IN) at Various Loads,

Figure 20. Ground Current vs. Input Voltage (V_IN) at Different Loads,

_OUT= 1.8 V

V_OUT= 1.8 V

V

10

9

8

7

6

5

4

3

2

1

0

I

= 100mA

= 200mA

= 400mA

= 600mA

LOAD

–20

–40

–60

–80

–100

–120

–140

I

= 1mA

LOAD

= 10mA

= 100mA

= 200mA

= 400mA

= 600mA

–40

–5

25

85

125

1

10

100

1k

10k

100k

1M

10M

JUNCTION TEMPERATURE (°C)

FREQUENCY (Hz)

Figure 18. Ground Current vs. Junction Temperature (T_J) at Various Loads,

_OUT= 1.8 V

Figure 21. Power Supply Rejection Ratio (PSRR) vs. Frequency at Various

Loads, V_OUT= 3.3 V, V_IN= 4.1 V

V

7

6

5

4

3

2

1

0

–20

–40

–60

–80

800mV

600mV

500mV

400mV

300mV

250mV

200mV

150mV

–100

–120

–140

1

10

100

1k

10k

100k

1M

10M

1

10

100

1000

FREQUENCY (Hz)

I

(mA)

LOAD

Figure 19. Ground Current vs. Load Current (I_LOAD), V_OUT= 1.8 V

Figure 22. Power Supply Rejection Ratio (PSRR) vs. Frequency at Various

Headroom Voltages, V_OUT= 3.3 V, 400 mA Load

Rev. B | Page 9 of 23

ADM7154

Data Sheet

0

–20

–40

–60

–80

0

–20

10Hz

100Hz

1kHz

100kHz

1MHz

10MHz

10kHz

–40

–60

–80

10Hz

–100

–120

–140

–100

–120

–140

100Hz

1kHz

10kHz

100kHz

1MHz

10MHz

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.25

0.35

0.45

0.55

0.65

0.75

HEADROOM (V)

Figure 23. Power Supply Rejection Ratio (PSRR) vs. Headroom Voltage at

Different Frequencies, V_OUT= 3.3 V, 400 mA Load

Figure 26. Power Supply Rejection Ratio (PSRR) vs. Headroom Voltage,

Different Frequencies, V_OUT= 1.8 V, 400 mA Load

0

I

= 100mA

= 200mA

= 400mA

= 600mA

1µF

10µF

100µF

LOAD

–20

–40

–20

–40

1000µF

–60

–80

–100

–120

–140

–100

–120

–140

1

10

100

1k

10k

100k

1M

10M

1

10

100

1k

10k

100k

1M

10M

FREQUENCY (Hz)

Figure 27. Power Supply Rejection Ratio (PSRR) vs. Frequency, Different C_BYP

,

Figure 24. Power Supply Rejection Ratio (PSRR) vs. Frequency at Various

Loads, V_OUT= 1.8 V, V_IN= 2.6 V

V_OUT= 3.3 V, 400 mA Load, 500 mV Headroom

2.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0

–20

–40

–60

–80

10Hz TO 100kHz

100Hz TO 100kHz

–100

800mV

600mV

500mV

400mV

300mV

–120

250mV

–140

10

100

1000

1

10

100

1k

10k

100k

1M 10M

LOAD CURRENT (mA)

FREQUENCY (Hz)

Figure 28. RMS Output Noise vs. Load Current

Figure 25. Power Supply Rejection Ratio (PSRR) vs. Frequency at Various

Headroom Voltages, V_OUT= 1.8 V, 400 mA Load

Rev. B | Page 10 of 23

Data Sheet

ADM7154

2.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

10k

1k

10Hz TO 100kHz

100Hz TO 100kHz

100

10

1

0

0.1

1.0

1.5

2.0

2.5

3.0

3.5

10M

1M

0.1

1

10

100

1k

10k

100k

1M

10M

OUTPUT VOLTAGE (V)

FREQUENCY (Hz)

Figure 29. RMS Output Noise vs. Output Voltage

Figure 32. Output Noise Spectral Density, 0.1 Hz to 10 MHz, I_LOAD= 100 mA

1k

100

10

10k

I

= 10mA

LOAD

= 100mA

= 200mA

= 400mA

= 600mA

1k

100

10

1

0.1

10

100

1k

10k

100k

1M

1

10

100

1k

10k

100k

1M

FREQUENCY (Hz)

Figure 30. Output Noise Spectral Density,

10 Hz to 10 MHz, I_LOAD= 100 mA

Figure 33. Output Noise Spectral Density at Various Loads,

0.1 Hz to 1 MHz

10k

1k

100

10

I

= 10mA

LOAD

= 100mA

= 200mA

= 400mA

= 600mA

100

10

1

0.1

10

0.1

1

10

100

1k

10k

100k

100

1k

10k

100k

1M

10M

FREQUENCY (Hz)

Figure 31. Output Noise Spectral Density,

0.1 Hz to 1 MHz, I_LOAD= 10 mA

Figure 34. Output Noise Spectral Density at Various Loads,

10 Hz to 10 MHz

Rev. B | Page 11 of 23

ADM7154

Data Sheet

T

1

2

1

2

B

CH1 200mA Ω

CH2 5mV

M4.0µs

W

T 10.2%

A CH1

212mA

CH1 200mA Ω

CH2 5mV

M4µs A CH1

T 10.6%

532mA

W

Figure 35. Load Transient Response, I_LOAD= 10 mA to 510 mA,

_OUT= 3.3 V, V_IN= 3.8 V, CH1 = I_OUT, CH2 = V_OUT

Figure 38. Load Transient Response, I_LOAD= 100 mA to 600 mA,

_OUT= 1.8 V, V_IN= 2.3 V, CH1 = I_OUT, CH2 = V_OUT

V

T

1

2

1

B

CH1 200mA Ω

CH2 5mV

M4.0µs

W

T 10.2%

A CH1

212mA

CH1 1V

CH2 1mV

M400ns

T 10.4%

A CH1

4.38V

W

Figure 36. Load Transient Response, I_LOAD= 100 mA to 600 mA,

_OUT= 3.3 V, V_IN= 3.8 V, CH1 = I_OUT, CH2 = V_OUT

Figure 39. Line Transient Response, 1 V Input Step, I_LOAD= 600 mA,

_OUT= 3.3 V, V_IN= 3.9 V, CH1 = V_IN, CH2 = V_OUT

V

T

1

2

1

2

B

CH1 200mA Ω

CH2 5mV

M4.0µs

W

T 10.4%

A CH1

204mA

CH1 1V

CH2 1mV

M400ns

T 11.4%

A CH1

3.5V

W

Figure 37. Load Transient Response, I_LOAD= 10 mA to 510 mA,

_OUT= 1.8 V, V_IN= 2.3 V, CH1 = I_OUT, CH2 = V_OUT

Figure 40. Line Transient Response, 1 V Input Step, I_LOAD= 600 mA,

_OUT= 1.8 V, V_IN= 2.4 V, CH1 = V_IN, CH2 = V_OUT

V

Rev. B | Page 12 of 23

Data Sheet

ADM7154

3.5

ENABLE (V

)

EN

1.2V

1.8V

3.3V

3.0

2.5

2.0

1.5

1.0

0.5

0

1

2

3

4

5

6

7

8

9

10

TIME (ms)

Figure 41. V_OUTStart-Up Time After V_ENRising, Different Output Voltages,

_IN= 5 V

V

Rev. B | Page 13 of 23

ADM7154

Data Sheet

THEORY OF OPERATION

The ADM7154 is an ultralow noise, high power supply rejection

ratio (PSRR) linear regulator targeting radio frequency (RF)

applications. The input voltage range is 2.3 V to 5.5 V, and it can

deliver up to 600 mA of load current. Typical shutdown current

consumption is 0.2 µA at room temperature.

By heavily filtering the reference voltage, the ADM7154 is able

to achieve 1.5 nV/√Hz output typical from 10 kHz to 1 MHz.

Because the error amplifier is always in unity gain, the output

noise is independent of the output voltage.

To maintain very high PSRR over a wide frequency range, the

ADM7154 architecture uses an internal active ripple filter. This

stage isolates the low output noise LDO from noise on the VIN

pin. The result is that the PSRR of the ADM7154 is significantly

higher over a wider frequency range than any single stage LDO.

Optimized for use with 10 µF ceramic capacitors, the ADM7154

provides excellent transient performance.

ACTIVE

RIPPLE

FILTER

VIN

VOUT

CURRENT-LIMIT,

THERMAL

The ADM7154 uses the EN pin to enable and disable the VOUT

pin under normal operating conditions. When EN is high,

VOUT turns on, and when EN is low, VOUT turns off. For

automatic startup, tie EN to VIN.

VREG

BYP

PROTECT

GND

OTA

REFERENCE

VIN

7V

REF_SENSE

REF

VREG

SHUTDOWN

EN

4V

REF

Figure 42. Simplified Internal Block Diagram

REF_SENSE

BYP

4V

Internally, the ADM7154 consists of a reference, an error

amplifier, and a P-channel MOSFET pass transistor. Output

current is delivered via the PMOS pass device, which is

controlled by the error amplifier. The error amplifier compares

the reference voltage with the feedback voltage from the output

and amplifies the difference. If the feedback voltage is lower

than the reference voltage, the gate of the PMOS device is

pulled lower, allowing more current to pass and increasing the

output voltage. If the feedback voltage is higher than the

reference voltage, the gate of the PMOS device is pulled higher,

allowing less current to pass and decreasing the output voltage.

4V

VOUT

EN

7V

4V

7V

GND

Figure 43. Simplified ESD Protection Block Diagram

The ESD protection devices are shown in the block diagram as

Zener diodes (see Figure 43).

Rev. B | Page 14 of 23

Data Sheet

ADM7154

APPLICATIONS INFORMATION

Input and VREG Capacitor

ADIsimPOWER DESIGN TOOL

Connecting a 10 µF capacitor from VIN to GND reduces the

circuit sensitivity to PCB layout, especially when long input

traces or high source impedance are encountered.

The ADM7154 is supported by the ADIsimPower™ design tool

set. ADIsimPower is a collection of tools that produce complete

power designs optimized for a specific design goal. The tools

enable the user to generate a full schematic, bill of materials,

and calculate performance within minutes. ADIsimPower can

optimize designs for cost, area, efficiency, and device count,

taking into consideration the operating conditions and

limitations of the IC and all real external components. For more

information about, and to obtain ADIsimPower design tools,

visit www.analog.com/ADIsimPower.

To maintain the best possible stability and PSRR performance,

connect a 10 µF capacitor from VREG to GND. When more

than 10 µF of output capacitance is required, increase the input

and the VREG capacitors, C_REG, to match it.

REF Capacitor

The REF capacitor, C_REF, is necessary to stabilize the reference

amplifier. Connect at least a 1 µF capacitor between REF and GND.

CAPACITOR SELECTION

BYP Capacitor

Multilayer ceramic capacitors (MLCCs) combine small size, low

ESR, low ESL, and wide operating temperature range, making

them an ideal choice for bypass capacitors. They are not without

faults, however. Depending on the dielectric material, the

capacitance can vary dramatically with temperature, dc bias,

and ac signal level. Therefore, selecting the proper capacitor

results in the best circuit performance.

The BYP capacitor, C_BYP, is necessary to filter the reference

buffer. A 1 µF capacitor is typically connected between BYP and

GND. Capacitors as small as 0.1 µF can be used; however, the

output noise voltage of the LDO increases as a result.

In addition, the BYP capacitor value can be increased to reduce

the noise below 1 kHz at the expense of increasing the start-up

time of the LDO. Very large values of C_BYPsignificantly reduce

the noise below 10 Hz. Tantalum capacitors are recommended

for capacitors larger than approximately 33 µF because solid

tantalum capacitors are less prone to microphonic noise issues.

A 1 μF ceramic capacitor in parallel with the larger tantalum

capacitor is recommended to ensure good noise performance at

higher frequencies.

Output Capacitor

The ADM7154 is designed for operation with ceramic

capacitors but functions with most commonly used capacitors

when care is taken with regard to the effective series resistance

(ESR) value. The ESR of the output capacitor affects the stability

of the LDO control loop. A minimum of 10 µF capacitance with

an ESR of 0.2 Ω or less is recommended to ensure the stability

of the ADM7154. Output capacitance also affects transient

response to changes in load current. Using a larger value of

output capacitance improves the transient response of the

ADM7154 to large changes in load current. Figure 44 shows the

transient responses for an output capacitance value of 10 µF.

2.0

10Hz TO 100kHz

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0

100Hz TO 100kHz

T

1

2

1

10

100

1000

C

(µF)

BYP

Figure 45. RMS Noise vs. C_BYP

B

CH1 200mA

Ω

CH2 5mV

M4µs A CH1

10.2%

212mA

W

T

Figure 44. Output Transient Response, V_OUT= 3.3 V, C_OUT= 10 µF,

CH1 = Load Current, CH2 = V_OUT

Rev. B | Page 15 of 23

ADM7154

Data Sheet

10k

Use Equation 1 to determine the worst case capacitance

accounting for capacitor variation over temperature,

component tolerance, and voltage.

NOISE FLOOR

1.0µF

3.3µF

10µF

33µF

100µF

330µF

1000µF

1k

100

10

C

_EFF= C_BIAS× (1 − TEMPCO) × (1 − TOL)

where:

_BIASis the effective capacitance at the operating voltage.

(1)

C

TEMPCO is the worst case capacitor temperature coefficient.

TOL is the worst case component tolerance.

In this example, the worst case temperature coefficient

1

(TEMPCO) over −40°C to +85°C is assumed to be 15% for an

X5R dielectric. The tolerance of the capacitor (TOL) is assumed

to be 10%, and C_BIASis 9.72 µF at 5 V, as shown in Figure 47.

0.1

1

10

100

1k

10k

100k

1M

FREQUENCY (Hz)

Substituting these values in Equation 1 yields

Figure 46. Noise Spectral Density vs. Frequency at

Different Capacitances (C_BYP

C_EFF= 9.72 µF × (1 − 0.15) × (1 − 0.1) = 7.44 µF

)

Therefore, the capacitor chosen in this example meets the

minimum capacitance requirement of the LDO over

temperature and tolerance at the chosen output voltage.

Capacitor Properties

Any good quality ceramic capacitors can be used with the

ADM7154 if they meet the minimum capacitance and maxi-

mum ESR requirements. Ceramic capacitors are manufactured

with a variety of dielectrics, each with different behavior over

temperature and applied voltage. Capacitors must have a

dielectric adequate to ensure the minimum capacitance over

the necessary temperature range and dc bias conditions. X5R

or X7R dielectrics with a voltage rating of 6.3 V to 50 V

are recommended. However, Y5V and Z5U dielectrics are

not recommended because of their poor temperature and dc

bias characteristics.

To guarantee the performance of the ADM7154, it is imperative

that the effects of dc bias, temperature, and tolerances on the

behavior of the capacitors be evaluated for each application.

UNDERVOLTAGE LOCKOUT (UVLO)

The ADM7154 also incorporates an internal UVLO circuit to

disable the output voltage when the input voltage is less than the

minimum input voltage rating of the regulator. The upper and

lower thresholds are internally fixed with about 200 mV of

hysteresis.

Figure 47 depicts the capacitance vs. dc bias voltage of a 1206,

10 µF, 10 V, X5R capacitor. The voltage stability of a capacitor is

strongly influenced by the capacitor size and voltage rating. In

general, a capacitor in a larger package or higher voltage rating

exhibits better stability. The temperature variation of the X5R

dielectric is ~ 15% over the −40°C to +85°C temperature range

and is not a function of package or voltage rating.

12

2.5

+125°C

+25°C

–40°C

2.0

1.5

1.0

0.5

0

10

8

1.90

1.95

2.00

2.05

2.10

2.15

2.20

2.25

2.30

6

INPUT VOLTAGE (V)

Figure 48. Typical UVLO Behavior at Different Temperatures, V_OUT= 3.3 V

4

Figure 48 shows the typical hysteresis of the UVLO function.

This hysteresis prevents on/off oscillations that can occur when

caused by noise on the input voltage as it passes through the

threshold points.

2

0

2

4

6

8

10

DC BIAS VOLTAGE (V)

Figure 47. Capacitance vs. DC Bias Voltage

Rev. B | Page 16 of 23

Data Sheet

ADM7154

The upper and lower thresholds are user programmable and can

be set higher than the nominal 1.22 V threshold by using two

resistors. The resistance values, R_EN1and R_EN2, can be

determined from

PROGRAMMABLE PRECISION ENABLE

The ADM7154 uses the EN pin to enable and disable the

VOUT pin under normal operating conditions. As shown in

Figure 49, when a rising voltage on EN crosses the upper threshold,

nominally 1.22 V, V _OUTturns on. When a falling voltage on EN

crosses the lower threshold, nominally 1.13 V, V _OUTturns off.

The hysteresis of the EN threshold is approximately 90 mV.

R

_EN1= R_EN2× (V_IN− 1.22 V)/1.22 V

where:

_EN2typically ranges from 10 kΩ to 100 kΩ.

_INis the desired turn-on voltage.

R

V

3.5

+125°C

+85°C

+25°C

The hysteresis voltage increases by the factor

3.0

–5°C

–40°C

(R_EN1+ R_EN2)/R_EN2

2.5

2.0

1.5

1.0

0.5

0

For the example shown in Figure 52, the EN threshold is 2.44 V

with a hysteresis of 200 mV.

ADM7154

V

= 2.3V

V

= 1.8V

OUT

IN

VIN

VOUT

C

IN

OUT

10µF

R

EN1

ON

100kΩ

EN

REF

C

REF

1µF

OFF

R

EN2

100kΩ

BYP REF_SENSE

C

BYP

1µF

1.0

1.1

1.2

1.3

VREG

GND

EN PIN VOLTAGE (V)

C

10µF

REG

Figure 49. Typical V_OUTResponse to EN Pin Operation

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

ENABLE (V

)

EN

Figure 52. Typical EN Pin Voltage Divider

V

OUT

Figure 52 shows the typical hysteresis of the EN pin. This

prevents on/off oscillations that can occur due to noise on the

EN pin as it passes through the threshold points.

START-UP TIME

The ADM7154 uses an internal soft start to limit the inrush current

when the output is enabled. The start-up time for a 3.3 V output is

approximately 1.2 ms from the time the EN active threshold is

crossed to when the output reaches 90% of the final value.

The rise time in seconds of the output voltage (10% to 90%) is

approximately

0

0.4

0.8

1.2

1.6

2.0

2.4

2.8

3.2

3.6

4.0

TIME (ms)

0.0012 × C_BYP

Figure 50. Typical V_OUTResponse to EN Pin Operation (V_EN),

_OUT= 3.3 V, V_IN= 5 V, C_BYP= 1 µF

where C_BYPis in microfarads.

V

3.5

1.250

1.225

1.200

1.175

1.150

1.125

1.100

3.0

2.5

2.0

1.5

1.0

–40°C RISING

+25°C RISING

+125°C RISING

–40°C FALLING

+25°C FALLING

+125°C FALLING

ENABLE (V

)

EN

C

= 1µF

= 3.3µF

= 10µF

BYP

0.5

0

5

10

15

20

25

30

35

40

2.5

3.0

3.5

4.0

4.5

5.0

5.5

TIME (ms)

INPUT VOLTAGE (V)

Figure 53. Typical Start-Up Behavior with C_BYP= 1 µF to 10 µF

Figure 51. Typical EN Threshold vs. Input Voltages (V_IN) for Different

Temperatures

Rev. B | Page 17 of 23

ADM7154

Data Sheet

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

Current-limit and thermal limit protections are intended to

protect the device against accidental overload conditions. For

reliable operation, device power dissipation must be externally

limited so that the junction temperature does not exceed 150°C.

THERMAL CONSIDERATIONS

In applications with a low input to output voltage differential,

the ADM7154 does not dissipate much heat. However, in

applications with high ambient temperature and/or high input

voltage, the heat dissipated in the package can become large

enough that it causes the junction temperature of the die to

exceed the maximum junction temperature of 150°C.

ENABLE (V

)

EN

C

= 10µF

= 33µF

= 100µF

= 330µF

BYP

When the junction temperature exceeds 150°C, the converter

enters thermal shutdown. It recovers only after the junction

temperature decreases below 135°C to prevent any permanent

damage. Therefore, thermal analysis for the chosen application

is important to guarantee reliable performance over all condi-

tions. The junction temperature of the die is the sum of the

ambient temperature of the environment and the temperature

rise of the package due to the power dissipation, as shown in

Equation 2.

0

20

40

60

80

100 120 140 160 180 200

TIME (ms)

Figure 54. Typical Start-Up Behavior with C_BYP= 10 µF to 330 µF

REF, BYP, AND VREG PINS

REF, BYP, and VREG generate voltages internally (V_REF, V_BYP

and V_REG) that require external bypass capacitors for proper

operation. Do not, under any circumstances, connect any loads

to these pins, because doing so compromises the noise and

PSRR performance of the ADM7154. Using larger values of

,

To guarantee reliable operation, the junction temperature of the

ADM7154 must not exceed 150°C. To ensure that the junction

temperature stays below this maximum value, the user must be

aware of the parameters that contribute to junction temperature

changes. These parameters include ambient temperature, power

dissipation in the power device, and thermal resistances between

the junction and ambient air (θ_JA). The θ_JAnumber is dependent

on the package assembly compounds that are used and the

amount of copper used to solder the package GND pin and

exposed pad to the PCB.

C

_BYP, C_REF, and C_REGis acceptable but can increase the start-up

time, as described in the Start-Up Time section.

CURRENT-LIMIT AND THERMAL OVERLOAD

PROTECTION

The ADM7154 is protected against damage due to excessive

power dissipation by current and thermal overload protection

circuits. The ADM7154 is designed to current limit when the

output load reaches 960 mA (typical). When the output load

exceeds 960 mA, the output voltage is reduced to maintain a

constant current limit.

Table 7 shows typical θ_JAvalues of the 8-lead SOIC and 8-lead

LFCSP packages for various PCB copper sizes.

Thermal overload protection is included, which limits the

junction temperature to a maximum of 150°C. Under extreme

conditions (that is, high ambient temperature and/or high

power dissipation), when the junction temperature starts to rise

above 150°C, the output is turned off, reducing the output

current to zero. When the junction temperature drops below

135°C, the output is turned on again, and the output current is

restored to the operating value.

Table 8 shows the typical Ψ_JBvalues of the 8-lead SOIC and

8-lead LFCSP.

Table 7. Typical θ_JAValues

θ_JA(°C/W)

Copper Size (mm²)

25¹

8-Lead LFCSP

165.1

8-Lead SOIC

165

100

500

125.8

68.1

126.4

69.8

Consider the case where a hard short from VOUT to GND

occurs. At first, the ADM7154 current limits, so that only

960 mA is conducted into the short. If self heating of the

junction is great enough to cause the temperature to rise above

150°C, thermal shutdown activates, turning off the output and

reducing the output current to zero. As the junction tempera-

ture cools and drops below 135°C, the output turns on and

conducts 900 mA into the short, again causing the junction

temperature to rise above 150°C. This thermal oscillation

between 135°C and 150°C causes a current oscillation between

900 mA and 0 mA that continues for as long as the short

remains at the output.

1000

6400

56.4

42.1

57.8

43.6

¹Device soldered to minimum size pin traces.

Table 8. Typical Ψ_JBValues

Package

Ψ_JB(°C/W)

8-Lead LFCSP

8-Lead SOIC

15.1

17.9

Rev. B | Page 18 of 23

Data Sheet

ADM7154

160

150

140

130

120

110

100

90

The junction temperature of the ADM7154 is calculated from

the following equation:

T_J= T_A+ (P_D× θ_JA)

(2)

where:

T_Ais the ambient temperature.

P_Dis the power dissipation in the die, given by

P_D= ((V_IN− V_OUT) × I_LOAD) + (V_IN× I_GND

where:

_INand V_OUTare the input and output voltages, respectively.

)

(3)

80

2

6400mm

V

70

2

500mm

2

I

_LOADis the load current.

_GNDis the ground current.

25mm

60

T

MAX

J

50

0

0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4

TOTAL POWER DISSIPATION (W)

Power dissipation caused by ground current is quite small and

can be ignored. Therefore, the junction temperature equation

simplifies to the following:

Figure 56. Junction Temperature vs. Total Power Dissipation for

the 8-Lead LFCSP, T_A= 50°C

155

145

135

125

115

105

95

T_J= T_A+ (((V_IN− V_OUT) × I_LOAD) × θ_JA)

(4)

As shown in Equation 4, for a given ambient temperature, input

to output voltage differential, and continuous load current,

there exists a minimum copper size requirement for the PCB to

ensure that the junction temperature does not rise above 150°C.

The heat dissipation from the package can be improved by

increasing the amount of copper attached to the pins and

exposed pad of the ADM7154. Adding thermal planes

underneath the package also improves thermal performance.

However, as shown in Table 7, a point of diminishing returns is

eventually reached, beyond which an increase in the copper

area does not yield significant reduction in the junction to

ambient thermal resistance.

85

75

65

2

6400mm

2

500mm

2

25mm

T

MAX

J

0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5

TOTAL POWER DISSIPATION (W)

Figure 55 to Figure 60 show junction temperature calculations

for different ambient temperatures, power dissipation, and areas

of PCB copper.

Figure 57. Junction Temperature vs. Total Power Dissipation for

the 8-Lead LFCSP, T_A= 85°C

155

145

135

125

115

105

95

155

145

135

125

115

105

95

85

75

65

85

75

65

2

6400mm

2

500mm

55

45

35

25

2

6400mm

2

25mm

2

500mm

T

MAX

J

2

25mm

T

MAX

0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5

TOTAL POWER DISSIPATION (W)

J

0

0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0

TOTAL POWER DISSIPATION (W)

Figure 58. Junction Temperature vs. Total Power Dissipation for

the 8-Lead SOIC, T_A= 25°C

Figure 55. Junction Temperature vs. Total Power Dissipation for

the 8-Lead LFCSP, T_A= 25°C

Rev. B | Page 19 of 23

ADM7154

Data Sheet

160

150

140

130

120

110

100

90

Thermal Characterization Parameter (Ψ_JB)

When board temperature is known, use the thermal

characterization parameter, Ψ_JB, to estimate the junction

temperature rise (see Figure 61 and Figure 62). Maximum

junction temperature (T_J) is calculated from the board

temperature (T_B) and power dissipation (P_D) using the following

formula:

T_J= T_B+ (P_D× Ψ_JB)

(5)

80

2

The typical value of Ψ_JBis 15.1°C/W for the 8-lead LFCSP

package and 17.9°C/W for the 8-lead SOIC package.

6400mm

70

2

500mm

2

25mm

60

160

T

MAX

J

50

0

0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4

TOTAL POWER DISSIPATION (W)

140

120

100

80

Figure 59. Junction Temperature vs. Total Power Dissipation for

the 8-Lead SOIC, T_A= 50°C

155

145

135

125

115

105

95

60

T

= 25°C

= 50°C

= 65°C

= 85°C

MAX

B

J

40

20

0

0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0

TOTAL POWER DISSIPATION (W)

85

75

65

2

6400mm

Figure 61. Junction Temperature vs. Total Power Dissipation for

the 8-Lead LFCSP

2

500mm

2

25mm

160

140

120

100

80

T

MAX

1.8

J

0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

2.0

TOTAL POWER DISSIPATION (W)

Figure 60. Junction Temperature vs. Total Power Dissipation for

the 8-Lead SOIC, T_A= 85°C

60

T

= 25°C

= 50°C

= 65°C

= 85°C

MAX

B

J

40

20

0

0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5

TOTAL POWER DISSIPATION (W)

Figure 62. Junction Temperature vs. Total Power Dissipation for

the 8-Lead SOIC

Rev. B | Page 20 of 23

Data Sheet

ADM7154

PCB LAYOUT CONSIDERATIONS

Place the input capacitor as close as possible to the VIN and

GND pins. Place the output capacitor as close as possible to the

VOUT and GND pins. Place the bypass capacitors (C_REG, C_REF

and C_BYP) for V_REG, V_REF, and V_BYPclose to the respective pins

(VREG, REF, and BYP) and GND. Use of an 0805, 0603, or

0402 size capacitor achieves the smallest possible footprint

solution on boards where area is limited.

,

Figure 64. Example 8-Lead SOIC PCB Layout

Figure 63. Example 8-Lead LFCSP PCB Layout

Rev. B | Page 21 of 23

ADM7154

Data Sheet

OUTLINE DIMENSIONS

2.54

2.44

2.34

3.10

3.00 SQ

2.90

0.50 BSC

5

8

PIN 1 INDEX

EXPOSED

PAD

1.70

1.60

1.50

AREA

0.50

0.40

0.30

0.20 MIN

4

1

TOP VIEW

PIN 1

BOTTOM VIEW

INDICATOR

(R 0.20)

0.80

0.75

0.70

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

0.05 MAX

0.02 NOM

SECTION OF THIS DATA SHEET.

0.30

0.25

0.20

SEATING

PLANE

0.203 REF

Figure 65. 8-Lead Lead Frame Chip Scale Package [LFCSP_WD]

3 mm × 3 mm Body, Very Very Thin, Dual Lead

(CP-8-21)

Dimensions shown in millimeters

5.00

4.90

4.80

2.29

0.356

5

6.20

6.00

5.80

8

4.00

3.90

3.80

2.29

0.457

4

1

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

BOTTOM VIEW

45°

1.27 BSC

3.81 REF

TOP VIEW

SECTION OF THIS DATA SHEET.

1.65

1.25

1.75

1.35

0.50

0.25

0.17

0.10 MAX

0.05 NOM

SEATING

PLANE

8°

0°

0.51

0.31

1.04 REF

COPLANARITY

0.10

1.27

0.40

COMPLIANT TO JEDEC STANDARDS MS-012-AA

Figure 66. 8-Lead Standard Small Outline Package, with Exposed Pad [SOIC_N_EP]

Narrow Body

(RD-8-1)

Dimensions shown in millimeters

Rev. B | Page 22 of 23

Data Sheet

ADM7154

ORDERING GUIDE

Model¹

Temperature Range

−40°C to +125°C

Output Voltage (V)

Package Description

8-Lead LFCSP_WD

8-Lead SOIC_N_EP

Evaluation Board

Package Option

CP-8-21

RD-8-1

Branding

LQS

LQT

LQU

LQ6

ADM7154ACPZ-1.2-R7

ADM7154ACPZ-1.8-R7

ADM7154ACPZ-2.5-R7

ADM7154ACPZ-2.8-R7

ADM7154ACPZ-3.0-R7

ADM7154ACPZ-3.3-R7

ADM7154ARDZ-1.2-R7

ADM7154ARDZ-1.8-R7

ADM7154ARDZ-2.5-R7

ADM7154ARDZ-2.8-R7

ADM7154ARDZ-3.0-R7

ADM7154ARDZ-3.3-R7

ADM7154CP-3.3EVALZ

ADM7154RD-1.8EVALZ

1.2

1.8

2.5

2.8

3.0

3.3

1.2

1.8

2.5

2.8

3.0

3.3

LRF

LQ7

RD-8-1

¹Z = RoHS Compliant Part.

registered trademarks are the property of their respective owners.

D12324-0-8/16(B)

Rev. B | Page 23 of 23


型号：	ADM7154ACPZ-1.8-R7
厂家：	ADI
描述：	600 mA, Ultralow Noise, High PSRR, RF Linear Regulator 光电二极管输出元件调节器
文件：	总24页 (文件大小：812K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADM7154ACPZ-1.8-R7 [ADI]

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