ADM7154 [ADI]
High PSRR, RF Linear Regulator;
| 型号： | ADM7154 |
| 厂家： | 
ADI |
| 描述： | High PSRR, RF Linear Regulator |
| 文件： | 总24页 (文件大小：1184K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
1.2 A, Ultralow Noise,
High PSRR, RF Linear Regulator
ADP7157
Data Sheet
FEATURES
Input voltage range: 2.3 V to 5.5 V
Adjustable output voltage range (VOUT): 1.2 V to 3.3 V
Maximum load current: 1.2 A
Low noise
0.9 µV rms typical output noise from 100 Hz to 100 kHz
1.6 µV rms typical output noise from 10 Hz to 100 kHz
Noise spectral density: 1.7 nV/√Hz from 10 kHz to 1 MHz
Power supply rejection ratio (PSRR)
82 dB from 1 kHz to 100 kHz
TYPICAL APPLICATION CIRCUIT
ADP7157
V
= 3.8V
V
= 3.3V
IN
OUT
VIN
VOUT
VOUT_SENSE
REF
C
10µF
C
OUT
10µF
IN
ON
OFF
EN
C
REF
1µF
R1
BYP
C
BYP
1µF
V
= 1.2V × (R1 + R2)/R2
OUT
REF_SENSE
R2
1kΩ < R2 < 200kΩ
VREG
C
REG
1µF
55 dB at 1 MHz
GND
Dropout voltage: 120 mV typical at IOUT = 1.2 A, VOUT = 3.3 V
Initial accuracy: 0.6% at ILOAD = 10 mA
Accuracy over line, load, and temperature: 1.5%
Figure 1. Regulated 3.3 V Output from a 3.8 V Input
Operating supply current (IGND
4.0 mA typical at 0 µA
)
7.0 mA typical at 1.2 A
Low shutdown current: 0.2 μA typical
Stable with a 10 µF ceramic output capacitor
10-lead, 3 mm × 3 mm LFCSP and 8-lead SOIC packages
Precision enable
Table 1. Related Devices
Input
Output
Current
Fixed/
Adjustable
Supported by ADIsimPower tool
Model
Voltage
Package
APPLICATIONS
2.3 V to
5.5 V
2 A
Fixed
10-lead LFCSP/
8-lead SOIC
ADP7159,
ADP7158
ADP7156
Regulation to noise sensitive applications: phase-locked
loops (PLLs), voltage controlled oscillators (VCOs), and
PLLs with integrated VCOs
2.3 V to
5.5 V
1.2 A
Fixed/
Adjustable
10-lead LFCSP/
8-lead SOIC
ADM7150, 4.5 V to
ADM7151 16 V
ADM7154, 2.3 V to
800 mA
600 mA
200 mA
Fixed/
Adjustable
Fixed/
Adjustable
8-lead LFCSP/
8-lead SOIC
8-lead LFCSP/
8-lead SOIC
6-lead LFCSP/
5-lead TSOT
Communications and infrastructure
Backhaul and microwave links
ADM7155
5.5 V
GENERAL DESCRIPTION
ADM7160
2.2 V to
5.5 V
Fixed
The ADP7157 is an adjustable linear regulator that operates from
2.3 V to 5.5 V and provides up to 1.2 A of output current. Output
voltages from 1.2 V to 3.3 V are possible depending on the model.
Using an advanced proprietary architecture, the device provides
high power supply rejection and ultralow noise, achieving excellent
line and load transient response with only a 10 µF ceramic
output capacitor.
1k
100
10
C
= 1µF
BYP
BYP
BYP
BYP
C
C
C
= 10µF
= 100µF
= 1000µF
The ADP7157 is available in four models that optimize power
dissipation and PSRR performance as a function of the input
and output voltage. See Table 9 and Table 10 for selection guides.
1
The typical output noise the ADP7157 regulator is 0.9 μV rms from
100 Hz to 100 kHz and 1.7 nV/√Hz for noise spectral density from
10 kHz to 1 MHz. The ADP7157 is available in 10-lead, 3 mm ×
3 mm LFCSP and 8-lead SOIC packages, making it not only a
very compact solution, but also providing excellent thermal
performance for applications requiring up to 1.2 A of output
current in a small, low profile footprint.
0.1
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 2. Noise Spectral Density at Different Values of CBYP, VOUT = 3.3 V
Rev. A
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Tel: 781.329.4700
Technical Support
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www.analog.com
ADP7157* Product Page Quick Links
Last Content Update: 11/01/2016
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ADP7157
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
ADIsimPower Design Tool ....................................................... 14
Capacitor Selection .................................................................... 14
Undervoltage Lockout (UVLO) ............................................... 15
Programmable Precision Enable .............................................. 16
Start-Up Time ............................................................................. 17
REF, BYP, and VREG Pins......................................................... 17
Current-Limit and Thermal Shutdown................................... 17
Thermal Considerations............................................................ 17
PSRR Performance..................................................................... 20
PCB Layout Considerations.......................................................... 21
Outline Dimensions....................................................................... 22
Ordering Guide .......................................................................... 23
Applications....................................................................................... 1
General Description......................................................................... 1
Typical Application Circuit ............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 5
Thermal Data ................................................................................ 5
Thermal Resistance ...................................................................... 5
ESD Caution.................................................................................. 5
Pin Configurations and Function Descriptions ........................... 6
Typical Performance Characteristics ............................................. 7
Theory of Operation ...................................................................... 13
Applications Information .............................................................. 14
REVISION HISTORY
5/2016—Rev. 0 to Rev. A
Added Note 2 to Table 2; Renumbered Sequentially ................... 4
Change to Figure 4 ........................................................................... 6
Change to Programmable Precision Enable Section ................. 16
3/2016—Revision 0: Initial Version
Rev. A | Page 2 of 23
Data Sheet
ADP7157
SPECIFICATIONS
VIN = VOUT_MAX1 + 0.5 V; VEN = VIN; ILOAD = 10 mA; CIN = COUT = 10 µF; CREG = CREF = CBYP = 1 µF; TA = 25°C for typical specifications;
TA = −40°C to +125°C for minimum/maximum specifications, unless otherwise noted.
Table 2.
Parameter
Symbol
VIN
Test Conditions/Comments
Min
Typ
Max
5.5
1.2
8.0
12.0
4
Unit
V
INPUT VOLTAGE RANGE
LOAD CURRENT
2.3
ILOAD
A
OPERATING SUPPLY CURRENT
IGND
ILOAD = 0 µA
ILOAD = 1.2 A
4.0
7.0
0.2
mA
mA
µA
SHUTDOWN CURRENT
NOISE2
IIN-SD
EN = ground
VOUT = 1.2 V to 3.3 V
Output Noise
OUTNOISE
10 Hz to 100 kHz
100 Hz to 100 kHz
10 kHz to 1 MHz
1.6
0.9
1.7
µV rms
µV rms
nV/√Hz
Noise Spectral Density
POWER SUPPLY REJECTION RATIO2
ADP7157-01
OUTNSD
PSRR
ILOAD = 1.2 A
1 kHz to 100 kHz, VIN = 2.3 V, VOUT = 1.8 V
1 MHz, VIN = 2.3 V, VOUT = 1.8 V
1 kHz to 100 kHz, VIN = 2.8 V, VOUT = 2.3 V
1 MHz, VIN = 2.8 V, VOUT = 2.3 V
1 kHz to 100 kHz, VIN = 3.4 V, VOUT = 2.9 V
1 MHz, VIN = 3.4 V, VOUT = 2.9 V
1 kHz to 100 kHz, VIN = 3.8 V, VOUT = 3.3 V
1 MHz, VIN = 3.8 V, VOUT = 3.3 V
70
52
72
53
75
55
82
55
dB
dB
dB
dB
dB
dB
dB
dB
ADP7157-02
ADP7157-03
ADP7157-04
OUTPUT VOLTAGE ACCURACY
Output Voltage3
Initial Accuracy
VOUT
VOUT
1.2
3.3
V
ILOAD = 10 mA, TA = 25°C
10 mA < ILOAD < 1.2 A, TA = 25°C
10 mA < ILOAD < 1.2 A, TA = −40°C to +125°C
−0.6
−1.0
−1.5
+0.6
+1.0
+1.5
%
%
%
REGULATION
Line
∆VOUT/∆VIN
∆VOUT/∆IOUT
ILIMIT
VIN = VOUT_MAX + 0.5 V to 5.5 V
IOUT = 10 mA to 1.2 A
−0.1
+0.1
0.3
%/V
%/A
Load4
CURRENT-LIMIT THRESHOLD5
REF
VOUT
DROPOUT VOLTAGE6
22
1.8
60
mA
A
1.4
2.4
80
170
VDROPOUT
IOUT = 600 mA, VOUT = 3.3 V
IOUT = 1.2 A, VOUT = 3.3 V
EN = 0 V, VIN = 5.5 V
VOUT = 1 V
VREG = 1 V
VREF = 1 V
mV
mV
120
PULL-DOWN RESISTANCE
VOUT
VREG
REF
VOUT-PULL
VREG-PULL
VREF-PULL
VBYP-PULL
650
31
850
650
Ω
kΩ
Ω
BYP
VBYP = 1 V
Ω
START-UP TIME2, 7
VOUT
VREG
REF
VOUT = 3.3 V
tSTART-UP
tREG-START-UP
tREF-START-UP
1.2
0.6
0.5
ms
ms
ms
THERMAL SHUTDOWN2
Threshold
Hysteresis
TSSD
TSSD-HYS
TJ rising
150
15
°C
°C
Rev. A | Page 3 of 23
ADP7157
Data Sheet
Parameter
UNDERVOLTAGE THRESHOLDS
Input Voltage
Rising
Falling
Hysteresis
VREG THRESHOLDS8
Rising
Symbol
Test Conditions/Comments
Min
1.95
1.60
Typ
Max
Unit
UVLORISE
UVLOFALL
UVLOHYS
2.22 2.29
2.02
200
V
V
mV
VREGUVLORISE
VREGUVLOFALL
VREGUVLOHYS
1.94
V
V
mV
Falling
Hysteresis
185
EN INPUT PRECISION
EN Input
2.3 V ≤ VIN ≤ 5.5 V
Logic High
Logic Low
Logic Hysteresis
LEAKAGE CURRENT
REF_SENSE
EN
ENHIGH
ENLOW
ENHYS
1.13
1.05
1.22 1.31
1.13 1.22
90
V
V
mV
IREF_SENSE_LKG
IEN_LKG
10
nA
µA
EN = VIN or ground
0.01
1
1 VOUT_MAX is the maximum output voltage of each version of the ADP7157.
2 Guaranteed by characterization, but not production tested.
3 This output voltage specification is for ADP7157-04 version. Table 10 provides a guide for selecting one of the four versions of the ADP7157 based on voltage range.
4 This specification is based on an endpoint calculation using 10 mA and 1.2 A loads.
5 Current-limit threshold is the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 3.0 V output voltage
is the current that causes the output voltage to drop to 90% of 3.0 V or 2.7 V.
6 Dropout voltage is the input to output voltage differential when the input voltage is set to the nominal output voltage. Dropout applies only for output voltages
above 2.3 V.
7 Start-up time is the time from the rising edge of VEN to VOUT, VREG, or VREF being at 90% of its nominal value.
8 The output voltage is disabled until the VREG UVLO rise threshold is crossed. The VREG output is disabled until the input voltage UVLO rising threshold is crossed.
Table 3. Input and Output Capacitors, Recommended Specifications
Parameter
Symbol
Test Conditions/Comments
Min
Typ
Max
Unit
MINIMUM CAPACITANCE
TA = −40°C to +125°C
Input1
CIN
10.0
1.0
10.0
1.0
µF
µF
µF
µF
µF
Regulator1
Output1
Bypass
Reference
CREG
COUT
CBYP
CREF
RESR
1.0
CAPACITOR EFFECTIVE SERIES RESISTANCE (ESR)
TA = −40°C to +125°C
CREG, COUT, CIN, CREF
CBYP
0.001
0.001
0.2
2.0
Ω
Ω
1 The minimum input, regulator, and output capacitances must be greater than 7.0 μF over the full range of operating conditions. The full range of operating conditions
in the application must be considered during device selection to ensure that the minimum capacitance specification is met. X7R and X5R type capacitors are
recommended, and Y5V and Z5U capacitors are not recommended for use with any LDO.
Rev. A | Page 4 of 23
Data Sheet
ADP7157
ABSOLUTE MAXIMUM RATINGS
Table 4.
The maximum TJ is calculated from the TA and the PD using the
following formula:
Parameter
Rating
TJ = TA + (PD × θJA)
VIN to Ground
VREG to Ground
−0.3 V to +7 V
−0.3 V to VIN or +4 V
(whichever is less)
The junction to ambient thermal resistance (θJA) of the package
is based on modeling and calculation using a 4-layer board. The
junction to ambient thermal resistance is highly dependent on
the application and board layout. In applications where high
maximum power dissipation exists, close attention to thermal
board design is required. The θJA value may vary, depending on
PCB material, layout, and environmental conditions. The specified
VOUT to Ground
−0.3 V to VREG or +4 V
(whichever is less)
VOUT_SENSE to Ground
−0.3 V to VREG or +4 V
(whichever is less)
VOUT to VOUT_SENSE
BYP to VOUT
0.3 V
0.3 V
θ
JA values are based on a 4-layer, 4 in. × 3 in. circuit board. See
EN to Ground
−0.3 V to +7 V
the JESD51-7 standard and the JESD51-9 standard for detailed
information on the board construction.
BYP to Ground
−0.3 V to VREG or +4 V
(whichever is less)
Ψ
JB is the junction to board thermal characterization parameter
REF to Ground
−0.3 V to VREG or +4 V
(whichever is less)
−0.3 V to +4 V
−65°C to +150°C
−40°C to +125°C
with units of °C/W. ΨJB of the package is based on modeling and
calculation using a 4-layer board. JESD51-12, Guidelines for
Reporting and Using Electronic Package Thermal Information,
states that thermal characterization parameters are not the same
as thermal resistances. ΨJB measures the component power
flowing through multiple thermal paths rather than a single
path as in thermal resistance, θJB. Therefore, ΨJB thermal paths
include convection from the top of the package as well as
radiation from the package, factors that make ΨJB more useful
in real-world applications. Use the board temperature (TB) and
power dissipation (PD) to calculate the maximum junction
temperature (TJ) by
REF_SENSE to Ground
Storage Temperature Range
Operational Junction Temperature
Range
Soldering Conditions
JEDEC J-STD-020
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
TJ = TB + (PD × ΨJB)
THERMAL DATA
See the JESD51-8 standard and the JESD51-12 standard for
more detailed information about ΨJB.
Absolute maximum ratings apply individually only, not in
combination. The ADP7157 can be damaged when the junction
temperature limits are exceeded. Monitoring ambient temperature
does not guarantee that TJ is within the specified temperature
limits. In applications with high power dissipation and poor
thermal resistance, the maximum ambient temperature may
need to be derated.
THERMAL RESISTANCE
θJA, θJC, and ΨJB are specified for the worst case conditions, that
is, a device soldered in a circuit board for surface-mount
packages.
Table 5. Thermal Resistance
Package Type
10-Lead LFCSP
8-Lead SOIC
θJA
θJC
ΨJB
Unit
°C/W
°C/W
In applications with moderate power dissipation and low
printed circuit board (PCB) thermal resistance, the maximum
ambient temperature can exceed the maximum limit as long as
the junction temperature is within specification limits. The
junction temperature (TJ) of the device is dependent on the
ambient temperature (TA), the power dissipation of the device
(PD), and the junction to ambient thermal resistance of the
package (θJA).
53.8
50.4
15.6
42.3
29.1
30.1
ESD CAUTION
Rev. A | Page 5 of 23
ADP7157
Data Sheet
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
VOUT
1
2
3
10 VIN
1
8
VIN
VOUT
VOUT_SENSE
BYP
2
3
4
ADP7157
7
6
5
VREG
REF
9
8
VIN
VOUT
TOP VIEW
ADP7157
(Not to Scale)
VREG
VOUT_SENSE
TOP VIEW
REF_SENSE
EN
(Not to Scale)
BYP 4
EN
7
6
REF
NOTES
5
REF_SENSE
1. THE EXPOSED PAD IS LOCATED ON THE BOTTOM OF
THE PACKAGE. THE EXPOSED PAD ENHANCES
THERMAL PERFORMANCE, AND IT IS ELECTRICALLY
CONNECTED TO GROUND INSIDE THE PACKAGE.
CONNECT THE EP TO THE GROUND PLANE ON THE
BOARD TO ENSURE PROPER OPERATION.
NOTES
1. THE EXPOSED PAD IS LOCATED ON THE BOTTOM OF
THE PACKAGE. THE EXPOSED PAD ENHANCES
THERMAL PERFORMANCE, AND IT IS ELECTRICALLY
CONNECTED TO GROUND INSIDE THE PACKAGE.
CONNECT THE EP TO THE GROUND PLANE ON THE
BOARD TO ENSURE PROPER OPERATION.
Figure 3. 10-Lead LFCSP Pin Configuration
Figure 4. 8-Lead SOIC Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
LFCSP SOIC
Mnemonic
Description
Regulated Output Voltage. Bypass VOUT to ground with a 10 μF or greater capacitor.
1, 2
3
1
2
VOUT
VOUT_SENSE Output Sense. VOUT_SENSE is internally connected to VOUT with a 10 Ω resistor. Connect VOUT_SENSE
as close to the load as possible.
4
5
6
3
4
5
BYP
Low Noise Bypass Capacitor. Connect a 1 μF or greater capacitor from the BYP pin to ground to
reduce noise. Do not connect a load to this pin.
Enable. Drive EN high to turn on the regulator, and drive EN low to turn off the regulator. For
automatic startup, connect EN to VIN.
EN
REF_SENSE
Reference Sense. This pin sets the output voltage with an external resistor divider.
VOUT = VREF × (R1 + R2)/R2, where VREF = 1.2 V. Connect REF_SENSE to the REF pin. Do not connect
REF_SENSE to VOUT or ground.
7
6
7
8
REF
Low Noise Reference Voltage Output. Bypass REF to ground with a 1 μF or greater capacitor. Short
REF_SENSE to REF for fixed output voltages. Do not connect a load to this pin.
Regulated Input Supply Voltage to the LDO Amplifier. Bypass VREG to ground with a 1 μF or greater
capacitor.
8
VREG
9, 10
VIN
EP
Regulator Input Supply Voltage. Bypass VIN to ground with a 10 μF or greater capacitor.
Exposed Pad. The exposed pad is located on the bottom of the package. The exposed pad enhances
thermal performance, and it is electrically connected to ground inside the package. Connect the
exposed pad to the ground plane on the board to ensure proper operation.
Rev. A | Page 6 of 23
Data Sheet
ADP7157
TYPICAL PERFORMANCE CHARACTERISTICS
VIN = VOUT + 0.5 V or 2.3 V, whichever is greater; VEN = VIN; VOUT = 3.3 V; ILOAD = 10 mA; CIN = COUT = 10 µF; CREG = CREF = CBYP = 1 µF;
TA = 25°C, unless otherwise noted.
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
3.35
3.34
3.33
3.32
3.31
3.30
3.29
3.28
3.27
3.26
3.25
I
I
I
I
I
= 0mA
LOAD
LOAD
LOAD
LOAD
LOAD
= 10mA
= 100mA
= 600mA
= 1200mA
5.5V
5.0V
4.0V
3.0V
2.5V
100
2.3V
40
–40
–20
0
20
60
80
120
140
3.8
4.0
4.2
4.4
4.6
V
4.8
(V)
5.0
5.2
5.4
5.6
TEMPERATURE (°C)
IN
Figure 5. Shutdown Current (IIN-SD) vs. Temperature
at Various Input Voltages (VIN), VOUT =1.8 V
Figure 8. Output Voltage (VOUT) vs. Input Voltage (VIN
at Various Loads, VOUT = 3.3 V
)
3.35
3.34
3.33
3.32
3.31
3.30
3.29
3.28
3.27
3.26
3.25
14
13
12
11
10
9
I
I
I
I
I
= 0mA
LOAD
LOAD
LOAD
LOAD
LOAD
I
I
I
I
I
= 0mA
LOAD
LOAD
LOAD
LOAD
LOAD
= 10mA
= 100mA
= 600mA
= 1200mA
= 10mA
= 100mA
= 600mA
= 1200mA
8
7
6
5
4
3
2
1
0
–40
–40
–20
0
20
40
60
80
100
120
140
–20
0
20
40
60
80
100
120
140
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 6. Output Voltage (VOUT) vs. Temperature
at Various Loads, VOUT = 3.3 V
Figure 9. Ground Current (IGND) vs. Temperature
at Various Loads, VOUT = 3.3 V
3.35
3.34
3.33
3.32
3.31
3.30
3.29
3.28
3.27
3.26
3.25
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0.1m
1m
10m
100m
(A)
1
10
0.1m
1m
10m
I
100m
(A)
1
10
I
LOAD
LOAD
Figure 7. Output Voltage (VOUT) vs. Load Current (ILOAD), VOUT = 3.3 V
Figure 10. Ground Current (IGND) vs. Load Current (ILOAD), VOUT = 3.3 V
Rev. A | Page 7 of 23
ADP7157
Data Sheet
14
13
12
11
10
9
14
I
I
I
I
I
= 0mA
LOAD
LOAD
LOAD
LOAD
LOAD
13
12
11
10
9
= 10mA
= 100mA
= 600mA
= 1200mA
8
8
7
7
6
6
5
5
4
4
3
3
I
I
I
I
I
= 0mA
LOAD
LOAD
LOAD
LOAD
LOAD
= 10mA
= 100mA
= 600mA
= 1200mA
2
2
1
1
0
3.1
0
3.8
3.2
3.3
3.4
3.5
(V)
3.6
3.7
3.8
4.0
4.2
4.4
4.6
V
4.8
(V)
5.0
5.2
5.4
5.6
V
IN
IN
Figure 11. Ground Current (IGND) vs. Input Voltage (VIN
at Various Loads, VOUT = 3.3 V
)
Figure 14. Ground Current (IGND) vs. Input Voltage (VIN) in Dropout,
OUT = 3.3 V
V
1.25
1.24
1.23
1.22
1.21
1.20
1.19
1.18
1.17
1.16
1.15
0.16
0.14
0.12
0.10
0.08
0.06
0.04
0.02
0
I
I
I
I
I
= 0mA
LOAD
LOAD
LOAD
LOAD
LOAD
= 10mA
= 100mA
= 600mA
= 1200mA
–40
–20
0
20
40
60
80
100
120
140
10m
100m
1
10
TEMPERATURE (°C)
I
(A)
LOAD
Figure 12. Dropout Voltage (VDROPOUT) vs. Load Current (ILOAD), VOUT = 3.3 V
Figure 15. Output Voltage (VOUT) vs. Temperature
at Various Loads, VOUT = 1.2 V
3.40
1.25
I
I
I
I
I
= 0mA
LOAD
LOAD
LOAD
LOAD
LOAD
= 10mA
= 100mA
= 600mA
= 1200mA
1.24
1.23
1.22
1.21
1.20
1.19
1.18
1.17
1.16
1.15
3.35
3.30
3.25
3.20
3.15
3.10
3.05
3.00
3.0
3.1
3.2
3.3
3.4
(V)
3.5
3.6
3.7
3.8
0.1m
1m
10m
100m
(A)
1
10
V
I
IN
LOAD
Figure 13. Output Voltage (VOUT) vs. Input Voltage (VIN) in Dropout,
OUT = 3.3 V
Figure 16. Output Voltage (VOUT) vs. Load Current (ILOAD), VOUT = 1.2 V
V
Rev. A | Page 8 of 23
Data Sheet
ADP7157
1.25
14
13
12
11
10
9
I
I
I
I
I
= 0mA
LOAD
LOAD
LOAD
LOAD
LOAD
= 10mA
= 100mA
= 600mA
= 1200mA
1.24
1.23
1.22
1.21
1.20
1.19
1.18
1.17
1.16
1.15
I
= 1200mA
LOAD
8
I
= 600mA
= 100mA
LOAD
7
6
I
LOAD
5
4
I
= 10mA
LOAD
3
I
= 0mA
LOAD
2
1
0
2.3
2.7
3.1
3.5
3.9
(V)
4.3
4.7
5.1
5.5
2.3 2.6 2.9 3.2 3.5 3.8 4.1 4.4 4.7
5
5.3 5.6
V
V
(V)
IN
IN
Figure 17. Output Voltage (VOUT) vs. Input Voltage (VIN
at Various Loads, VOUT = 1.2 V
)
Figure 20. Ground Current (IGND) vs. Input Voltage (VIN
at Various Loads, VOUT = 1.2 V
)
14
13
12
11
10
9
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
I
I
I
I
= 10mA
LOAD
LOAD
LOAD
LOAD
= 100mA
= 600mA
= 1200mA
I
= 1200mA
LOAD
8
7
I
= 600mA
= 100mA
LOAD
6
I
5
LOAD
4
I
= 10mA
3
LOAD
I
= 0mA
LOAD
2
1
0
–40
–20
0
20
40
60
80
100
120
140
1
10
100
1k
10k
100k
1M
10M
TEMPERATURE (°C)
FREQUENCY (Hz)
Figure 18. Ground Current (IGND) vs. Temperature
at Various Loads, VOUT = 1.2 V
Figure 21. Power Supply Rejection Ratio (PSRR) vs. Frequency
at Various Loads, VOUT = 3.3 V
14
0
900mV
13
12
11
10
9
800mV
–10
700mV
600mV
500mV
–20
–30
–40
–50
–60
–70
–80
–90
–100
8
7
6
5
4
3
2
1
0
0.1m
1m
10m
100m
(A)
1
10
1
10
100
1k
10k
100k
1M
10M
I
FREQUENCY (Hz)
LOAD
Figure 22. Power Supply Rejection Ratio (PSRR) vs. Frequency
at Various Headroom Voltages, VOUT = 3.3 V, 1.2 A Load
Figure 19. Ground Current (IGND) vs. Load Current (ILOAD), VOUT = 1.2 V
Rev. A | Page 9 of 23
ADP7157
Data Sheet
0
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
10Hz
10Hz
100Hz
1kHz
100Hz
1kHz
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
10kHz
100kHz
1MHz
10MHz
10kHz
100kHz
1MHz
10MHz
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
HEADROOM (V)
HEADROOM (V)
Figure 23. Power Supply Rejection Ratio (PSRR) vs. Headroom Voltage
at Various Frequencies, VOUT = 3.3 V, 1.2 A Load
Figure 26. Power Supply Rejection Ratio (PSRR) vs. Headroom Voltage
at Various Frequencies, VOUT = 1.2 V, 1.2 A Load
0
0
I
I
I
I
= 10mA
1µF
LOAD
LOAD
LOAD
LOAD
= 100mA
= 600mA
= 1200mA
10µF
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–10
100µF
1000µF
–20
–30
–40
–50
–60
–70
–80
–90
–100
1
10
100
1k
10k
100k
1M
10M
1
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 24. Power Supply Rejection Ratio (PSRR) vs. Frequency
at Various Loads, VOUT = 1.2 V
Figure 27. Power Supply Rejection Ratio (PSRR) vs. Frequency
at Different CBYP Values, VOUT = 3.3 V, VIN = 4.0 V, 1.2 A Load
0
2.5
1.4V
1.3V
1.2V
1.1V
1.0V
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
2.0
1.5
1.0
0.5
0
10Hz TO 100kHz
100Hz TO 100kHz
1
10
100
1k
10k
100k
1M
10M
10m
100m
1
10
FREQUENCY (Hz)
LOAD CURRENT (A)
Figure 25. Power Supply Rejection Ratio (PSRR) vs. Frequency
at Various Headroom Voltages, VOUT = 1.2 V, 1.2 A Load
Figure 28. RMS Output Noise vs. Load Current (ILOAD)
Rev. A | Page 10 of 23
Data Sheet
ADP7157
2.5
2.0
1.5
1.0
0.5
0
1k
100
10
I
I
I
I
= 10mA
LOAD
LOAD
LOAD
LOAD
= 100mA
= 600mA
= 1200mA
10Hz TO 100kHz
100Hz TO 100kHz
1
0.1
10
1.0
1.5
2.0
2.5
3.0
3.5
100
1k
10k
100k
1M
10M
OUTPUT VOLTAGE (V)
FREQUENCY (Hz)
Figure 29. RMS Output Noise vs. Output Voltage
Figure 32. Output Noise Spectral Density vs. Frequency
at Various Loads, 10 Hz to 10 MHz
1k
C
C
C
C
= 1µF
BYP
BYP
BYP
BYP
= 10µF
= 100µF
SLEW RATE = 2.5A/µs
= 1000µF
100
10
1
I
OUT
1
2
V
OUT
0.1
10
B
CH1 500mA B CH2 5.00mV
M4.00µs A CH1
21.10%
700mA
W
W
100
1k
10k
100k
1M
10M
T
FREQUENCY (Hz)
Figure 30. Noise Spectral Density vs. Frequency at Various Values of CBYP
Figure 33. Load Transient Response, ILOAD = 100 mA to 1.2 A,
VOUT = 3.3 V, VIN = 4.0 V, Channel 1 = IOUT, Channel 2 = VOUT
100k
I
I
I
I
= 10mA
LOAD
LOAD
LOAD
LOAD
= 100mA
= 600mA
= 1200mA
SLEW RATE = 1.5A/µs
10k
1k
I
OUT
1
2
100
10
V
OUT
1
0.1
0.1
B
B
W
CH1 500mA
CH2 5.00mV
M4.00µs A CH1
690mA
W
1
10
100
1k
10k
100k
1M
T
22.60%
FREQUENCY (Hz)
Figure 31. Output Noise Spectral Density vs. Frequency
at Various Loads, 0.1 Hz to 1 MHz
Figure 34. Load Transient Response, ILOAD = 100 mA to 1.2 A, VOUT = 3.3 V,
VIN = 4.0 V, COUT = 22 μF, Channel 1 = IOUT, Channel 2 = VOUT
Rev. A | Page 11 of 23
ADP7157
Data Sheet
SLEW RATE = 2.5A/µs
SLEW RATE = 1V/µs
V
IN
1
2
1
2
V
OUT
B
B
B
B
CH1 500mA
CH2 5.00mV
M4.00µs A CH1
W
740mA
W
CH1 1.00V
CH2 2.00mV
M10.0µs A CH1
W
3.00V
W
T
21.30%
T
21.80%
Figure 35. Load Transient Response, ILOAD = 100 mA to 1.2 A,
VOUT = 1.8 V, VIN = 2.5 V, Channel 1 = IOUT, Channel 2 = VOUT
Figure 38. Line Transient Response, 1 V Input Step, ILOAD = 1.2 A,
VOUT = 1.8 V, VIN = 2.5 V, Channel 1 = VIN, Channel 2 = VOUT
3.5
EN
3.3V
SLEW RATE = 2.4A/µs
2.5V
1.8V
3.0
2.5
2.0
1.5
1.0
0.5
0
I
OUT
1
2
V
OUT
B
B
W
CH1 500mA
CH2 5.00mV
M4.00µs A CH1
740mA
W
–2
–1
0
1
2
3
4
5
6
7
8
T
20.70%
TIME (ms)
Figure 36. Load Transient Response, ILOAD = 100 mA to 1.2 A, VOUT = 1.8 V,
VIN = 2.5 V, COUT = 22 μF, Channel 1 = IOUT, Channel 2 = VOUT
Figure 39. VOUT Start-Up Time After VEN Rising
at Various Output Voltages, VIN = 5.0 V, CBYP = 1 ꢀF
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
SLEW RATE = 1V/µs
V
IN
V
OUT
2
1
EN
1µF
4.7µF
10µF
B
B
W
CH1 1.00V
CH2 5.00mV
M10.0µs A CH1
4.34V
W
–2
0
2
4
6
8
10
12
14
16
18
20
T
21.10%
TIME (ms)
Figure 37. Line Transient Response, 1 V Input Step, ILOAD = 1.2 A,
VOUT = 3.3 V, VIN = 3.8 V, Channel 1 = VIN, Channel 2 = VOUT
Figure 40. VOUT Start-Up Time Behavior at Various Values of CBYP
,
VOUT = 3.3 V
Rev. A | Page 12 of 23
Data Sheet
ADP7157
THEORY OF OPERATION
The ADP7157 is an ultralow noise, high PSRR linear regulator
targeting radio frequency (RF) applications. The input voltage
range is 2.3 V to 5.5 V, and the device delivers up to a 1.2 A load
current. The typical shut-down current consumption is 0.2 μA
at room temperature.
ADP7157
V
= 3.8V
V
= 3.3V
IN
OUT
VIN
VOUT
C
10µF
C
OUT
10µF
IN
VOUT_SENSE
REF
ON
OFF
EN
C
REF
1µF
R1
OUT
Optimized for use with 10 μF ceramic capacitors, the ADP7157
provides excellent transient performance.
BYP
C
BYP
1µF
V
= 1.2V × (R1 + R2)/R2
REF_SENSE
R2
1kΩ < R2 < 200kΩ
VREG
C
VIN
VOUT
REG
1µF
VOUT_SENSE
CURRENT-LIMIT,
THERMAL
PROTECT
GND
INTERNAL
VREG
BYP
REGULATOR
GND
Figure 42. Typical Adjustable Output Voltage Application Schematic
OTA
REFERENCE
The R2 value must be greater than 1 kΩ to prevent excessive
loading of the reference voltage appearing on the REF pin. To
minimize errors in the output voltage caused by the REF_
SENSE pin input current, the R2 value must be less than 200 kΩ.
For example, when R1 and R2 each equal 100 kΩ, the output
voltage is 2.4 V. The output voltage error introduced by the
REF_SENSE pin input current is 10 mV or 0.33%, assuming a
maximum REF_SENSE pin input current of 100 nA at TA = 125°C.
REF_SENSE
REF
EN
SHUTDOWN
Figure 41. Simplified Internal Block Diagram
Internally, the ADP7157 consists of a reference, an error amplifier,
and a P-channel MOSFET pass transistor. The output current is
delivered via the PMOS pass device, which is controlled by the
error amplifier. The error amplifier compares the reference voltage
with the feedback voltage from the output and amplifies the
difference. If the feedback voltage is lower than the reference
voltage, the gate of the PMOS device pulls lower, allowing more
current to pass and increasing the output voltage. If the feedback
voltage is higher than the reference voltage, the gate of the
PMOS device pulls higher, allowing less current to pass and
decreasing the output voltage.
The ADP7157 uses the EN pin to enable and disable the VOUT pin
under normal operating conditions. When EN is high, VOUT
turns on, and when EN is low, VOUT turns off. For automatic
startup, tie EN to VIN.
VIN
7V
VREG
4V
REF
By heavily filtering the reference voltage, the ADP7157 achieves
1.7 nV/√Hz output typical from 10 kHz to 1 MHz. Because the
error amplifier is always in unity gain, the output noise is
independent of the output voltage.
REF_SENSE
4V
BYP
4V
VOUT
4V
The ADP7157 output voltage can be adjusted between 1.2 V and
3.3 V and is available in four models that optimize the input voltage
and output voltage ranges to keep power dissipation as low as
possible without compromising PSRR performance. The output
voltage is determined by an external voltage divider according
to the following equation:
VOUT_SENSE
EN
4V
7V
4V
4V
4V
4V
4V
7V
GND
Figure 43. Simplified ESD Protection Block Diagram
VOUT = 1.2 V × (1 + R1/R2)
The ESD protection devices are shown in the block diagram as
Zener diodes (see Figure 43).
Rev. A | Page 13 of 23
ADP7157
Data Sheet
APPLICATIONS INFORMATION
Input and VREG Capacitor
ADIsimPOWER DESIGN TOOL
Connecting a 10 µF or greater capacitor from VIN to ground
reduces the circuit sensitivity to PCB layout, especially when
long input traces or high source impedance are encountered.
The ADP7157 is supported by the ADIsimPower™ design tool set.
ADIsimPower is a collection of tools that produces complete
power designs optimized for a specific design goal. The tools
enable the user to generate a full schematic, bill of materials,
and calculate performance within minutes. ADIsimPower can
optimize designs for cost, area, efficiency, and device count,
taking into consideration the operating conditions and limitations
of the IC and all real external components. For more information
about, and to obtain ADIsimPower design tools, visit
www.analog.com/ADIsimPower.
To maintain the best possible stability and PSRR performance,
connect a 1 µF or greater capacitor from VREG to ground.
REF Capacitor
The REF capacitor, CREF, is necessary to stabilize the reference
amplifier. Connect a 1 µF or greater capacitor between REF and
ground
BYP Capacitor
CAPACITOR SELECTION
The BYP capacitor, CBYP, is necessary to filter the reference
buffer. A 1 µF capacitor is typically connected between BYP and
ground. Capacitors as small as 0.1 µF can be used; however, the
output noise voltage of the LDO increases as a result.
Multilayer ceramic capacitors (MLCCs) combine small size, low
ESR, low effective series inductance (ESL), and wide operating
temperature range, making them an ideal choice for bypass
capacitors. They are not without faults, however. Depending on
the dielectric material, the capacit-ance can vary dramatically
with temperature, dc bias, and ac signal level. Therefore, selecting
the proper capacitor results in the best circuit performance.
In addition, the BYP capacitor value can be increased to reduce
the noise below 1 kHz at the expense of increasing the start-up
time of the LDO. Very large values of CBYP significantly reduce
the noise below 10 Hz. Tantalum capacitors are recommended
for capacitors larger than approximately 33 µF because solid
tantalum capacitors are less prone to microphonic noise issues.
A 1 μF ceramic capacitor in parallel with the larger tantalum
capacitor is recommended to ensure good noise performance at
higher frequencies.
Output Capacitor
The ADP7157 is designed for operation with ceramic capacitors
but functions with most commonly used capacitors when care
is taken with regard to the ESR value. The ESR of the output
capacitor affects the stability of the LDO control loop. A minimum
of 10 µF capacitance with an ESR of 0.2 Ω or less is recommended
to ensure the stability of the ADP7157. Output capacitance also
affects transient response to changes in load current. Using a
larger value of output capacitance improves the transient
response of the ADP7157 to large changes in load current.
Figure 44 shows the transient responses for an output
capacitance value of 10 µF.
2.0
1.8
1.6
10Hz TO 100kHz
1.4
1.2
1.0
100Hz TO 100kHz
0.8
SLEW RATE = 2.5A/µs
0.6
0.4
0.2
0
I
OUT
1
10
100
1000
C
(µF)
BYP
V
OUT
Figure 45. RMS Output Noise vs. Bypass Capacitance (CBYP
)
B
B
W
CH1 500mA
CH2 5.00mV
M4.00µs A CH1
700mA
W
T
21.10%
Figure 44. Output Transient Response, VOUT = 3.3 V, COUT = 10 µF,
Channel 1 = Load Current, Channel 2 = VOUT
Rev. A | Page 14 of 23
Data Sheet
ADP7157
1k
Use Equation 1 to determine the worst case capacitance
accounting for capacitor variation over temperature,
component tolerance, and voltage.
C
C
C
C
= 1µF
BYP
BYP
BYP
BYP
= 10µF
= 100µF
= 1000µF
100
10
1
C
EFF = CBIAS × (1 − Tempco × (1 − TOL)
where:
BIAS is the effective capacitance at the operating voltage.
(1)
C
Tempco is the worst case capacitor temperature coefficient.
TOL is the worst case component tolerance.
In this example, the worst case temperature coefficient (TEMPCO)
over −40°C to +85°C is assumed to be 15% for an X5R dielectric.
The tolerance of the capacitor (TOL) is assumed to be 10%, and
0.1
10
C
BIAS is 9.72 µF at 5 V, as shown in Figure 47.
Substituting these values in Equation 1 yields
EFF = 9.72 µF × (1 − 0.15) × (1 − 0.1) = 7.44 µF
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 46. Noise Spectral Density vs. Frequency at Various CBYP Values
C
Capacitor Properties
Therefore, the capacitor chosen in this example meets the
minimum capacitance requirement of the LDO over temperature
and tolerance at the chosen output voltage.
Any good quality ceramic capacitors can be used with the
ADP7157 if they meet the minimum capacitance and maximum
ESR requirements. Ceramic capacitors are manufactured with a
variety of dielectrics, each with different behavior over temperature
and applied voltage. Capacitors must have a dielectric adequate
to ensure the minimum capacitance over the necessary
temperature range and dc bias conditions. X5R or X7R dielectrics
with a voltage rating of 6.3 V to 50 V are recommended. However,
Y5V and Z5U dielectrics are not recommended because of their
poor temperature and dc bias characteristics.
To guarantee the performance of the ADP7157, it is imperative
that the effects of dc bias, temperature, and tolerances on the
behavior of the capacitors be evaluated for each application.
UNDERVOLTAGE LOCKOUT (UVLO)
The ADP7157 also incorporates an internal UVLO circuit to
disable the output voltage when the input voltage is less than the
minimum input voltage rating of the regulator. The upper and
lower thresholds are internally fixed with about 200 mV of
hysteresis.
Figure 47 depicts the capacitance vs. dc bias voltage of a 1206,
10 µF, 10 V, X5R capacitor. The voltage stability of a capacitor is
strongly influenced by the capacitor size and voltage rating. In
general, a capacitor in a larger package or higher voltage rating
exhibits better stability. The temperature variation of the X5R
dielectric is ~ 15% over the −40°C to +85°C temperature range
and is not a function of package or voltage rating.
12
2.5
+125°C
+25°C
–40°C
2.0
1.5
1.0
0.5
0
10
8
6
1.9
2.0
2.1
V
2.2
2.3
4
(V)
IN
Figure 48. Typical UVLO Behavior at Various Temperatures, VOUT = 3.3 V
2
Figure 48 shows the typical hysteresis of the UVLO function.
This hysteresis prevents on/off oscillations that can occur when
caused by noise on the input voltage as it passes through the
threshold points.
0
0
2
4
6
8
10
DC BIAS VOLTAGE (V)
Figure 47. Capacitance vs. DC Bias Voltage
Rev. A | Page 15 of 23
ADP7157
Data Sheet
1.250
1.225
1.200
1.175
1.150
1.125
1.100
PROGRAMMABLE PRECISION ENABLE
The ADP7157 uses the EN pin to enable and disable the VOUT pin
under normal operating conditions. As shown in Figure 49, when a
rising voltage on EN crosses the upper threshold, nominally 1.22 V,
RISING
V
OUT turns on. When a falling voltage on EN crosses the lower
threshold, nominally 1.13 V, VOUT turns off. The hysteresis of
the EN threshold is approximately 90 mV.
The ADP7157 includes the discharge resistor on each VOUT,
VREG, VREF, and BYP pin. These resistors are turned on when
the device is disabled, helping to quickly discharge the associated
capacitor.
FALLING
4.0
3.5
2.5
3.0
3.5
4.5
5.0
5.5
–40°C
–5°C
INPUT VOLTAGE (V)
+25°C
3.0
+85°C
+125°C
Figure 51. Typical EN Threshold vs. Input Voltages (VIN) for Different
Temperatures
2.5
2.0
1.5
1.0
0.5
0
The upper and lower thresholds are user programmable and can be
set higher than the nominal 1.22 V threshold by using two resistors.
The resistance values, REN1 and REN2, can be determined from
R
EN1 = REN2 × (VEN − 1.22 V)/1.22 V
where:
EN2 typically ranges from 10 kΩ to 100 kΩ.
EN is the desired turn-on voltage.
R
V
1.00
1.05
1.10
1.15
1.20
1.25
1.30
The hysteresis voltage increases by the factor
EN PIN VOLTAGE (V)
(REN1 + REN2)/REN2
Figure 49. Typical VOUT Response to EN Pin Operation
For the example shown in Figure 52, the EN threshold is 2.44 V
with a hysteresis of 200 mV.
3.5
EN
OUT
V
3.0
2.5
2.0
1.5
1.0
0.5
0
ADP7157
V
= 3.8V
V
= 3.3V
IN
OUT
VIN
VOUT
VOUT_SENSE
REF
C
C
OUT
10µF
IN
10µF
R
EN1
100kΩ
ON
OFF
EN
C
REF
1µF
R
EN2
100kΩ
R1
BYP
C
BYP
1µF
V
= 1.2V × (R1 + R2)/R2
OUT
REF_SENSE
R2
1kΩ < R2 < 200kΩ
VREG
C
REG
1µF
GND
–2
–1
0
1
2
3
4
5
6
7
8
Figure 52. Typical EN Pin Voltage Divider
TIME (ms)
Figure 50. Typical VOUT Response to EN Pin Operation (VEN),
OUT = 3.3 V, VIN = 5 V, CBYP = 1 µF
Figure 52 shows the typical hysteresis of the EN pin. This
hysteresis prevents on/off oscillations that can occur due to
noise on the EN pin as it passes through the threshold points.
V
Rev. A | Page 16 of 23
Data Sheet
ADP7157
START-UP TIME
CURRENT-LIMIT AND THERMAL SHUTDOWN
The ADP7157 uses an internal soft start to limit the inrush
current when the output is enabled. The start-up time for a
3.3 V output is approximately 1.2 ms from the time the EN
active threshold is crossed to when the output reaches 90% of
its final value.
The ADP7157 is protected against damage due to excessive
power dissipation by current and thermal overload protection
circuits. The ADP7157 is designed to current limit when the
output load reaches 1.8 A (typical). When the output load
exceeds 1.8 A, the output voltage is reduced to maintain a
constant current limit.
The rise time in seconds of the output voltage (10% to 90%) is
approximately 0.0012 × CBYP, where CBYP is in microfarads.
When the ADP7157 junction temperature exceeds 150°C, the
thermal shutdown circuit turns off the output voltage, reducing
the output current to zero. Extreme junction temperature can
be the result of high current operation, poor circuit board
design, or high ambient temperature. A 15°C hysteresis is
included so that the ADP7157 does not return to operation after
thermal shutdown until the on-chip temperature falls below
135°C. When the device exits thermal shutdown, a soft start is
initiated to reduce the inrush current.
3.5
3.0
2.5
2.0
1.5
Current limit and thermal shutdown protections are intended to
protect the device against accidental overload conditions. Cases
with a hard short from VOUT to ground or an extremely long
soft-start timer typically cause the device to experience thermal
oscillations between current limit and thermal shutdown.
1.0
EN
0.5
1µF
4.7µF
10µF
0
–2
0
2
4
6
8
10
12
14
16
18
20
TIME (ms)
THERMAL CONSIDERATIONS
Figure 53. Typical Start-Up Behavior with CBYP = 1 µF
In applications with a low input to output voltage differential, the
ADP7157 does not dissipate much heat. However, in applications
with high ambient temperature and/or high input voltage, the
heat dissipated in the package may become large enough that it
causes the junction temperature of the die to exceed the
maximum junction temperature of 125°C.
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
The junction temperature of the die is the sum of the ambient
temperature of the environment and the temperature rise of the
package due to the power dissipation, as shown in Equation 2.
To guarantee reliable operation, the junction temperature of the
ADP7157 must not exceed 125°C. To ensure that the junction
temperature stays below this maximum value, the user must be
aware of the parameters that contribute to junction temperature
changes. These parameters include ambient temperature, power
dissipation in the power device, and thermal resistances between
the junction temperature and ambient air (θJA). The θJA number
is dependent on the package assembly compounds used, as well as
the amount of copper used to solder the package ground and the
exposed pad to the PCB.
EN
10µF
47µF
100µF
–20
0
20
40
60
80
100
120
140
160
TIME (ms)
Figure 54. Typical Start-Up Behavior with CBYP = 1 µF to 100 µF
REF, BYP, AND VREG PINS
REF, BYP, and VREG generate voltages internally (VREF, VBYP
and VREG) that require external bypass capacitors for proper
operation. Do not, under any circumstances, connect any loads
to these pins, because doing so compromises the noise and
,
PSRR performance of the ADP7157. Using larger values of CBYP
REF, and CREG is acceptable but can increase the start-up time,
as described in the Start-Up Time section.
,
C
Rev. A | Page 17 of 23
ADP7157
Data Sheet
140
120
100
80
Table 7 shows typical θJA values of the 8-lead SOIC and 10-lead
LFCSP packages for various PCB copper sizes.
T
MAXIMUM
J
Table 8 shows the typical ΨJB values of the 8-lead SOIC and
10-lead LFCSP.
2
2
500mm
2
25mm
6400mm
Table 7. Typical θJA Values
θJA (°C/W)
60
Copper Size (mm2)
10-Lead LFCSP
8-Lead SOIC
123.8
90.4
251
130.2
93.0
65.8
55.6
44.1
40
100
500
1000
6400
20
66.0
56.6
45.5
0
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0
TOTAL POWER DISSIPATION (W)
1 Device soldered to minimum size pin traces.
Figure 55. Junction Temperature vs. Total Power Dissipation for
the 10-Lead LFCSP, TA = 25°C
Table 8. Typical ΨJB Values
140
Package
ΨJB (°C/W)
T
MAXIMUM
J
10-Lead LFCSP
8-Lead SOIC
29.1
30.1
120
100
80
2
2
500mm
2
25mm
6400mm
The junction temperature of the ADP7157 is calculated from the
following equation:
TJ = TA + (PD × θJA)
where:
(2)
60
TA is the ambient temperature.
PD is the power dissipation in the die, given by
40
PD = ((VIN − VOUT) × ILOAD) + (VIN × IGND
where:
VIN and VOUT are the input and output voltages, respectively.
)
(3)
20
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6
TOTAL POWER DISSIPATION (W)
I
I
LOAD is the load current.
GND is the ground current.
Figure 56. Junction Temperature vs. Total Power Dissipation for
the 10-Lead LFCSP, TA = 50°C
130
Power dissipation caused by ground current is quite small and
can be ignored. Therefore, the junction temperature equation
simplifies to the following equation:
T
MAXIMUM
J
125
120
115
110
105
100
95
2
2
500mm
2
25mm
6400mm
TJ = TA + (((VIN − VOUT) × ILOAD) × θJA)
(4)
As shown in Equation 4, for a given ambient temperature, input
to output voltage differential, and continuous load current, a
minimum copper size requirement exists for the PCB to ensure
that the junction temperature does not rise above 150°C.
The heat dissipation from the package can be improved by
increasing the amount of copper attached to the pins and
exposed pad of the ADP7157. Adding thermal planes
underneath the package also improves thermal performance.
However, as shown in Table 7, a point of diminishing returns is
eventually reached, beyond which an increase in the copper
area does not yield significant reduction in the junction to
ambient thermal resistance.
90
85
80
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
TOTAL POWER DISSIPATION (W)
Figure 57. Junction Temperature vs. Total Power Dissipation for
the 10-Lead LFCSP, TA = 85°C
Figure 55 to Figure 60 show junction temperature calculations
for different ambient temperatures, power dissipation, and areas
of PCB copper.
Rev. A | Page 18 of 23
Data Sheet
ADP7157
140
120
100
80
Thermal Characterization Parameter (ΨJB)
T
MAXIMUM
J
When board temperature is known, use the thermal character-
ization parameter, ΨJB, to estimate the junction temperature rise
(see Figure 61 and Figure 62). Use the board temperature (TB)
and the power dissipation (PD) to calculate the maximum
junction temperature (TJ) by
2
2
500mm
2
25mm
6400mm
60
TJ = TB + (PD × ΨJB)
(5)
The typical ΨJB value is 29.1°C/W for the 10-lead LFCSP
40
package and 30.1°C/W for the 8-lead SOIC package.
20
140
T
MAXIMUM
J
0
120
100
80
60
40
20
0
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4
TOTAL POWER DISSIPATION (W)
Figure 58. Junction Temperature vs. Total Power Dissipation for
the 8-Lead SOIC, TA = 25°C
130
T
MAXIMUM
J
120
110
100
90
T
T
T
T
= 25°C
= 50°C
= 65°C
= 85°C
B
B
B
B
2
2
500mm
2
25mm
6400mm
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
TOTAL POWER DISSIPATION (W)
80
70
Figure 61. Junction Temperature vs. Total Power Dissipation for
the 10-Lead LFCSP
60
140
50
T
MAXIMUM
J
40
120
100
80
60
40
20
0
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
TOTAL POWER DISSIPATION (W)
Figure 59. Junction Temperature vs. Total Power Dissipation for
the 8-Lead SOIC, TA = 50°C
130
T
MAXIMUM
J
125
120
115
110
105
100
95
T
T
T
T
= 25°C
= 50°C
= 65°C
= 85°C
B
B
B
B
2
2
2
25mm
500mm
6400mm
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
TOTAL POWER DISSIPATION (W)
Figure 62. Junction Temperature vs. Total Power Dissipation for
the 8-Lead SOIC
90
85
80
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
TOTAL POWER DISSIPATION (W)
Figure 60. Junction Temperature vs. Total Power Dissipation for
the 8-Lead SOIC, TA = 85°C
Rev. A | Page 19 of 23
ADP7157
Data Sheet
When considering a VOUT = 1.8 V case, note that all four product
models can generate a 1.8 V output, but the ADP7157-01 model
provides the best PSRR performance, though other models, like
the ADP7157-04, are still capable of generating 1.8 V output for
PSRR relaxed applications.
PSRR PERFORMANCE
The ADP7157 is available in four models that optimize power
dissipation and PSRR performance as a function of input and
output voltage. See Table 9 and Table 10 for selection guides.
It is recommended to select the corresponding product model for a
particular output voltage range to achieve optimized PSRR
performance. For example, select the ADP7157-04 model for
The ADP7157 supports a 2.3 V to 5.5 V input range. Typically, a
minimum 500 mV headroom is required to achieve the best PSRR
performance above the maximum output voltage (VOUT
_MAX) at
1.2 A. For example, ADP7157-04 requires a minimum 3.8 V
input voltage to achieve the best PSRR performance for a 3.3 V
output at 1.2 A.
V
OUT = 3.3V to achieve >80 dB PSRR (10 Hz to 100 kHz) with
500 mV headroom.
Table 9. Model Selection Guide for PSRR
PSRR (dB) at 1.2 A; VIN = VOUT
_
MAX + 0.5 V
PSRR (dB) at 1.2 A; VIN = VOUT
_
MAX + 0.6 V
Model
VOUT
1.8
2.3
2.9
3.3
_
MAX (V)
10 kHz
70
72
75
82
100 kHz
1 MHz
52
53
55
55
10 kHz
100 kHz
1 MHz
55
57
60
60
ADP7157-01
ADP7157-02
ADP7157-03
ADP7157-04
78
70
78
72
75
75
79
84
85
83
94
86
Table 10. Model Selection Guide for Input Voltage
Model
Adjustable VOUT Range (V)
VOUT Range (V) for Optimized PSRR
VREG (V)
2.1
2.6
3.2
3.6
VIN Range (V)
2.3 to 5.5
2.8 to 5.5
3.4 to 5.5
3.8 to 5.5
ADP7157-01
ADP7157-02
ADP7157-03
ADP7157-04
1.2 to 1.8
1.2 to 2.3
1.2 to 2.9
1.2 to 3.3
1.2 to 1.8
1.8 to 2.3
2.3 to 2.9
2.9 to 3.3
Rev. A | Page 20 of 23
Data Sheet
ADP7157
PCB LAYOUT CONSIDERATIONS
Place the input capacitor as close as possible to the VIN pin and
ground. Place the output capacitor as close as possible to the
VOUT pin and ground. Place the bypass capacitors (CREG, CREF
and CBYP) for VREG, VREF, and VBYP close to the respective pins
,
(VREG, REF, and BYP) and ground. The use of a 0805, a 0603,
or a 0402 size capacitor achieves the smallest possible footprint
solution on boards where area is limited. Maximize the amount of
ground metal for the exposed pad, and use as many vias as
possible on the component side to improve thermal dissipation.
Figure 64. Sample 8-Lead SOIC PCB Layout
Figure 63. Sample 10-Lead LFCSP PCB Layout
Rev. A | Page 21 of 23
ADP7157
Data Sheet
OUTLINE DIMENSIONS
2.48
2.38
2.23
3.10
3.00 SQ
2.90
0.50 BSC
10
6
PIN 1 INDEX
EXPOSED
PAD
1.74
1.64
1.49
AREA
0.50
0.40
0.30
0.20 MIN
1
5
BOTTOM VIEW
TOP VIEW
PIN 1
INDICATOR
(R 0.15)
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.80
0.75
0.70
0.05 MAX
0.02 NOM
COPLANARITY
0.08
SECTION OF THIS DATA SHEET.
SEATING
PLANE
0.30
0.25
0.20
0.20 REF
Figure 65. 10-Lead Lead Frame Chip Scale Package [LFCSP]
3 mm × 3 mm Body and 0.75 mm Package Height
(CP-10-9)
Dimensions shown in millimeters
5.00
4.90
4.80
2.29
0.356
5
4
6.20
8
1
4.00
6.00
3.90
3.80
2.29
5.80
0.457
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
BOTTOM VIEW
45°
1.27 BSC
3.81 REF
TOP VIEW
SECTION OF THIS DATA SHEET.
1.65
1.25
1.75
1.35
0.50
0.25
0.25
0.17
0.10 MAX
0.05 NOM
SEATING
PLANE
8°
0°
0.51
0.31
1.04 REF
COPLANARITY
0.10
1.27
0.40
COMPLIANT TO JEDEC STANDARDS MS-012-AA
Figure 66. 8-Lead Standard Small Outline Package, with Exposed Pad [SOIC_N_EP]
Narrow Body
(RD-8-1)
Dimensions shown in millimeters
Rev. A | Page 22 of 23
Data Sheet
ADP7157
ORDERING GUIDE
Model1, 2
Temperature Range Output Voltage Range (V) Package Description
Package Option
CP-10-9
CP-10-9
CP-10-9
CP-10-9
RD-8-1
RD-8-1
RD-8-1
RD-8-1
Branding
LSX
LT0
LT1
LT2
ADP7157ACPZ-01-R7
ADP7157ACPZ-02-R7
ADP7157ACPZ-03-R7
ADP7157ACPZ-04-R7
ADP7157ARDZ-01-R7
ADP7157ARDZ-02-R7
ADP7157ARDZ-03-R7
ADP7157ARDZ-04-R7
ADP7157CP-04-EVALZ
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
1.2 to 1.8
1.2 to 2.3
1.2 to 2.9
1.2 to 3.3
1.2 to 1.8
1.2 to 2.3
1.2 to 2.9
1.2 to 3.3
10-Lead LFCSP
10-Lead LFCSP
10-Lead LFCSP
10-Lead LFCSP
8-Lead SOIC_N_EP
8-Lead SOIC_N_EP
8-Lead SOIC_N_EP
8-Lead SOIC_N_EP
Evaluation Board
1 Z = RoHS Compliant Part.
2 To order a device with voltage options other than the listed options, contact your local Analog Devices sales or distribution representative.
©2016 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D12938-0-5/16(A)
Rev. A | Page 23 of 23
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