ADM8692ARN-REEL [ADI]
IC 2-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO8, MS-012AA, SOIC-8, Power Management Circuit;
| 型号： | ADM8692ARN-REEL |
| 厂家： | 
ADI |
| 描述： | IC 2-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO8, MS-012AA, SOIC-8, Power Management Circuit 光电二极管 |
| 文件： | 总20页 (文件大小：471K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Microprocessor
Supervisory Circuits
ADM8690/ADM8691/ADM8692/ADM8693/ADM8694/ADM8695
FEATURES
FUNCTIONAL BLOCK DIAGRAMS
Upgrade for ADM690 to ADM695, MAX690 to MAX695
Specified over temperature
V
BATT
V
Low power consumption (0.7 mW)
Precision voltage monitor
OUT
V
CC
Reset assertion down to 1 V VCC
Low switch on resistance 0.7 Ω normal, 7 Ω in backup
High current drive (100 mA)
RESET
GENERATOR
1
RESET
4.65V
2
Watchdog timer: 100 ms, 1.6 s, or adjustable
400 nA standby current
Automatic battery backup power switching
Extremely fast gating of chip enable signals (3 ns)
Voltage monitor for power fail
WATCHDOG
TRANSITION DETECTOR
(1.6s)
ADM8690/
ADM8692/
ADM8694
WATCHDOG
INPUT (WDI)
POWER FAIL
INPUT (PFI)
POWER FAIL
OUTPUT (PFO)
1.3V
Available in TSSOP package
1
2
VOLTAGE DETECTOR = 4.65V (ADM8690, ADM8694)
4.40V (ADM8692)
RESET PULSE WIDTH = 50ms (AD8690, ADM8692)
200ms (ADM8694)
APPLICATIONS
Microprocessor systems
Computers
Figure 1. ADM8690/ADM8692/ADM8694
Controllers
Intelligent instruments
Automotive systems
BATT ON
ADM8691/
ADM8693/
ADM8695
V
BATT
PRODUCT HIGHLIGHTS
V
OUT
The ADM8690, ADM8692, and ADM8694 are available in
8-lead, PDIP packages and provide:
V
CC
CE
IN
CE
OUT
1. Power-on reset output during power-up, power-down, and
LOW LINE
RESET
1
4.65V
RESET
brownout conditions. The
output remains
operational with VCC as low as 1 V.
RESET AND
RESET
OSC IN
2. Battery backup switching for CMOS RAM, CMOS
microprocessor, or other low power logic.
WATCHDOG
GENERATOR
TIME BASE
RESET
OSC SEL
3. A reset pulse if the optional watchdog timer has not been
toggled within a specified time.
WATCHDOG
INPUT (WDI)
WATCHDOG
TRANSITION DETECTOR
WATCHDOG
TIMER
WATCHDOG
OUTPUT (WDO)
4. A 1.3 V threshold detector for power-fail warning, low battery
detection, or to monitor a power supply other than 5 V.
POWER FAIL
INPUT (PFI)
POWER FAIL
OUTPUT (PFO)
1.3V
The ADM8691, ADM8693, and ADM8695 are available in 16-lead
PDIP and small outline packages (including TSSOP) and
provide three additional functions:
1
VOLTAGE DETECTOR = 4.65V (ADM8691, ADM8695)
4.40V (ADM8693)
Figure 2. ADM8691/ADM8693/ADM8695
1. Write protection of CMOS RAM or EEPROM.
2. Adjustable reset and watchdog timeout periods.
3. Separate watchdog timeout, backup battery switchover, and
low VCC status outputs.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights ofthird parties that may result fromits use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2006 Analog Devices, Inc. All rights reserved.
ADM8690/ADM8691/ADM8692/ADM8693/ADM8694/ADM8695
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Product Highlights ........................................................................... 1
Functional Block Diagrams............................................................. 1
Revision History ............................................................................... 2
General Description......................................................................... 3
Specifications..................................................................................... 4
Absolute Maximum Ratings............................................................ 6
ESD Caution.................................................................................. 6
Pin Configurations and Function Descriptions ........................... 7
Typical Performance Characteristics ............................................. 8
Circuit Information........................................................................ 10
Battery Switchover Section........................................................ 10
Power-Fail Warning Comparator............................................. 13
Application Information................................................................ 14
Increasing the Drive Current.................................................... 14
Using a Rechargeable Battery for Backup ............................... 14
Adding Hysteresis to the Power-Fail Comparator................. 14
Monitoring the Status of the Battery ....................................... 14
Alternate Watchdog Input Drive Circuits............................... 15
Typical Applications....................................................................... 16
ADM8690, ADM8692, and ADM8694 ................................... 16
ADM8691, ADM8693, and ADM8695 ................................... 16
RESET
Output ............................................................................ 16
Power-Fail Detector ................................................................... 17
RAM Write Protection............................................................... 17
Watchdog Timer......................................................................... 17
Outline Dimensions....................................................................... 18
Ordering Guide .......................................................................... 19
RESET
Power-Fail
Output......................................................... 10
RESET
Watchdog Timer
Watchdog Output (
............................................................ 11
WDO
) ........................................................ 12
CE
Gating and RAM Write Protection
(ADM8691/ADM8693/ADM8695)......................................... 12
REVISION HISTORY
9/06—Rev. 0 to Rev. A
Updated Format..................................................................Universal
Changes to Absolute Maximum Ratings....................................... 6
Updated Ordering Guide............................................................... 20
2/97—Revision 0: Initial Version
Rev. A | Page 2 of 20
ADM8690/ADM8691/ADM8692/ADM8693/ADM8694/ADM8695
GENERAL DESCRIPTION
The ADM869x family of supervisory circuits offers complete
single- chip solutions for power supply monitoring and battery
control functions in microprocessor systems. These functions
include microprocessor reset, backup battery switchover,
watchdog timer, CMOS RAM write protection, and power
failure warning. The complete family provides a variety of
configurations to satisfy most microprocessor system
requirements.
extremely fast chip enable gating (3 ns), and high reliability.
RESET
addition, the power switching circuitry is designed for minimal
voltage drop thereby permitting increased output current drive
of up to 100 mA without the need of an external pass transistor.
assertion is guaranteed with VCC as low as 1 V. In
See Table 1 for a product selection guide listing the characteristics
of each device in the ADM869x family. To place an order, use
the Ordering Guide provided as the last section of this data sheet.
The ADM869x family is fabricated using an advanced epitaxial
CMOS process combining low power consumption (0.7 mW),
Table 1. Product Selection Guide
Part
Number
Nominal
Reset Time
Nominal VCC Reset
Threshold
Nominal Watchdog
Timeout Period
Battery Backup
Switching
Base Drive
Ext PNP
Chip Enable
Signals
ADM8690
ADM8691
ADM8692
ADM8693
ADM8694
ADM8695
50 ms
50 ms or ADJ
50 ms
50 ms or ADJ
200 ms
200 ms or ADJ
4.65 V
4.65 V
4.4 V
4.4 V
4.65 V
4.65 V
1.6 s
100 ms, 1.6 s, ADJ
1.6 s
100 ms, 1.6 s, ADJ
1.6 s
100 ms, 1.6 s, ADJ
Yes
Yes
Yes
Yes
Yes
Yes
No
Yes
No
Yes
No
Yes
No
Yes
No
Yes
No
Yes
Rev. A | Page 3 of 20
ADM8690/ADM8691/ADM8692/ADM8693/ADM8694/ADM8695
SPECIFICATIONS
VCC = full operating range, VBATT = 2.8 V, TA = TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
BATTERY BACKUP SWITCHING
VCC Operating Voltage Range
ADM8690, ADM8691, ADM8694, ADM8695
ADM8692, ADM8693
4.75
4.5
5.5
5.5
V
V
VBATT Operating Voltage Range
ADM8690, ADM8691, ADM8694, ADM8695
ADM8692, ADM8693
2.0
2.0
4.25
4.0
V
V
VOUT Output Voltage
VCC − 0.005
VCC − 0.2
VCC − 0.0025
VCC − 0.125
V
V
IOUT = 1 mA
IOUT ≤ 100 mA
VOUT in Battery Backup Mode
Supply Current (Excludes IOUT
VBATT − 0.005 VBATT − 0.002
V
μA
μA
IOUT = 250 μA, VCC < VBATT − 0.2 V
IOUT = 100 μA
VCC = 0 V, VBATT = 2.8 V
5.5 V > VCC > VBATT + 0.2 V
TA = 25°C
)
140
0.4
200
1
Supply Current in Battery Backup Mode
Battery Standby Current
+ = Discharge, − = Charge
Battery Switchover Threshold
VCC – VBATT
Battery Switchover Hysteresis
BATT ON Output Voltage
BATT ON Output Short-Circuit Current
−0.1
+0.02 μA
70
50
20
mV
mV
mV
V
mA
μA
Power-up
Power-down
0.3
25
ISINK = 3.2 mA
BATT ON = VOUT = 4.5 V sink current
BATT ON = 0 V source current
55
0.5
2.5
RESET AND WATCHDOG TIMER
Reset Voltage Threshold
ADM8690, ADM8691, ADM8694, ADM8695
ADM8692, ADM8693
Reset Threshold Hysteresis
4.5
4.25
4.65
4.4
40
4.73
4.48
V
V
mV
Reset Timeout Delay
ADM8690, ADM8691, ADM8692, ADM8693
ADM8694, ADM8695
Watchdog Timeout Period, Internal Oscillator
35
50
200
1.6
100
4064
1011
70
ms
ms
s
OSC SEL = high
OSC SEL = high
Long period
140
1.0
70
3840
768
50
280
2.25
140
4097
1025
ms
Short period
Watchdog Timeout Period, External Clock
cycles Long period
cycles Short period
ns
mV
V
Minimum WDI Input Pulse Width
RESET Output Voltage @ VCC = 1 V
RESET, LOW LINE Output Voltage
VIL = 0.4, VIH = 3.5 V
4
20
I
I
SINK = 10 μA, VCC = 1 V
0.05
0.4
SINK = 1.6 mA, VCC = 4.25 V
3.5
V
V
ISOURCE = 1 μA
ISINK = 1.6 mA
RESET, WDO Output Voltage
0.4
25
3.5
1
V
μA
mA
ISOURCE = 1 μA
Output Short-Circuit Source Current
Output Short-Circuit Sink Current
WDI Input Threshold1
Logic Low
Logic High
WDI Input Current
10
25
0.8
10
V
V
μA
μA
3.5
1
−1
WDI = VOUT
WDI = 0 V
−10
Rev. A | Page 4 of 20
ADM8690/ADM8691/ADM8692/ADM8693/ADM8694/ADM8695
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
POWER-FAIL DETECTOR
PFI Input Threshold
PFI Input Current
PFO Output Voltage
1.25
−25
1.3
0.01
1.35
+25
0.4
V
nA
V
VCC = 5 V
I
SINK = 3.2 mA
3.5
1
V
ꢀA
mA
ISOURCE = 1 μA
PFI = low, PFO = 0 V
PFI = high, PFO = VOUT
PFO Short-Circuit Source Current
PFO Short-Circuit Sink Current
3
25
25
CHIP ENABLE GATING
CEIN Threshold
0.8
0.4
7
V
VIL
3.0
V
μA
V
VIH
CEIN Pull-Up Current
CEOUT Output Voltage
3
3
I
SINK = 3.2 mA
VOUT − 1.5
VOUT − 0.05
V
V
ns
ISOURCE = 3.0 mA
ISOURCE = 1 μA, VCC = 0 V
CE Propagation Delay
OSCILLATOR
OSC IN Input Current
2
5
μA
μA
kHz
kHz
OSC SEL Input Pull-Up Current
OSC IN Frequency Range
OSC IN Frequency with External Capacitor
0
500
OSC SEL = 0 V
OSC SEL = 0 V, COSC = 47 pF
4
1 WDI is a three-level input that is internally biased to 38% of VCC and has an input impedance of approximately 5 MΩ.
Rev. A | Page 5 of 20
ADM8690/ADM8691/ADM8692/ADM8693/ADM8694/ADM8695
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Table 3.
Parameter
Rating
VCC
VBATT
All Other Inputs
−0.3 V to +6 V
−0.3 V to +6 V
−0.3 V to VOUT + 0.5 V
Input Current
VCC
VBATT
ESD CAUTION
200 mA
50 mA
GND
20 mA
Digital Output Current
Power Dissipation, N-8 PDIP
θJA Thermal Impedance
Power Dissipation, R-8 SOIC
θJA Thermal Impedance
Power Dissipation, N-16 PDIP
θJA Thermal Impedance
Power Dissipation, RU-16 TSSOP
θJA Thermal Impedance
Power Dissipation, R-16 SOIC_N
θJA Thermal Impedance
Power Dissipation, RW-16 SOIC_W
θJA Thermal Impedance
Operating Temperature Range
Industrial (A Version)
Lead Temperature (Soldering, 10 sec)
Storage Temperature Range
20 mA
400 mW
120°C/W
400 mW
120°C/W
600 mW
135°C/W
600 mW
158°C/W
600 mW
110°C/W
600 mW
73°C/W
−40°C to +85°C
300°C
−65°C to +150°C
Rev. A | Page 6 of 20
ADM8690/ADM8691/ADM8692/ADM8693/ADM8694/ADM8695
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
V
1
2
3
4
5
6
7
8
16 RESET
BATT
V
RESET
15
OUT
ADM8691/
ADM8693/
ADM8695
V
WDO
14
CC
V
V
1
2
3
4
8
7
6
5
OUT
BATT
ADM8690/
ADM8692/
ADM8694
GND
13 CE
12 CE
IN
V
RESET
WDI
CC
BATT ON
LOW LINE
OSC IN
TOP VIEW
OUT
GND
PFI
(Not to Scale)
TOP VIEW
(Not to Scale)
11 WDI
10 PFO
PFO
OSC SEL
9
PFI
Figure 3. ADM8690, ADM8692, and ADM8694
Pin Configuration
Figure 4. ADM8691, ADM8693, and ADM8695
Pin Configuration
Table 4. Pin Function Descriptions
Mnemonic Function
VCC
VBATT
VOUT
Power Supply Input. 5 V nominal.
Backup Battery Input.
Output Voltage. VCC or VBATT is internally switched to VOUT, depending on which is at the highest potential. VOUT can supply up to
100 mA to power CMOS RAM. Connect VOUT to VCC if VOUT and VBATT are not used.
GND
Ground. This is the 0 V ground reference for all signals.
RESET
Logic Output. RESET goes low if VCC falls below the reset threshold, or the watchdog timer is not serviced within its timeout
period. The reset threshold is typically 4.65 V for the ADM8690/ADM8691/ADM8694/ADM8695 and 4.4 V for the ADM8692
and ADM8693. RESET remains low for 50 ms (ADM8690/ADM8691/ADM8692/ADM8693) or 200 ms (ADM8694/ADM8695)
after VCC returns above the threshold. RESET also goes low for 50 ms (ADM8690/ADM8691/ADM8692/ADM8693) or 200 ms
(ADM8694/ADM8695) if the watchdog timer is enabled but not serviced within its timeout period. The RESET pulse width can
be adjusted on the ADM8691/ADM8693/ADM8695, as shown in Table 5. The RESET output has an internal 3 μA pull-up, and
can either connect to an open collector reset bus or directly drive a CMOS gate without an external pull-up resistor.
WDI
Watchdog Input. WDI is a three-level input. If WDI remains either high or low for longer than the watchdog timeout period,
RESET pulses low and WDO goes low. The timer resets with each transition on the WDI line. The watchdog timer can be
disabled if WDI is left floating or is driven to midsupply.
PFI
Power-Fail Input. PFI is the noninverting input to the power-fail comparator. When PFI is less than 1.3 V, PFO goes low.
Connect PFI to GND or VOUT when not used.
PFO
Power-Fail Output. PFO is the output of the power-fail comparator. It goes low when PFI is less than 1.3 V. The comparator is
turned off and PFO goes low when VCC is below VBATT
.
CEIN
Logic Input. The input to the CE gating circuit. When not in use, connect this pin to GND or VOUT
.
CEOUT
Logic Output. CEOUT is a gated version of the CEIN signal. CEOUT tracks CEIN when VCC is above the reset threshold. If VCC is below
the reset threshold, CEOUT is forced high. See Figure 21 and Figure 22.
BATT ON
Logic Output. BATT ON goes high when VOUT is internally switched to the VBATT input. It goes low when VOUT is internally
switched to VCC. The output typically sinks 35 mA and can directly drive the base of an external PNP transistor to increase the
output current above the 100 mA rating of VOUT
.
LOW LINE
Logic Output. LOW LINE goes low when VCC falls below the reset threshold. It returns high as soon as VCC rises above the reset
threshold.
RESET
Logic Output. RESET is an active high output. It is the inverse of RESET.
OSC SEL
Logic Oscillator Select Input. When OSC SEL is unconnected (floating) or driven high, the internal oscillator sets the reset
active time and watchdog timeout period. When OSC SEL is low, the external oscillator input, OSC IN, is enabled. OSC SEL has
a 3 μA internal pull-up (see Table 5).
OSC IN
WDO
Oscillator Logic Input. With OSC SEL low, OSC IN can be driven by an external clock signal or an external capacitor can be
connected between OSC IN and GND. This sets both the reset active pulse timing and the watchdog timeout period (see
Table 5 and Figure 17, Figure 18, Figure 19, and Figure 20). With OSC SEL high or floating, the internal oscillator is enabled and
the reset active time is fixed at 50 ms typical (ADM8691/ADM8693) or 200 ms typical (ADM8695). In this mode, the OSC IN pin
selects between fast (100 ms) and slow (1.6 s) watchdog timeout periods. In both modes, the timeout period immediately
after a reset is 1.6 s typical.
Logic Output. The watchdog output, WDO, goes low if WDI remains either high or low for longer than the watchdog timeout
period. WDO is set high by the next transition at WDI. If WDI is unconnected or at midsupply, the watchdog timer is disabled
and WDO remains high. WDO also goes high when LOW LINE goes low.
Rev. A | Page 7 of 20
ADM8690/ADM8691/ADM8692/ADM8693/ADM8694/ADM8695
TYPICAL PERFORMANCE CHARACTERISTICS
1.315
1.310
1.305
1.300
1.295
1.290
1.285
1.280
5.00
4.99
4.98
4.97
4.96
4.95
4.94
–60
–30
0
30
60
90
120
10
20
30
40
50
60
70
80
90
100
TEMPERATURE (°C)
I
(mA)
OUT
Figure 5. VOUT vs. IOUT Normal Operation
Figure 8. PFI Input Threshold vs. Temperature
2.800
2.798
2.796
2.794
2.792
2.790
2.788
2.786
53
52
51
V
= 5V
CC
ADM8690/
ADM8691/
ADM8692/
ADM8693
50
49
20
40
60
80
100
120
150
250
350
450
550
650
750
850
950 1050
TEMPERATURE (°C)
I
(µA)
OUT
Figure 6. VOUT vs. IOUT Battery Backup
Figure 9. Reset Active Time vs. Temperature
4.69
4.67
V
= 5V
CC
A4
3.36V
100
90
4.65
4.63
4.61
4.59
4.57
4.55
10
0%
1V
1V
500ms
–60
–30
0
30
60
90
120
TEMPERATURE (°C)
Figure 7. Reset Output Voltage vs. Supply Voltage
Figure 10. Reset Voltage Threshold vs. Temperature
Rev. A | Page 8 of 20
ADM8690/ADM8691/ADM8692/ADM8693/ADM8694/ADM8695
6
5
4
3
2
1
0
6
V
T
= 5V
PFI
V
T
= 5V
CC
= 25°C
CC
= 25°C
5
4
3
2
1
0
A
A
V
PFI
5V
PFO
1.3V
10kΩ
30pF
V
PFI
PFO
PFI
1.3V
30pF
PFO
1.35
1.25
1.35
1.25
PFO
0
0.2
0.4
0.6
0.8
TIME (µs)
1.0
1.2
1.4
1.6
1.8
0
0.1
0.2
0.3
0.4
TIME (µs)
0.5
0.6
0.7
0.8
Figure 11. Power-Fail Comparator Response Time Falling
Figure 13. Power-Fail Comparator Response Time with Pull-Up Resistor
6
5
4
3
2
1
0
V
= 5V
CC
= 25°C
T
A
V
PFI
PFO
1.3V
30pF
PFI
1.35
1.25
PFO
0
10
20
30
40
50
60
70
80
90
TIME (µs)
Figure 12. Power-Fail Comparator Response Time Rising
Rev. A | Page 9 of 20
ADM8690/ADM8691/ADM8692/ADM8693/ADM8694/ADM8695
CIRCUIT INFORMATION
charged condition. This extends the life of the backup battery by
BATTERY SWITCHOVER SECTION
compensating for its self-discharge current. Also note that this
current poses no problem when lithium batteries are used for
backup because the maximum charging current (0.1 μA) is safe
for even the smallest lithium cells.
The battery switchover circuit compares VCC to the VBATT input,
and connects VOUT to whichever is higher. Switchover occurs
when VCC is 50 mV higher than VBATT as VCC falls, and when VCC
is 70 mV greater than VBATT as VCC rises. This 20 mV of
hysteresis prevents repeated rapid switching if VCC falls very
slowly or remains nearly equal to the battery voltage.
If the battery switchover section is not used, VBATT should be
connected to GND and VOUT should be connected to VCC
.
V
CC
POWER-FAIL RESET OUTPUT
V
OUT
V
BATT
RESET
RESET
is an active low output that provides a signal to
the microprocessor whenever VCC is at an invalid level. When
RESET
output is forced
GATE DRIVE
V
CC falls below the reset threshold, the
low. The nominal reset voltage threshold is 4.65 V (ADM8690/
ADM8691/ADM8694/ADM8695) or 4.4 V (ADM8692/
ADM8693).
100
mV
BATT ON
(ADM8690,
ADM8695)
INTERNAL
SHUTDOWN SIGNAL
WHEN
700
mV
V
> (V + 0.7V)
BATT
CC
V2
V2
V
V1
V1
CC
Figure 14. Battery Switchover Schematic
t1
t1
RESET
During normal operation, with VCC higher than VBATT, VCC
is internally switched to VOUT through an internal PMOS tran-
sistor switch. This switch has a typical on resistance of 0.7 Ω
and can supply up to 100 mA at the VOUT terminal. VOUT is
normally used to drive a RAM memory bank, requiring
instantaneous currents of greater than 100 mA. If this is the
case, a bypass capacitor should be connected to VOUT. The
capacitor provides the peak current transients to the RAM.
A capacitance value of 0.1 μF or greater can be used.
LOW LINE
t
= RESET TIME
1
V1 = RESET VOLTAGE THRESHOLD LOW
V2 = RESET VOLTAGE THRESHOLD HIGH
HYSTERESIS = V2–V1
Figure 15. Power-Fail Reset Timing
RESET
On power-up,
remains low for 50 ms (200 ms for
If the continuous output current requirement at VOUT exceeds
100 mA, or if a lower VCC − VOUT voltage differential is desired,
an external PNP pass transistor can be connected in parallel
with the internal transistor. The BATT ON output (ADM8691/
ADM8693/ADM8695) can directly drive the base of the
external transistor.
ADM8694 and ADM8695) after VCC rises above the appropriate
reset threshold. This allows time for the power supply and micro-
RESET
processor to stabilize. On power-down, the
output remains
low with VCC as low as 1 V. This ensures that the microprocessor
is held in a stable shutdown condition.
RESET
This
active time is adjustable on the ADM8691/ADM8693/
A 7 Ω MOSFET switch connects the VBATT input to VOUT during
battery backup. This MOSFET has very low input-to-output
differential (dropout voltage) at the low current levels required
for battery back up of CMOS RAM or other low power CMOS
circuitry. The supply current in battery back up is typically 0.4 μA.
ADM8695 by using an external oscillator or by connecting an
external capacitor to the OSC IN pin. Refer to Table 5 and
Figure 17, Figure 18, Figure 19, and Figure 20.
The guaranteed minimum and maximum thresholds of the
ADM8690/ADM8691/ADM8694/ADM8695 are 4.5 V and
4.73 V, and the guaranteed thresholds of the ADM8692/ADM8693
are 4.25 V and 4.48 V. The ADM8690/ADM8691/ADM8694/
ADM8695 are, therefore, compatible with 5 V supplies with a
+10%, −5% tolerance and the ADM8692/ADM8693 are com-
patible with 5 V 10% supplies. The reset threshold comparator
has approximately 50 mV of hysteresis. The response time of
the reset voltage comparator is less than1 μs. If glitches are
present on the VCC line that could cause spurious reset pulses,
The ADM8690/ADM8691/ADM8694/ADM8695 operate with
battery voltages from 2.0 V to 4.25 V, and the ADM8692/
ADM8693 operate with battery voltages from 2.0 V to 4.0 V.
High value capacitors, either standard electrolytic or the farad-
size, double-layer capacitors, can also be used for short-term
memory backup. A small charging current of typically 10 nA
(0.1 μA maximum) flows out of the VBATT terminal. This current
is useful for maintaining rechargeable batteries in a fully
VCC should be decoupled close to the device.
Rev. A | Page 10 of 20
ADM8690/ADM8691/ADM8692/ADM8693/ADM8694/ADM8695
RESET
In addition to
contain an active high RESET output. This is the complement of
RESET
, the ADM8691/ADM8693/ADM8695
The normal (short) timeout period becomes effective following
RESET
the first transition of WDI after
has gone inactive. The
and is intended for processors requiring an active high
watchdog timeout period restarts with each transition on the
WDI pin. To ensure that the watchdog timer does not time out,
either a high-to-low or low-to-high transition on the WDI pin
must occur at, or less than, the minimum timeout period. If
WDI remains permanently either high or low, reset pulses are
issued after each long (1.6 s) timeout period. The watchdog
monitor can be deactivated by floating the watchdog input
(WDI) or by connecting it to midsupply.
reset signal.
WATCHDOG TIMER RESET
The watchdog timer circuit monitors the activity of the micro-
processor to check that it is not stalled in an indefinite loop. An
output line on the processor is used to toggle the watchdog input
(WDI) line. If this line is not toggled within the selected timeout
RESET
period, a
pulse is generated. The nominal watchdog
timeout period is preset at 1.6 seconds on the ADM8690/
ADM8692/ADM8694. The ADM8691/ADM8693/ADM8695
can be configured for either a fixed short 100 ms, or a long
1.6 second timeout period, or for an adjustable timeout period. If
the short period is selected, some systems are unable to service
the watchdog timer immediately after a reset, so the ADM8691/
ADM8693/ADM8695 automatically select the long timeout
period directly after a reset is issued. The watchdog timer is
restarted at the end of reset, whether the reset was caused by
lack of activity on WDI or by VCC falling below the reset
threshold.
WDI
WDO
t2
t3
RESET
t1
t1
t1
t1 = RESET TIME
t2 = NORMAL (SHORT) WATCHDOG TIMEOUT PERIOD
t3 = WATCHDOG TIMEOUT PERIOD IMMEDIATELY FOLLOWING A RESET
Figure 16. Watchdog Timeout Period and Reset Active Time
Table 5. ADM8691, ADM8693, ADM8695 Reset Pulse Width and Watchdog Timeout Selections
Watchdog Timeout Period
Reset Active Period
OSC SEL
OSC IN
Normal
Immediately After Reset
ADM8691/ADM8693
ADM8695
2048 CLKs
520 ms × C/47 pF
200 ms
Low1
External clock input
External capacitor
Low
1024 CLKs
400 ms × C/47 pF
100 ms
4096 CLKs
1.6 s × C/47 pF
1.6 s
512 CLKs
200 ms × C/47 pF
50 ms
Low1
Floating or high
Floating or high
Floating or high
1.6 s
1.6 s
50 ms
200 ms
1 With the OSC SEL pin low, OSC IN can be driven by an external clock signal, or an external capacitor (C) can be connected between OSC IN and GND. The nominal
internal oscillator frequency is 10.24 kHz. The nominal oscillator frequency with external capacitor is: FOSC (Hz) = 184,000/C (pF).
Rev. A | Page 11 of 20
ADM8690/ADM8691/ADM8692/ADM8693/ADM8694/ADM8695
8
7
On the ADM8690/ADM8692 the watchdog timeout period is
OSC SEL
NC
fixed at 1.6 seconds and the reset pulse width is fixed at 50 ms.
On the ADM8694 the watchdog timeout period is also 1.6 seconds
but the reset pulse width is fixed at 200 ms. The ADM8691/
ADM8693/ADM8695 allow these times to be adjusted, as shown
in Table 5. Figure 17, Figure 18, Figure 19, and Figure 20 show
ADM8691/
ADM8693/
ADM8695
OSC IN
Figure 20. Internal Oscillator (100 ms Watchdog)
the various oscillator configurations that can be used to adjust
the reset pulse width and watchdog timeout period.
CE GATING AND RAM WRITE PROTECTION
(ADM8691/ADM8693/ADM8695)
The internal oscillator is enabled when OSC SEL is high or
floating. In this mode, OSC IN selects between the 1.6 second
and 100 ms watchdog timeout periods. With OSC IN connected
high or floating, the 1.6 second timeout period is selected; and
with it connected low, the 100 ms timeout period is selected. In
either case, the timeout period is 1.6 seconds immediately after
a reset. This gives the microprocessor time to reinitialize the
system. If OSC IN is low, the 100 ms watchdog period becomes
effective after the first transition of WDI. The software should
be written such that the input/output port driving WDI is left in
its power-up reset state until the initialization routines are
completed and the microprocessor is able to toggle WDI at the
minimum watchdog timeout period of 70 ms.
The ADM8691/ADM8693/ADM8695 products include
memory protection circuitry that ensures the integrity of data
in memory by preventing write operations when VCC is at an
CE
CE
invalid level. There are two additional pins ( IN and
)
OUT
that can be used to control the chip enable or write inputs of
CE
CMOS RAM. When VCC is present, OUT is a buffered replica
CE
of IN, with a 3 ns propagation delay. When VCC falls below the
CE
reset voltage threshold or VBATT, an internal gate forces
CE
OUT
high, independent of
.
IN
CE
CE CS
, or write input of battery
OUT typically drives the
,
backed up CMOS RAM. This ensures the integrity of the data in
memory by preventing write operations when VCC is at an
invalid level. Similar protection of EEPROMs can be achieved
WATCHDOG OUTPUT (WDO)
CE
using the OUT to drive the store or write inputs.
WDO
The Watchdog Output
(ADM8691/ADM8693/ADM8695)
provides a status output that goes low if the watchdog timer
times out and remains low until set high by the next transition
ADM8691
ADM8693
ADM8695
WDO
on the watchdog input.
is also set high when VCC goes
CE
IN
CE
OUT
below the reset threshold.
V
V
LOW = 0
OK = 1
CC
CC
8
7
OSC SEL
ADM8691/
ADM8693/
ADM8695
Figure 21. Chip Enable Gating
CLOCK
0 TO 500kHz
V2
V2
OSC IN
V
V1
V1
CC
Figure 17. External Clock Source
t1
t1
RESET
8
OSC SEL
ADM8691/
ADM8693/
ADM8695
LOW LINE
7
OSC IN
C
OSC
Figure 18. External Capacitor
CE
IN
8
OSC SEL
NC
NC
ADM8691/
ADM8693/
ADM8695
CE
OUT
7
OSC IN
t
= RESET TIME
1
V1 = RESET VOLTAGE THRESHOLD LOW
V2 = RESET VOLTAGE THRESHOLD HIGH
HYSTERESIS = V2–V1
Figure 19. Internal Oscillator (1.6 Second Watchdog)
Figure 22. Chip Enable Timing
Rev. A | Page 12 of 20
ADM8690/ADM8691/ADM8692/ADM8693/ADM8694/ADM8695
POWER-FAIL WARNING COMPARATOR
Table 6. Input and Output Status in Battery Backup Mode
An additional comparator is provided for early warning of
failure in the microprocessor power supply. The power-fail
input (PFI) is compared to an internal 1.3 V reference. The
Signal
Status
VOUT
VOUT is connected to VBATT via an internal PMOS
switch.
PFO
power-fail output (
) goes low when the voltage at PFI is less
RESET
RESET
Logic low.
than 1.3 V. Typically, PFI is driven by an external voltage divider
that senses either the unregulated dc input to the system 5 V
regulator or the regulated 5 V output. The voltage divider ratio
can be chosen such that the voltage at PFI falls below 1.3 V
several milliseconds before the 5 V power supply falls below the
PFO
Logic high. The open-circuit output voltage is equal
to VOUT
.
LOW LINE Logic low.
BATT ON
WDI
Logic high. The open-circuit voltage is equal to VOUT
.
WDI is ignored. It is internally disconnected from the
internal pull-up resistor and does not source or sink
current as long as its input voltage is between GND
and VOUT. The input voltage does not affect supply
current.
reset threshold.
is normally used to interrupt the
microprocessor so that data can be stored in RAM and the shut-
down procedure executed before power is lost.
WDO
PFI
Logic high. The open circuit voltage is equal to VOUT.
ADM869x
INPUT
POWER
The power-fail comparator is turned off and has no
effect on the power-fail output.
Logic low.
POWER
FAIL
OUTPUT
1.3V
PFO
R1
R2
PFO
CEIN
POWER
FAIL
INPUT
CEIN is ignored. It is internally disconnected from its
internal pull-up and does not source or sink current
as long as its input voltage is between GND and
Figure 23. Power-Fail Comparator
V
OUT. The input voltage does not affect supply
current.
CEOUT
Logic high. The open circuit voltage is equal to VOUT
OSC IN is ignored.
OSC SEL is ignored.
.
OSC IN
OSC SEL
Rev. A | Page 13 of 20
ADM8690/ADM8691/ADM8692/ADM8693/ADM8694/ADM8695
APPLICATION INFORMATION
7V TO 15V
INPUT
POWER
5V
INCREASING THE DRIVE CURRENT
7805
If the continuous output current requirements at VOUT exceed
100 mA, or if a lower VCC – VOUT voltage differential is desired,
an external PNP pass transistor can be connected in parallel
with the internal transistor. The BATT ON output (ADM8691/
ADM8693/ADM8695) can directly drive the base of the
external transistor.
V
R
4
CC
R
1
1.3V
PFO
TO
PFI
MICROPROCESSOR
NMI
ADM869x
R
2
R
3
R
R
R
R
1
2
1
3
5V
PNP TRANSISTOR
1+
= 1.3V
+
–
V
H
(
)
5V INPUT
POWER
R
R (5V – 1.3V)
(1.3V (R + R ))
0.1µF
0.1µF
1
1
V
L
= 1.3V 1+
(
)
PFO
0V
R
R
2
3
3
4
V
V
OUT
BATT
ON
CC
ASSUMING R < < R THEN
4
3
R
V
1
BATT
HYSTERESIS V – V = 5V (R )
H
L
0V
V
V
H
ADM8691/
ADM8693/
ADM8695
L
2
BATTERY
V
IN
Figure 26. Adding Hysteresis to the Power-Fail Comparator
MONITORING THE STATUS OF THE BATTERY
Figure 24. Increasing the Drive Current
The power-fail comparator can be used to monitor the status of
the backup battery instead of the power supply, if desired. This
is shown in Figure 27. The PFI input samples the battery voltage
USING A RECHARGEABLE BATTERY FOR BACKUP
If a capacitor or a rechargeable battery is used for backup then
the charging resistor should be connected to VOUT because this
eliminates the discharge path that would exist during power-
PFO
and generates an active low
signal when the battery voltage
drops below a chosen threshold. It can be necessary to apply a
test load to determine the loaded battery voltage. This is done
down if the resistor is connected to VCC
.
V
– V
R
CE
CE
under processor control using OUT. Because OUT is forced
high during the battery backup mode, the test load is not
applied to the battery while it is in use, even if the
microprocessor is not powered.
OUT
BATT
I =
5V INPUT
POWER
0.1µF
R
0.1µF
V
V
OUT
CC
ADM869x
5V INPUT
POWER
V
BATT
RECHARGEABLE
BATTERY
V
V
BATT
CC
Figure 25. Rechargeable Battery
PFO
R
R
LOW BATTERY
SIGNAL TO
MICROPROCESSOR
I/O PIN
BATTERY
10MΩ
10MΩ
1
PFI
ADM869x
ADDING HYSTERESIS TO THE POWER-FAIL
COMPARATOR
2
20kΩ
OPTIONAL
CE
IN
FROM
TEST LOAD
For increased noise immunity, hysteresis can be added to the
power-fail comparator. Because the comparator circuit is
noninverting, hysteresis can be added simply by connecting a
MICROPROCESSOR
I/O PIN APPLIES
TEST LOAD
CE
OUT
TO BATTERY
Figure 27. Monitoring the Battery Status
PFO
resistor between the
output and the PFI input as shown in
is low, Resistor R3 sinks current from the
PFO
Figure 26. When
PFO
summing junction at the PFI pin. When
is high, the series
combination of R3 and R4 sources current into the PFI
summing junction. This results in differing trip levels for the
comparator.
Rev. A | Page 14 of 20
ADM8690/ADM8691/ADM8692/ADM8693/ADM8694/ADM8695
This can be done under program control using the circuit
shown in Figure 29. When the control input is high, the
OSC SEL pin is low and the watchdog timeout is set by the
external capacitor. A 0.01 μF capacitor sets a watchdog time-
out delay of 100 seconds. When the control input is low, the
OSC SEL pin is driven high, selecting the internal oscillator.
The 100 ms or the 1.6 s period is chosen, depending on which
diode is used, as shown in Figure 29. With D1 inserted, the
internal timeout is set at 100 ms; with D2 inserted, the timeout
is set at 1.6 seconds.
ALTERNATE WATCHDOG INPUT DRIVE CIRCUITS
The watchdog feature can be enabled and disabled under
program control by driving WDI with a three-state buffer (see
Figure 28). When three-stated, the WDI input floats, thereby
disabling the watchdog timer.
WATCHDOG
WDI
STROBE
ADM869x
CONTROL
INPUT
Figure 28. Programming the Watchdog Input
CONTROL
INPUT
OSC SEL
1
This circuit is not entirely foolproof, and it is possible for a
software fault to erroneously three-state the buffer preventing
the ADM869x from detecting that the microprocessor is no
longer operating correctly. In most cases, a better method is to
extend the watchdog period rather than disable the watchdog.
D2
ADM869x
D1
OSC IN
1
LOW = INTERNAL TIMEOUT
HIGH = EXTERNAL TIMEOUT
Figure 29. Programming the Watchdog Input
Rev. A | Page 15 of 20
ADM8690/ADM8691/ADM8692/ADM8693/ADM8694/ADM8695
TYPICAL APPLICATIONS
INPUT
POWER
V > 8V
5V
ADM8690, ADM8692, AND ADM8694
7805
0.1µF
0.1µF
R
1
Figure 30 shows the ADM8690/ADM8692/ADM8694 in a
typical power monitoring, battery backup application. VOUT
powers the CMOS RAM. Under normal operating conditions
with VCC present, VOUT is internally connected to VCC. If a power
failure occurs, VCC decays and VOUT is switched to VBATT, thereby
V
POWER
CC
CMOS RAM
POWER
V
PFI
OUT
ADM8690/
ADM8692/
ADM8694
R
2
MICROPROCESSOR
SYSTEM
RESET
RESET
V
BATT
+
PFO
WDI
NMI
RESET
maintaining power for the CMOS RAM. A
generated when VCC falls below 4.65 V for the ADM8690/
RESET
pulse is also
BATTERY
I/O LINE
GND
ADM8694 or 4.4 V for the ADM8692.
remains low for
Figure 31. ADM8690/ADM8692/ADM8694 Typical Application Circuit B
50 ms (200 ms for the ADM8694) after VCC returns to 5 V.
ADM8691, ADM8693, AND ADM8695
The watchdog timer input (WDI) monitors an input/output line
from the microprocessor system. This line must be toggled once
every 1.6 seconds to verify correct software execution. Failure to
toggle the line indicates that the microprocessor system is not
correctly executing its program and can be tied up in an endless
loop. If this happens, a reset pulse is generated to initialize the
microprocessor.
A typical connection for the ADM8691/ADM8693/ADM8695
is shown in Figure 32. CMOS RAM is powered from VOUT
When 5 V power is present, this is routed to VOUT. If VCC fails,
BATT is routed to VOUT. VOUT can supply up to 100 mA from
.
V
VCC, but if more current is required, an external PNP transistor
can be added. When VCC is higher than VBATT, the BATT ON
output goes low, providing up to 25 mA of base drive for the
external transistor. A 0.1 μF capacitor is connected to VOUT to
supply the transient currents for CMOS RAM. When VCC is
lower than VBATT, an internal 20 Ω MOSFET connects the
If the watchdog timer is not needed, the WDI input should be
left floating.
The power-fail input, PFI, monitors the input power supply via
a resistive divider network. The voltage on the PFI input is
compared with a precision 1.3 V internal reference. If the input
backup battery to VOUT
.
INPUT POWER
5V
PFO
voltage drops below 1.3 V, a power-fail output (
) signal is
0.1µF
0.1µF
generated. This warns of an impending power failure and can
be used to interrupt the processor so that the system can be shut
down in an orderly fashion. The resistors in the sensing
network are ratioed to give the desired power-fail threshold
voltage (VT).
V
BATT
ON
V
CC
OUT
CMOS
RAM
3V
BATTERY
CE
V
OUT
BATT
ADM8691/
ADM8693/
ADM8695
ADDRESS
DECODE
CE
R
R
IN
1
PFI
A0 TO 15
I/O LINE
GND
2
WDI
PFO
VT = (1.3 R1/R2) + 1.3 V
NC
OSC IN
NMI
OSC SEL
RESET
RESET
0.1µF
R1/R2 = (VT/1.3) − 1
MICROPROCESSOR
SYSTEM
LOW LINE WDO
RESET
5V
R
R
SYSTEM STATUS
INDICATORS
1
2
POWER
V
CC
CMOS RAM
POWER
V
PFI
OUT
Figure 32. ADM8691/ADM8693/ADM8695 Typical Application
0.1µF
ADM8690/
ADM8692/
ADM8694
MICROPROCESSOR
SYSTEM
RESET OUTPUT
RESET
The internal voltage detector monitors VCC and generates a
RESET
V
BATT
+
PFO
WDI
NMI
RESET
output to hold the microprocessor reset line low when
CC is below 4.65 V (4.4 V for ADM8693). An internal timer
BATTERY
I/O LINE
GND
V
RESET
holds
low for 50 ms (200 ms for the ADM8695) after
Figure 30. ADM8690/ADM8692/ADM8694 Typical Application Circuit A
VCC rises above 4.65 V (4.4 V for the ADM8693). This prevents
RESET
repeated toggling of
, even if the 5 V power drops out
Figure 31 shows a similar application, but in this case the PFI
input monitors the unregulated input to the 7805 voltage
regulator. This gives an earlier warning of an impending power
failure. It is useful with processors operating at low speeds or
where there are a significant number of housekeeping tasks to
be completed before the power is lost.
and recovers with each power line cycle.
The crystal oscillator normally used to generate the clock for
microprocessors can take several milliseconds to stabilize.
Because most microprocessors need several clock cycles to
RESET
reset,
must be held low until the microprocessor clock
RESET
oscillator has started. The power-up
pulse lasts 50 ms
Rev. A | Page 16 of 20
ADM8690/ADM8691/ADM8692/ADM8693/ADM8694/ADM8695
(200 ms for the ADM8695) to allow for this oscillator start-up
microprocessor from writing erroneous data into RAM during
power-up, power-down, brownouts, and momentary power
interruptions.
time. If a different reset pulse width is required, a capacitor
should be connected to OSC IN, or an external clock can be
used. Refer to Table 5 and Figure 17, Figure 18, Figure 19, and
Figure 20. The manual reset switch and the 0.1 μF capacitor
connected to the reset line can be omitted if a manual reset is
not needed. An inverted, active high, RESET output is also
available.
WATCHDOG TIMER
The microprocessor drives the watchdog input (WDI) with an
input/output line. When OSC IN and OSC SEL are unconnected,
the microprocessor must toggle the WDI pin once every
1.6 seconds to verify proper software execution. If a hardware
or software failure occurs such that WDI is not toggled, the
ADM8691/ADM8693 issues a 50 ms (200 ms for the ADM8695)
POWER-FAIL DETECTOR
The 5 V VCC power line is monitored via a resistive potential
divider connected to the power-fail input (PFI). When the
RESET
pulse after 1.6 seconds. This typically restarts the micro-
PFO
voltage at PFI falls below 1.3 V, the power-fail output (
)
RESET
processor power-up routine. A new
pulse is issued every
drives the processor’s NMI input low. If, for example, a power-
fail threshold of 4.8 V is set with Resistor R1 and Resistor R2, the
microprocessor has the time when VCC falls from 4.8 V to 4.65 V
to save data into RAM. An earlier power-fail warning can be
generated if the unregulated dc input to the 5 V regulator is
available for monitoring. This allows more time for microprocessor
housekeeping tasks to be completed before power is lost.
1.6 seconds until WDI is again strobed. If a different watchdog
timeout period is required, a capacitor should be connected to
OSC IN or an external clock can be used. Refer to Table 5 and
Figure 17, Figure 18, Figure 19, and Figure 20.
WDO
The watchdog output (
not serviced within its timeout period. Once
) goes low if the watchdog timer is
WDO
goes low, it
remains low until a transition occurs at WDI. The watchdog
timer feature can be disabled by leaving WDI unconnected.
RAM WRITE PROTECTION
CE
The ADM8691/ADM8693/ADM8695 OUT line drives the
RESET
The
output has an internal 3 μA pull-up and can either
CE
CE
chip select inputs of the CMOS RAM. OUT follows IN as
long as VCC is above the 4.65 V (4.4 V for the ADM8693) reset
threshold.
connect to an open collector reset bus or directly drive a CMOS
gate without an external pull-up resistor.
CE
If VCC falls below the reset threshold, OUT goes high,
CE
independent of the logic level at IN. This prevents the
Rev. A | Page 17 of 20
ADM8690/ADM8691/ADM8692/ADM8693/ADM8694/ADM8695
OUTLINE DIMENSIONS
0.400 (10.16)
0.365 (9.27)
5.00 (0.1968)
4.80 (0.1890)
0.355 (9.02)
8
1
5
4
8
5
4
0.280 (7.11)
0.250 (6.35)
0.240 (6.10)
6.20 (0.2440)
5.80 (0.2284)
4.00 (0.1574)
3.80 (0.1497)
1
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
PIN 1
0.100 (2.54)
1.27 (0.0500)
BSC
0.50 (0.0196)
0.25 (0.0099)
BSC
× 45°
0.060 (1.52)
MAX
0.195 (4.95)
0.130 (3.30)
0.115 (2.92)
1.75 (0.0688)
1.35 (0.0532)
0.210
(5.33)
MAX
0.25 (0.0098)
0.10 (0.0040)
0.015
(0.38)
MIN
0.150 (3.81)
0.130 (3.30)
0.115 (2.92)
0.015 (0.38)
GAUGE
8°
0.51 (0.0201)
0.31 (0.0122)
0.014 (0.36)
0.010 (0.25)
0.008 (0.20)
0° 1.27 (0.0500)
PLANE
COPLANARITY
0.10
0.25 (0.0098)
0.17 (0.0067)
SEATING
PLANE
SEATING
PLANE
0.40 (0.0157)
0.022 (0.56)
0.430 (10.92)
MAX
0.005 (0.13)
MIN
0.018 (0.46)
0.014 (0.36)
COMPLIANT TO JEDEC STANDARDS MS-012-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
0.070 (1.78)
0.060 (1.52)
0.045 (1.14)
COMPLIANT TO JEDEC STANDARDS MS-001-BA
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.
Figure 33. 8-Lead Plastic Dual In-Line Package [PDIP]
(N-8)
Figure 35. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-8)
Dimensions shown in inches and (millimeters)
Dimensions shown in millimeters and (inches)
0.800 (20.32)
0.790 (20.07)
0.780 (19.81)
10.50 (0.4134)
10.10 (0.3976)
16
1
9
8
0.280 (7.11)
0.250 (6.35)
0.240 (6.10)
16
1
9
8
7.60 (0.2992)
7.40 (0.2913)
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
PIN 1
0.100 (2.54)
10.65 (0.4193)
10.00 (0.3937)
BSC
0.060 (1.52)
MAX
0.195 (4.95)
0.130 (3.30)
0.115 (2.92)
0.210
(5.33)
MAX
0.015
(0.38)
MIN
0.150 (3.81)
0.015 (0.38)
GAUGE
PLANE
1.27 (0.0500)
0.130 (3.30)
0.115 (2.92)
0.75 (0.0295)
0.25 (0.0098)
2.65 (0.1043)
2.35 (0.0925)
0.014 (0.36)
0.010 (0.25)
0.008 (0.20)
BSC
× 45°
SEATING
PLANE
0.30 (0.0118)
0.10 (0.0039)
0.022 (0.56)
0.430 (10.92)
MAX
0.005 (0.13)
MIN
0.018 (0.46)
0.014 (0.36)
8°
0°
0.070 (1.78)
0.060 (1.52)
0.045 (1.14)
0.51 (0.0201)
0.31 (0.0122)
SEATING
PLANE
COPLANARITY
0.10
1.27 (0.0500)
0.40 (0.0157)
0.33 (0.0130)
0.20 (0.0079)
COMPLIANT TO JEDEC STANDARDS MS-001-AB
COMPLIANT TO JEDEC STANDARDS MS-013-AA
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 36. 16-Lead Standard Small Outline Package [SOIC_W]
Figure 34. 16-Lead Plastic Dual In-Line Package [PDIP]
(N-16)
Wide Body
(RW-16)
Dimensions shown in inches and (millimeters)
Dimensions shown in millimeters and (inches)
Rev. A | Page 18 of 20
ADM8690/ADM8691/ADM8692/ADM8693/ADM8694/ADM8695
5.10
5.00
4.90
10.00 (0.3937)
9.80 (0.3858)
16
1
9
8
6.20 (0.2441)
5.80 (0.2283)
4.00 (0.1575)
3.80 (0.1496)
16
9
4.50
4.40
4.30
6.40
BSC
1.75 (0.0689)
1.35 (0.0531)
1.27 (0.0500)
BSC
0.50 (0.0197)
0.25 (0.0098)
× 45°
0.25 (0.0098)
0.10 (0.0039)
1
8
PIN 1
8°
0°
0.51 (0.0201)
0.31 (0.0122)
SEATING
PLANE
1.27 (0.0500)
0.40 (0.0157)
COPLANARITY
0.10
0.25 (0.0098)
0.17 (0.0067)
1.20
MAX
0.15
0.05
0.20
0.09
0.75
0.60
0.45
COMPLIANT TO JEDEC STANDARDS MS-012-AC
8°
0°
0.30
0.19
0.65
BSC
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
SEATING
PLANE
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-153-AB
Figure 37. 16-Lead Standard Small Outline Package [SOIC_N]
Figure 38. 16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Narrow Body
(R-16)
Dimensions shown in millimeters
Dimensions shown in millimeters and (inches)
ORDERING GUIDE
Model
ADM8690AN
ADM8690ANZ1
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
Package Option
8-Lead Plastic Dual In-Line Package [PDIP]
8-Lead Plastic Dual In-Line Package [PDIP]
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Standard Small Outline Package [SOIC_N]
16-Lead Plastic Dual In-Line Package [PDIP]
N-8
N-8
R-8
R-8
ADM8690ARN
ADM8690ARN-REEL
ADM8690ARNZ1
ADM8691AN
ADM8691ANZ1
ADM8691ARN
ADM8691ARN-REEL
ADM8691ARNZ1
ADM8691ARW
ADM8691ARW-REEL
ADM8691ARWZ1
ADM8691ARU
ADM8691ARU-REEL
ADM8691ARUZ1
ADM8692AN
ADM8692ANZ1
ADM8692ARN
ADM8692ARN-REEL
ADM8692ARNZ1
ADM8693AN
ADM8693ANZ1
ADM8693ARN
R-8
N-16
N-16
R-16
R-16
R-16
RW-16
RW-16
RW-16
RU-16
RU-16
RU-16
N-8
16-Lead Plastic Dual In-Line Package [PDIP]
16-Lead Standard Small Outline Package [SOIC_N]
16-Lead Standard Small Outline Package [SOIC_N]
16-Lead Standard Small Outline Package [SOIC_N]
16-Lead Standard Small Outline Package [SOIC_W]
16-Lead Standard Small Outline Package [SOIC_W]
16-Lead Standard Small Outline Package [SOIC_W]
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Thin Shrink Small Outline Package [TSSOP]
8-Lead Plastic Dual In-Line Package [PDIP]
8-Lead Plastic Dual In-Line Package [PDIP]
N-8
R-8
R-8
R-8
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Standard Small Outline Package [SOIC_N]
16-Lead Plastic Dual In-Line Package [PDIP]
N-16
N-16
R-16
R-16
R-16
RW-16
RW-16
RW-16
RU-16
RU-16
RU-16
16-Lead Plastic Dual In-Line Package [PDIP]
16-Lead Standard Small Outline Package [SOIC_N]
16-Lead Standard Small Outline Package [SOIC_N]
16-Lead Standard Small Outline Package [SOIC_N]
16-Lead Standard Small Outline Package [SOIC_W]
16-Lead Standard Small Outline Package [SOIC_W]
16-Lead Standard Small Outline Package [SOIC_W]
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Thin Shrink Small Outline Package [TSSOP]
ADM8693ARN-REEL
ADM8693ARNZ1
ADM8693ARW
ADM8693ARW-REEL
ADM8693ARWZ1
ADM8693ARU
ADM8693ARU-REEL
ADM8693ARUZ1
Rev. A | Page 19 of 20
ADM8690/ADM8691/ADM8692/ADM8693/ADM8694/ADM8695
Model
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
Package Option
ADM8694AN
8-Lead Plastic Dual In-Line Package [PDIP]
8-Lead Plastic Dual In-Line Package [PDIP]
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Standard Small Outline Package [SOIC_N]
16-Lead Standard Small Outline Package [SOIC_W]
16-Lead Standard Small Outline Package [SOIC_W]
16-Lead Standard Small Outline Package [SOIC_W]
N-8
N-8
R-8
R-8
ADM8694ANZ1
ADM8694ARN
ADM8694ARN-REEL
ADM8694ARNZ1
ADM8695ARW
ADM8695ARW-REEL
ADM8695ARWZ1
R-8
RW-16
RW-16
RW-16
1 Z = Pb-free part.
©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C00093-0-9/06(A)
Rev. A | Page 20 of 20
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