ADMOD79JQ [ADI]
IC SPECIALTY ANALOG CIRCUIT, CDIP28, 0.600 INCH, CERDIP-28, Analog IC:Other;
| 型号： | ADMOD79JQ |
| 厂家： | 
ADI |
| 描述： | IC SPECIALTY ANALOG CIRCUIT, CDIP28, 0.600 INCH, CERDIP-28, Analog IC:Other CD 信息通信管理 |
| 文件： | 总9页 (文件大小：166K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
a
Dual-Channel ∑∆ Modulator
ADM0D79*
FEATURES
FUNCTIO NAL BLO CK D IAGRAM
High-Perform ance ∑∆ ADC Building Block
Fifth-Order, 64 Tim es Oversam pling Modulator w ith
Patented Noise-Shaping
VINL+
DAC
Modulator Clock Rate to 3.57 MHz
103 dB Dynam ic Range (for 20 kHz Input
Bandw idth)
LOUT
∫
∫
∫
∫
∫
Differential Architecture for Superior SNR and Dynam ic
Range
Dual-Channel Differential Analog Inputs (±6.2 V
Differential Input Voltage)
DAC
VINL–
VINR+
REFERENCE
DAC
On-Chip Voltage Reference
APPLICATIONS
Digital Audio
ROUT
Medical Electronics
Electronic Im aging
Sonar Signal Processing
Instrum entation
∫
∫
∫
∫
∫
DAC
VINR–
P RO D UCT O VERVIEW
dynamic range and excellent common-mode rejection character-
istics. Because its modulator is single-bit, the ADMOD79 is
inherently monotonic and has no mechanism for producing
differential linearity errors. Analog and digital supply connec-
tions are separated to isolate the analog circuitry from the digital
supplies.
T he ADMOD79 Sigma-Delta (∑∆) modulator is a building
block which can be used to build a superior analog-to-digital
conversion system customized to a particular application’s
requirement. T he ADMOD79 is a two-channel, fully differen-
tial modulator. Each channel consists of a fifth-order one-bit
noise shaping modulator. An on-chip voltage reference provides
a voltage source to both channels that is stable over temperature
and time. T here are separate single-bit digital outputs for each
channel. T he ADMOD79 accepts a 64 × FS input master clock
(SMPCLK) that can range from 2.5 kHz to 3.57 MHz.
T he ADMOD79 is fabricated in a BiCMOS process and is
supplied in a 0.6" wide 28-lead cerdip package. T he
ADMOD79 operates from ±5 V power supplies over the
temperature range of –25°C to +70°C.
Input signals are sampled at 64 × FS on switched-capacitors,
eliminating external sample-and-hold amplifiers and minimizing
the requirements for antialias filtering at the input. With
simplified antialiasing, linear phase can be preserved across the
passband. T he ADMOD79’s proprietary fifth-order differential
switched-capacitor modulator architecture shapes the one-bit
comparator’s quantization noise out of the passband. T he high
order of the modulator randomizes the modulator output,
reducing idle tones in the output spectrum to very low levels.
T he ADMOD79’s differential architecture provides increased
*P r otected by U.S. P atent Num ber s 5055843, 5126653, and other s pending.
REV. 0
Inform ation furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assum ed by Analog Devices for its
use, nor for any infringem ents of patents or other rights of third parties
which m ay result from its use. No license is granted by im plication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norw ood. MA 02062-9106, U.S.A.
Tel: 617/ 329-4700
Fax: 617/ 326-8703
ADMOD79–SPECIFICATIONS
TEST CO ND ITIO NS UNLESS O TH ERWISE NO TED
Supply Voltages
±5
V
Input Signal
974
Hz
Ambient T emperature
Input Clock (SMPCLK)
25
3.072
°C
MHz
–0.5
0 to 20
dB Full-Scale
kHz
Passband
Min
Typ
Max
Units
ANALOG PERFORMANCE
Dynamic Range (0 Hz to 20 kHz, –60 dB Input)
No A-Weight Filter
With A-Weight Filter
Signal to (Distortion + Noise)
Full-Scale Input
100
90
103
105
dB
dB
96
83
–20 dB Input
T rimmed1 Signal to (Distortion + Noise)
Full-Scale Input
93
98
83
dB
dB
–20 dB Input
T rimmed1 Signal to T otal Harmonic Distortion
Full-Scale Input
98
100
dB
dB
–20 dB Input
Analog Inputs
Differential Input Range2
Input Impedance at Each Input Pin
DC Accuracy
±5.89
±6.2
7.0
±6.51
V
kΩ
Gain Error
±5
%
Interchannel Gain Mismatch
Gain Drift
Offset Error (Referrred to Input)
Offset Drift (Referred to Input)
Voltage Reference*
±0.15
dB
±200
±0.057
±13
ppm/°C
% of FS
ppm/°C
V
±0.343
2.4
2.8
3.2
Crosstalk (EIAJ Method)
100
dB
Interchannel Phase Deviation
±0.001
Degrees
DIGIT AL T IMING (Guaranteed over 0°C ≤ T A ≤ 70°C, AVSS = –5.0 V ± 5%, AVDD = DVDD = +5.0 V ± 5%)
tSCP
SMPCLK Period
0.28
140
140
400
µs
ns
ns
ns
tSCPWL
tSCPWH
tOPD
SMPCLK LO Pulse Width
SMPCLK HI Pulse Width
Propagation Delay, SMPCLK
Falling Edge to ROUT , LOUT
Propagation Delay, SMPCLK
Rising Edge to RRESET, LRESET
100
125
tRPD
ns
DIGIT AL I/O (Guaranteed over 0°C ≤ T A ≤ 70°C, AVSS = –5.0 V ± 5%, AVDD = DVDD = +5.0 V ± 5%)
Input Voltage HI (VIH)
3.4
V
Input Voltage LO (VIL)
IIH @ VIH = 5 V
IIL @ VIL = 0 V
Output Voltage HI (VOH @ IOH = 360 µA)
Output Voltage LO (VOL @ IOL = 1.6 mA)
0.8
10
10
V
µA
µA
V
4.0
0.5
V
POWER SUPPLIES
Current, DVDD
1.0
76
8
1.5
95
12
20
mA
mA
mA
mA
Current, AVDD1, AVSS1
Current, AVDD2, AVSS2
Current, AVDD1, AVSS1 – Power Down
Dissipation
14
Operation (All Supplies)
Power Down (All Supplies)
Power Supply Rejection
1 kHz 300 mV p-p Signal at Analog Supply Pins
845
225
1078
328
mW
mW
102
+25
dBFS
T EMPERAT URE RANGE
Specifications Guaranteed
Functionality Guaranteed
Storage
°C
°C
°C
–25
–60
+70
+100
NOT ES
1Differential gain imbalance manually trimmed to eliminate second harmonic. See “Application Issues” below.
2T he differential input range is twice the range seen at each input pin. T he input range corresponds to the full-scale digital output range.
*Guaranteed, not tested.
Specifications subject to change without notice.
–2–
REV. 0
ADMOD79
ABSO LUTE MAXIMUM RATINGS*
P IN D ESCRIP TIO NS
Input/
Min
Max
Units
P in
Num ber Mnem onic O utput D escription
DVDD to DGND and
AVDD1/AVDD2 to AGND
AVSS1/AVSS2 to AGND
AVSS2 to AVSS1
Digital Input to DGND
Analog Inputs
AGND to DGND
Reference Voltage
Soldering
0
–6
–0.3
–0.3
6
0
V
V
V
V
V
V
1
2
RRESET
ROUT
O
O
Right Modulator Reset
Right Bitstream Modulator
Output
3.072 MHz (Nominal)
Modulator Input Clock
Digital Ground
DVDD + 0.3
AVSS1 + 0.3
0.3
3
SMPCLK
I
AVSS1 – 0.3
–0.3
Indefinite Short Circuit to Ground
4
DGND
AVSS1
AVSS2
AGND
N/C
I
I
I
I
5
–5 V Analog Supply
–5 V Analog Logic Supply
+300
10
°C
sec
6
7
Analog Ground
*Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. T his is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
8
No Connect
9
PWRDWN
N/C
I
Power Down
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
No Connect
VINR–
VINR+
VREFIR
VREFOR
VREFOL
VREFIL
VINL+
VINL–
AGND
N/C
I
Right Inverting Input
Right Noninverting Input
Right Reference Input
Right Reference Output
Left Reference Output
Left Reference Input
Left Noninverting Input
Left Inverting Input
Analog Ground
O RD ERING GUID E
I
I
Tem perature
Range
P ackage
D escription
P ackage
O ption
O
O
I
Model
ADMOD79JQ
0°C to +70°C
Cerdip
Q-28
I
I
P IN CO NFIGURATIO NS
I
No Connect
RRESET
1
2
3
4
5
6
7
8
9
28 LRESET
27
N/C
No Connect
ROUT
SMPCLK
DGND
LOUT
AVDD
N/C
1
2
I
+5 V Analog Supply
No Connect
26 CALIB
25 DVDD
AVSS
AVSS
1
2
24 AVDD
23 N/C
22 AVDD
21 N/C
20 N/C
2
AVDD
I
+5 V Analog Logic Supply
+5 V Digital Supply
Calibration
Left Bitstream Modulator
Output
DVDD
I
ADMOD79
TOP VIEW
(Not to Scale)
AGND
N/C
1
CALIB
LOUT
I
O
PWRDWN
N/C 10
VINR– 11
VINR+ 12
19 AGND
18 VINL–
17 VINL+
16 VREF IL
15 VREF OL
28
LRESET
O
Left Modulator Reset Signal
V
REF IR 13
V
REF OR 14
N/C = NO CONNECT
CAUTIO N
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADMOD79 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. T herefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. 0
–3–
ADMOD79
D EFINITIO NS
TH EO RY O F O P ERATIO N
Resonators in the proprietary fifth-order ADMOD79 modulator
architecture place zeros in the noise-shaping spectrum, reducing
the quantization noise at lower frequencies. (See Figure 1.)
T he ADMOD79’s fully differential architecture increases its
signal-to-noise ratio performance. Completely independent
right and left channels with separate references minimize
crosstalk. Modulator clock rates as high as 3.57 MHz are
supported.
D ynam ic Range
T he ratio of a full-scale output signal to the integrated output
noise in the passband (0 kHz to 20 kHz with a 3.072 MHz
modulator clock rate), expressed in decibels (dB). Dynamic
range is measured with a –60 dB input signal and is equal to (S/
[T HD+N]) +60 dB.
Signal to (D istor tion + Noise) (or S/[TH D +N])
T he ratio of the root-mean-square (rms) value of the fundamen-
tal input signal to the rms sum of all spectral components in the
passband, expressed in decibels (dB).
–80
–85
–90
Signal to Total H ar m onic D istor tion (or S/TH D )
T he ratio of the rms value of the fundamental input signal to the
rms sum of all harmonically related spectral components in the
passband, expressed in decibels (dB).
–95
–100
–105
–110
Gain Er r or
–115
–120
–125
–130
–135
–140
–145
With a near full-scale input, the ratio of actual output to
expected output, expressed as a percentage.
Inter channel Gain Mism atch
With near full-scale inputs, the ratio of outputs of the two stereo
channels, expressed in decibels.
Gain D r ift
0
10
20
30
40
50
60
70
80
90
100
FREQUENCY – kHz
Change in response to a near full-scale input with a change in
temperature, expressed as parts-per-million (ppm) per °C.
Figure 1. Noise Spectrum per 5 Hz (3.072 MHz Modulator
Clock)
Midscale O ffset Er r or
Output response to a midscale input (i.e., zero volts dc),
expressed as a percentage of full scale.
User-supplied digital decimation filters allow for a broad range
of performance and filter functions. For standard, brick-wall
digital low-pass filters with sufficient stopband attenuation, the
following performance can be achieved with the ADMOD79
running at a 3.072 MHz modulator clock rate:
Midscale D r ift
Change in midscale offset error with a change in temperature,
expressed as parts-per-million (ppm) of full scale per °C.
Cr osstalk
Filter Cut-O ff
Frequency
O versam pling
Ratio
Signal-to-Noise
Ratio
Ratio of response on one channel with a grounded input to a
full-scale 1 kHz sine-wave input on the other channel, expressed
in decibels.
20 kHz
10 kHz
5 kHz
2.5 kHz
1.25 kHz
625 Hz
64
103 dB
106 dB
109 dB
112 dB
115 dB
118 dB
Inter channel P hase D eviation
128
256
512
1024
2048
Difference in input sampling times between stereo channels,
expressed as a phase difference in degrees between 1 kHz
inputs.
P ower Supply Rejection
With analog inputs grounded, energy at the output when a
300 mV p-p signal applied to the power supply pins, expressed
in decibels of full scale.
–4–
REV. 0
ADMOD79
In general, since the noise is spectrally white in the passband,
each halving of the input bandwidth with a constant modulator
clock frequency will increase the SNR across the bandwidth by
3 dB.
O P ERATING FEATURES
T he ADMOD79 produces a pair of noise-shaped bitstreams
(LOUT and ROUT ) from a pair of differential analog inputs
(+VINL & –VINL and +VINR & –VINR). T he analog input
signal range at any given signal input pin is ±3.1 V. T his
implies that voltage difference across each differential pair can
range ±6.2 V. T he modulator clock oversamples the analog
input at a rate much higher than the input bandwidth, signifi-
cantly reducing the requirements on antialiasing filters. Only
signals with frequency components near the very high modula-
tor clock rate will alias into the passband. T he high clock rate
also eliminates the requirement for a sample-and-hold amplifier.
Power consumption of the ADMOD79 is 1078 mW maximum.
However, in power-down mode, consumption is reduced to
328 mW (with a 3.072 MHz modulator clock). Note that the
ADMOD79 will still function in this mode. In the power-down
mode, the ADMOD79 will operate with a slower modulator
clock over a more limited bandwidth. T he SNR over the band
of interest is reduced relative to that possible with a full-speed
modulator clock.
Holding the calibration input, CALIB, LO disconnects the
input from the modulators, regardless of the signal applied to
the input pins. T his feature allows for system calibration.
Allow at least ten modulator clock cycles after asserting CALIB
before reading the output bit streams.
T ypical modulator noise integrated across the passband of the
modulator as shown in Figure 1 is always 103 dB, regardless of
modulator clock rate. T he width of that passband, however,
scales down linearly with a slower clock. For example, if the
modulator clock is slowed by a factor of two, noise will begin to
rise at 10 kHz instead of 20 kHz. Since the same inband noise
is now spread across a narrower passband, the noise per one Hz
bin will also increase accordingly. T hus, the passband of
Figure 1 will narrow and its floor will rise.
Should an input overdrive the modulator to instability, the
ADMOD79 will reset itself within 25 modulator clock cycles.
Each modulator independently produces an output signal on
pins LRESET and RRESET, respectively, indicating the
initiation of a reset sequence. T hese pins, normally HI, will go
LO for one cycle should instability occur.
Modulator
Clock
Modulator
P assband
SNR per
O ne H z Bin
SNR
T he pair of modulator outputs are T T L-compatible but are in
fact driven to CMOS logic levels. Digital output data is valid on
the rising edge of SMPCLK. For highest performance, the
ADMOD79 modulator has been designed so that the full-scale
range of the one’s density is from 20% to 80% (i.e., –dc full
scale = 20% one’s density, +dc full scale = 80% one’s density).
T he user’s decimator should effectively gain up the modulator’s
output by a factor of 5/3 to produce a full-scale output corre-
sponding to a full-scale input.
3.072 MHz
1.536 MHz
768 kHz
384 kH z
192 kHz
96 kHz
20 kHz
10 kHz
5 kHz
2.5 kH z
1.25 kHz
625 Hz
103 dB
103 dB
103 dB
103 dB
103 dB
103 dB
145 dB
142 dB
139 dB
136 dB
133 dB
130 dB
T he power-down mode will support modulator clocks as fast as
384 kHz, shown above in bold.
T he ADMOD79 contains a pair of +2.8 V voltage references.
T he user has the option of using these internal references or
supplying an external reference. In the former case, two
external capacitors and two external resistors are required for
voltage reference noise reduction. T hese capacitors and
resistors should be connected between reference inputs (VREFIL
and VREFIR) and analog ground as shown in Figure 2. T he
reference outputs (VREFOL and VREFOR) should be connected
directly to the reference input pair. T o use external
As described above, the SNR can always be increased at a
constant modulator clock rate by limiting the input band-
width with a brick-wall digital decimation filter. T his same
technique can be used in the power-down mode. T hus,
with a 384 kHz clock in the power-down mode, 105 dB
would be achievable over a 1.25 kHz bandwidth (128 times
oversampling) and 108 dB over a 625 Hz band of interest
(256 times oversampling).
reference(s), bypass the reference(s) to analog ground and
connect to the reference inputs (VREFIL and VREFIR). T he
reference outputs become no connects.
T he ADMOD79’s fifth-order modulators use a distinctive
architecture of feed-forward and feed-back signal paths to
achieve a high performance level. Gain is controlled by
switched capacitors. Resonator loops feeding back from the
third and fifth stage outputs allow the placement of zeros in the
quantization-noise transfer function. T hese zeros have been
chosen to further reduce noise in the passband. T he noise
floor is dominated by spectrally flat thermal circuit noise in the
passband.
T he ADMOD79 requires a ±5 V analog supply and a +5 V
digital supply. T he analog supply should be connected to the
two sets of analog supply pins, which should be decoupled from
each other. (T he AVSS1 and AVDD1 pins power the amplifiers
and other active analog circuitry; the AVSS2 and AVDD2 pins
provide voltage for the modulator’s switches.) See Figure 4 for
the recommended bypassing configuration.
REV. 0
–5–
ADMOD79
100pF
10µF
5.76kΩ
NE5532 OR
OP275
200Ω
249kΩ
5.62kΩ
V
CC
RIGHT
INPUT
0.1µF
51Ω
13
14
0.1µF
5.62kΩ
5.62kΩ
0.01µF
NPO
100kΩ
V
IR
V
OR
REF
REF
0.0047µF
NPO
51Ω
V
SS
11
12
VINR–
VINR+
5.62kΩ
0.01µF
NPO
0.1µF
ADMOD79
249kΩ
5.49kΩ
V
17
18
VINL+
SS
NE5532 OR
OP275
100pF
100pF
VINL–
V
IL
V
OL
REF
REF
5.36kΩ
V
CC
16
15
249kΩ
5.62kΩ
0.1µF
51Ω
200Ω
0.01µF
NPO
100kΩ
5.62kΩ
5.62kΩ
V
CC
0.0047µF
0.1µF
NPO
LEFT
INPUT
51Ω
5.62kΩ
10µF
0.01µF
NPO
0.1µF
V
SS
NE5532 OR
OP275
249kΩ
5.9kΩ
100pF
Figure 2. Recom m ended Input Structure
VINL+ signals that can be found in Figure 2. By trimming gain
imbalance, second harmonic distortion can always be elimi-
nated. In the “Specifications” section of this data sheet, a
AP P LICATIO NS ISSUES
Recom m ended Input Str uctur e
T he ADMOD79 input structure is fully differential for im-
proved common-mode rejection properties and increased
dynamic range. Since each input pin sees ±3.1 V swings, each
channel’s input signal effectively swings ±6.2 V, i.e., across a
12.4 V range.
+5V ANALOG
7805
V
IN
OUT
CC
GND
0.1µF
22µF
0.1µF
10µF
AGND
In most cases, a single-ended-to-differential input circuit is
required. Shown in Figure 2 is the recommended circuit, based
on extensive experimentation. Note that to maximize signal
swing, the op amps in this circuit are powered by ±12 V or
greater supplies. T he ADMOD79 itself requires ±5 V supplies.
If ±5 V supplies are not available in the target system, Figure 3
illustrates the recommended circuit for generating these
supplies.
0.1µF
22µF
0.1µF
10µF –5V ANALOG
GND
V
SS
IN
OUT
7905
+5V DIGITAL
V
DD
+12V < V < +18V
CC
0.1µF
22µF
–12V > V > –18V
SS
DGND
Figure 3. ADMOD79 Recom m ended Power Conditioning
Circuit
T he trim potentiometers shown in Figure 2 connecting the
minus (–) inputs of the driving op amps permit trimming out dc
offset, if desired.
distinction is drawn between trimmed and untrimmed signal-to-
(noise + distortion) and trimmed and untrimmed total har-
monic distortion. T he untrimmed specifications are tested with
the input structure shown in Figure 2. T he trimmed specifica-
tions are based on a part-by-part trim of this differential gain to
eliminate the second harmonic.
Note that the driving op amp feedback resistors all have slightly
different values. T hese values produce a slight differential gain
imbalance and were derived empirically to minimize second
harmonic distortion on average and produce the lowest overall
T HD without part-by-part trimming. Replacing one of these
feedback resistors in each channel with a trim potentiometer
allows trimming the differential gain imbalance for part-by-part
optimal performance. Analog Devices has done this in the lab
by paralleling 100 kΩ trim potentiometers around the 5.49 kΩ
and 5.36 kΩ input feedback resistors for the VINR+ and
T he input circuit of Figure 2 could be implemented with a
single pair of operational amplifiers per channel, one inverting
and one noninverting. T he recommended architecture shown in
Figure 2 using three inverting op amps per channel provides
isolation of the op amp inputs from charge dumped back from
–6–
REV. 0
ADMOD79
the ADMOD79’s input capacitors when these large capacitors
switch. T he performance from a two op amp per channel input
structure may be adequate in many applications.
RRESET
ROUT
1
2
3
4
5
6
7
8
9
28 LRESET
DIGITAL
GROUND PLANE
27 LOUT
26 CALIB
25 DVDD
Layout and D ecoupling Consider ations
SMPCLK
DGND
Obtaining the best possible performance from a state-of-the-art
modulator like the ADMOD79 requires close attention to board
layout. From extensive experimentation, Analog Devices has
discovered principles that produce typical values of 103 dB
dynamic range and 98 dB S/(T HD+N) in target systems with an
oversampling ratio of 64. T he principles and their rationales are
listed below in descending order of importance. T he first two
pertain to bypassing and are illustrated in Figure 4.
AVSS1
24 AVDD
23 N/C
22 AVDD
21 N/C
20 N/C
2
AVSS
2
AGND
N/C
1
ANALOG
GROUND PLANE
PWRDWN
N/C 10
VINR– 11
VINR+ 12
VREF IR 13
19 AGND
18 VINL–
17 VINL+
16 VREF IL
15 VREF OL
+5V ANALOG
10µF
–5V ANALOG
ADMOD79
10µF
14
VREF OR
+5V DIGITAL
OSCILLATOR
5
22
DD
19
7
N/C = NO CONNECT
AV
1
AV
1
AGND
AGND
SS
3
SMPCLK
0.1µF
ADMOD79
Figure 5. ADMOD79 Recom m ended Ground Plane
AV
2
AV
2
DV
DD
DGND
SS
DD
Each reference input pin (13 and 16) should be bypassed with
a 200 Ω resistor and a 10 µF capacitor as shown in Figure 2.
One end of the resistor should be placed as close to the package
pin as possible, and the trace to it from the reference pin should
be as short and as wide as possible. Keep this trace away from
input pin traces! Coupling between input and reference traces
will cause second harmonic distortion. T he resistor is used to
reduce the high-frequency coupling into the references from the
board.
6
24
25
4
10µF
–5V ANALOG
0.1µF
10µF
+5V DIGITAL
+5V ANALOG
Figure 4. Recom m ended Bypassing and Oscillator
Circuits
T he digital bypassing of the ADMOD79 is a critical item on the
board layout. T he user should tie a bypass capacitor set (0.1 µF
ceramic and 10 µF tantalum) on the DVDD supply pin as close to
the pin as possible. T he trace between the package pin and the
capacitors should be as short and as wide as possible. T his will
prevent digital supply current transients from being inductively
transmitted to the inputs of the part.
Wherever possible, minimize the capacitive load on digital
outputs of the part. T his will reduce the digital spike currents
drawn from the digital supply pins.
D igital Tim ing
T he delay from a SMPCLK falling edge to ROUT and LOUT
data valid is tOPD. T he minimum SMPCLK LO pulse width is
tSCPWL, and the minimum SMPCLK HI pulse width is tSCPWH
T he minimum SMPCLK period is tSCP. T he delay from a
.
T he analog input bypassing is a second critical item. Use
0.01 µF NPO ceramic capacitors from each input pin to the
analog ground plane, with a clear ground path from the bypass
capacitor to the AGND pin on the same side of the package
(Pins 7 and 19). T he trace between this package pin and the
capacitor should be as short and as wide as possible. A
0.0047 µF NPO ceramic capacitor should be placed between
each set of input pins (11 to 12, and 17 to 18) to complete the
input bypassing. T his input bypassing minimizes the RF
transmission and reception capability of the ADMOD79 inputs.
SMPCLK rising edge to RRESET or LRESET is tRPD. T hese
timing relationships are shown in Figure 6.
tSCP
tSCPWL
tOPD
SMPCLK
tSCPWH
ROUT, LOUT
RRESET,
T he ADMOD79 should be placed on a split ground plane as
illustrated in Figure 5. T he digital ground plane should be
placed under the top end of the package and the analog ground
plane should be placed under the bottom end of the package as
shown in Figure 5. T he split should be between Pins 4 and 5
and between Pins 24 and 25. T he ground planes should be tied
together at one spot underneath the center of the package. T his
ground plane technique also minimizes RF transmission and
reception.
LRESET
tRPD
Figure 6. Digital Tim ing Diagram
REV. 0
–7–
ADMOD79
O UTLINE D IMENSIO NS
D imensions shown in inches and (mm).
Q -28
28-Lead Cer dip
0.005 (0.13) MIN
0.100 (2.54) MAX
15
28
0.610 (15.49)
PIN 1
0.500 (12.70)
14
1
0.015
(0.38)
MIN
0.620 (15.75)
0.590 (14.99)
1.490 (37.85) MAX
0.225
(5.72)
MAX
0.150
(3.81)
MIN
0.018 (0.46)
0.008 (0.20)
0.200 (5.08)
0.125 (3.18)
15°
0°
0.110 (2.79)
0.090 (2.29)
0.026 (0.66)
0.014 (0.36)
SEATING
PLANE
0.070 (1.78)
0.030 (0.76)
–8–
REV. 0
ADMOD79
O RD ERING GUID E
Tem perature
Range
P ackage
D escription
P ackage
O ption*
Model
ADMOD79JQ
0°C to +70°C
Cerdip
Q-28
*For outline information see Package Information section.
REV. 0
–9–
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