ADMV1013ACCZ-R7_技术文档

24 GHz to 44 GHz,

Wideband, Microwave Upconverter

ADMV1013

Data Sheet

FEATURES

FUNCTIONAL BLOCK DIAGRAM

Wideband RF input frequency range: 24 GHz to 44 GHz

2 upconversion modes

Direct conversion from baseband I/Q to RF

Single-sideband upconversion from real IF

LO input frequency range: 5.4 GHz to 10.25 GHz

LO quadrupler for up to 41 GHz

RST

DVDD

IF_I

I_N

Matched 50 Ω single-ended RF output and IF inputs

Option between matched 100 Ω balanced or 50 Ω single-

ended LO inputs

SCLK

I_P

×4

90°

0°

SDI

SDO

GND

100 Ω balanced baseband inputs

Q_P

Sideband suppression and carrier feedthrough optimization

Variable attenuator for transceiver power control

Programmable via 4-wire SPI interface

40-terminal land grid array package (LGA)

BG_RBIAS2

VCC_DRV

GND

Q_N

ADMV1013

IF_Q

VCC_BG2

VENV_P

VENV_N

APPLICATIONS

RF

VVA2

VVA1

Point to point microwave radios

Radar, electronic warfare systems

GND

DET

Instrumentation, automatic test equipment (ATE)

Figure 1.

GENERAL DESCRIPTION

The ADMV1013 is a wideband, microwave upconverter optimized

for point to point microwave radio designs operating in the

24 GHz to 44 GHz radio frequency (RF) range.

while suppressing the unwanted sideband by typically better than

26 dBc. The serial port interface (SPI) allows adjustment of the

quadrature phase and mixer gate voltage to allow optimum

sideband suppression and local oscillator (LO) nulling. In

addition, the SPI interface allows powering down the output

envelope detector to reduce power consumption.

The upconverter offers two modes of frequency translation. The

device is capable of direct conversion to RF from baseband in-phase

quadrature (I/Q) input signals, as well as single-sideband (SSB)

upconversion from complex intermediate frequency (IF) inputs.

The baseband I/Q input path can be disabled and modulated

complex IF signals, anywhere from 0.8 GHz to 6.0 GHz, can be

inserted in the IF path and upconverted to 24 GHz to 44 GHz

The ADMV1013 upconverter comes in a 40-terminal land grid

array package (LGA) package. The ADMV1013 operates over

the −40°C to +85°C case temperature range.

Rev. A

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ADMV1013

Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Sideband Suppression Optimization ....................................... 25

Carrier Feedthrough Nulling.................................................... 26

Envelope Detector...................................................................... 26

Power Down and Reset.............................................................. 26

Serial Port Interface (SPI) ......................................................... 26

Applications Information.............................................................. 28

Baseband Quadrature Modulation from Low Frequencies.. 28

Performance at Different Quad Filter Settings....................... 28

VVA Temperature Compensation............................................ 28

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description......................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Serial Port Register Timing......................................................... 5

Absolute Maximum Ratings............................................................ 6

Thermal Resistance ...................................................................... 6

ESD Caution.................................................................................. 6

Pin Configuration and Function Descriptions............................. 7

Typical Performance Characteristics ............................................. 9

I/Q Mode ....................................................................................... 9

IF Mode........................................................................................ 14

Envelope Detector Performance............................................... 19

Return Loss.................................................................................. 21

M × N Spurious Performance................................................... 24

Theory of Operation ...................................................................... 25

Start-Up Sequence...................................................................... 25

Baseband Quadrature Modulation (I/Q Mode)..................... 25

Single-Sideband Upconversion (IF Mode) ............................. 25

LO Input Path ............................................................................. 25

Performance Between Differential vs. Single-Ended LO Input

....................................................................................................... 29

Performance Across RF Frequency at Fixed Input

Frequencies ................................................................................. 30

Performance Across Common-Mode Voltage in I/Q Mode 31

Operating VCTRL1 and VCTRL2 Independently..................... 31

Recommended Land Pattern.................................................... 33

Evaluation Board Information ................................................. 33

Register Summary .......................................................................... 34

Register Details ............................................................................... 35

Outline Dimensions....................................................................... 39

Ordering Guide .......................................................................... 39

REVISION HISTORY

4/2019—Rev. 0 to Rev. A

Moved Figure 70; Renumbered Sequentially.............................. 21

Moved Figure 72............................................................................. 22

Moved Figure 77............................................................................. 22

Moved Figure 80............................................................................. 23

Changes to M × N Spurious Performance Section, I/Q Mode

Section, and IF Mode Section....................................................... 24

Changes to Start-Up Sequence Section ....................................... 25

Changes to Figure 1.......................................................................... 1

Changes to Frequency Ranges Parameter, Table 1....................... 3

Changes to Thermal Resistance Section........................................ 6

Changes to Figure 3.......................................................................... 7

Changes to Table 5............................................................................ 8

Changes to Figure 50 Caption....................................................... 16

Changes to Figure 58 Caption....................................................... 18

Change to Return Loss and Isolation Section............................. 21

12/2018—Revision 0: Initial Version

Rev. A | Page 2 of 39

Data Sheet

ADMV1013

SPECIFICATIONS

IF and I/Q amplitude = −20 dBm, VCC_DRV = VCC2_DRV = VCC_AMP2 = VCC_ENV = VCC_AMP1 = VCC_BG2 = VCC_MIXER =

VCC_BG = VCC_QUAD = 3.3 V, DVDD = VCC_VVA = 1.8 V, T_A= 25°C, and set Register 0x0A to 0xE700, unless otherwise noted.

Measurements in IF mode performed with a 90° hybrid, Register 0x03, Bit 7 = 1, IF input frequency (f_IF) = 3.5 GHz.

Measurements in I/Q mode are measured as a composite of the I and Q channel performance, common-mode voltage (V_CM) = 0 V,

Register 0x03, Bit 7 = 0, and Register 0x05, Bits[6:0] = 0x051, unless otherwise noted. I/Q baseband frequency (f_BB) = 100 MHz.

VCTRL1 = VCTRL2. V_CTRLis the attenuation voltage at the VCTRL1 and VCTRL2 pins. V_CTRL=1800 mV, unless otherwise specified.

Table 1.

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

FREQUENCY RANGES

RF Output

24

44

GHz

LO Input

LO Quadrupler

IF Input

Baseband (BB) I/Q Input

LO AMPLITUDE RANGE

I/Q MODULATOR PERFORMANCE

Conversion Gain

24 GHz to 40 GHz

5.4

21.6

0.8

DC

−6

10.25 GHz

41

GHz

dBm

6.0

+6

0

At maximum gain

f_BB≤ 3.5 GHz

6 GHz > f_BB> 3.5 GHz

18

23

21

19

35

dB

40 GHz to 44 GHz

dB

Voltage Variable Attenuator (VVA) Control Range

Single-Sideband (SSB) Noise Figure

24 GHz to 40 GHz

At maximum gain

18

19

dB

40 GHz to 44 GHz

Output Third-Order Intercept (IP3)

24 GHz to 40 GHz

40 GHz to 44 GHz

Output 1 dB Compression Point (P1dB)

24 GHz to 40 GHz

40 GHz to 44 GHz

At maximum gain

20

10

23

22

dBm

At maximum gain

13

12

dBm

Sideband Rejection (SBR)

Uncalibrated

24 GHz to 44 GHz, at maximum gain

32

dBc

dB

IF SINGLE-SIDEBAND UPCONVERSION PERFORMANCE

Conversion Gain

At maximum gain

f_IF≤ 3.5 GHz

6 GHz > f_IF> 3.5 GHz

24 GHz to 40 GHz

13

18

12

14

35

40 GHz to 44 GHz

VVA Control Range

SSB Noise Figure

24 GHz to 40 GHz

40 GHz to 44 GHz

Output IP3

dB

At maximum gain

25

28

dB

At maximum gain

24 GHz to 40 GHz

40 GHz to 44 GHz

Output P1dB

24 GHz to 40 GHz

40 GHz to 44 GHz

SBR

20

10

23

22

dBm

At maximum gain

13

12

dBm

24 GHz to 44 GHz, at maximum gain

Uncalibrated

Calibrated

26

36

dBc

Calibrated using LOAMP_PH_ADJ_

Q_FINE and LOAMP_PH_ADJ_I_FINE bits

Rev. A | Page 3 of 39

ADMV1013

Data Sheet

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

ENVELOPE DETECTOR PERFORMANCE

Output Level

For optimum performance

Minimum

Maximum

−45

−20

dBm

Envelope Bandwidth

Measured with two tones with total

power output (P_OUT) at RF = 10 dBm

3 dB

10 dB

RF frequency (f_RF) = 28 GHz

f_RF= 28 GHz

350

1

MHz

GHz

RETURN LOSS

RF Output

LO Input

IF Input

BB Input

50 Ω single-ended

100 Ω differential

50 Ω single-ended

100 Ω differential

−8

dB

Ω

−12

−10

100

BB I/Q Input Impedance

LEAKAGE

At maximum gain

Fundamental LO to RF

4 × LO to RF

−80

dBm

5.4 GHz to 6.8 GHz LO

6.8 GHz to 10.25 GHz LO

5.4 GHz to 10.25 GHz LO

Uncalibrated

Calibrated using MXER_OFF_ADJ_I_N,

MXER_OFF_ADJ_I_P, MXER_OFF_

−12

−20

−45

dBm

ADJ_Q_N, MXER_OFF_ADJ_Q_P bits at

V

_CTRL= 1800 mV, IF mode

5 × LO to RF

−55

−70

−75

dBm

Fundamental LO to IF

Fundamental LO to I/Q

LOGIC INPUTS

Input Voltage Range

High, V_INH

Low, V_INL

DVDD − 0.4

0

1.8

0.4

V

Input Current, I_INH/I_INL

Input Capacitance, C_IN

LOGIC OUTPUTS

Output Voltage Range

High, V_OH

Low, V_OL

Output High Current, I_OH

POWER INTERFACE

100

3

µA

pF

DVDD − 0.4

0

1.8

0.4

500

V

µA

VCC_DRV, VCC2_DRV, VCC_AMP2, VCC_ENV,

VCC_AMP1, VCC_BG2, VCC_MIXER, VCC_BG,

VCC_QUAD

3.15

1.7

3.3

3.45

V

3.3 V Supply Current

V_CTRL= 1.8 V, no IF and I/Q or LO input

signal

550

mA

DVDD, VCC_VVA

1.8 V Supply Current

1.8

3

1.9

V

mA

V_CTRL= 1.8 V, no IF and I/Q or LO input

signal

Total Power Consumption

Power-Down

1.9

77

W

mW

136

Rev. A | Page 4 of 39

Data Sheet

ADMV1013

SERIAL PORT REGISTER TIMING

Table 2.

Parameter

t_{SDI, SETUP}

t_{SDI, HOLD}

t_{SCLK, HIGH}

t_{SCLK, LOW}

t_SCLK,

Description

Min

Typ

Max

Unit

ns

%

Data to clock setup time

Data to clock hold time

Clock high duration

Clock low duration

10

40 to 60

30

Clock to

SEN SEN2

/

setup time

ns

/

_SETUP

SEN SEN2

t_{SCLK, DOT}

t_{SCLK, DOV}

t_SCLK,

Clock to data out transition time

Clock to data out valid time

10

ns

Clock to

Inactive

SEN SEN2

/

inactive

20

80

/

_INACTIVE

SEN SEN2

t_{SEN SEN2}

/

(between two operations)

ns

SEN SEN2

/

_INACTIVE

Timing Diagram

t_{SCLK, HIGH}

t_{SCLK, LOW}

SCLK

t_{SCLK, SEN/SEN2_SETU P}

t_{SEN/SEN2_INACTIVE}

SEN/SEN2

t_{SCLK, DOT}

t_{SCLK, SEN/SEN2_INACTIVE}

t_{SCLK, DOV}

SDO

SDI

t_{SDI, HOLD}

t_{SDI, SETUP}

Figure 2. Serial Port Register Timing Diagram

Rev. A | Page 5 of 39

ADMV1013

Data Sheet

ABSOLUTE MAXIMUM RATINGS

Table 3.

T_J= (P × Ѱ_JT) + T_Top(Equation 1)

_Top: Refers to package top temperature (°C). T_Topis measured at

the top-center of the package.

T

Parameter

Rating

Supply Voltage

Ѱ_JT: Refers to junction-to-top thermal characterization number.

P: Refers to total power dissipation in the chip (W).

T_J= (P × Ѱ_JB) + T_Board(Equation 2)

VCC_DRV, VCC2_DRV, VCC_AMP2,

VCC_ENV, VCC_AMP1, VCC_BG2,

VCC_BG, VCC_MIXER

4.3 V

DVDD, VCC_VVA

2.3 V

IF Input Power

I/Q Input Power

LO Input Power

Maximum Junction Temperature

Maximum Power Dissipation¹

5 dBm

9 dBm

125°C

2.9 W

T

_Board: Refers to board temperature measured on the mid-point

of the longest side of the package no more than 1 mm from the

edge of the package body (°C).

Ѱ_JB: Refers to junction-to-board thermal characterization number.

Lifetime at Maximum Junction Temperature (T_J) 1 ×10⁶hours

P: Refers to total power dissipation in the chip (W).

Operating Case Temperature Range

Storage Temperature Range

Lead Temperature (Soldering 60 sec)

Moisture Sensitivity Level (MSL) Rating²

Electrostatic Discharge (ESD) Sensitivity

Human Body Model (HBM)

−40°C to +85°C

−55°C to +125°C

260°C

As stated in JEDEC51-12, Equation 1 and Equation 2 must only

be used when no heat sink/heat spreader is present. When a

heat sink/heat spreader is added, estimating and calculating

MSL3

junction temperature can be achieved using θ_{JC_TOP}

.

Table 4. Thermal Resistance

1250 V

750 V

Package Type¹

θ_JA

θ_{JC_TOP}

θ_JB

11.1 6.4

Ψ_JT

Ψ_JB

13.8 °C/W

Unit

2

3

4

5

6

Field Induced Charged Device Model

(FICDM)

CC-40-5

28

13.8

¹The thermal resistance values specified in Table 4 are simulated based on

JEDEC specifications, unless specified otherwise, and must be used in

compliance with JESD51-12.

¹The maximum power dissipation is a theoretical number calculated by

(T_J− 85°C)/θ_{JC_TOP}

.

²Based on IPC/JEDEC J-STD-20 MSL classifications.

²θ_JAis the junction to ambient thermal resistance in a natural convection,

JEDEC environment.

Stresses at or above those listed under Absolute Maximum

Ratings may cause permanent damage to the product. This is a

stress rating only; functional operation of the product at these

or any other conditions above those indicated in the operational

section of this specification is not implied. Operation beyond

the maximum operating conditions for extended periods may

affect product reliability.

³θ_{JC_TOP}is the junction to case (top) JEDEC thermal resistance.

⁴θ_JBis the junction to board JEDEC thermal resistance.

⁵Ψ_JTis the junction to top JEDEC thermal characterization parameter.

⁶Ψ_JBis the junction to board JEDEC thermal characterization parameter.

ESD CAUTION

THERMAL RESISTANCE

Thermal performance is directly linked to printed circuit board

(PCB) design and operating environment. Careful attention to

PCB thermal design is required.

θ

_JAis the natural convection junction to ambient thermal

resistance measured in a one cubic foot sealed enclosure. θ_JC

is the junction to case thermal resistance.

θ

_JAand θ_JCmust only be used to compare thermal performance

of different packages if all test conditions listed are similar to

JEDEC specifications. Instead, Ѱ_JTand Ѱ_JBcan be used to

calculate the junction temperature of the device using the

following equations:

Rev. A | Page 6 of 39

Data Sheet

ADMV1013

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

ADMV1013

TOP VIEW

(Not to Scale)

40 39 38 37 36 35 34 33 32 31

30

29

28

27

26

25

24

23

22

21

1

2

IF_I

I_N

RST

DVDD

SCLK

SDI

SDO

3

I_P

GND

Q_P

4

5

6

BG_RBIAS2

VCC_DRV

GND

Q_N

IF_Q

VCC_BG2

VENV_P

VENV_N

7

8

9

RF

10

GND

11 12 13 14 15 16 17 18 19 20

NOTES

1. NIC = NOT INTERNALLY CONNECTED. THIS PIN IS NOT CONNECTED INTERNALLY.

2. EXPOSED PAD. SOLDER THE EXPOSED PAD TO A LOW IMPEDANCE GROUND PLANE.

Figure 3. Pin Configuration

Table 5. Pin Function Descriptions

Pin No.

Mnemonic

Description

1

2

3

4

5

6

RST

DVDD

SCLK

SDI

SDO

SPI Reset. Connect this pin to logic high for normal operation. The SPI logic is 1.8 V.

1.8 V SPI Digital Supply.

SPI Clock Digital Input.

SPI Serial Data Input.

SPI Serial Data Output.

BG_RBIAS2

Voltage Gain Amplifier (VGA) Chip Band Gap Circuit, External High Precision Resistor. Place a 1.1 kΩ,

high precision resistor shunt to ground close to this pin.

7

VCC_DRV

GND

3.3 V Power Supply for RF Driver. Place a 100 pF, a 0.01 µF, and a 10 µF capacitor close to this pin.

Ground.

8, 10, 27, 36, 39

9

11

12, 13, 31

RF

RF Output. This pin is dc-coupled internally to GND and matched to 50 Ω single ended.

3.3 V Power Supply for RF Predriver. Place a 100 pF, a 0.01 µF, and a 10 µF capacitor close to this pin.

Not Internally Connected. This pin is not connected internally.

VCC2_DRV

NIC

14

15

16

17

VCC_VVA

VCTRL1

VCTRL2

VCC_AMP2

1.8 V Power Supply for VVA Control Circuit. Place a 100 pF, 0.01 µF, and a 10 µF capacitor close to this pin.

RF Voltage Variable Attenuator 1 (VVA1) Control Voltage. Place a 1 kΩ series resistor with this pin.

RF Voltage Variable Attenuator 2 (VVA2) Control Voltage. Place a 1 kΩ series resistor with this pin.

3.3 V Power Supply for RF Amplifier 2 (AMP2). Place a 100 pF, a 0.01 µF, and a 10 µF capacitor close to

this pin.

18

19

20

SPI Serial Enable for VGA Chip. Connect this pin with Pin 40 ( ).

SEN

SEN2

VCC_ENV

VCC_AMP1

3.3 V Power Supply for Envelope Detector. Place a 100 pF, a 0.01 µF, and a 10 µF capacitor close to this pin.

3.3 V Power Supply for RF Amplifier 1 (AMP1). Place a 100 pF, a 0.01 µF, and a 10 µF capacitor close to

this pin.

21

22

23

VENV_N

VENV_P

VCC_BG2

Negative Differential Envelope Detector Output.

Positive Differential Envelope Detector Output.

3.3 V Power Supply for VGA Chip Band Gap Circuit. Place a 100 pF, a 0.01 µF, and a 10 µF capacitor

close to this pin.

24, 30

IF_Q, IF_I

IF Single-Ended Complex Inputs. These pins are internally ac-coupled. When in IF mode, Pin 25 (Q_P),

Pin 26 (Q_N), Pin 28 (I_P), and Pin 29 (I_N) must be kept floating.

25, 26

28, 29

Q_N, Q_P

I_P, I_N

Differential Baseband Q Inputs. These pins are dc-coupled. Do not connect these pins in IF mode.

Differential Baseband I Inputs. These pins are dc-coupled. Do not connect these pins in IF mode.

Rev. A | Page 7 of 39

ADMV1013

Data Sheet

Pin No.

32

33

Mnemonic

VCC_MIXER

VCC_BG

Description

3.3 V Power Supply for Mixer. Place a 100 pF, a 0.01 µF, and a 10 µF capacitor close to this pin.

3.3 V Power Supply for Mixer Chip Band Gap Circuit. Place a 100 pF, a 0.01 µF, and a 10 µF capacitor

close to this pin.

34

BG_RBIAS1

Mixer Chip Band Gap Circuit, External High Precision Resistor. Place a 1.1 kΩ, high precision resistor

shunt to ground close to this pin.

35

37, 38

VCC_QUAD

LON, LOP

3.3 V Power Supply for Quadruppler. Place a 100 pF, a 0.01 µF, and a 10 µF capacitor close to this pin.

Negative and Positive Differential Local Oscillator Input. This pin is dc-coupled internally to ground

and matched to 100 Ω differential or 50 Ω single ended. If using the LO as single ended, terminate

the unused LO port with 50 Ω impedance to ground.

40

SPI Serial Enable for Mixer Chip. Connect this pin with Pin 18 (

SEN2

).

SEN

EPAD

Exposed Pad. Solder the exposed pad to a low impedance ground plane.

Rev. A | Page 8 of 39

Data Sheet

ADMV1013

TYPICAL PERFORMANCE CHARACTERISTICS

I/Q MODE

I/Q amplitude = −20 dBm, VCC_DRV = VCC2_DRV = VCC_AMP2 = VCC_ENV = VCC_AMP1 = VCC_BG2 = VCC_MIXER =

VCC_BG = VCC_QUAD = 3.3 V, DVDD = VCC_VVA = 1.8 V, T_A= 25°C, and set Register 0x0A to 0xE700, unless otherwise noted.

VCTRL1 = VCTRL2. V_CTRLis the attenuation voltage at the VCTRL1 and VCTRL2 pins. V_CTRL= 1800 mV, unless otherwise specified.

Measurements in I/Q mode are measured as a composite of the I and Q channel performance, V_CM= 0 V, Register 0x03, Bit 7 = 0, and

Register 0x05, Bits[6:0] = 0x051, unless otherwise noted. I/Q f_BB= 100 MHz.

35

30

25

20

+85°C AT 1.8V UPPER SIDEBAND

+25°C AT 1.8V UPPER SIDEBAND

–40°C AT 1.8V UPPER SIDEBAND

15

10

5

+85°C AT 0.8V UPPER SIDEBAND

+25°C AT 0.8V UPPER SIDEBAND

–40°C AT 0.8V UPPER SIDEBAND

–5

5

0

–10

–15

–20

–25

–30

–35

–40

–45

–50

–5

+85°C AT 39GHz

+25°C AT 39GHz

–40°C AT 9GHz

+85°C AT 28GHz

+25°C AT 28GHz

–40°C AT 28GHz

–10

–15

–20

–25

–30

+85°C AT 0V UPPER SIDEBAND

+25°C AT 0V UPPER SIDEBAND

–40°C AT 0V UPPER SIDEBAND

23

25

27

29

31

33

35

37

39

41

43

45

0

0.2

0.4

0.6

0.8

1.0

(V)

1.2

1.4

1.6

1.8

RF FREQUENCY (GHz)

V

CTRL

Figure 4. Conversion Gain vs. RF Frequency (f_RF) at Three Different Gain

Figure 7. Conversion Gain vs. V_CTRLat Various Temperatures and

Settings for Various Temperatures, f_BB= 100 MHz (Upper Sideband)

f_RF= 28 GHz and 39 GHz, f_BB= 100 MHz

30

28

26

24

22

20

18

16

14

12

10

25

20

15

10

5

8

6

4

2

0

39GHz UPPER SIDEBAND

28GHz UPPER SIDEBAND

3.5V UPPER SIDEBAND

3.3V UPPER SIDEBAND

3.1V UPPER SIDEBAND

0

–5

23

25

27

29

31

33

35

37

39

41

43

45

0

0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0

BASEBAND FREQUENCY (GHz)

RF FREQUENCY (GHz)

Figure 5. Conversion Gain vs. RF Frequency at for Various Supply

Figure 8. Conversion Gain vs. Baseband Frequency at

f_RF= 28 GHz and 39 GHz (Upper Sideband)

Voltages, f_BB= 100 MHz (Upper Sideband)

30

28

26

24

22

20

18

16

14

12

10

8

25

20

15

10

5

39GHz LOWER SIDEBAND

28GHz LOWER SIDEBAND

+6dBm UPPER SIDEBAND

0dBm UPPER SIDEBAND

–6dBm UPPER SIDEBAND

6

0

4

2

–5

23

0

25

27

29

31

33

35

37

39

41

43

45

0

0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0

BASEBAND FREQUENCY (GHz)

RF FREQUENCY (GHz)

Figure 6. Conversion Gain vs. RF Frequency at for Various LO Inputs,

f_BB= 100 MHz (Upper Sideband)

Figure 9. Conversion Gain vs. Baseband Frequency at

f_RF= 28 GHz and 39 GHz (Lower Sideband)

Rev. A | Page 9 of 39

ADMV1013

Data Sheet

28

26

24

22

20

18

16

14

12

10

30

25

20

15

10

5

0

–5

–10

–15

–20

+85°C UPPER SIDEBAND

+25°C UPPER SIDEBAND

–40°C UPPER SIDEBAND

8

6

4

2

0

39GHz UPPER SIDEBAND

28GHz UPPER SIDEBAND

23

25

27

29

31

33

35

37

39

41

43

45

0

0.2

0.4

0.6

0.8

1.0

(V)

1.2

1.4

1.6

1.8

RF FREQUENCY (GHz)

V

CTRL

Figure 10. Output IP3 vs. RF Frequency at Maximum Gain for

Various Temperatures, RF Amplitude = −20 dBm per Tone at 20 MHz

Spacing, f_BB= 100 MHz (Upper Sideband)

Figure 13. Output IP3 vs. V_CTRL, RF Amplitude = −20 dBm per Tone at

20 MHz Spacing, f_BB= 100 MHz at f_RF= 28 GHz and 39 GHz (Upper Sideband)

28

26

24

22

20

18

16

14

12

10

8

28

26

24

22

20

18

16

14

12

10

8

6

4

2

0

39GHz UPPER BASEBAND

28GHz UPPER BASEBAND

39GHz LOWER BASEBAND

28GHz LOWER BASEBAND

3.5V UPPER SIDEBAND

3.3V UPPER SIDEBAND

3.1V UPPER SIDEBAND

6

4

2

0

23

25

27

29

31

33

35

37

39

41

43

45

0

0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0

BASEBAND FREQUENCY (GHz)

RF FREQUENCY (GHz)

Figure 11. Output IP3 vs. RF Frequency at Maximum Gain for

Supply Voltages, RF Amplitude = −20 dBm per Tone at 20 MHz Spacing,

Figure 14. Output IP3 vs. Baseband Frequency at f_RF= 28 GHz and 39 GHz

at Maximum Gain, RF Amplitude = −20 dBm per Tone at 20 MHz Spacing

(Upper Sideband and Lower Sideband)

f

_BB= 100 MHz (Upper Sideband)

28

26

24

22

20

18

16

14

12

10

8

24.0

23.8

23.6

23.4

23.2

23.0

22.8

+6dBm UPPER SIDEBAND

0dBm UPPER SIDEBAND

–6dBm UPPER SIDEBAND

22.6

6

4

39GHz UPPER SIDEBAND

28GHz UPPER SIDEBAND

22.4

2

0

23

22.2

25

27

29

31

33

35

37

39

41

43

45

–20 –19 –18 –17 –16 –15 –14 –13 –12 –11 –10

RF FREQUENCY (GHz)

TOTAL INPUT POWER (dBm)

Figure 12. Output IP3 vs. RF Frequency at Maximum Gain for

Figure 15. Output IP3 vs. Total Input Power at 20 MHz Spacing,

Various LO Inputs, RF Amplitude = −20 dBm per Tone at 20 MHz Spacing,

f_BB= 100 MHz, f_RF= 28 GHz and 39 GHz (Upper Sideband)

f

_BB= 100 MHz (Upper Sideband)

Rev. A | Page 10 of 39

Data Sheet

ADMV1013

50

45

40

35

30

25

20

15

10

5

45

+85°C UPPER SIDEBAND

+25°C UPPER SIDEBAND

–40°C UPPER SIDEBAND

40

35

30

25

20

15

10

5

+85°C AT 39GHz

+25°C AT 39GHz

–40°C AT 39GHz

+85°C AT 28GHz

+25°C AT 28GHz

–40°C AT 28GHz

0

23

0

25

27

29

31

33

35

37

39

41

43

45

0

0.2

0.4

0.6

0.8

1.0

(V)

1.2

1.4

1.6

1.8

RF FREQUENCY (GHz)

V

CTRL

Figure 19. Noise Figure vs. V_CTRLfor Various Temperatures at

_RF= 28 GHz 39 GHz, f_BB= 100 MHz

Figure 16. Noise Figure vs. RF Frequency at Maximum Gain for

Various Temperatures, f_BB= 100 MHz (Upper Sideband)

f

50

45

40

35

30

25

20

15

10

5

50

45

39GHz UPPER SIDEBAND

28GHz UPPER SIDEBAND

3.5V UPPER SIDEBAND

40

3.3V UPPER SIDEBAND

3.1V UPPER SIDEBAND

35

30

25

20

15

10

5

0

23

0

0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0

BASEBAND FREQUENCY (GHz)

25

27

29

31

33

35

37

39

41

43

45

RF FREQUENCY (GHz)

Figure 17. Noise Figure vs. RF Frequency for Various Supply Voltages,

_BB= 100 MHz (Upper Sideband)

Figure 20. Noise Figure vs. Baseband Frequency at

f

_RF= 28 GHz and 39 GHz (Upper Sideband)

50

45

40

35

30

25

20

15

10

5

50

45

40

35

30

25

20

15

10

5

39GHz LOWER SIDEBAND

28GHz LOWER SIDEBAND

+6dBm UPPER SIDEBAND

0dBm UPPER SIDEBAND

–6dBm UPPER SIDEBAND

0

23

0

25

27

29

31

33

35

37

39

41

43

45

0

0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0

BASEBAND FREQUENCY (GHz)

RF FREQUENCY (GHz)

Figure 18. Noise Figure vs. RF Frequency for Various LO Inputs, f_BB= 100 MHz

(Upper Sideband)

Figure 21. Noise Figure vs. Baseband Frequency at

f

_RF= 28 GHz and 39 GHz (Lower Sideband)

Rev. A | Page 11 of 39

ADMV1013

Data Sheet

45

40

35

30

25

20

15

10

5

45

40

35

30

25

20

15

10

5

+85°C AT 39GHz

+25°C AT 39GHz

–40°C AT 39GHz

+85°C AT 28GHz

+25°C AT 28GHz

–40°C AT 28GHz

+85°C UPPER SIDEBAND

+25°C UPPER SIDEBAND

–40°C UPPER SIDEBAND

0

23

0

25

27

29

31

33

35

37

39

41

43

45

0

0.2

0.4

0.6

0.8

1.0

(V)

1.2

1.4

1.6

1.8

RF FREQUENCY (GHz)

V

CTRL

Figure 25. Sideband Rejection vs. V_CTRLfor Various Temperatures at

Figure 22. Sideband Rejection vs. RF Frequency at Maximum Gain for

Various Temperatures, f_BB= 100 MHz (Upper Sideband)

f

_RF= 28 GHz and 39 GHz, f_BB= 100 MHz

50

45

40

35

30

25

20

15

10

5

45

40

35

30

25

20

15

39GHz UPPER SIDEBAND

28GHz UPPER SIDEBAND

39GHz LOWER SIDEBAND

28GHz LOWER SIDEBAND

3.5V UPPER SIDEBAND

3.3V UPPER SIDEBAND

3.1V UPPER SIDEBAND

10

5

0

23

0

0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0

BASEBAND FREQUENCY (GHz)

25

27

29

31

33

35

37

39

41

43

45

RF FREQUENCY (GHz)

Figure 26. Sideband Rejection vs. Baseband Frequency at

_RF= 28 GHz and 39 GHz (Upper Sideband and Lower Sideband)

Figure 23. Sideband Rejection vs. RF Frequency at for Various Supply

Voltages, f_BB= 100 MHz (Upper Sideband)

f

45

40

35

30

25

20

15

10

+6dBm UPPER SIDEBAND

0dBm UPPER SIDEBAND

–6dBm UPPER SIDEBAND

5

0

–5

23

25

27

29

31

33

35

37

39

41

43

45

RF FREQUENCY (GHz)

Figure 24. Sideband Rejection vs. RF Frequency for Various LO Inputs,

_BB= 100 MHz (Upper Sideband)

f

Rev. A | Page 12 of 39

Data Sheet

ADMV1013

20

15

10

5

20

15

10

5

0

–5

+85°C AT 39GHz

0

+25°C AT 39GHz

–40°C AT 39GHz

+85°C AT 28GHz

+25°C AT 28GHz

–40°C AT 28GHz

+85°C UPPER SIDEBAND

+25°C UPPER SIDEBAND

–40°C UPPER SIDEBAND

–10

–15

–20

–5

–10

23

25

27

29

31

33

35

37

39

41

43

45

0

0.2

0.4

0.6

0.8

1.0

(V)

1.2

1.4

1.6

1.8

RF FREQUENCY (GHz)

V

CTRL

Figure 27. Output P1dB vs. RF Frequency at Maximum Gain for Various

Temperatures, f_BB= 100 MHz (Upper Sideband)

Figure 30. Output P1dB vs. V_CTRLfor Various Temperatures at

_RF= 28 GHz and 39 GHz, f_BB= 100 MHz

f

20

15

10

5

20

15

10

5

0

–5

39GHz UPPER SIDEBAND

28GHz UPPER SIDEBAND

–10

3.5V UPPER SIDEBAND

3.3V UPPER SIDEBAND

0

3.1V UPPER SIDEBAND

–15

–20

23

–5

25

27

29

31

33

35

37

39

41

43

45

0

0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0

BASEBAND FREQUENCY (GHz)

RF FREQUENCY (GHz)

Figure 28. Output P1dB vs. RF Frequency for Various Supply Voltages,

_BB= 100 MHz (Upper Sideband)

Figure 31. Output P1dB vs. Baseband Frequency at

f

f_RF= 28 GHz and 39 GHz (Upper Sideband)

20

15

20

15

10

5

10

5

39GHz LOWER SIDEBAND

28GHz LOWER SIDEBAND

0

–5

–10

–15

–20

+6dBm UPPER SIDEBAND

0dBm UPPER SIDEBAND

–6dBm UPPER SIDEBAND

0

–5

23

25

27

29

31

33

35

37

39

41

43

45

0

0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0

BASEBAND FREQUENCY (GHz)

RF FREQUENCY (GHz)

Figure 32. Output P1dB vs. Baseband Frequency at

Figure 29. Output P1dB vs. RF Frequency for Various LO Inputs,

_BB= 100 MHz (Upper Sideband)

f_RF= 28 GHz and 39 GHz (Lower Sideband)

f

Rev. A | Page 13 of 39

ADMV1013

Data Sheet

IF MODE

IF amplitude = −20 dBm, VCC_DRV = VCC2_DRV = VCC_AMP2 = VCC_ENV = VCC_AMP1 = VCC_BG2 = VCC_MIXER =

VCC_BG = VCC_QUAD = 3.3 V, DVDD = VCC_VVA = 1.8 V, T_A= 25°C, and set Register 0x0A to 0xE700, unless otherwise noted.

VCTRL1 = VCTRL2. V_CTRLis the attenuation voltage at the VCTRL1 and VCTRL2 pins. V_CTRL= 1800 mV, unless otherwise specified.

Measurements in IF mode performed with a 90° hybrid, Register 0x03, Bit 7 = 1, and f_IF= 3.5 GHz.

28

26

24

22

20

18

16

14

12

10

8

28

26

24

22

20

18

16

14

12

10

8

+85°C UPPER SIDEBAND

+25°C UPPER SIDEBAND

–40°C UPPER SIDEBAND

+85°C LOWER SIDEBAND

+25°C LOWER SIDEBAND

–40°C LOWER SIDEBAND

39GHz UPPER SIDEBAND

28GHz UPPER SIDEBAND

39GHz LOWER SIDEBAND

28GHz LOWER SIDEBAND

6

4

2

0

23

0

25

27

29

31

33

35

37

39

41

43

45

0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0

RF FREQUENCY (GHz)

IF FREQUENCY (GHz)

Figure 33. Conversion Gain vs. RF Frequency at Maximum Gain for Various

Temperatures, f_IF= 3.5 GHz (Upper Sideband and Lower Sideband)

Figure 36. Conversion Gain vs. IF Frequency at f_RF= 28 GHz and 39 GHz at

Maximum Gain (Upper Sideband and Lower Sideband)

28

26

24

22

20

18

16

14

12

10

30

+85°C AT 39GHz

+25°C AT 39GHz

–40°C AT 39GHz

+85°C AT 28GHz

+25°C AT 28GHz

20

10

–40°C AT 28GHz

0

–10

–20

–30

–40

3.5V UPPER SIDEBAND

8

3.3V UPPER SIDEBAND

3.1V UPPER SIDEBAND

3.5V LOWER SIDEBAND

3.3V LOWER SIDEBAND

3.1V LOWER SIDEBAND

6

4

2

0

23

25

27

29

31

33

35

37

39

41

43

45

0

0.2

0.4

0.6

0.8

1.0

(V)

1.2

1.4

1.6

1.8

RF FREQUENCY (GHz)

V

CTRL

Figure 37. Conversion Gain vs. V_CTRLat Various Temperatures at

Figure 34. Conversion Gain vs. RF Frequency at Maximum Gain for Various

Supply Voltages, f_IF= 3.5 GHz (Upper Sideband and Lower Sideband)

f

_RF= 28 GHz and 39 GHz, f_IF= 3.5 GHz (Upper Sideband)

30

20

28

26

24

22

20

18

16

14

12

10

+85°C AT 39GHz

+25°C AT 39GHz

–40°C AT 39GHz

+85°C AT 28GHz

+25°C AT 28GHz

–40°C AT 28GHz

10

0

–10

–20

–30

–40

+6dBm UPPER SIDEBAND

8

0dBm UPPER SIDEBAND

–6dBm UPPER SIDEBAND

+6dBm LOWER SIDEBAND

0dBm LOWER SIDEBAND

6

4

2

–6dBm LOWER SIDEBAND

0

23

0

0.2

0.4

0.6

0.8

V

1.0

(V)

1.2

1.4

1.6

1.8

25

27

29

31

33

35

37

39

41

43

45

RF FREQUENCY (GHz)

CTRL

Figure 38. Conversion Gain vs. V_CTRLat Various Temperatures at

_RF= 28 GHz and 39 GHz, f_IF= 3.5 GHz (Lower Sideband)

Figure 35. Conversion Gain vs. RF Frequency at Maximum Gain for Various

LO Inputs, f_IF= 3.5 GHz (Upper Sideband and Lower Sideband)

f

Rev. A | Page 14 of 39

Data Sheet

ADMV1013

25

20

15

10

5

28

26

24

22

20

18

16

14

12

10

+85°C UPPER SIDEBAND

8

6

4

2

0

39GHz UPPER SIDEBAND

+25°C UPPER SIDEBAND

–40°C UPPER SIDEBAND

+85°C LOWER SIDEBAND

+25°C LOWER SIDEBAND

–40°C LOWER SIDEBAND

28GHz UPPER SIDEBAND

39GHz LOWER SIDEBAND

28GHz LOWER SIDEBAND

–5

–10

23

25

27

29

31

33

35

37

39

41

43

45

0

0.2

0.4

0.6

0.8

1.1

(V)

1.2

1.4

1.6

1.8

RF FREQUENCY (GHz)

V

CTRL

Figure 39. Output IP3 vs. RF Frequency at Maximum Gain for Various

Temperatures, RF Amplitude = −20 dBm per Tone at 20 MHz Spacing,

f_IF= 3.5 GHz (Upper Sideband and Lower Sideband)

Figure 42. Output IP3 vs. V_CTRLat f_RF= 28 GHz and 39 GHz,

RF Amplitude = −20 dBm per Tone at 20 MHz Spacing, f_IF= 3.5 GHz

(Upper Sideband and Lower Sideband)

28

26

24

22

20

18

16

14

12

10

28

26

24

22

20

18

16

14

12

10

3.5V UPPER SIDEBAND

8

6

4

2

0

39GHz UPPER SIDEBAND

28GHz UPPER SIDEBAND

39GHz LOWER SIDEBAND

28GHz LOWER SIDEBAND

3.3V UPPER SIDEBAND

6

3.1V UPPER SIDEBAND

3.5V LOWER SIDEBAND

3.3V LOWER SIDEBAND

3.1V LOWER SIDEBAND

4

2

0

23

25

27

29

31

33

35

37

39

41

43

45

0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0

RF FREQUENCY (GHz)

IF FREQUENCY (GHz)

Figure 43. Output IP3 vs. IF Frequency at f_RF= 28 GHz and 39 GHz at

Maximum Gain, RF Amplitude = −20 dBm per Tone at 20 MHz Spacing

(Upper Sideband and Lower Sideband)

Figure 40. Output IP3 vs. RF Frequency at Maximum Gain for Various Supply

Voltages, RF Amplitude = −20 dBm per Tone at 20 MHz Spacing,

f_IF= 3.5 GHz (Upper Sideband and Lower Sideband)

25

24

23

22

21

20

19

28

26

24

22

20

18

16

14

12

10

18

+6dBm UPPER SIDEBAND

8

39GHz UPPER SIDEBAND

28GHz UPPER SIDEBAND

39GHz LOWER SIDEBAND

28GHz LOWER SIDEBAND

0dBm UPPER SIDEBAND

6

–6dBm UPPER SIDEBAND

17

+6dBm LOWER SIDEBAND

0dBm LOWER SIDEBAND

–6dBm LOWER SIDEBAND

4

2

0

16

17

–20 –19 –18 –17 –16 –15 –14 –13 –12 –11 –10

23

25

27

29

31

33

35

37

39

41

43

45

TOTAL INPUT POWER (dBm)

RF FREQUENCY (GHz)

Figure 41. Output IP3 vs. RF Frequency at Maximum Gain for Various

LO Inputs, RF Amplitude = −20 dBm per Tone at 20 MHz Spacing,

f_IF= 3.5 GHz (Upper Sideband and Lower Sideband)

Figure 44. Output IP3 vs. Total Input Power at f_RF= 28 GHz and 39 GHz at

20 MHz Spacing, f_IF= 3.5 GHz (Upper Sideband and Lower Sideband)

Rev. A | Page 15 of 39

ADMV1013

Data Sheet

50

45

40

35

30

25

20

15

10

5

+85°C UPPER SIDEBAND

+25°C UPPER SIDEBAND

–40°C UPPER SIDEBAND

+85°C LOWER SIDEBAND

+25°C LOWER SIDEBAND

–40°C LOWER SIDEBAND

45

40

35

30

25

20

15

10

39GHz UPPER SIDEBAND

28GHz UPPER SIDEBAND

39GHz LOWER SIDEBAND

28GHz LOWER SIDEBAND

0

23

25

27

29

31

33

35

37

39

41

43

45

0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0

RF FREQUENCY (GHz)

IF FREQUENCY (GHz)

Figure 48. Noise Figure vs. IF Frequency at f_RF= 28 GHz and 39 GHz at

Maximum Gain (Upper Sideband and Lower Sideband)

Figure 45. Noise Figure vs. RF Frequency at Maximum Gain for Various

Temperatures, f_IF= 3.5 GHz (Upper Sideband and Lower Sideband)

55

50

45

40

35

50

3.5V UPPER SIDEBAND

45

3.3V UPPER SIDEBAND

3.1V UPPER SIDEBAND

3.5V LOWER SIDEBAND

3.3V LOWER SIDEBAND

3.1V LOWER SIDEBAND

40

35

30

25

20

15

10

30

+85°C UPPER SIDEBAND

+25°C UPPER SIDEBAND

–40°C UPPER SIDEBAND

+85°C LOWER SIDEBAND

+25°C LOWER SIDEBAND

–40°C LOWER SIDEBAND

25

20

15

10

0

0.2

0.4

0.6

0.8

V

1.0

(V)

1.2

1.4

1.6

1.8

23

25

27

29

31

33

35

37

39

41

43

45

RF FREQUENCY (GHz)

CTRL

Figure 46. Noise Figure vs. RF Frequency at Maximum Gain for Various

Supply Voltages, f_IF= 3.5 GHz (Upper Sideband and Lower Sideband)

Figure 49. Noise Figure vs. V_CTRLat Various Temperatures, f_IF= 3.5 GHz,

(Upper Sideband and Lower Sideband)

50

45

40

35

30

+6dBm UPPER SIDEBAND

45

40

35

30

25

20

15

10

0dBm UPPER SIDEBAND

–6dBm UPPER SIDEBAND

+6dBm LOWER SIDEBAND

0dBm LOWER SIDEBAND

–6dBm LOWER SIDEBAND

25

+85°C AT 39GHz

+25°C AT 39GHz

–40°C AT 39GHz

+85°C AT 28GHz

+25°C AT 28GHz

–40°C AT 28GHz

20

15

10

23

25

27

29

31

33

35

37

39

41

43

45

0

0.2

0.4

0.6

0.8

1.0

(V)

1.2

1.4

1.6

1.8

RF FREQUENCY (GHz)

V

CTRL

Figure 47. Noise Figure vs. RF Frequency at Maximum Gain for Various

LO Inputs, f_IF= 3.5 GHz (Upper Sideband and Lower Sideband)

Figure 50. Noise Figure vs. V_CTRLfor Various Temperatures at f_RF= 28 GHz and

39 GHz, f_IF= 3.5 GHz (Lower Sideband)

Rev. A | Page 16 of 39

Data Sheet

ADMV1013

20

15

10

5

20

15

10

5

+85°C UPPER SIDEBAND

+25°C UPPER SIDEBAND

–40°C UPPER SIDEBAND

+85°C LOWER SIDEBAND

+25°C LOWER SIDEBAND

–40°C LOWER SIDEBAND

0

–5

0

39GHz UPPER SIDEBAND

28GHz UPPER SIDEBAND

39GHz LOWER SIDEBAND

28GHz LOWER SIDEBAND

–5

–10

23

25

27

29

31

33

35

37

39

41

43

45

0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0

RF FREQUENCY (GHz)

IF FREQUENCY (GHz)

Figure 54. Output P1dB vs. IF Frequency at f_RF= 28 GHz and 39 GHz at

Maximum Gain (Upper Sideband and Lower Sideband)

Figure 51. Output P1dB vs. RF Frequency at Maximum Gain for Various

Temperatures, f_IF= 3.5 GHz (Upper Sideband and Lower Sideband)

20

15

10

5

20

15

10

0

5

–5

+85°C AT 39GHz

3.5V UPPER SIDEBAND

+25°C AT 39GHz

–40°C AT 39GHz

+85°C AT 28GHz

+25°C AT 28GHz

–40°C AT 28GHz

–10

0

–5

3.3V UPPER SIDEBAND

3.1V UPPER SIDEBAND

3.5V LOWER SIDEBAND

3.3V LOWER SIDEBAND

3.1V LOWER SIDEBAND

–15

–20

–25

–10

23

0

0.2

0.4

0.6

0.8

V

1.1

(V)

1.2

1.4

1.6

1.8

25

27

29

31

33

35

37

39

41

43

45

RF FREQUENCY (GHz)

CTRL

Figure 52. Output P1dB vs. RF Frequency at Maximum Gain for Various

Supply Voltages, f_IF= 3.5 GHz (Upper Sideband and Lower Sideband)

Figure 55. Output P1dB vs. V_CTRLfor Various Temperatures at

f

_RF= 28 GHz and 39 GHz, f_IF= 3.5 GHz (Upper Sideband)

15

10

5

20

15

10

5

0

–5

+85°C AT 39GHz

+25°C AT 39GHz

–40°C AT 39GHz

+85°C AT 28GHz

+25°C AT 28GHz

–40°C AT 28GHz

0

–10

–15

–20

–25

+6dBm UPPER SIDEBAND

0dBm UPPER SIDEBAND

–6dBm UPPER SIDEBAND

+6dBm LOWER SIDEBAND

0dBm LOWER SIDEBAND

–6dBm LOWER SIDEBAND

–5

–10

23

25

27

29

31

33

35

37

39

41

43

45

0

0.2

0.4

0.6

0.8

V

1.1

(V)

1.2

1.4

1.6

1.8

RF FREQUENCY (GHz)

CTRL

Figure 53. Output P1dB vs. RF Frequency at Maximum Gain for Various

LO Inputs, f_IF= 3.5 GHz (Upper Sideband and Lower Sideband)

Figure 56. Output P1dB vs. V_CTRLfor Various Temperatures at

_RF= 28 GHz and 39 GHz, f_IF= 3.5 GHz (Lower Sideband)

f

Rev. A | Page 17 of 39

ADMV1013

Data Sheet

40

35

30

25

20

15

10

5

60

55

50

45

40

35

30

25

20

15

10

5

+6dBm UPPER SIDEBAND

0dBm UPPER SIDEBAND

–6dBm UPPER SIDEBAND

+6dBm LOWER SIDEBAND

0dBm LOWER SIDEBAND

–6dBm LOWER SIDEBAND

+85°C UPPER SIDEBAND

+25°C UPPER SIDEBAND

–40°C UPPER SIDEBAND

+85°C LOWER SIDEBAND

+25°C LOWER SIDEBAND

–40°C LOWER SIDEBAND

0

23

25

27

29

31

33

35

37

39

41

43

45

23

25

27

29

31

33

35

37

39

41

43

45

RF FREQUENCY (GHz)

Figure 57. Sideband Rejection vs. RF Frequency at Maximum Gain for

Various Temperatures, f_IF= 3.5 GHz, Uncalibrated

(Upper Sideband and Lower Sideband)

Figure 60. Sideband Rejection vs. RF Frequency at Maximum Gain for

Various LO Inputs, f_IF= 3.5 GHz (Upper Sideband and Lower Sideband)

60

55

50

45

40

35

30

25

20

55

50

45

40

35

30

25

20

15

10

5

39GHz UPPER SIDEBAND

28GHz UPPER SIDEBAND

39GHz LOWER SIDEBAND

28GHz LOWER SIDEBAND

+85°C UPPER SIDEBAND

+25°C UPPER SIDEBAND

–40°C UPPER SIDEBAND

15

10

5

0

23

25

27

29

31

33

35

37

39

41

43

45

0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0

RF FREQUENCY (GHz)

IF FREQUENCY (GHz)

Figure 58. Sideband Rejection vs. RF Frequency at Maximum Gain for Various

Temperatures, f_IF= 3.5 GHz, Calibrated at 25°C (Upper Sideband). Note:

Calibrated Using LOAMP_PH_ADJ_ Q_FINE and LOAMP_PH_ADJ_I_FINE Bits

Figure 61. Sideband Rejection vs. IF Frequency at f_RF= 28 GHz and 39 GHz at

Maximum Gain (Upper Sideband and Lower Sideband)

40

35

30

25

20

40

35

30

25

20

15

3.5V UPPER SIDEBAND

15

10

5

3.3V UPPER SIDEBAND

3.1V UPPER SIDEBAND

3.5V LOWER SIDEBAND

3.3V LOWER SIDEBAND

3.1V LOWER SIDEBAND

39GHz UPPER SIDEBAND

28GHz UPPER SIDEBAND

39GHz LOWER SIDEBAND

10

28GHz LOWER SIDEBAND

5

0

0.2

0.4

0.6

0.8

1.0

(V)

1.2

1.4

1.6

1.8

0

23

25

27

29

31

33

35

37

39

41

43

45

V

CTRL

RF FREQUENCY (GHz)

Figure 62. Sideband Rejection vs. V_CTRLat f_RF= 28 GHz and 39 GHz,

f_IF= 3.5 GHz (Upper Sideband and Lower Sideband)

Figure 59. Sideband Rejection vs. RF Frequency at Maximum Gain for Various

Supply Voltages, f_IF= 3.5 GHz (Upper Sideband and Lower Sideband)

Rev. A | Page 18 of 39

Data Sheet

ADMV1013

ENVELOPE DETECTOR PERFORMANCE

IF and I/Q amplitude = −20 dBm, VCC_DRV = VCC2_DRV = VCC_AMP2 = VCC_ENV = VCC_AMP1 = VCC_BG2 = VCC_MIXER =

VCC_BG = VCC_QUAD = 3.3 V, DVDD = VCC_VVA = 1.8 V, T_A= 25°C, and set Register 0x0A to 0xE700, unless otherwise noted.

Measurements in IF mode performed with a 90° hybrid, Register 0x03, Bit 7 = 1, IF f_IF= 3.5 GHz.

Measurements in I/Q mode are measured as a composite of the I and Q channel performance, V_CM= 0 V, Register 0x03, Bit 7 = 0, and

Register 0x05, Bits[6:0] = 0x051, unless otherwise noted. I/Q f_BB= 100 MHz.

VCTRL1 = VCTRL2. V_CTRLis the attenuation voltage at the VCTRL1 and VCTRL2 pins. V_CTRL= 1800 mV, unless otherwise specified.

Envelope detector measurements made with Register 0x03, Bit 5 = 1.

20

10

280

260

240

220

200

180

160

140

120

100

80

200

175

150

125

100

75

0

VENV_N/VENV_P DELTA, P

= 13dBm

= 5dBm

= 0dBm

OUT

0

–10

–20

–30

–40

–50

–60

–70

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

–120

P

RF

OUT

ENVELOPE AT HD1

ENVELOPE AT HD2

VENV_N/VENV_P DELTA

60

ENVELOPE P

, P

= 13dBm

= 5dBm

= 0dBm

OUT OUT

40

50

, P

OUT OUT

20

, P

OUT OUT

0

25

–20 –18 –16 –14 –12 –10

–8

–6

–4

–2

0

2

23

25

27

29

31

33

35

37

39

41

43

45

POWER IN TOTAL (dBm)

RF FREQUENCY (GHz)

Figure 65. P_OUTand VENV_N/VENV_P Delta vs. Power In Total for P_OUTRF,

_OUTEnvelope HD1, P_OUTEnvelope HD2, and VENV_N/VENV_P Delta,

Measurements Performed with Two Tones with 100 MHz Separation,

_RF= 28 GHz, V_CTRL= 1800 mV

Figure 63. VENV_N/VENV_P Delta and Envelope P_OUTDelta vs. RF Frequency

at Various Output Power Levels, Envelope Frequency = 100 MHz, V_CTRL= 1800 mV,

T_A= 25°C, LO = 0 dBm, IF = 2 GHz (Upper Sideband)

P

f

0

–5

–10

–15

NORMALIZED HD1, 1×

NORMALIZED HD2, 2×

–20

–25

–30

–35

–40

–45

–50

–55

–60

–65

–70

ENVELOPE FREQUENCY (MHz)

Figure 64. Output Level vs. Envelope Frequency for Normalized Harmonic

Distortion (HD1), 1× and Normalized Harmonic Distortion(HD2), 2×,

f

_RF= 28 GHz, LO = 0 dBm at 25°C, HD1 and HD2 Measurement Performed

with Two Tones with Delta Equal to Envelope Frequency,

HD2 Normalized to HD1 Level at 50 MHz

Rev. A | Page 19 of 39

ADMV1013

Data Sheet

0

–5

0

–10

–20

–30

–40

–50

–60

140

130

120

110

100

90

–10

–15

–20

–25

–30

–35

–40

–45

–50

–55

–60

–65

–70

P

ENVELOPE AT +25°C

ENVELOPE AT +85°C

ENVELOPE AT –40°C

OUT

80

70

60

50

P

ENVELOPE AT P = –10dBm

IN

OUT

40

ENVELOPE AT P = –15dBm

OUT

IN

30

VENV_N/VENV_P DELTA, P = –10dBm

IN

20

VENV_N/VENV_P DELTA, P = –15dBm

IN

10

0

V

(V)

CTRL

P

RF PER TONE (dBm)

OUT

Figure 66. HD1 P_OUTEnvelope and VENV_N/VENV_P Delta vs. V_CTRLat

Various Total Input Power (P_IN) Levels, Measurements Performed at 28 GHz

with Two Input Tones with Separation of 100 MHz

Figure 67. P_OUTEnvelope vs. P_OUTRF per Tone at Various Temperatures at

f

_RF= 33 GHz, Measurement Performed at 3.5 GHz IF with Two Tones at

100 MHz Spacing, V_CTRL= 1800 mV

Rev. A | Page 20 of 39

Data Sheet

ADMV1013

RETURN LOSS AND ISOLATION

IF and I/Q amplitude = −20 dBm, VCC_DRV = VCC2_DRV = VCC_AMP2 = VCC_ENV = VCC_AMP1 = VCC_BG2 = VCC_MIXER =

VCC_BG = VCC_QUAD = 3.3 V, DVDD = VCC_VVA = 1.8 V, T_A= 25°C, and set Register 0x0A to 0xE700, unless otherwise noted.

Measurements in IF mode performed with a 90° hybrid, Register 0x03, Bit 7 = 1, and f_IF= 3.5 GHz.

Measurements in I/Q mode are measured as a composite of the I and Q channel performance, V_CM= 0 V, Register 0x03, Bit 7 = 0, and

Register 0x05, Bits[6:0] = 0x051, unless otherwise noted. I/Q f_BB= 100 MHz.

VCTRL1 = VCTRL2. V_CTRLis the attenuation voltage at the VCTRL1 and VCTRL2 pins. V_CTRL= 1800 mV, unless otherwise specified.

Envelope detector measurements made with Register 0x03, Bit 5 = 1.

0

–5

I SIDE

Q SIDE

–10

–15

–20

–25

–30

–35

–10

–15

–20

–25

–30

–35

0V

0.9V

1.8V

23

25

27

29

31

33

35

37

39

41

43

45

0

1

2

3

4

5

6

7

RF FREQUENCY (GHz)

IF FREQUENCY (GHz)

Figure 68. RF Return Loss vs. RF Frequency at Various V_CTRLVoltages

Figure 70. IF Return Loss vs. IF Frequency (Taken Without Hybrid)

0

–5

LOP

I SIDE

Q SIDE

–10

–5

LON

LO DIFFERENTIAL

–10

–15

–20

–25

–30

–35

–15

–20

–25

–30

–35

0

1

2

3

4

5

6

7

4

5

6

7

8

9

10

11

12

FREQUENCY (GHz)

LO FREQUENCY (GHz)

Figure 71. I/Q Differential Return Loss vs. Frequency

(Taken Without Hybrids or Baluns)

Figure 69. LO Return Loss vs. LO Frequency

Rev. A | Page 21 of 39

ADMV1013

Data Sheet

0

–5

0

–5

4× LO AT +85°C

4× LO AT +25°C

4× LO AT –40°C

–10

–15

–20

–25

–30

–35

–40

–45

–50

–55

–60

–65

–70

–75

–80

–85

–90

–95

–100

–105

4

5× LO LEAKAGE, V

= 0mV

–10

–15

–20

–25

–30

–35

–40

–45

–50

–55

–60

–65

–70

–75

–80

–85

CTRL

= 300mV

= 600mV

= 900mV

= 1200mV

= 1500mV

= 1800mV

5× LO AT +85°C

5× LO AT +25°C

5× LO AT –40°C

1× LO AT +85°C

1× LO AT +25°C

1× LO AT –40°C

6

8

10

12

4

5

6

7

8

9

10

11

12

LO FREQUENCY (GHz)

Figure 72. LO to RF Leakage vs. LO Frequency for 4× LO, 5× LO, and 1× LO at

Various Temperatures (Uncalibrated)

Figure 75. 5× LO Leakage vs. LO Frequency at Different V_CTRLSettings

(Uncalibrated)

0

4× LO LEAKAGE, V

= 0mV

= 300mV

= 600mV

CTRL

–5

–10

–15

–20

–25

–30

–35

–40

–45

–50

–55

–60

–65

–70

–75

–80

–85

1× LO LEAKAGE, V

= 0mV

–10

–15

–20

–25

–30

–35

–40

–45

–50

–55

–60

–65

–70

–75

–80

–85

CTRL

= 300mV

= 600mV

= 900mV

= 1200mV

= 1500mV

= 1800mV

1× LO LEAKAGE, V

CTRL

4× LO LEAKAGE, V

= 900mV

CTRL

= 1200mV

= 1500mV

= 1800mV

4× LO LEAKAGE, V

CTRL

4

5

6

7

8

9

10

11

12

4

5

6

7

8

9

10

11

12

LO FREQUENCY (GHz)

Figure 73. 1× LO Leakage vs. LO Frequency at Different V_CTRLSettings

(Uncalibrated)

Figure 76. 4× LO Leakage vs. LO Frequency at Different V_CTRLSettings

(Uncalibrated)

0

V

= 0V

CTRL

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

= 0.4V

= 0.8V

= 1.2V

= 1.4V

= 1.8V

–10

–40°C

+25°C

+85°C

–20

–30

–40

–50

–60

–70

80

4

5

6

7

8

9

10

11

12

4

5

6

7

8

9

10

11

12

LO FREQUENCY (GHz)

Figure 74. 4× LO to RF Leakage vs. LO Frequency at Various Temperatures

(Calibrated). Note: Calibrated at Each Frequency Using MXER_OFF_ADJ_I_N,

MXER_OFF_ADJ_I_P, MXER_OFF_ADJ_Q_N, and MXER_OFF_ADJ_Q_P Bits

at T_A= 25°C

Figure 77. 4× LO to RF Leakage vs. LO Frequency at Various V_CTRL(Calibrated)

Note: Calibrated at Each Frequency Using MXER_OFF_ADJ_I_N,

MXER_OFF_ADJ_I_P, MXER_OFF_ADJ_Q_N, and MXER_OFF_ADJ_Q_P Bits

at V_CTRL= 1800 mV

Rev. A | Page 22 of 39

Data Sheet

ADMV1013

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

0

+25°C, I_P

–40°C, I_P

+85°C, I_P

+25°C, I_N

–40°C, I_N

+85°C, I_N

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

+25°C, Q_N

–40°C, Q_N

+85°C, Q_N

+25°C, Q_P

–40°C, Q_P

+85°C, Q_P

–40°C, IF_I

+25°C, IF_I

+85°C, IF_I

–40°C, IF_Q

+25°C, IF_Q

+85°C, IF_Q

4

5

6

7

8

9

10

11

12

4

5

6

7

8

9

10

11

12

LO FREQUENCY (GHz)

Figure 78. LO Leakage vs. LO Frequency at Various Temperatures at I_N, I_P,

Q_N, and Q_P (Taken Without Hybrid(s))

Figure 80. LO Leakage vs. LO Frequency at Various Temperatures at IF_I and

IF_Q Ports(Taken Without Hybrid)

0

–5

–10

–15

–20

–25

–30

–35

0

1

2

3

4

5

FREQUENCY (GHz)

Figure 79. Envelope Detector Differential Return Loss vs. Frequency

Rev. A | Page 23 of 39

ADMV1013

Data Sheet

IF Mode

f_IF= 3.5 GHz at −20 dBm, LO = 6.125 GHz at +6 dBm, and

M × N SPURIOUS PERFORMANCE

Mixer spurious products are measured in dBc from the RF

output power level. Spurious frequencies are calculated by

f_RF= 28 GHz.

N × LO

4

|(M × IF) + (N × LO) | (for IF Mode)

|(M × IQ) + (N × LO) | (for IQ Mode)

0

1

2

3

5

6

7

8

−2 76

−1 68

117 120 109 77

92 90 84 45

46 56 53 44

34 24 20 30

N/A means not applicable. Blank cells in the spurious

performance tables indicate that the frequency is above 50 GHz

and is not measured. REF stands for reference RF output signal.

90

80

71

58

75

77

26

18

70

23

9

M × IF

0

N/A 71

+1 76

+2 68

92

84

REF 24 32 61

58 80 82 75

The LO frequencies are referred from the frequencies applied to

the ADMV1013. IF and I/Q amplitude = −20 dBm.

f_IF= 3.5 GHz at −20 dBm, LO = 8.875 GHz at +6 dBm, and

_RF= 39 GHz.

VCC_DRV = VCC2_DRV = VCC_AMP2 = VCC_ENV =

VCC_AMP1 = VCC_BG2 = VCC_MIXER = VCC_BG =

VCC_QUAD = 3.3 V, DVDD = VC C _V VA = 1. 8 V, T _A= 25°C,

and set Register 0x0A to 0xE700, unless otherwise noted.

f

N × LO

3

0

1

2

4

5

6

83

69

N/A

83

69

132

95

69

89

114

109

76

44

24

93

96 68

54 25

53 16

33 REF

98 75

99 107

57 83

52

−2

Measurements in IF mode performed with a 90° hybrid,

Register 0x03, Bit 7 = 1, and f_IF= 3.5 GHz.

−1

0

M × IF

Measurements in I/Q mode are measured as a composite of the

I and Q channel performance, V_CM= 0 V, Register 0x03, Bit 7 = 0,

and Register 0x05, Bits[6:0] = 0x051, unless otherwise noted. I/Q

58

+1

+2

f_IF= 3.5 GHz at −20 dBm, LO = 7.875 GHz at +6 dBm, and

f

_BB= 100 MHz.

f_RF= 28 GHz.

VCTRL1 = VCTRL2. V_CTRLis the attenuation voltage at the

VCTRL1 and VCTRL2 pins. V_CTRL= 1800 mV, unless otherwise

specified.

N × LO

0

1

2

3

4

5

6

7

82

65

140 115 107 69

99

97 95

46

−2

−1

I/Q Mode

120 91

41

52

70

REF 47

f_BB= 100 MHz at −20 dBm, LO = 6.975 GHz at +6 dBm.

N/A 82

75

60

23

26

49

56

M × IF

0

N × LO

82

65

94

75

+1

+2

0

1

2

3

4

5

6

7

120 107 111 93

115

93

105 103 122 79

109 89 108

−2

−1

0

f_IF= 3.5 GHz at −20 dBm, LO = 10.5 GHz at +6 dBm, and

95

85

72

74

57

53

32

91

26

20

65

61

53 110

35 73

37 84

91 83

f_RF= 39 GHz.

N/A 80

M × IQ

N × LO

3

93

96

REF 41

57 89

+1

+2

0

1

2

4

5

107 86

96

80

N/A

97

79

122

85

83

95

113

99

28

34

45

88

91

26

43

49

103

70

REF

16

41

102

94

64

−2

−1

0

f_BB= 100 MHz at −20 dBm, LO = 9.725 GHz at +6 dBm, and

_RF= 39 GHz.

f

M × IF

N × LO

3

+1

+2

0

1

2

4

5

97

116

100

77

95

37

40

18

80

116

62

63

36

99

89

26

20

REF

64

113

90

77

68

103

−2

−1

0

101

N/A

97

M × IQ

91

+1

+2

101

118

Rev. A | Page 24 of 39

Data Sheet

ADMV1013

THEORY OF OPERATION

The ADMV1013 is a wideband microwave upconverter optimized

for microwave radio designs operating in the 24 GHz to 44 GHz

RF frequency range. See Figure 1 for a functional block diagram

of the device. The ADMV1013 digital settings are controlled via the

SPI. The ADMV1013 has two modes of operation:

LO INPUT PATH

The LO input path operates from 5.4 GHz to 10.25 GHz with

an LO amplitude range of −6 dBm to +6 dBm. The LO has an

internal quadrupler (×4) and a programmable band-pass filter.

The LO band-pass filter is programmable using the QUAD_

FILTERS bits (Register 0x09, Bits[3:0]). See the Performance at

Different Quad Filter Settings section for more information on

the QUAD_FILTERS settings.

•

Baseband quadrature modulation (I/Q mode)

Single-sideband upconversion (IF mode)

START-UP SEQUENCE

The LO path can operate either differentially or single ended.

LOP and LON are the inputs to the LO path. The LO path can

switch from differential to single-ended operation by setting the

QUAD_SE_MODE bits (Register 0x09, Bits[9:6]). See the

Performance Between Differential vs. Single-Ended LO Input

section for more information. When using the LO as single

ended, the unused LO input pin must be terminated with a

50 Ω load.

To use the voltage control RF VVA1 and RF VVA2, the

VCC_VVA (1.8 V) supply must be on. The VCTRL1 pin and

VCTRL2 pin control the gain of the RF VVA1 and the RF

VVA2. Similarly, to use the SPI control, it is necessary to first

turn on DVDD and then perform a hard reset by toggling the

RST pin to logic low and then to logic high.

The ADMV1013 SPI settings require the default settings to be

changed during startup for optimum performance.

Figure 81 shows a block diagram of the LO path.

Set Register 0x0A to 0xE700 after each power-up or reset.

BASEBAND QUADRATURE MODULATION

(I/Q MODE)

In I/Q mode, the input impedance of the baseband pins (I_P,

I_N, Q_P, and Q_N) are 100 Ω differential. These inputs can be

loaded with a dc-coupled 100 Ω differential load. I_P and I_N

are the differential baseband I inputs, and Q_P and Q_N are the

differential baseband Q inputs. These inputs can operate from a

LON

LOP

4 × LON

4 × LOP

×4

AMP

V

_CMof 0 V to 2.6 V. The baseband I/Q ports can operate from

Figure 81. LO Path Block Diagram

dc to 6.0 GHz at each I and Q channel.

Enable the quadrupler by setting the QUAD_PD bits

(Register 0x03, Bits[13:11]) to 0x0. To power down the

quadrupler, set these bits to 0x7.

To set the ADMV1013 in I/Q mode, set MIXER_IF_EN bit

(Register 0x03, Bit 7) to 0.

When changing the external V_CM, the internal mixer gate

voltage also must be changed. To make this change, set the

MIXER_VGATE bits (Register 0x05, Bits[6:0]). The MIXER_

VGATE value follows the V_CMsuch as, that for a 0 V to 1.8 V

SIDEBAND SUPPRESSION OPTIMIZATION

Unwanted sideband can be upconverted from the quadrature

error by generating the quadrature LO signals and the external

quadrature inputs. Deviation from ideal quadrature (that is,

total sideband rejection and no sideband tone upconverts) on

these signals limits the amount of achievable sideband rejection.

V

_CM, MIXER_VGATE = 23.89 V_CM+ 81, and for a >1.8 V to

2.6 V V_CM, MIXER_VGATE = 23.75 V_CM+ 1.25.

SINGLE-SIDEBAND UPCONVERSION (IF MODE)

The ADMV1013 offers approximately 25° of quadrature phase

adjustment in the LO path quadrature signals to suppress the

sideband. Make these adjustments through the LOAMP_PH_

ADJ_I_FINE bits (Register 0x05, Bits[13:7]) and the LOAMP_

PH_ADJ_Q_FINE bits (Register 0x06, Bits[13:7]). These bits

reject the unwanted sideband signal. To achieve the required

sideband suppression, it may be necessary to adjust the

amplitude difference between the quadrature inputs, as well

externally.

The ADMV1013 features the ability to upconvert a real IF input

anywhere from 0.8 GHz to 6.0 GHz while suppressing the

unwanted sideband by typically better than 26 dBc. The IF

inputs are quadrature to each other, 50 Ω single ended, and are

internally dc-coupled. IF_I and IF_Q are the quadrature IF inputs.

An external 90° hybrid is required to select the appropriate

sideband. To configure the ADMV1013 in IF mode, set the

MIXER_IF_EN bit (Register 0x03, Bit 7) to 1. The MIXER_IF_EN

bit defaults to IF mode on SPI startup and reset.

In I/Q mode, the recommendation is to adjust the sideband

suppression through the external transceiver digital-to-analog

converter (DAC).

In addition, the baseband pins (I_P, I_N, Q_P, and Q_N) must

see an open load for optimum performance in IF mode.

Rev. A | Page 25 of 39

ADMV1013

Data Sheet

CARRIER FEEDTHROUGH NULLING

POWER DOWN AND RESET

Carrier feedthrough results from minute dc offsets that occur

on the internal mixer. In an I/Q modulator, nonzero differential

offsets mix with the LO and result in carrier feedthrough to the

RF output. In addition to this effect, some of the signal power at

the LO input couples directly to the RF output (this may be

because of the bond wire to bond wire coupling or coupling

through the silicon substrate). The net carrier feedthrough at

the RF output is the vector combination of the signals that appear

at the output because of these two effects.

The SPI of the ADMV1013 allows the user to power down the

device circuits and reduce power consumption to typically 77 mW.

To turn off the entire chip, set the BG_PD bit (Register 0x03,

Bit 10) to 1. In addition, individual blocks of the circuit can be

powered down individually. To power down the quadrupler,

set the QUAD_PD bits (Register 0x03, Bits[13:11]) to 0x7. To

power down the VGA, set the VGA_PD bit (Register 0x03,

Bit 15) to 1. To power down the mixer, set the MIXER_PD bit

(Register 0x03, Bit 14) to 1. To power down the detector, set the

DET_EN bit (Register 0x03, Bit 5) to 0.

The ADMV1013 offers, in IF mode, LO feedthrough offset

calibration adjustment in the LO path. Make these adjustments

through the MXER_OFF_ADJ_I_N bits (Register 0x07,

Bits[8:2], the MXER_OFF_ADJ_I_P bits (Register 0x07,

Bits[15:9]), the MXER_OFF_ADJ_Q_N bits (Register 0x08,

Bits[8:2]), and the MXER_OFF_ADJ_Q_P bits (Register 0x08,

Bits[15:9] in order to reject the unwanted LO signal.

SERIAL PORT INTERFACE (SPI)

The SPI of the ADMV1013 allows the user to configure the device

for specific functions or operations via a 4-wire SPI port. This

interface provides users with added flexibility and customization.

The SPI consists of four control lines: SCLK, SDI, SDO, and

SEN SEN2 SEN

SEN2

active low chip select lines,

connected together.

/

.

and

must be

For I/Q mode, the LO feedthrough offset amplitude and phase

calibration optimization can be adjusted externally through a

transceiver DAC.

The ADMV1013 protocol consists of a write/read bit followed

by six register address bits, 16 data bits, and a parity bit. Both

the address and data fields are organized MSB first and end with

the LSB. For a write, set the first bit to 0. For a read, set the first

bit to 1.

ENVELOPE DETECTOR

The ADMV1013 features an envelope detector with a pseudo

differential voltage output. The envelope detector output pins

are VENV_P and VENV_N. The ADMV1013 turns on with the

envelope detector turned off. To turn on the envelope detector,

set the DET_EN bit (Bit 5, Register 0x03). The differential voltage

output of the envelope detector rises linearly to the square of

the input envelope voltage to the detector. The detector output

ranges from −45 dBm to −20 dBm when the input two tone

power ranges from −20 dBm to 0 dBm. The envelope detector

has 350 MHz, 3 dB envelope bandwidth and 1 GHz, 10 dB

envelope bandwidth. The envelope detector precedes the VVA

and the output driver of the ADMV1013.

The write cycle sampling must be performed on the rising edge.

The 16 bits of the serial write data are shifted in, MSB to lower

sideband. The ADMV1013 input logic level for the write cycle

supports a 1.8 V interface.

For a read cycle, up to 16 bits of serial read data are shifted out,

MSB first. After the 16 bits of data shift out, the parity bit shifts

out. The output logic level for a read cycle is 1.8 V.

The parity bit always follows the direction of the data. If parity

is not used, the transmitting end transmits zero instead of parity.

The parity is odd, which means that the total number of ones

transmitted during a command, including the read/write bit,

the address bit, the data bit, and the parity bit, must be odd.

Figure 82 and Figure 83 show the SPI write and read protocol,

respectively.

SEN/SEN2

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

SCLK

SDI

R/W

A5

A4

A3

A2

A1

A0

D15 D14 D13 D12 D11 D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

P

Figure 82. SPI Write Timing Diagram

Rev. A | Page 26 of 39

Data Sheet

ADMV1013

SEN/SEN2

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

SCLK

R/W A5

A4

A3

A2

A1

A0

SDI

D15 D14 D13 D12 D11 D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

P

SDO

Figure 83. SPI Read Timing Diagram

Rev. A | Page 27 of 39

ADMV1013

Data Sheet

APPLICATIONS INFORMATION

BASEBAND QUADRATURE MODULATION FROM

LOW FREQUENCIES

Figure 86 shows the 4× LO to RF leakage vs. 4× LO frequency at

different quad filter settings.

0

Figure 84 shows the I/Q mode performance at low baseband

input frequencies. The measurements were performed at 28 GHz,

−10 dBm input power, V_CM= 0 V, Register 0x03, Bit 7 = 0, 0 dBm

LO input power, and T_A= 25°C.

–5

–10

–15

–20

–25

–30

–35

45

40

35

QUAD FILTERS = 0

QUAD FILTERS = 5

QUAD FILTERS = 10

–40

SIDEBAND REJECTION

CONVERSION GAIN

30

–45

QUAD FILTERS = 15

–50

25

20

15

10

5

–55

–60

16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48

4× LO FREQUENCY (GHz)

Figure 86.4× LO to RF Leakage vs. 4× LO Frequency for Four Different

QUAD_FILTERS Settings

0

VVA TEMPERATURE COMPENSATION

1

10

100

1k

10k

100k

1M 10M

100M

BASEBAND FREQUENCY (Hz)

Figure 87 shows the conversion gain vs. RF frequency at two

different Register 0x0A settings, the recommended setting

(0xE700) and a setting for higher gain, and three different

temperatures for IF mode. The recommended value suggested

in the Start-Up Sequence section provides the least variation in

conversion gain over temperature. If the priority is to increase

the conversion gain, Register 0x0A can be set to 0xFA00.

However, at this value, the conversion gain variation over

temperature can increase by 2 dB.

Figure 84. Conversion Gain and Sideband Rejection vs. Baseband Frequency

PERFORMANCE AT DIFFERENT QUAD FILTER

SETTINGS

Figure 85 shows the conversion gain vs. RF frequency in

IF mode at T_A= 25°C and LO input power = 0 dBm for

different QUAD_FILTERS settings.

24

22

20

18

16

14

12

10

26

24

22

20

18

16

14

12

QUAD FILTERS = 0

QUAD FILTERS = 5

QUAD FILTERS = 10

QUAD FILTERS = 15

8

6

4

2

–40°C, 0xFA00

+25°C, 0xFA00

0

10

–2

–4

–6

–8

–10

+85°C, 0xFA00

–40°C, 0xE700

+25°C, 0xE700

+85°C, 0xE700

8

6

4

2

0

23

25

27

29

31

33

35

37

39

41

43

45

RF FREQUENCY (GHz)

23

25

27

29

31

33

35

37

39

41

43

45

Figure 85. Conversion Gain vs. RF Frequency for Four Different

QUAD_FILTERS Settings, f_IF= 3.5 GHz (Upper Sideband)

RF FREQUENCY (GHz)

Figure 87. Conversion Gain vs. RF Frequency at Maximum Gain for

Various Temperatures and Register 0x0A Settings (Recommended and

Higher Gain Setting), f_IF= 3.5 GHz

Rev. A | Page 28 of 39

Data Sheet

ADMV1013

28

26

24

22

20

18

16

14

12

10

8

Figure 88 shows the conversion gain vs. RF frequency at two

different Register 0x0A settings, the recommended setting and

the default setting, and three different temperatures for IF mode.

The default values provides slightly less gain and a larger gain

variation across temperature compared to the recommended

setting.

SINGLE-ENDED POSITIVE SIDE DISABLE

SINGLE-ENDED NEGATIVE SIDE DISABLE

DIFFERENTIAL

28

26

24

22

20

18

16

14

6

4

2

0

23

25

27

29

31

33

35

37

39

41

43

45

12

10

8

–40°C, 0xE700

+25°C, 0xE700

+85°C, 0xE700

–40°C, 0x0000

+25°C, 0x0000

+85°C, 0x0000

RF FREQUENCY (GHz)

Figure 90. Output IP3 vs. RF Frequency for Three Different LO Mode Settings,

RF Amplitude = −20 dBm per Tone at 20 MHz Spacing, f_IF= 3.5 GHz

(Upper Sideband)

6

4

40

2

0

35

23

25

27

29

31

33

35

37

39

41

43

45

SINGLE-ENDED POSITIVE SIDE DISABLE

30

25

20

15

10

5

SINGLE-ENDED NEGATIVE SIDE DISABLE

DIFFERENTIAL

RF FREQUENCY (GHz)

Figure 88. Conversion Gain vs. RF Frequency at Maximum Gain for

Various Temperatures and Register 0x0A Settings (Default and

Recommended Register 0x0A Settings), f_IF= 2 GHz

PERFORMANCE BETWEEN DIFFERENTIAL vs.

SINGLE-ENDED LO INPUT

Figure 89 to Figure 91 show the conversion gain, output IP3, and

sideband rejection performance for operating the ADMV1013 LO

input as differential vs. single ended. The measurements were

performed with 0 dBm LO input power, IF mode, with an IF

frequency of 3.5 GHz, upper sideband, and T_A= 25°C.

28

0

23

25

27

29

31

33

35

37

39

41

43

45

RF FREQUENCY (GHz)

Figure 91. Sideband Rejection vs. RF Frequency for Three Different LO Mode

Settings, RF Amplitude = −30 dBm per Tone at 20 MHz Spacing,

f_IF= 3.5 GHz (Upper Sideband)

SINGLE-ENDED POSITIVE SIDE DISABLE

SINGLE-ENDED NEGATIVE SIDE DISABLE

DIFFERENTIAL

26

24

22

20

18

16

14

12

10

8

6

4

2

0

23

25

27

29

31

33

35

37

39

41

43

45

RF FREQUENCY (GHz)

Figure 89. Conversion Gain vs. RF Frequency for Three Different LO Mode

Settings, f_IF= 3.5 GHz (Upper Sideband)

Rev. A | Page 29 of 39

ADMV1013

Data Sheet

Figure 94 and Figure 95 show the conversion gain vs. RF

PERFORMANCE ACROSS RF FREQUENCY AT FIXED

INPUT FREQUENCIES

frequency in I/Q mode for multiple baseband (BB) frequencies

(T_A= 25°C, LO = 0 dBm) for upper sideband and lower

sideband, respectively.

The ADMV1013 quadrupler operates from 21.6 GHz to 41 GHz.

When using the lower sideband, the conversion gain starts

rolling off gradually after the quadrupler frequency reaches

41 GHz. When using the upper sideband, the conversion gain

starts rolling off when the quadrupler frequency is 21.6 GHz.

28

26

24

22

20

18

Figure 92 and Figure 93 show the conversion gain vs. RF frequency

in IF mode for fixed IF frequencies (T_A= 25°C, LO = 0 dBm) for

the upper sideband and lower sideband, respectively.

I/Q, 0.8GHz

I/Q, 1GHz

16

14

12

10

8

I/Q, 2GHz

I/Q, 3GHz

I/Q, 4GHz

I/Q, 5GHz

I/Q, 6GHz

28

0.8GHz UPPER SIDEBAND

26

1GHz UPPER SIDEBAND

2GHz UPPER SIDEBAND

24

3GHz UPPER SIDEBAND

4GHz UPPER SIDEBAND

22

20

18

16

14

12

10

8

6

4

2

0

23

25

27

29

31

33

35

37

39

41

43

45

RF FREQUENCY (GHz)

Figure 94. Conversion Gain vs. RF Frequency for Multiple Baseband

Frequency Settings (Upper Sideband)

6

28

26

24

22

20

18

5GHz UPPER SIDEBAND

4

6GHz UPPER SIDEBAND

7GHz UPPER SIDEBAND

2

0

23

25

27

29

31

33

35

37

39

41

43

45

RF FREQUENCY (GHz)

I/Q, 0.8GHz

I/Q, 1GHz

Figure 92. Conversion Gain vs. RF Frequency for Multiple IF Frequency

Settings (Upper Sideband)

16

14

12

10

8

I/Q, 2GHz

I/Q, 3GHz

I/Q, 4GHz

I/Q, 5GHz

I/Q, 6GHz

28

0.8GHz LOWER SIDEBAND

26

24

22

20

18

16

14

12

10

8

1GHz LOWER SIDEBAND

2GHz LOWER SIDEBAND

3GHz LOWER SIDEBAND

4GHz LOWER SIDEBAND

6

4

2

0

23

25

27

29

31

33

35

37

39

41

43

45

RF FREQUENCY (GHz)

Figure 95. Conversion Gain vs. RF Frequency at Multiple Baseband Frequency

Settings (Lower Sideband)

6

5GHz LOWER SIDEBAND

6GHz LOWER SIDEBAND

7GHz LOWER SIDEBAND

4

2

0

23

25

27

29

31

33

35

37

39

41

43

45

RF FREQUENCY (GHz)

Figure 93. Conversion Gain vs. RF Frequency at Multiple IF Frequency

Settings (Lower Sideband)

Rev. A | Page 30 of 39

Data Sheet

ADMV1013

PERFORMANCE ACROSS COMMON-MODE

VOLTAGE IN I/Q MODE

OPERATING VCTRL1 AND VCTRL2 INDEPENDENTLY

The data shown in the Specifications section and the Typical

Performance Characteristics section is based on the VCTRL1

and VCTRL2 voltages being equal. Finer gain regulation can be

obtained if VCTRL1 and VCTRL2 are used separately. Operating

VCTRL1 and VCTRL2 also allows either maintaining IP3 or

noise figure performance while attenuating the RF output.

Figure 96, Figure 97, and Figure 98 show the performance at

various common-mode voltages in I/Q mode. For each

common-mode voltage, the mixer gate voltage was changed

based on the equation described in the Baseband Quadrature

Modulation (I/Q Mode) section.

30

Figure 99, Figure 102, and Figure 105 show the conversion gain,

input IP3, and noise figure vs. the RF frequency, respectively (IF =

2 GHz, upper sideband, LO = 0 dBm at T_A= 25°C), when

VCTRL1 is equal to VCTRL2.

25

20

Figure 100, Figure 103, and Figure 106 show the conversion

gain, input IP3, and noise figure vs. the RF frequency, respectively

(IF = 2 GHz, upper sideband, LO = 0 dBm at T_A= 25°C), when

VCTRL2 is held at a minimum attenuation and VCTRL1 is

changed.

0V

0.4V

15

1.0V

1.2V

1.4V

1.8V

10

5

2.0V

2.4V

2.6V

Figure 101, Figure 104, and Figure 107 show the conversion

gain, input IP3, and noise figure vs. the RF frequency, respectively

(IF = 2 GHz, upper sideband, LO = 0 dBm at T_A= 25°C), when

VCTRL1 is held at minimum attenuation and VCTRL2

is changed.

0

23

25

27

29

31

33

35

37

39

41

43

45

RF FREQUENCY (GHz)

Figure 96. Conversion Gain vs. RF Frequency at Multiple Common-Mode

Voltages in I/Q Mode (f_BB= 100 MHz, LO = 0 dBm, T_A= 25°C)

30

28

20

10

26

24

22

20

0

0V

0.4V

18

–10

1.0V

1.2V

1.4V

1.8V

2.0V

2.4V

2.6V

16

14

12

10

8

–20

VCTRL1 = 0V, VCTRL2 = 0V

VCTRL1 = 0.1V, VCTRL2 = 0.1V

VCTRL1 = 0.2V, VCTRL2 = 0.2V

VCTRL1 = 0.3V, VCTRL2 = 0.3V

VCTRL1 = 0.4V, VCTRL2 = 0.4V

VCTRL1 = 0.5V, VCTRL2 = 0.5V

VCTRL1 = 0.6V, VCTRL2 = 0.6V

VCTRL1 = 0.7V, VCTRL2 = 0.7V

VCTRL1 = 0.8V, VCTRL2 = 0.8V

VCTRL1 = 0.9V, VCTRL2 = 0.9V

VCTRL1 = 1.0V, VCTRL2 = 1.0V

VCTRL1 = 1.1V, VCTRL2 = 1.1V

–30

VCTRL1 = 1.2V, VCTRL2 = 1.2V

VCTRL1 = 1.3V, VCTRL2 = 1.3V

VCTRL1 = 1.4V, VCTRL2 = 1.4V

VCTRL1 = 1.5V, VCTRL2 = 1.5V

VCTRL1 = 1.6V, VCTRL2 = 1.6V

VCTRL1 = 1.7V, VCTRL2 = 1.7V

VCTRL1 = 1.8V, VCTRL2 = 1.8V

–40

–50

–60

6

4

2

0

23

25

27

29

31

33

35

37

39

41

43

45

23

25

27

29

31

33

35

37

39

41

43

45

RF FREQUENCY (GHz)

Figure 99. Conversion Gain vs. RF Frequency at Various V_CTRLVoltages

(VCTRL1 = VCTRL2), IF Mode, IF Frequency = 2 GHz, Upper Sideband

Figure 97. Output IP3 vs. RF Frequency at Multiple Common-Mode Voltages

in I/Q Mode (f_BB= 100 MHz, LO = 0 dBm, T_A= 25°C)

30

20

10

20

18

16

14

12

10

0

VCTRL1 = 0V

VCTRL1 = 0.1V

–10

0V

1.4V

1.6V

1.8V

2.0V

2.2V

2.4V

2.6V

VCTRL1 = 0.2V

VCTRL1 = 0.3V

VCTRL1 = 0.4V

VCTRL1 = 0.5V

VCTRL1 = 0.6V

VCTRL1 = 0.7V

VCTRL1 = 0.8V

VCTRL1 = 0.9V

VCTRL1 = 1.0V

VCTRL1 = 1.1V

8

6

4

2

0

0.2V

0.4V

0.6V

0.8V

1.0V

1.2V

VCTRL1 = 1.2V

VCTRL1 = 1.3V

VCTRL1 = 1.4V

VCTRL1 = 1.5V

VCTRL1 = 1.6V

VCTRL1 = 1.7V

VCTRL1 = 1.8V

–20

–30

–40

23

25

27

29

31

33

35

37

39

41

43

45

23

25

27

29

31

33

35

37

39

41

43

45

RF FREQUENCY (GHz)

Figure 100. Conversion Gain vs. RF Frequency at Various VCTRL1 Voltages

(VCTRL2 = 1.8 V), IF Mode, IF Frequency = 2 GHz, Upper Sideband

Figure 98. Output P1dB vs. RF Frequency at Multiple Common-Mode

Voltages in I/Q Mode (f_BB= 100 MHz, LO = 0 dBm, T_A= 25°C)

Rev. A | Page 31 of 39

ADMV1013

Data Sheet

30

20

15

10

5

20

10

0

VCTRL2 = 0V

VCTRL2 = 0.1V

VCTRL2 = 0.2V

VCTRL2 = 0.3V

VCTRL2 = 0.4V

VCTRL2 = 0.5V

VCTRL2 = 0.6V

VCTRL2 = 0.7V

VCTRL2 = 0.8V

VCTRL2 = 0.9V

VCTRL2 = 1.0V

VCTRL2 = 1.1V

–10

–20

–30

–40

VCTRL2 = 0V

VCTRL2 = 0.9V

VCTRL2 = 1.0V

VCTRL2 = 1.1V

VCTRL2 = 1.2V

VCTRL2 = 1.3V

VCTRL2 = 1.4V

VCTRL2 = 1.5V

VCTRL2 = 1.6V

VCTRL2 = 1.7V

VCTRL2 = 0.1V

VCTRL2 = 0.2V

VCTRL2 = 0.3V

VCTRL2 = 0.4V

VCTRL2 = 0.5V

VCTRL2 = 0.6V

VCTRL2 = 0.7V

VCTRL2 = 0.8V

0

VCTRL2 = 1.2V

VCTRL2 = 1.3V

VCTRL2 = 1.4V

VCTRL2 = 1.5V

VCTRL2 = 1.6V

VCTRL2 = 1.7V

VCTRL2 = 1.8V

–5

–10

VCTRL2 = 1.8V

23

25

27

29

31

33

35

37

39

41

43

45

23

25

27

29

31

33

35

37

39

41

43

45

RF FREQUENCY (GHz)

Figure 101. Conversion Gain vs. RF Frequency at Various VCTRL2 Voltages

(VCTRL1 = 1.8 V), IF Mode, IF Frequency = 2 GHz, Upper Sideband

Figure 104. Input IP3 vs. RF Frequency at Various VCTRL2 Voltages (VCTRL1 =

1.8 V), IF Mode, IF Frequency = 2 GHz, Upper Sideband

60

55

50

45

40

35

30

25

20

15

10

5

VCTRL1 = 0V, VCTRL2 = 0V

VCTRL1 = 0.9V, VCTRL2 = 0.9V

VCTRL1 = 1.0V, VCTRL2 = 1.0V

VCTRL1 = 1.1V, VCTRL2 = 1.1V

VCTRL1 = 1.2V, VCTRL2 = 1.2V

VCTRL1 = 1.3V, VCTRL2 = 1.3V

VCTRL1 = 1.4V, VCTRL2 = 1.4V

VCTRL1 = 1.5V, VCTRL2 = 1.5V

VCTRL1 = 1.6V, VCTRL2 = 1.6V

VCTRL1 = 1.7V, VCTRL2 = 1.7V

VCTRL1 = 1.8V, VCTRL2 = 1.8V

0

–5

VCTRL1 = 0V, VCTRL2 = 0V

VCTRL1 = 0.9V, VCTRL2 = 0.9V

VCTRL1 = 1.0V, VCTRL2 = 1.0V

VCTRL1 = 1.1V, VCTRL2 = 1.1V

VCTRL1 = 1.2V, VCTRL2 = 1.2V

VCTRL1 = 1.3V, VCTRL2 = 1.3V

VCTRL1 = 1.4V, VCTRL2 = 1.4V

VCTRL1 = 1.5V, VCTRL2 = 1.5V

VCTRL1 = 1.6V, VCTRL2 = 1.6V

VCTRL1 = 1.7V, VCTRL2 = 1.7V

VCTRL1 = 1.8V, VCTRL2 = 1.8V

VCTRL1 = 0.1V, VCTRL2 = 0.1V

VCTRL1 = 0.2V, VCTRL2 = 0.2V

VCTRL1 = 0.3V, VCTRL2 = 0.3V

VCTRL1 = 0.4V, VCTRL2 = 0.4V

VCTRL1 = 0.5V, VCTRL2 = 0.5V

VCTRL1 = 0.6V, VCTRL2 = 0.6V

VCTRL1 = 0.7V, VCTRL2 = 0.7V

VCTRL1 = 0.8V, VCTRL2 = 0.8V

VCTRL1 = 0.1V, VCTRL2 = 0.1V

VCTRL1 = 0.2V, VCTRL2 = 0.2V

VCTRL1 = 0.3V, VCTRL2 = 0.3V

VCTRL1 = 0.4V, VCTRL2 = 0.4V

VCTRL1 = 0.5V, VCTRL2 = 0.5V

VCTRL1 = 0.6V, VCTRL2 = 0.6V

VCTRL1 = 0.7V, VCTRL2 = 0.7V

VCTRL1 = 0.8V, VCTRL2 = 0.8V

15

10

5

0

–10

23

25

27

29

31

33

35

37

39

41

43

45

23

25

27

29

31

33

35

37

39

41

43

45

RF FREQUENCY (GHz)

Figure 105. Noise Figure vs. RF Frequency at Various V_CTRLVoltages (VCTRL1 =

VCTRL2), IF Mode, IF Frequency = 2 GHz, Upper Sideband

Figure 102. Input IP3 vs. RF Frequency at Various V_CTRLVoltages (VCTRL1 =

VCTRL2), I IF Mode, IF Frequency = 2 GHz, Upper Sideband

60

20

15

10

5

VCTRL1 = 0V

VCTRL1 = 0.9V

VCTRL1 = 1.0V

VCTRL1 = 1.1V

VCTRL1 = 1.2V

VCTRL1 = 1.3V

VCTRL1 = 1.4V

VCTRL1 = 1.5V

VCTRL1 = 1.6V

VCTRL1 = 1.7V

VCTRL1 = 0.1V

VCTRL1 = 0.2V

VCTRL1 = 0.3V

VCTRL1 = 0.4V

VCTRL1 = 0.5V

VCTRL1 = 0.6V

VCTRL1 = 0.7V

VCTRL1 = 0.8V

55

50

45

40

35

30

25

20

15

10

5

VCTRL1 = 1.8V

VCTRL1 = 0V,

VCTRL1 = 0.1V

VCTRL1 = 0.2V

VCTRL1 = 0.3V

VCTRL1 = 0.4V

VCTRL1 = 0.5V

VCTRL1 = 0.6V

VCTRL1 = 0.7V

VCTRL1 = 0.8V

VCTRL1 = 0.9V

VCTRL1 = 1.0V

VCTRL1 = 1.1V

VCTRL1 = 1.2V

VCTRL1 = 1.3V

VCTRL1 = 1.4V

VCTRL1 = 1.5V

VCTRL1 = 1.6V

VCTRL1 = 1.7V

VCTRL1 = 1.8V

0

–5

0

–10

23

25

27

29

31

33

35

37

39

41

43

45

23

25

27

29

31

33

35

37

39

41

43

45

RF FREQUENCY (GHz)

Figure 106. Noise Figure vs. RF Frequency at Various VCTRL1 Voltages

(VCTRL2 = 1.8 V), IF Mode, IF Frequency = 2 GHz, Upper Sideband

Figure 103. Input IP3 vs. RF Frequency at Various VCTRL1 Voltages (VCTRL2 =

1.8 V), IF Mode, IF Frequency = 2 GHz, Upper Sideband

Rev. A | Page 32 of 39

Data Sheet

ADMV1013

60

55

50

45

40

35

30

25

20

15

10

5

VCTRL2 = 0V

VCTRL2 = 0.9V

VCTRL2 = 1.0V

VCTRL2 = 1.1V

VCTRL2 = 1.2V

VCTRL2 = 1.3V

VCTRL2 = 1.4V

VCTRL2 = 1.5V

VCTRL2 = 1.6V

VCTRL2 = 1.7V

VCTRL2 = 1.8V

VCTRL2 = 0.1V

VCTRL2 = 0.2V

VCTRL2 = 0.3V

VCTRL2 = 0.4V

VCTRL2 = 0.5V

VCTRL2 = 0.6V

VCTRL2 = 0.7V

VCTRL2 = 0.8V

0

23

25

27

29

31

33

35

37

39

41

43

45

RF FREQUENCY (GHz)

Figure 107. Noise Figure vs. RF Frequency at Various VCTRL2 Voltages

(VCTRL1 = 1.8 V), IF Mode, IF Frequency = 2 GHz, Upper Sideband

RECOMMENDED LAND PATTERN

Solder the exposed pad on the underside of the ADMV1013 to a

low thermal and electrical impedance ground plane. This pad is

typically soldered to an exposed opening in the solder mask on

the evaluation board. Connect these ground vias to all other

ground layers on the evaluation board to maximize heat

dissipation from the device package.

Figure 108. Evaluation Board Layout for the LGA Package

EVALUATION BOARD INFORMATION

For more information about the ADMV1013 evaluation board,

refer to the ADMV1013-EVALZ user guide.

Rev. A | Page 33 of 39

ADMV1013

Data Sheet

REGISTER SUMMARY

Table 6.

Reg.

Bit 15

Bit 7

Bit 14

Bit 6

Bit 13

Bit 5

Bit 12

Bit 4

Bit 11 Bit 10

Bit 3 Bit 2

Bit 9 Bit 8

Bit 1 Bit 0

(Hex) Register Name

Bits

Reset

R/W

00

01

SPI_CONTROL

ALARM

[15:8] PARITY_EN

SPI_SOFT_

RESET

RESERVED

CHIP_ID

0x00A4

R/W

[7:0]

CHIP_ID

REVISION

RESERVED

[15:8] PARITY_

ERROR

TOO_FEW_ TOO_MANY_ ADDRESS_

ERRORS

0x0000

0xFFFF

R

ERRORS

RANGE_

ERROR

[7:0]

RESERVED

02

ALARM_MASKS

[15:8] PARITY_

ERROR_

TOO_FEW_ TOO_MANY_ ADDRESS_

ERRORS_

MASK

RESERVED

R/W

ERRORS_

MASK

RANGE_

ERROR_MASK

MASK

[7:0]

RESERVED

QUAD_PD

03

05

ENABLE

[15:8] VGA_PD

MIXER_PD

BG_PD

RESERVED

0x01D7 R/W

[7:0]

[15:8]

[7:0]

MIXER_IF_EN RESERVED

RESERVED

DET_EN

RESERVED

LO_AMP_I

LOAMP_PH_ADJ_I_FINE

MIXER_VGATE

0x5051

R/W

LOAMP_

PH_ADJ_

I_FINE

06

LO_AMP_Q

[15:8]

[7:0]

RESERVED

LOAMP_PH_ADJ_Q_FINE

RESERVED

0x5000

R/W

LOAMP_

PH_ADJ_

Q_FINE

07

08

OFFSET_ADJUST_I

OFFSET_ADJUST_Q

QUAD

[15:8]

MXER_OFF_ADJ_I_P

MXER_OFF_ADJ_I_N

MXER_OFF_ 0xFFFC

ADJ_I_N

R/W

[7:0]

RESERVED

[15:8]

MXER_OFF_ADJ_Q_P

MXER_OFF_ 0xFFFC

ADJ_Q_N

[7:0]

[15:8]

[7:0]

MXER_OFF_ADJ_Q_N[5:0]

RESERVED

QUAD_SE_MODE

QUAD_FILTERS

09

0A

0x5700

0x0000

R/W

QUAD_SE_MODE

RESERVED

VVA_TEMPERATURE_ [15:8]

COMPENSATION

VVA_TEMPERATURE_COMPENSATION

[7:0]

Rev. A | Page 34 of 39

Data Sheet

ADMV1013

REGISTER DETAILS

Address: 0x00, Reset: 0x00A4, Name: SPI_CONTROL

15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

1

0

1

0

1

0

[15] PARITY_EN (R/W)

[3:0] REVISION (R)

Enable the Parity for Write Execution

Revision ID

[14] SPI_SOFT_RESET (R/W)

[11:4] CHIP_ID (R)

SPI Soft Reset

Chip ID

[13:12] RESERVED

Table 7. Bit Descriptions for SPI_CONTROL

Bits

Bit Name

Settings

Description

Reset

0x0

Access

15

PARITY_EN

SPI_SOFT_RESET

RESERVED

CHIP_ID

Enable the Parity for Write Execution

R/W

R

14

SPI Soft Reset

Reserved

0x0

[13:12]

[11:4]

[3:0]

0x0

Chip ID

0xA

0x4

R

REVISION

Revision ID

R

Address: 0x01, Reset: 0x0000, Name: ALARM

15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

[15] PARITY_ERROR (R)

[11:0] RESERVED

Parity Error

[12] ADDRESS_RANGE_ERROR (R)

[14] TOO_FEW_ERRORS (R)

Address Range Error

Too Few Errors

[13] TOO_MANY_ERRORS (R)

Too Many Errors

Table 8. Bit Descriptions for ALARM

Bits

15

14

Bit Name

Settings Description

Reset

0x0

Access

PARITY_ERROR

TOO_FEW_ERRORS

TOO_MANY_ERRORS

ADDRESS_RANGE_ERRO

R

Parity Error

Too Few Errors

Too Many Errors

R

13

12

0x0

Address Range Error

[11:0] RESERVED

Reserved

0x0

R

Address: 0x02, Reset: 0xFFFF, Name: ALARM_MASKS

15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

1

[15] PARITY_ERROR_MASK (R/W)

[11:0] RESERVED

Parity Error Mask

[12] ADDRESS_RANGE_ERROR_MASK (R/W)

[14] TOO_FEW_ERRORS_MASK (R/W)

Address Range Error Mask

Too Few Errors Mask

[13] TOO_MANY_ERRORS_MASK (R/W)

Too Many Errors Mask

Table 9. Bit Descriptions for ALARM_MASKS

Bits

15

Bit Name

Settings Description

Reset

0x1

Access

R/W

R

PARITY_ERROR_MASK

TOO_FEW_ERRORS_MASK

TOO_MANY_ERRORS_MASK

ADDRESS_RANGE_ERROR_MASK

Parity Error Mask

14

13

Too Few Errors Mask

Too Many Errors Mask

0x1

12

Address Range Error Mask

Reserved

0x1

0xFFF

[11:0] RESERVED

Rev. A | Page 35 of 39

ADMV1013

Data Sheet

Address: 0x03, Reset: 0x01D7, Name: ENABLE

15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

1

0

1

0

1

[15] VGA_PD (R/W)

[4:0] RESERVED

Power Down the VGA Circuit

[5] DET_EN (R/W)

[14] MIXER_PD (R/W)

Enable the Envelope Detector

Power Down the Mixer Circuit

[6] RESERVED

[13:11] QUAD_PD (R/W)

Power Down the Quad

0: Enable LO Quad Circuit.

111: Disable LO Quad Circuit.

[7] MIXER_IF_EN (R/W)

Enable the IF Mode

[10] BG_PD (R/W)

Power Down the Transmitter Band Gap

[9:8] RESERVED

Table 10. Bit Descriptions for ENABLE

Bits

15

Bit Name

VGA_PD

Settings

Description

Power Down the VGA Circuit

Reset

0x0

Access

R/W

14

[13:11]

MIXER_PD

QUAD_PD

Power Down the Mixer Circuit

Power Down the Quad

0x0

R/W

000 Enable LO Quad Circuit

111 Disable LO Quad Circuit

10

[9:8]

7

BG_PD

Power Down the Transmitter Band Gap

Reserved

Enable the IF Mode

Reserved

Enable the Envelope Detector

Reserved

0x0

0x1

0x0

0x17

R/W

R

R/W

R

R/W

R

RESERVED

MIXER_IF_EN

RESERVED

DET_EN

6

5

[4:0]

RESERVED

Address: 0x05, Reset: 0x5051, Name: LO_AMP_I

15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

1

0

1

0

1

0

1

0

1

[15:14] RESERVED

[6:0] MIXER_VGATE (R/W)

Control Mixer Gate Voltage. For 0 V to 1.8

V, MIXER_VGATE = 23.89 x Common-Mode

Voltage +81, and for 1.8 V to 2.6 V, MIXER_VGATE

= 23.75 x Common-Mode Voltage +1.25.

[13:7] LOAMP_PH_ADJ_I_FINE (R/W)

Mixer Image Rejection Calibration

Table 11. Bit Descriptions for LO_AMP_I

Bits

Bit Name

Settings Description

Reset Access

[15:14] RESERVED

Reserved.

0x1

R

[13:7]

[6:0]

LOAMP_PH_ADJ_I_FINE

MIXER_VGATE

Mixer Image Rejection Calibration.

0x20

0x51

R/W

Control Mixer Gate Voltage. For 0 V to 1.8 V, MIXER_VGATE = 23.89 ×

Common-Mode Voltage + 81, and for 1.8 V to 2.6 V, MIXER_VGATE =

23.75 × Common-Mode Voltage + 1.25.

Address: 0x06, Reset: 0x5000, Name: LO_AMP_Q

15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

1

0

1

0

[15:14] RESERVED

[6:0] RESERVED

[13:7] LOAMP_PH_ADJ_Q_FINE (R/W)

Mixer Image Rejection Calibration

Table 12. Bit Descriptions for LO_AMP_Q

Bits

Bit Name

Settings Description

Reset

0x1

Access

R

[15:14] RESERVED

Reserved

[13:7]

[6:0]

LOAMP_PH_ADJ_Q_FINE

RESERVED

Mixer Image Rejection Calibration

Reserved

0x20

0x0

R/W

R

Rev. A | Page 36 of 39

Data Sheet

ADMV1013

Address: 0x07, Reset: 0xFFFC, Name: OFFSET_ADJUST_I

15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

1

0

[15:9] MXER_OFF_ADJ_I_P (R/W)

LO Feedthrough Offset Calibration

I Positive for IF Mode

[1:0] RESERVED

[8:2] MXER_OFF_ADJ_I_N (R/W)

LO Feedthrough Offset Calibration

I Negative for IF Mode

Table 13. Bit Descriptions for OFFSET_ADJUST_I

Bits

Bit Name

Settings Description

Reset

Access

R/W

R

[15:9] MXER_OFF_ADJ_I_P

LO Feedthrough Offset Calibration I Positive for IF Mode

LO Feedthrough Offset Calibration I Negative for IF Mode

Reserved

0x7F

0x0

[8:2]

[1:0]

MXER_OFF_ADJ_I_N

RESERVED

Address: 0x08, Reset: 0xFFFC, Name: OFFSET_ADJUST_Q

15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

1

0

[15:9] MXER_OFF_ADJ_Q_P (R/W)

LO Feedthrough Offset Calibration

Q Positive for IF Mode

[1:0] RESERVED

[8:2] MXER_OFF_ADJ_Q_N (R/W)

LO Feedthrough Offset Calibration

Q Negative for IF Mode

Table 14. Bit Descriptions for OFFSET_ADJUST_Q

Bits

Bit Name

Settings Description

Reset

0x7F

0x0

Access

R/W

R

[15:9] MXER_OFF_ADJ_Q_P

LO Feedthrough Offset Calibration Q Positive for IF Mode

LO Feedthrough Offset Calibration Q Negative for IF Mode

Reserved

[8:2]

[1:0]

MXER_OFF_ADJ_Q_N

RESERVED

Address: 0x09, Reset: 0x5700, Name: QUAD

15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

1

0

1

0

1

0

[15:10] RESERVED

[9:6] QUAD_SE_MODE (R/W)

[3:0] QUAD_FILTERS (R/W)

LO Filters Bandwidth Selection

0000: LO Frequency Bandwidth: 8.62 GHz to 10.25

Switch Differential/Single-Ended Modes

GHz.

0110: Single Ended Mode, N Side Disable.

1001: Single Ended Mode, P Side Disable.

1100: Differential Mode.

0101: LO Frequency Bandwidth: 6.6 GHz to 9.2

GHz.

1010: LO Frequency Bandwidth: 5.4 GHz to 8 GHz.

1111: LO Frequency Bandwidth: 5.4 GHz to 7 GHz.

[5:4] RESERVED

Table 15. Bit Descriptions for QUAD

Bits

Bit Name

Settings Description

Reset

Access

[15:10] RESERVED

Reserved.

0x15

0xC

R

[9:6]

QUAD_SE_MODE

Switch Differential/Single-Ended Modes.

0110 Single-Ended Mode, Negative Side Disable.

1001 Single-Ended Mode, Positive Side Disable.

1100 Differential Mode.

R/W

[5:4]

[3:0]

RESERVED

QUAD_FILTERS

Reserved.

LO Filters Bandwidth Selection.

0x0

R

R/W

0000 LO Frequency Bandwidth: 8.62 GHz to 10.25 GHz.

0101 LO Frequency Bandwidth: 6.6 GHz to 9.2 GHz.

1010 LO Frequency Bandwidth: 5.4 GHz to 8 GHz.

1111 LO Frequency Bandwidth: 5.4 GHz to 7 GHz.

Rev. A | Page 37 of 39

ADMV1013

Data Sheet

Address: 0x0A, Reset: 0x0000, Name: VVA_TEMPERATURE_COMPENSATION

15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

[15:0] VVA_TEMPERATURE_COMPENSATION (R/W)

VVA Temperature Compensation. PARITY_EN

must be disabled when updating the VVA

temperature compensation

Table 16. Bit Descriptions for VVA_TEMPERATURE_COMPENSATION

Bits Bit Name Settings Description

[15:0] VVA_TEMPERATURE_COMPENSATION

Reset Access

VVA Temperature Compensation. PARITY_EN must be

disabled when updating the VVA temperature

compensation. Set to 0xE700 on startup.

0x0

R/W

Rev. A | Page 38 of 39

Data Sheet

ADMV1013

OUTLINE DIMENSIONS

6.10

6.00

5.90

0.32

0.27

0.22

1.06 BSC

SQ

0.40

0.35

0.30

PIN 1

INDICATOR

PIN 1

CORNER AREA

40

1

31

30

4.50 REF

SQ

4.77 BSC

2.22 BSC

SQ

0.50

BSC

21

10

11

20

BOTTOM VIEW

TOP VIEW

SIDE VIEW

0.750

BSC

0.275

0.165

BSC

0.52

0.45

0.38

0.75 MAX

0.67 NOM

FOR PROPER CONNECTION OF

THE EXPOSED PADS, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

0.25

0.22

0.19

SEATING

PLANE

SECTION OF THIS DATA SHEET.

Figure 109. 40-Terminal Land Grid Array Package [LGA]

6 mm × 6 mm Body and 0.67 mm Package Height

(CC-40-5)

Dimensions shown in millimeters

ORDERING GUIDE

Model¹

ADMV1013ACCZ

ADMV1013ACCZ-R7

ADMV1013-EVALZ

Temperature Range

−40°C to +85°C

Package Description

Package Option

CC-40-5

40-Terminal Land Grid Array Package [LGA]

Evaluation Board

¹Z = RoHS-Compliant Part.

registered trademarks are the property of their respective owners.

D17267-0-4/19(A)

Rev. A | Page 39 of 39


型号：	ADMV1013ACCZ-R7
厂家：	ADI
描述：	Wideband, Microwave Upconverter
文件：	总39页 (文件大小：1457K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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