ADMV7310BCEZ_技术文档

E-Band Upconverter SiP,

71 GHz to 76 GHz

ADMV7310

Data Sheet

FEATURES

GENERAL DESCRIPTION

Maximum conversion gain: 35 dB typical

Gain tuning range: 40 dB minimum

The ADMV7310 is a fully integrated system in package (SiP),

in phase/quadrature (I/Q) upconverter that operates between

an intermediate frequency (IF) input range of dc to 2 GHz and a

radio frequency (RF) output range of 71 GHz to 76 GHz. The

device uses an image rejection mixer that is driven by a 6× local

oscillator (LO) multiplier. The mixer RF output is followed by a

variable gain amplifier (VGA) and a power amplifier (PA),

providing a conversion gain of 35 dB typical. Differential I and

Q mixer inputs are provided and can be driven with differential

I and Q baseband waveforms for direct conversion applications.

Alternatively, the inputs can be driven using an external 90° hybrid

and two external 180° hybrids for single-ended applications.

P_SAT: 26 dBm typical for a gain = 23.5 dB and 19.5 dB

OIP3: 31 dBm typical for a gain = 23.5 dB and P_OUT

16.5 dBm per tone

OP1dB: 25 dBm typical for a gain = 23.5 dB and 19.5 dB

Built-in power detector

Built-in envelope detector for LO nulling

Fully integrated, surface-mount, 50-terminal, 16.00 mm ×

14.00 mm LGA_CAV package

=

APPLICATIONS

E-band communication systems

High capacity wireless backhauls

Test and measurement

The ADMV7310 comes in a fully integrated, surface-mount,

50-terminal, 16.00 mm × 14.00 mm, chip array small outline no

lead cavity (LGA_CAV) package. The ADMV7310 operates

over the −40°C to +85°C temperature range.

Aerospace and defense

FUNCTIONAL BLOCK DIAGRAM

1

2

3

4

5

6

7

8

GND

IF_IP

×6

IF_IN

IF_QN

IF_QP

ADMV7310

GND

PORT 1

RFOUT

VGA_VG12

GND

VGA

PA

VGA_VD12

ENV_DET

VGA_CTL12

GND

9

10

11

12

Figure 1.

Rev. A

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rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Technical Support

www.analog.com

ADMV7310

Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Theory of Operation ...................................................................... 23

Mixer and LO Path..................................................................... 23

Envelope Detector, VGA, and Power Detector ...................... 23

Power Amplifier and Power Detector ..................................... 23

Applications Information.............................................................. 25

Power-Up Bias Sequence........................................................... 25

Power-Down Bias Sequence ..................................................... 25

LO Nulling................................................................................... 25

Gain Tuning Procedure ............................................................. 26

Layout .......................................................................................... 27

Typical Application Circuit........................................................... 28

Outline Dimensions....................................................................... 29

Ordering Guide .......................................................................... 29

Applications....................................................................................... 1

General Description......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Absolute Maximum Ratings............................................................ 5

Thermal Resistance ...................................................................... 5

ESD Caution.................................................................................. 5

Pin Configuration and Function Descriptions............................. 6

Interface Schematics..................................................................... 8

Typical Performance Characteristics ............................................. 9

Detector Performance................................................................ 19

Return Loss Performance.......................................................... 21

Spurious Performance................................................................ 22

REVISION HISTORY

10/2019—Revision A: Initial Version

Rev. A | Page 2 of 29

Data Sheet

ADMV7310

SPECIFICATIONS

T_A= −40°C to +85°C, IF = 1 GHz, LO power = 4 dBm, VD_AMP = +4 V, VGA_CTL12 = −5 V, VG_MIXER = −1 V, VD_MULT = +1.5 V,

VGA_VD12 = VGA_VD345 = VGA_VD6 = +4 V, and PA_VD1 = PA_VD2 = +4 V, unless otherwise noted. Measurements performed as

upconverter with lower sideband selected and an external 90° hybrid followed by two external 180° hybrids at the IF ports.

Table 1.

Parameter

Test Conditions/Comments

Min Typ Max Unit

OPERATING CONDITIONS

Frequency Range

Output RF

71

76

12.7

2

GHz

dBm

LO

Input IF

11.8

DC

0

LO Drive Level Range

Input Signal Level

PERFORMANCE

Maximum Conversion Gain

Gain Tuning Range

Gain Flatness

4

−4

8

Total baseband power

−20 dBm input

24.5 35

40

44.5

dB

dBc

3

20

Sideband Rejection

Output Power for 1 dB Compression (OP1dB)

−4 dBm input

15

Gain = 23.5 dB

Gain = 19.5 dB

Gain = 10.5 dB

Gain = 3.5 dB

21.5 25

16.5 20

dBm

9.5

13

Saturated Output Power (P_SAT

Noise Figure (NF)

)

Gain = 23.5 dB

Gain = 19.5 dB

Gain = 10.5 dB

Gain = 3.5 dB

23

26

dBm

17.5 23

10.5 16

Gain = 23.5 dB

Gain = 19.5 dB

Gain = 10.5 dB

Gain = 3.5 dB

26

29

31

dB

6× LO to RF Rejection

RF port uncalibrated

Gain = 23.5 dB

Gain = 19.5 dB

Gain = 10.5 dB

Gain = 3.5 dB

5

18

dBc

Output Third-Order Intercept (OIP3)

Gain = 23.5 dB, output power (P_OUT) =

16.5 dBm per tone

27

31

dBm

Gain = 19.5 dB, P_OUT= 12.5 dBm per tone

Gain = 10.5 dB, P_OUT= 3.5 dBm per tone

Gain = 3.5 dB, P_OUT= −3.5 dBm per tone

26

22

16

29

25

20

6

dBm

dB

Output Waveguide Port Return Loss

Baseband Input Return Loss

LO Port Return Loss

10

dB

Rev. A | Page 3 of 29

ADMV7310

Data Sheet

Parameter

Test Conditions/Comments

Min Typ Max Unit

Minimum Power Amplifier Detector Sensitivity

−5 dBm ≤ P_OUT≤ 0 dBm

0 dBm ≤ P_OUT≤ 23 dBm

0.5

2

mV/dB

Power Amplifier Detector Voltage

Minimum (DET2_REF − DET2_OUT)

Maximum (DET2_REF − DET2_OUT)

DET2_REF

−5 dBm ≤ P_OUT≤ 0 dBm

0 dBm ≤ P_OUT≤ 23 dBm

−5 dBm ≤ P_OUT≤ 23 dBm

3

600

0.9

mV

V

0

−1

2.5

DET2_OUT

V

Envelope Detector

Minimum AC Detected Signal

3 dB Bandwidth

Load resistance (R_LOAD) = 200 Ω

−4 dBm ≤ input power (P_IN) ≤ 9.5 dBm

45

750

24

mV p-p

MHz

dBc

Ω

Second Harmonic

DIFFERENTIAL BASEBAND INPUT PORT IMPEDANCE

LO INPUT PORT IMPEDANCE

POWER SUPPLY

100

50

Ω

DC Power Dissipation

5

4

W

V

mA

PA (PA_VD1 and PA_VD2) Drain Voltage

PA (PA_VG1 and PA_VG2) Gate Voltage

VGA (VGA_VG12, VGA_VG345, and VGA_VG6) Gate Voltage

Multiplier Drain Voltage (VD_MULT)

VGA Voltage Control (VGA_CTL12)

PA (I_{PA_VD1}and I_{PA_VD2}) Drain Current

VGA (I_{VGA_VD12}, I_{VGA_VD345}, and I_{VGA_VD6}) Drain Current

3.88

−2

4.12

+0.2

1.55

0

1.46 1.5

−5

800

250

175

80

Amplifier Drain (VD_AMP) Current (I_{VD_AMP}

Multiplier Drain (VD_MULT) Current (I_{VD_MULT}

)

Rev. A | Page 4 of 29

Data Sheet

ADMV7310

ABSOLUTE MAXIMUM RATINGS

THERMAL RESISTANCE

Table 2.

Thermal performance is directly linked to printed circuit board

(PCB) design and operating environment. Careful attention to

PCB thermal design is required.

Parameter

Rating

VD_AMP

VD_MULT

4.5 V

3 V

VGA_VD12, VGA_VD345, and VGA_VD6

PA_VD1 and PA_VD2

VG_AMP

4.5 V

θ_JCis the junction to case (or die to package) thermal resistance.

Table 3. Thermal Resistance¹

−3 V to +0.2 V

−6 V to 0 V

10 dBm

Package Type

θ_JC

Unit

VG_MULT

VGA_VG12, VGA_VG345, and VGA_VG6

PA_VG1 and PA_VG2

VGA_CTL12

CE-50-2

15

°C/W

¹Thermal impedance simulated values are based on a JEDEC 2S2P test board

with 16 mm × 14 mm thermal vias. Refer to JEDEC standard JESD51-2 for

additional information.

LO Drive

Baseband Input (IF_IP, IF_IN, IF_QP, and

IF_QN)

4 dBm

ESD CAUTION

IF Source and Sink Current

3 mA

Nominal Junction Temperature (T_A= 85°C) 160°C

Maximum Junction Temperature

(to Maintain 1 Million Hours Mean Time

to Failure (MTTF))

190°C

Maximum Junction Temperature

(to Maintain 3 Million MTTF)

175°C

Operating Temperature Range

Storage Temperature Range

Maximum Peak Reflow Temperature

(Moisture Sensitivity Level 3 (MSL3))

−40°C to +85°C

−55°C to +150°C

260°C

Thermal Humidity Bias (THB)

Thermal Humidity Storage (THS)

Electrostatic Discharge (ESD) Sensitivity

Human Body Model (HBM)

Field Induced Charged Device Model

(FICDM)

JESD22-A101^{1, 2, 3}

JESD22-A101^{1, 3}

200 V

300 V

¹Samples subject to preconditioning (per J-STD-020 Level 3) prior to the start

of the stress test. Level 3 preconditioning consists of the following: bake for

24 hours at 125°C, unbiased soak for 192 hours at 30°C and 60% relative

humidity (RH), and reflow of three passes through an oven with a peak

temperature of 260°C.

²Results valid for 600 mW of nominal dc power dissipation for all active

devices. Analog Devices, Inc., recommends that users perform their own THB

test for all other bias conditions.

³Valid for package vent hole solder sealed or unsealed during test.

Stresses at or above those listed under Absolute Maximum

Ratings may cause permanent damage to the product. This is a

stress rating only; functional operation of the product at these

or any other conditions above those indicated in the operational

section of this specification is not implied. Operation beyond

the maximum operating conditions for extended periods may

affect product reliability.

Rev. A | Page 5 of 29

ADMV7310

Data Sheet

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

1

2

GND

IF_IP

3

IF_IN

4

IF_QN

5

IF_QP

ADMV7310

6

GND

PORT 1

RFOUT

TOP VIEW

7

VGA_VG12

GND

(Not to Scale)

8

9

VGA_VD12

ENV_DET

VGA_CTL12

GND

10

11

12

NOTES

1. EXPOSED PADS. THE EXPOSED GROUND PADS MUST BE CONNECTED

TO RF AND DC GROUND.

Figure 2. Pin Configuration

Table 4. Pin Function Descriptions

Pin No.

Mnemonic

Description

1, 6, 8, 12 to 15, 18, 23, 25, 27, 30 to 34, 36,

38, 39, 41, 43, 45, 47, 50

GND

Ground Connections. These pins must be connected to RF and dc ground.

2

3

4

5

IF_IP

Positive IF In Phase Input. This pin is dc-coupled. When operation to dc is not

required, block this pin externally using a series capacitor with a value

chosen to pass the necessary frequency range. For operation to dc, this pin

must not source or sink more than 3 mA of current or device malfunction

and device failure may result.

Negative IF In Phase Input. This pin is dc-coupled. When operation to dc is

not required, block this pin externally using a series capacitor with a value

chosen to pass the necessary frequency range. For operation to dc, this pin

must not source or sink more than 3 mA of current or device malfunction

and device failure may result.

Negative IF Quadrature Input. This pin is dc-coupled. When operation to dc is

not required, block this pin externally using a series capacitor with a value

chosen to pass the necessary frequency range. For operation to dc, this pin

must not source or sink more than 3 mA of current or device malfunction

and device failure may result.

Positive IF Quadrature Input. This pin is dc-coupled. When operation to dc is

not required, block this pin externally using a series capacitor with a value

chosen to pass the necessary frequency range. For operation to dc, this pin

must not source or sink more than 3 mA of current or device malfunction

and device failure may result.

IF_IN

IF_QN

IF_QP

7

VGA_VG12

VGA_VD12

ENV_DET

Gate Control for the First and Second Stage Variable Gain Amplifier. See

Figure 86 for the recommended external components.

Drain Voltage for the First and Second Stage Variable Gain Amplifier. See

Figure 86 for the recommended external components.

9

10

Envelope Detector. See Figure 86 for the recommended external components.

Rev. A | Page 6 of 29

Data Sheet

ADMV7310

Pin No.

Mnemonic

Description

11

VGA_CTL12

Gain Control Voltage for the First and Second Stage Variable Gain Amplifier.

See Figure 86 for the recommended external components.

16

17

19

20

21

VGA_VG345

VGA_VD345

VGA_VG6

Gate Control for the Third, Fourth, and Fifth Stage Variable Gain Amplifier.

See Figure 86 for the recommended external components.

Drain Voltage for the Third, Fourth, and Fifth Stage Variable Gain Amplifier.

See Figure 86 for the recommended external components.

Gate Control for the Sixth Stage Variable Gain Amplifier. See Figure 86 for the

recommended external components.

Drain Voltage for the Sixth Stage Variable Gain Amplifier. See Figure 86 for

the recommended external components.

VGA_VD6

DET1_REF

Reference Voltage for the VGA Power Detector. DET1_REF is the dc bias of

the diode biased through an external resistor used for the temperature

compensation of DET1_OUT.

22

DET1_OUT

Detector Voltage for the VGA Power Detector. DET1_OUT is the dc voltage

representing the RF output power rectified by the diode, which is biased

through an external resistor.

24

26

28

PA_VG1

PA_VG2

DET2_REF

Gate Voltage for the First Power Amplifier. See Figure 86 for the

recommended external components.

Gate Voltage for the Second Power Amplifier. See Figure 86 for the

recommended external components.

Reference Voltage for the PA Power Detector. DET2_REF is the dc bias of the

diode biased through an external resistor used for the temperature

compensation of DET2_OUT.

29

DET2_OUT

Detector Voltage for the VGA Power Detector. DET2_OUT is the dc voltage

representing the RF output power rectified by the diode, which is biased

through an external resistor.

35

37

PA_VD2

PA_VD1

Drain Voltage for the Second Power Amplifier. See Figure 86 for the

recommended external components.

Drain Voltage for the First Power Amplifier. See Figure 86 for the

recommended external components.

40

42

LOIN

VG_MULT

LO Input. This pin is dc-coupled and matched to 50 Ω.

Gate Voltage for the LO Multiplier. See Figure 86 for the recommended

external components.

44

VD_MULT

VG_AMP

VD_AMP

VG_MIXER

RFOUT

Drain Voltage for the LO Multiplier. See Figure 86 for the recommended

external components.

Gate Voltage for the LO Amplifier. See Figure 86 for the recommended

external components.

Drain Voltage for the LO Amplifier. See Figure 86 for the recommended

external components.

Gate Voltage for the Field Effect Transistor (FET) Mixer. See Figure 86 for the

recommended external components.

46

48

49

PORT 1

WR-12 Waveguide Port. This port is ac-coupled and matched to the waveguide

output impedance.

EPAD

Exposed Pads. The exposed ground pads must be connected to RF and dc

ground.

Rev. A | Page 7 of 29

ADMV7310

Data Sheet

INTERFACE SCHEMATICS

DET1_REF

DET2_REF

DET1_OUT

DET2_OUT

GND

Figure 3. GND Interface Schematic

Figure 9. DET1_REF, DET2_REF, DET1_OUT, and DET2_OUT Interface

Schematic

IF_IP, IF_IN

IF_QN, IF_QP

VG_MIXER

PA_VG1,

PA_VG2

Figure 4. IF_IP, IF_IN, IF_QN, IF_QP, and VG_MIXER Interface Schematic

Figure 10. PA_VG1, PA_VG2 Interface Schematic

PA_VD1

PA_VD2

VGA_VG12

VGA_VG345

VGA_VG6

Figure 5. VGA_VG12, VGA_VG345, and VGA_VG6 Interface Schematic

Figure 11. PA_VD1, PA_VD2 Interface Schematic

VGA_VD12

VGA_VD345

VGA_VD6

LOIN

Figure 6. VGA_VD12, VGA_VD345, and VGA_VD6 Interface Schematic

Figure 12. LOIN Interface Schematic

VD_AMP,

VD_MULT

VG_AMP,

VG_MULT

ENV_DET

Figure 7. ENV_DET Interface Schematic

Figure 13. VD_AMP, VD_MULT, VG_AMP, and VG_MULT Interface

Schematic

VGA_CTL12

RFOUT

Figure 8. VGA_CTL12 Interface Schematic

Figure 14. RFOUT Interface Schematic

Rev. A | Page 8 of 29

Data Sheet

ADMV7310

TYPICAL PERFORMANCE CHARACTERISTICS

T_A= 25°C, IF = 1 GHz, IF input power = −4 dBm combined, LO power = +4 dBm, gain adjusted per Applications Information section,

and lower sideband selected, unless otherwise noted.

44

42

40

38

36

34

32

30

28

26

24

44

42

40

38

36

34

32

30

28

26

24

0dBm

2dBm

4dBm

6dBm

8dBm

+85°C

+25°C

–40°C

71.0 71.5 72.0 72.5 73.0 73.5 74.0 74.5 75.0 75.5 76.0

RF FREQUENCY (GHz)

Figure 15. Maximum Conversion Gain vs. RF Frequency over Temperature,

IF Input Power = −20 dBm

Figure 18. Maximum Conversion Gain vs. RF Frequency over LO Power,

IF Input Power = −20 dBm

40

38

36

34

32

30

28

40

38

36

34

32

30

28

2dBm

26

4dBm

6dBm

8dBm

+85°C

+25°C

–40°C

24

22

20

24

22

20

71.0 71.5 72.0 72.5 73.0 73.5 74.0 74.5 75.0 75.5 76.0

RF FREQUENCY (GHz)

Figure 16. Output IP3 vs. RF Frequency over Temperature, Gain = 23.5 dB

Figure 19. Output IP3 vs. RF Frequency over LO Power, Gain = 23.5 dB

40

35

30

25

20

40

35

30

25

20

15

10

2dBm

4dBm

6dBm

8dBm

+85°C

+25°C

–40°C

15

10

71.0 71.5 72.0 72.5 73.0 73.5 74.0 74.5 75.0 75.5 76.0

RF FREQUENCY (GHz)

Figure 17. Sideband Rejection vs. RF Frequency over Temperature,

Gain = 23.5 dB

Figure 20. Sideband Rejection vs. RF Frequency over LO Power,

Gain = 23.5 dB

Rev. A | Page 9 of 29

ADMV7310

Data Sheet

32

28

24

20

16

12

8

32

28

24

20

16

12

8

2dBm

4dBm

6dBm

8dBm

+85°C

+25°C

–40°C

4

0

71.0 71.5 72.0 72.5 73.0 73.5 74.0 74.5 75.0 75.5 76.0

RF FREQUENCY (GHz)

Figure 24. 6× LO Rejection vs. RF Frequency over LO Power,

Gain = 23.5 dB

Figure 21. 6× LO Rejection vs. RF Frequency over Temperature,

Gain = 23.5 dB

36

30

29

28

27

26

25

24

34

32

30

28

26

24

22

20

18

16

23.5dB

19.5dB

10.5dB

3.5dB

23

+85°C

+25°C

–40°C

22

21

20

71.0 71.5 72.0 72.5 73.0 73.5 74.0 74.5 75.0 75.5 76.0

RF FREQUENCY (GHz)

Figure 25. Output IP3 vs. RF Frequency at Various Gains

Figure 22. Output P1dB vs. RF Frequency over Temperature,

Gain = 23.5 dB

40

30

29

28

27

26

25

24

23

22

21

20

35

30

25

20

15

10

23.5dB

19.5dB

10.5dB

3.5dB

+85°C

+25°C

–40°C

71.0 71.5 72.0 72.5 73.0 73.5 74.0 74.5 75.0 75.5 76.0

RF FREQUENCY (GHz)

Figure 23. P_SATvs. RF Frequency over Temperature, Gain = 23.5 dB

Figure 26. Sideband Rejection vs. RF Frequency at Various Gains

Rev. A | Page 10 of 29

Data Sheet

ADMV7310

40

35

30

25

20

15

10

5

32

28

24

20

16

12

8

MAXIMUM GAIN

VGA_CTL12 = –1V, VGA_VD345 + VGA_VD6 = 30mA

VGA_CTL12 = –1V, VGA_VD345 + VGA_VD6 = 30mA,

PA_VD1 = 80mA, PA_VD2 = 80mA

23.5dB

19.5dB

10.5dB

3.5dB

0

–5

–10

–15

–20

VGA_CTL12 = –1V

VGA_CTL12 = –1V, VGA_VD345 + VGA_VD6 = 30mA,

PA_VD1 = 80mA

4

0

71.0 71.5 72.0 72.5 73.0 73.5 74.0 74.5 75.0 75.5 76.0

RF FREQUENCY (GHz)

Figure 30. Conversion Gain vs. RF Frequency at Various Gain Tuning Modes

Figure 27. 6× LO to RF Rejection vs. RF Frequency at Various Gains

30

28

26

24

22

40

38

36

34

32

30

20

18

16

14

12

10

23.5dB

19.5dB

10.5dB

3.5dB

28

71.0GHz

26

73.5GHz

76.0GHz

24

22

20

71.0 71.5 72.0 72.5 73.0 73.5 74.0 74.5 75.0 75.5 76.0

–5.0

–4.5

–4.0

–3.5

–3.0

–2.5

–2.0

–1.5

–1.0

RF FREQUENCY (GHz)

VGA CONTROL VOLTAGE (V)

Figure 31. Conversion Gain vs. VGA Control Voltage at Various RF

Frequencies

Figure 28. Output P1dB vs. RF Frequency at Various Gains

10

30

28

26

24

22

20

18

16

14

12

10

71.0GHz

8

73.5GHz

76.0GHz

6

4

2

0

23.5dB

19.5dB

10.5dB

3.5dB

–2

–4

500

550

600

650

700

750

800

71.0 71.5 72.0 72.5 73.0 73.5 74.0 74.5 75.0 75.5 76.0

PA CURRENT (mA)

RF FREQUENCY (GHz)

Figure 32. Conversion Gain vs. PA Current at Various RF Frequencies,

VGA_CTL12 = −1 V, VGA_VD12 = 75 mA, VGA_VD345 = 75 mA, VGA_VD6 =

75 mA

Figure 29. P_SATvs. RF Frequency at Various Gains

Rev. A | Page 11 of 29

ADMV7310

Data Sheet

30

25

20

15

10

5

850

800

750

700

650

600

550

500

450

71.0GHz

73.5GHz

76.0GHz

71GHz

73.5GHz

76GHz

0

70

90

110

130

150

170

190

210

230

250

–0.80 –0.75 –0.70 –0.65 –0.60 –0.55 –0.50 –0.45 –0.40

VGA DRAIN CURRENT (mA)

VGA_VG345 + VGA_VG6 VOLTAGE (V)

Figure 33. Conversion Gain vs. VGA Current at Various RF Frequencies,

VGA_CTL12 = −1 V

Figure 35. PA Drain Current vs. VGA_VG345 + VGA_VG6 Voltage at Various

Frequencies

250

71.0GHz

73.5GHz

76.0GHz

230

210

190

170

150

130

110

90

70

50

–0.80 –0.75 –0.70 –0.65 –0.60 –0.55 –0.50 –0.45 –0.40

VGA_VG345 + VGA_VG6 VOLTAGE (V)

Figure 34. VGA Drain Current vs. VGA_VG345 + VGA_VG6 Voltage at Various

Frequencies

Rev. A | Page 12 of 29

Data Sheet

ADMV7310

T_A= 25°C, IF = 0.1 GHz, IF input power = −4 dBm combined, LO power = 4 dBm, gain adjusted per Applications Information section,

and lower sideband selected, unless otherwise noted.

44

42

40

38

36

34

32

30

28

26

24

40

35

30

25

20

15

10

5

+85°C

+25°C

–40°C

+85°C

+25°C

–40°C

0

71.0 71.5 72.0 72.5 73.0 73.5 74.0 74.5 75.0 75.5 76.0

RF FREQUENCY (GHz)

Figure 39. 6× LO Rejection vs. RF Frequency over Temperature,

Gain = 23.5 dB

Figure 36. Maximum Conversion Gain vs. RF Frequency over Temperature, IF

Input Power = −20 dBm

30

29

28

27

26

25

24

40

38

36

34

32

30

28

23

26

+85°C

22

21

20

+25°C

–40°C

24

22

20

+25°C

–40°C

71.0 71.5 72.0 72.5 73.0 73.5 74.0 74.5 75.0 75.5 76.0

RF FREQUENCY (GHz)

Figure 37. Output IP3 vs. RF Frequency over Temperature, Gain = 23.5 dB

Figure 40. Output P1dB vs. RF Frequency over Temperature,

Gain = 23.5 dB

40

35

30

25

20

15

30

29

28

27

26

25

24

23

22

21

20

10

5

+85°C

+25°C

–40°C

+85°C

+25°C

–40°C

0

71.0 71.5 72.0 72.5 73.0 73.5 74.0 74.5 75.0 75.5 76.0

RF FREQUENCY (GHz)

Figure 38. Sideband Rejection vs. RF Frequency over Temperature,

Gain = 23.5 dB

Figure 41. P_SATvs. RF Frequency over Temperature, Gain = 23.5 dB

Rev. A | Page 13 of 29

ADMV7310

Data Sheet

36

34

32

30

28

26

24

22

20

18

16

30

28

26

24

22

20

18

16

14

12

10

23.5dB

19.5dB

10.5dB

3.5dB

23.5dB

19.5dB

10.5dB

3.5dB

71.0 71.5 72.0 72.5 73.0 73.5 74.0 74.5 75.0 75.5 76.0

RF FREQUENCY (GHz)

Figure 42. Output IP3 vs. RF Frequency at Various Gains

Figure 45. Output P1dB vs. RF Frequency at Various Gains

40

30

28

26

24

22

20

18

16

14

12

10

35

30

25

20

15

10

23.5dB

19.5dB

10.5dB

3.5dB

23.5dB

19.5dB

10.5dB

3.5dB

71.0 71.5 72.0 72.5 73.0 73.5 74.0 74.5 75.0 75.5 76.0

RF FREQUENCY (GHz)

Figure 46. P_SATvs. RF Frequency at Various Gains

Figure 43. Sideband Rejection vs. RF Frequency at Various Gains

32

38

24

20

16

12

23.5dB

19.5dB

10.5dB

3.5dB

8

4

0

71.0 71.5 72.0 72.5 73.0 73.5 74.0 74.5 75.0 75.5 76.0

RF FREQUENCY (GHz)

Figure 44. 6× LO to RF Rejection vs. RF Frequency at Various Gains

Rev. A | Page 14 of 29

Data Sheet

ADMV7310

T_A= 25°C, IF = 0.5 GHz, IF input power = −4 dBm combined, LO power = 4 dBm, gain adjusted per Applications Information section,

and lower sideband selected, unless otherwise noted.

44

42

40

38

36

34

32

30

28

26

24

40

35

30

25

20

15

10

5

+85°C

+25°C

–40°C

+85°C

+25°C

–40°C

0

71.0 71.5 72.0 72.5 73.0 73.5 74.0 74.5 75.0 75.5 76.0

RF FREQUENCY (GHz)

Figure 47. Maximum Conversion Gain vs. RF Frequency over Temperature,

IF Input Power = −20 dBm

Figure 50. 6× LO Rejection vs. RF Frequency over Temperature,

Gain = 23.5 dB

40

38

36

34

32

30

28

30

28

26

24

22

20

18

26

16

+85°C

24

22

20

+25°C

–40°C

14

12

10

+25°C

–40°C

71.0 71.5 72.0 72.5 73.0 73.5 74.0 74.5 75.0 75.5 76.0

RF FREQUENCY (GHz)

Figure 48. Output IP3 vs. RF Frequency over Temperature, Gain = 23.5 dB

Figure 51. Output P1dB vs. RF Frequency over Temperature,

Gain = 23.5 dB

42

38

34

30

26

22

30

29

28

27

26

25

24

23

22

21

20

18

14

10

+85°C

+25°C

–40°C

+85°C

+25°C

–40°C

71.0 71.5 72.0 72.5 73.0 73.5 74.0 74.5 75.0 75.5 76.0

RF FREQUENCY (GHz)

Figure 49. Sideband Rejection vs. RF Frequency over Temperature,

Gain = 23.5 dB

Figure 52. P_SATvs. RF Frequency over Temperature, Gain = 23.5 dB

Rev. A | Page 15 of 29

ADMV7310

Data Sheet

36

34

32

30

28

26

24

22

20

18

16

30

28

26

24

22

20

18

16

14

12

10

23.5dB

19.5dB

10.5dB

3.5dB

23.5dB

19.5dB

10.5dB

3.5dB

71.0 71.5 72.0 72.5 73.0 73.5 74.0 74.5 75.0 75.5 76.0

RF FREQUENCY (GHz)

Figure 53. Output IP3 vs. RF Frequency at Various Gains

Figure 56. Output P1dB vs. RF Frequency at Various Gains

42

30

28

26

24

22

20

18

16

14

12

10

38

34

30

26

22

18

14

10

23.5dB

19.5dB

10.5dB

3.5dB

23.5dB

19.5dB

10.5dB

3.5dB

71.0 71.5 72.0 72.5 73.0 73.5 74.0 74.5 75.0 75.5 76.0

RF FREQUENCY (GHz)

Figure 54. Sideband Rejection vs. RF Frequency at Various Gains

Figure 57. P_SATvs. RF Frequency at Various Gains

32

28

24

20

16

12

23.5dB

19.5dB

10.5dB

3.5dB

8

4

0

71.0 71.5 72.0 72.5 73.0 73.5 74.0 74.5 75.0 75.5 76.0

RF FREQUENCY (GHz)

Figure 55. 6× LO to RF Rejection vs. RF Frequency at Various Gains

Rev. A | Page 16 of 29

Data Sheet

ADMV7310

T_A= 25°C, IF = 2 GHz, IF input power = −4 dBm combined, LO power = 4 dBm, gain adjusted per Applications Information section, and

lower sideband selected, unless otherwise noted.

44

42

40

38

36

34

32

30

28

26

24

32

28

24

20

16

12

8

+85°C

+25°C

–40°C

+85°C

+25°C

–40°C

4

0

71.0 71.5 72.0 72.5 73.0 73.5 74.0 74.5 75.0 75.5 76.0

RF FREQUENCY (GHz)

Figure 58. Maximum Conversion Gain vs. RF Frequency over Temperature,

IF Input Power = −20 dBm

Figure 61. 6× LO Rejection vs. RF Frequency over Temperature,

Gain = 23.5 dB

40

38

36

34

32

30

28

30

29

28

27

26

25

24

26

23

+85°C

+25°C

–40°C

+85°C

+25°C

–40°C

24

22

20

22

21

20

71.0 71.5 72.0 72.5 73.0 73.5 74.0 74.5 75.0 75.5 76.0

RF FREQUENCY (GHz)

Figure 59. Output IP3 vs. RF Frequency over Temperature, Gain = 23.5 dB

Figure 62. Output P1dB vs. RF Frequency over Temperature,

Gain = 23.5 dB

40

35

30

25

20

15

30

29

28

27

26

25

24

23

22

21

20

10

5

+85°C

+25°C

–40°C

+85°C

+25°C

–40°C

0

71.0 71.5 72.0 72.5 73.0 73.5 74.0 74.5 75.0 75.5 76.0

RF FREQUENCY (GHz)

Figure 63. P_SATvs. RF Frequency over Temperature, Gain = 23.5 dB

Figure 60. Sideband Rejection vs. RF Frequency over Temperature,

Gain = 23.5 dB

Rev. A | Page 17 of 29

ADMV7310

Data Sheet

36

34

32

30

28

26

24

22

20

18

16

30

28

26

24

22

20

18

16

14

12

10

23.5dB

19.5dB

10.5dB

3.5dB

23.5dB

19.5dB

10.5dB

3.5dB

71.0 71.5 72.0 72.5 73.0 73.5 74.0 74.5 75.0 75.5 76.0

RF FREQUENCY (GHz)

Figure 64. Output IP3 vs. RF Frequency at Various Gains

Figure 67. Output P1dB vs. RF Frequency at Various Gains

42

30

28

26

24

22

20

18

16

14

12

10

38

34

30

26

22

18

14

10

23.5dB

19.5dB

10.5dB

3.5dB

23.5dB

19.5dB

10.5dB

3.5dB

71.0 71.5 72.0 72.5 73.0 73.5 74.0 74.5 75.0 75.5 76.0

RF FREQUENCY (GHz)

Figure 68. P_SATvs. RF Frequency at Various Gains

Figure 65. Sideband Rejection vs. RF Frequency at Various Gains

32

28

24

20

16

12

23.5dB

19.5dB

10.5dB

3.5dB

8

4

0

71.0 71.5 72.0 72.5 73.0 73.5 74.0 74.5 75.0 75.5 76.0

RF FREQUENCY (GHz)

Figure 66. 6× LO to RF Rejection vs. RF Frequency at Various Gains

Rev. A | Page 18 of 29

Data Sheet

ADMV7310

DETECTOR PERFORMANCE

0.40

1

10MHz

0.35

0.30

0.25

0.20

0.15

0.10

0.05

0

100MHz

240MHz

490MHz

740MHz

990MHz

0.1

0.01

0.001

+85°C

+25°C

–40°C

–10

–8

–6

–4

–2

0

2

4

6

–5

0

5

10

15

20

25

TOTAL INPUT POWER (dBm)

OUTPUT POWER (dBm)

Figure 69. Envelope Detector Output Voltage vs. Total Input Power at Various

Input Tone Spacings, RF = 71 GHz

Figure 72. PA Detector Output Voltage (DET2_REF − DET2_OUT) vs. Output

Power over Temperatures, RF = 71 GHz

0.40

1

10MHz

0.35

0.30

0.25

0.20

0.15

0.10

0.05

0

100MHz

240MHz

490MHz

740MHz

990MHz

0.1

0.01

+85°C

+25°C

–40°C

0.001

–10

–8

–6

–4

–2

0

2

4

6

–5

0

5

10

15

20

25

TOTAL INPUT POWER (dBm)

OUTPUT POWER (dBm)

Figure 70. Envelope Detector Output Voltage vs. Total Input Power at Various

Input Tone Spacings, RF = 73.5 GHz

Figure 73. PA Detector Output Voltage (DET2_REF − DET2_OUT) vs. Output

Power over Temperatures, RF = 73.5 GHz

0.35

1

10MHz

100MHz

240MHz

490MHz

740MHz

990MHz

0.30

0.25

0.20

0.15

0.10

0.05

0

0.1

0.01

+85°C

+25°C

–40°C

0.001

–5

–10

–8

–6

–4

–2

0

2

4

6

0

5

10

15

20

25

TOTAL INPUT POWER (dBm)

OUTPUT POWER (dBm)

Figure 71. Envelope Detector Output Voltage vs. Total Input Power at Various

Input Tone Spacings, RF = 76 GHz

Figure 74. PA Detector Output Voltage (DET2_REF − DET2_OUT) vs. Output

Power over Temperatures, RF = 76 GHz

Rev. A | Page 19 of 29

ADMV7310

Data Sheet

1000

100

10

1000

+85°C

+25°C

–40°C

+85°C

+25°C

–40°C

100

10

1

0.1

–5

0

5

10

15

20

25

–5

0

5

10

15

20

25

OUTPUT POWER (dBm)

Figure 75. PA Detector Sensitivity vs. Output Power over Temperature,

RF = 71 GHz

Figure 77. PA Detector Sensitivity vs. Output Power over Temperature,

RF = 76 GHz

1000

+85°C

+25°C

–40°C

100

10

1

0.1

-5

0

5

10

15

20

25

OUTPUT POWER (dBm)

Figure 76. PA Detector Sensitivity vs. Output Power over Temperature,

RF = 73.5 GHz

Rev. A | Page 20 of 29

Data Sheet

ADMV7310

RETURN LOSS PERFORMANCE

0

–2

+85°C

+25°C

–40°C

+25°C

–40°C

–2

–4

–6

–4

–6

–8

–10

–12

–14

–16

–18

–20

–10

–12

–14

–16

–18

–20

0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

11.8

12.0

12.2

12.4

12.6

12.8

LO FREQUENCY (GHz)

IF FREQUENCY (GHz)

Figure 80. IF Return Loss vs. IF Frequency over Temperature

Figure 78. LO Return Loss vs. LO Frequency over Temperature

0

+85°C

+25°C

–40°C

–2

–4

–6

–8

–10

–12

–14

–16

–18

–20

71.0 71.5 72.0 72.5 73.0 73.5 74.0 74.5 75.0 75.5 76.0

RF FREQUENCY (GHz)

Figure 79. RF Return Loss vs. RF Frequency over Temperature

Rev. A | Page 21 of 29

ADMV7310

Data Sheet

SPURIOUS PERFORMANCE

T_A= 25°C, IF = 1 GHz, IF input power = −4 dBm, and LO power = 4 dBm, unless otherwise noted. Mixer spurious products are measured

in dBc from the RF output power for 60 GHz to 90 GHz due to the waveguide bandwidth. Spur values are (M × IF) + (N × LO). N/A means not

applicable.

M × N Spurious Outputs, RF = 71 GHz, LO = 12 GHz

N × LO

5

6

7

N/A

−79

−72

−47

−41

0

−73

−72

−71

−68

−67

−71

−72

−68

−69

−66

−67

−5

−4

−3

−2

−1

0

N/A

−73

<−80

−18

−23

−49

−62

−78

−77

M × IF

+1

+2

+3

+4

+5

M × N Spurious Outputs, RF = 73.5 GHz, LO = 12.417 GHz

N × LO

5

6

7

N/A

<−80

−79

−56

−46

0

−72

−71

−70

−71

−69

−68

−66

−68

N/A

−5

−4

−3

−2

−1

0

N/A

<−80

−75

−74

−20

−27

−58

−74

−73

M × IF

<−80

+1

+2

+3

+4

+5

M × N Spurious Outputs, RF = 76 GHz, LO = 12.833 GHz

N × LO

5

6

7

N/A

<−80

−69

−56

−40

0

−71

−69

−67

−65

N/A

−5

−4

−3

−2

−1

0

<−80

−73

−68

−13

−26

−59

−73

−71

−70

M × IF

−80

+1

+2

+3

+4

+5

<−80

Rev. A | Page 22 of 29

Data Sheet

ADMV7310

THEORY OF OPERATION

The ADMV7310 is a fully integrated SiP, I/Q upconverter that is

made up of three functional blocks: a mixer and LO path, an

envelope detector, a VGA, and a power detector, and a power

amplifier and power detector.

The preamp is followed by the first voltage variable attenuator in

the signal path. Then, a second stage amplifier provides additional

gain and isolation before driving the second variable attenuator

block. Three cascaded gain stages follow the second variable

attenuator.

MIXER AND LO PATH

At the output of the second stage, another coupler taps off a

small portion of the output signal. The coupled signal is

presented to an on-chip diode detector for external monitoring

of the output power. A matched reference diode, Detector 1

(DET1), is included to help correct for detector temperature

dependencies. A typical application circuit for the power

detector is shown in Figure 83.

The first functional block is a gallium arsenide (GaAs) I/Q

upconverter driven by a 6× LO multiplier. The 6× multiplier

allows the use of a lower frequency range LO input signal between

11.8 GHz and 12.7 GHz. The 6× multiplier is implemented using

a cascade of 3× and 2× multipliers. LO buffer amplifiers are

included on chip to allow a typical LO drive level of 4 dBm for

typical performance. The LO path feeds a quadrature splitter

followed by on-chip baluns that drive the I and Q mixer cores.

The mixer cores comprise of singly balanced passive mixers.

The RF outputs of the I and Q mixers are then summed through

an on-chip Wilkinson power combiner, which is then fed into

the second functional block.

See the Applications Information section for further details on

biasing the different blocks. The output of the VGA then feeds

into the third functional block of the ADMV7310.

POWER AMPLIFIER AND POWER DETECTOR

The third block is a power amplifier that uses four cascaded

gain stages to form the amplifier (see Figure 82). At the output

of the last stage, a coupler taps off a small portion of the output

signal. The coupled signal is presented to an on-chip diode

detector for external monitoring of the output power. A matched

reference diode, Detector 2 (DET2), is included to help correct

for detector temperature dependencies.

ENVELOPE DETECTOR, VGA, AND POWER

DETECTOR

The second functional block is a VGA (see Figure 81). The

VGA utilizes multiple gain stages and staggered voltage variable

attenuation stages to form a low noise, high linearity variable

gain amplifier. The first stage of the VGA is a low noise preamp.

A portion of the signal is coupled away and further amplified

before driving an on-chip envelope detector. The envelope

detector provides an output that is proportional to the peak

envelope power of the incoming signal.

INPUT

OUTPUT

ENVELOPE

DETECTOR

DET1_REF DET1_OUT

ENV_DET VGA_CTL12

Figure 81. Variable Gain Amplifier Circuit Architecture

INPUT

OUTPUT

DET2_REF DET2_OUT

Figure 82. Power Amplifier Circuit Architecture

Rev. A | Page 23 of 29

ADMV7310

Data Sheet

DET1_REF DET1_OUT

OR OR

DET2_REF DET2_OUT

A typical application circuit for the power detector is shown in

Figure 83. See the Applications Information section for further

details on biasing the different blocks.

+4V

100kΩ 100kΩ

+4V

10kΩ

V

= DET2_REF – DET2_OUT

OUT

10kΩ

OR

DET1_REF– DET1_OUT

–4V

SUGGESTED INTERFACE CIRCUIT

Figure 83. Typical Application Circuit for Power Detector

Rev. A | Page 24 of 29

Data Sheet

ADMV7310

APPLICATIONS INFORMATION

POWER-UP BIAS SEQUENCE

LO NULLING

The ADMV7310 functional blocks use active multiple amplifier

and multiplier stages that all use depletion mode pseudomorphic

high electron mobility transistors (pHEMTs). To ensure

transistor damage does not occur, use the following power-up

bias sequence and do not apply RF power to the device on the

LO or IF ports before powering up the device:

LO nulling is required to achieve optimal overall RF

performance, especially for LO to RF rejection. This nulling is

achieved by applying dc voltages (V_DC) between −0.2 V and

0.2 V to the IF_IN, IF_IP, IF_QN, and IF_QP ports to suppress

the 6× LO signal at the RFOUT port across the RF frequency

band by approximately 40 dBc. To suppress the 6× LO signal at

the RFOUT port, use the following nulling sequence:

1. Apply −2 V bias to VG_MULT, VG_AMP, VGA_VG12,

VGA_VG345, VGA_VG6, PA_VG1, and PA_VG2.

2. Apply −1 V bias to VG_MIXER.

3. Apply between −5 V (minimum attenuation) and −1 V

(maximum attenuation) bias to VGA_CTL12.

4. Apply −1.5 V bias to VD_MULT.

5. Apply a 4 V bias to VD_AMP, VGA_VD12, VGA_VD345,

VGA_VD6, PA_VD1, PA_VD2, DET1_REF_BIAS,

DET1_OUT_BIAS, DET2_REF_BIAS, and

1. Adjust IF_IN V_DCbetween −0.2 V and +0.2 V. Monitor the

6× LO leakage on the RFOUT port. When the desired or

maximum level of suppression is achieved, proceed to

Step 2.

2. Adjust IF_IP V_DCbetween −0.2 V and +0.2 V. Monitor the

6× LO leakage on the RFOUT port. When the desired or

maximum level of suppression is achieved, proceed to

Step 3.

DET2_OUT_BIAS (see Figure 86).

6. Adjust VG_AMP between −2 V and 0 V to achieve a total

3. Adjust IF_QN V_DCinput between −0.2 V and +0.2 V.

Monitor the 6× LO leakage on the RFOUT port. When the

desired or maximum level of suppression is achieved,

proceed to Step 4.

4. Adjust IF_QP V_DCbetween −0.2 V and +0.2 V. Monitor the

6× LO leakage on the RFOUT port. When the desired or

maximum level of suppression is achieved, proceed to

Step 5.

I

_{VD_AMP}current of 175 mA.

7. Adjust VGA_VG12 between −2 V and 0 V to achieve a

total I_{VGA_VD12}current of 50 mA.

8. Adjust VGA_VG345 and VGA_VG6 between −2 V and 0 V

to achieve a total I_{VGA_VD345}and I_{VGA_VD6}current of 200 mA.

9. Adjust PA_VG1 between −2 V and 0 V to achieve a total

I

_{PA_VD1}current of 400 mA.

10. Adjust PA_VG2 between −2 V and 0 V to achieve a total

_{PA_VD2}current of 400 mA.

5. If the desired level of the 6× LO signal on the RFOUT port

is still not achieved, further tune each dc voltage to the

IF_IN, IF_IP, IF_QN, and IF_QP ports by repeating Step 1

through Step 4. The resolution of the voltage changed on

the dc voltage of the inputs must be in the millivolt.

6. To ensure that the mixer core is not damaged during the

LO nulling, limit each current to IF_IN, IF_IP, IF_QN, and

IF_QP to 3 mA.

7. LO nulling must be conducted with any change in input

LO frequency, temperature change, or when Gain Tuning

Order 1 is conducted. The level of suppression changes as

those conditions vary.

I

11. Apply a LO input signal on the LO port and adjust

VG_MULT between −2 V and 0 V to achieve a total

I

_{VD_MULT}current of 80 mA.

POWER-DOWN BIAS SEQUENCE

To power-down the ADMV7310, take the following steps:

1. Apply a 0 V bias to VD_MULT, VD_AMP, VGA_VD12,

VGA_VD345, VGA_VD6, PA_VD1, PA_VD2,

DET1_REF_BIAS, DET1_OUT_BIAS, DET2_REF_BIAS,

and DET2_OUT_BIAS supply voltage per application

circuit.

2. Apply a 0 V bias to VGA_CTL12.

3. Apply a 0 V bias to VG_MIXER.

4. Apply a 0 V bias to VG_MULT, VG_AMP, VGA_VG12,

VGA_VG345, VGA_VG6, PA_VG1, and PA_VG2.

Rev. A | Page 25 of 29

ADMV7310

Data Sheet

current consumption. The third mechanism is to lower the

_{PA_VD1}current consumption via PA_VG1 from the nominal

PA_VG1 voltage to achieve the nominal I_{PA_VD1}+ I_{PA_VD2}current

GAIN TUNING PROCEDURE

I

The ADMV7310 features three different mechanisms to control

the total gain of the transmitter. The first mechanism is the

variable gain control of the variable gain control amplifier of the

transmitter. The variable gain control is controlled by the

VGA_CTL12 pin. The voltage control range to achieve maximum

and minimum gain from the VGA is −5 V to −1 V. The second

mechanism for further gain control is to lower the I_{VGA_VD345}and

consumption.

See Table 5 for additional details as to which gain control

mechanism to use per the desired gain control range required.

The settings detailed in Table 5 are guidelines for a gain control

approach and may need adjustment depending on application

requirements over temperature and frequency.

I

_{VGA_VD6}current consumption via the VGA_VG345 and

VGA_VG6 pins from the nominal VGA_VG345 + VGA_VG6

voltage to achieve the nominal I_{VGA_VD12}+ I_{VGA_VD345}+ I_{VGA_VD6}

Follow the gain tuning order to control the gain to achieve the

correct gain level for optimal performance.

Table 5. Recommended Gain Settings

Gain

Tuning

Order

Gain

Reduction

Range (dB)

Recommended

Gain Tuning

Voltage Range (V)

Gain Tuning

Description of Gain Tuning Procedure

1

0 to 10

VGA_CTL12

−5 to −1

To achieve maximum gain, set VGA_CTL12 to −5 V. To achieve a gain

reduction between 0 dB and 10 dB, adjust VGA_CTL12 between −5 V

and −1 V (−1 V is the typical minimum gain for the VGA). For both of

these conditions, follow the bias procedure in the Theory of Operation

section to bias the ADMV7310 to the normal operating currents.

2

10 to 25

VGA_VG345 + −2 to 0

VGA_VG6

To achieve greater than 10 dB to 25 dB gain reduction, adjust VGA_CTL12

between −5 V and −1 V. If further gain reduction is required to achieve

25 dB gain reduction after conducting Gain Tuning Order 1, lower

I_{VGA_VD345}+ I_{VGA_VD6}by adjusting VGA_VG345 + VGA_VG6 between −2 V

and 0 V to achieve the correct gain level. The total current consumption of

I

_{VGA_VD345}+ I_{VGA_VD6}while adjusting the VGA_VG345 + VGA_VG6 to drop

to 25 mA (nominal I_{VGA_VD345}+ I_{VGA_VD6}is 200 mA).

3

25 to 40

PA_VG1

−2 to 0

To achieve greater than 25 dB to 40 dB gain reduction, adjust VGA_CTL12

to −1 V and adjust the total current consumption of I_{VGA_VD345}+ I_{VGA_VD6}

between 200 mA and 25 mA per Gain Tuning Order 2. If further gain

reduction is needed to achieve 40 dB gain reduction after conducting

Gain Tuning Order 2, lower I_{PA_VD1}by adjusting PA_VG1 between −2 V

and 0 V to achieve the correct gain level. The total current consumption

of I_{PA_VD1}while adjusting PA_VG1 must not drop below 80 mA (nominal

I

_{PA_VD1}is 400 mA).

Rev. A | Page 26 of 29

Data Sheet

ADMV7310

Figure 84 illustrates the recommended mechanical layout on the

interface plate used to interface to the WR-12 waveguide

opening of the ADMV7310. The recommended PCB land

pattern footprint is shown in Figure 85.

LAYOUT

Solder the exposed pad on the underside of the ADMV7310 to a

low thermal and electrical impedance ground plane. This pad

is typically soldered to an exposed opening in the solder mask.

Connect these ground vias to all other ground layers to

maximize heat dissipation from the device package.

(Ø0.563)

4× R0.016

2× Ø0.0595±0.0005 THRU

MARKED A

2× Ø0.067±0.003 THRU

MARKED B

0.981

2× 0.899

A

B

A

NOTE: 7

PRESS FIT ALIGNMENT PINS (QTY 2)

TO HEIGHT SHOWN THIS SIDE

0.761

0.639

2× 0.501

0.419

B

0.061 (1.55)

0.122 (3.10)

0.000

DETAIL A

PART LIST

ITEM QTY VENDOR

STOCK NUMBER

VARIOUS

DESCRIPTION

PIN, ALIGNMENT, FLANGE, 0.0615 DIA

1

2

VARIOUS

NOTES:

1. REMOVE BURRS AND BREAK SHARP EDGES.

2. ALL INTERNAL RADII ARE 0.090 UNLESS OTHERWISE NOTED.

3. SURFACE FINISH 32 RMS UNLESS OTHERWISE SPECIFIED.

4. DIMENSIONS APPLY AFTER PLATING.

5. MATERIAL: ALUMINUM 6061-T6 PER QQ-A-250/11.

6. FINISH: NONE.

7. INSTALL DOWEL PINS.

8. USE ELECTRONIC DATA FOR ALL GEOMETRY THAT IS NOT DIMENSIONED.

Figure 84. Recommended Standard WR-12 Footprint

PCB SOLDERMASK KEEPOUT

0.124

(3.15)

0.012

(0.30)

0.041

(1.05)

PCB METAL FOOTPRINT

0.546

(13.88)

0.225

(5.73)

0.016

(0.40)

0.079

(2.00)

0.185

(4.70)

0.031

(0.80)

0.124

(3.15)

0.280

(7.10)

0.061

(1.55)

0.102

(2.60)

0.186

(4.73)

0.085

(2.15)

0.559

(14.20)

0.372

(9.45)

0.110

(2.80)

0.173

(4.40)

0.022

(0.55)

SEE

DETAIL A

PCB SOLDER PASTE MASK

0.061

(1.55)

0.014

(0.36)

0.120

(3.05)

R0.010

(R.25)

0.208

(5.29)

0.037

(0.95)

0.319

(8.10)

0.122

(3.10)

0.185

(4.70)

0.132

(3.35)

DETAIL A

WAVEGUIDE

0.124

(3.14)

0.044

(1.11)

NOTES

1. WAVEGUIDE OPENING TO BE FULLY EDGE PLATED.

2. FILL AREA UNDER DEVICE WITH AN ARRAY OF

0.049

(1.24)

0.014

(0.35)

0.010 INCH VIAS (FILLED, RECOMMENDED 0.025 INCH PITCH).

Figure 85. PCB Land Pattern Footprint

Rev. A | Page 27 of 29

ADMV7310

Data Sheet

TYPICAL APPLICATION CIRCUIT

Figure 86 shows the typical application circuit.

4.7µF 4.7µF 4.7µF 4.7µF 4.7µF

4.7µF 4.7µF

+

LOIN

180°

COUPLER

IN

90°

COUPLER

IFI_IN

IFIN

1

2

IF_IP

IF_IN

180°

COUPLER

IFQ_IN

3

IF_QN

IF_QP

IN

4

5

RFOUT

6

ADMV7310

VGA_VG12

TOP VIEW

7

(Not to Scale)

8

VGA_VD12

9

ENV_DET

10

11

12

VGA_CTL12

+

4.7µF

1MF

150Ω

3.48kΩ

+

4.7µF

+

4.7µF

4.7µF 4.7µF

4.7µF

Figure 86. Typical Application Circuit

Rev. A | Page 28 of 29

Data Sheet

ADMV7310

OUTLINE DIMENSIONS

16.15

16.00

15.85

2.75

BSC

9.74

PIN 1

0.38

3.15

INDICATOR

15.24

BSC

9.00

0.40 × 0.45°

32

50

1

2.80

BSC

1.05

EXPOSED

PAD

14.15

14.00

13.85

EXPOSED

PAD

EXPOSED

PAD

EXPOSED

PAD

PORT 1

(See Detail A)

8.40

EXPOSED

PAD

EXPOSED

PAD

EXPOSED

PAD

13.24

BSC

0.80

BSC

EXPOSED

PAD

EXPOSED

PAD

EXPOSED

PAD

VENT HOLE

Ø 0.125

7.00

BSC

EXPOSED

PAD

12

13

1.80

31

1.70

1.55

BOTTOM VIEW

0.36

TOP VIEW

0.25 BSC

0.48

0.42

0.36

1.93 BSC

0.30

0.24

2.93

MAX

SIDE VIEW

2.54 REF

3.15 BSC

0.46 BSC

FOR PROPER CONNECTION OF

THE EXPOSED PADS, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

1.55 BSC

0.320

0.290

0.260

SEATING

PLANE

SECTION OF THIS DATA SHEET.

4.70

BSC

3.10

BSC

DETAIL A

Figure 87. 50-Terminal Chip Array Small Outline No Lead Cavity [LGA_CAV]

16.00 mm × 14.00 mm Body and 2.93 mm Package Height

(CE-50-2)

Dimensions shown in millimeters

ORDERING GUIDE

Model¹

Temperature Range

Package Description

Package Option

ADMV7310BCEZ

ADMV7310-EVALZ

−40°C to +85°C

50-Terminal Chip Array Small Outline No Lead Cavity [LGA_CAV]

Evaluation Board

CE-50-2

¹Z = RoHS Compliant Part.

registered trademarks are the property of their respective owners.

D20977-0-10/19(A)

Rev. A | Page 29 of 29


型号：	ADMV7310BCEZ
厂家：	ADI
描述：	E-Band Upconverter SiP, 71 GHz to 76 GHz
文件：	总29页 (文件大小：437K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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