ADMV7420-EVALZ [ADI]
E-Band Low Noise Downconverter SiP, 81 GHz to 86 GHz;
| 型号： | ADMV7420-EVALZ |
| 厂家： | 
ADI |
| 描述： | E-Band Low Noise Downconverter SiP, 81 GHz to 86 GHz |
| 文件： | 总25页 (文件大小：800K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
E-Band Low Noise Downconverter SiP,
81 GHz to 86 GHz
Data Sheet
ADMV7420
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Conversion gain: 10 dB typical
Image rejection: 30 dBc typical
Noise figure: 5 dB typical
Input IP3: 1 dBm typical
Input IP2: 26 dBm typical
Input P1dB: −5 dBm typical
GND
IF_IP
IF_IN
IF_QN
IF_QP
GND
1
2
3
4
5
6
7
8
9
6× LO leakage at RFIN: <−55 dBm typical
I/Q amplitude imbalance: 0.5 dB typical
I/Q phase imbalance: 5° typical
Fully integrated, surface-mount, 34-terminal, 11 mm ×
13 mm LGA_CAV package
x6
APPLICATIONS
PORT 1
RFIN
E-band communication systems
High capacity wireless backhauls
Test and measurement
GND
GND
Aerospace and defense
GND
ADMV7420
GND 10
Figure 1.
GENERAL DESCRIPTION
The ADMV7420 is a fully integrated system in package (SiP) in
phase/quadrature (I/Q) downconverter that operates between
an intermediate frequency (IF) output range of dc and 2 GHz
and a radio frequency (RF) input range of 81 GHz and 86 GHz.
The device provides a small signal conversion gain of 10 dB
with 30 dBc of image rejection. The ADMV7420 uses a low
noise amplifier followed by an image rejection mixer that is
driven by a 6× local oscillator (LO) multiplier. Differential I and
Q mixer outputs are provided for direct conversion applications.
Alternatively, the outputs can be combined using an external
90° hybrid and two external 180° hybrids for single-ended
applications.
The ADMV7420 comes in a fully integrated, surface-mount,
34-terminal, 11 mm × 13 mm, chip array small outline no lead
cavity (LGA_CAV) package. The ADMV7420 operates over the
−40°C to +85°C case temperature range.
Rev. A
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Technical Support
©2019 Analog Devices, Inc. All rights reserved.
www.analog.com
Data Sheet
ADMV7420
TABLE OF CONTENTS
Features .............................................................................................. 1
Return Loss and 6× LO Leakage .............................................. 19
Spurious Performance ............................................................... 20
Theory of Operation ...................................................................... 21
Applications Information.............................................................. 22
Power-Up Bias Sequence........................................................... 22
Power-Down Sequence.............................................................. 22
Layout .......................................................................................... 22
Typical Application Circuit........................................................... 24
Outline Dimensions....................................................................... 25
Ordering Guide .......................................................................... 25
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 4
Thermal Resistance ...................................................................... 4
ESD Caution.................................................................................. 4
Pin Configuration and Function Descriptions............................. 5
Interface Schematics..................................................................... 6
Typical Performance Characteristics ............................................. 7
REVISION HISTORY
10/2019—Revision A: Initial Version
Rev. A | Page 2 of 25
Data Sheet
ADMV7420
SPECIFICATIONS
TA = −40°C to +85°C, IF = 1 GHz, LO power = 4 dBm, VD_AMP = +4 V, VG_MIXER = −1 V, VD_MULT = +1.5 V, VD12_LNA = +2 V,
and VD34_LNA = +4 V, unless otherwise noted. Measurements performed as a downconverter with upper sideband selected and an
external 90° hybrid followed by two external 180° hybrids at the IF ports, unless otherwise noted.
Table 1.
Parameter
Symbol
Min
Typ
Max
Unit
OPERATING CONDITIONS
Frequency Range
RF
LO
IF Output
81
86
14.6
2
GHz
GHz
GHz
dBm
13.2
DC
0
LO Drive Level Range
PERFORMANCE
4
8
Conversion Gain
Gain Flatness
6
10
2
17
dB
dB
Image Rejection
15
30
−5
1
26
−55
0.5
5
dBc
Input Power for 1 dB Compression (Input P1dB)
Input Third-Order Intercept (Input IP3)
Input Second-Order Intercept (Input IP2)
6× LO Leakage at the RF Input Port (RFIN)
I/Q Amplitude Imbalance
I/Q Phase Imbalance
Noise Figure
−13
−6
14
dBm
dBm
dBm
dBm
dB
−50
3
10
8
−10
Degrees
dB
5
Return Loss
RFIN
10
10
10
dB
dB
dB
Ω
LO Input Port (LOIN)
Baseband Output Port1
DIFFERENTIAL BASEBAND OUTPUT PORT IMPEDANCE
LOIN PORT IMPEDANCE
POWER SUPPLY
100
50
Ω
DC Power Dissipation
Low Noise Amplifier Gate Voltage
Low Noise Amplifier Drain Voltage
First and Second Stage
Third and Fourth Stage
Multiplier Drain Voltage
Multiplier Gate Voltage
Mixer Gate Voltage
1
1.25
0
W
V
VG12_LNA, VG34_LNA
−2
VD12_LNA
VD34_LNA
VD_MULT
VG_MULT
VG_MIX
1.9
3.8
1.42
−2
2
4
2.1
4.2
1.58
0
V
V
1.5
V
V
V
−2
0
Low Noise Amplifier Supply Current
Amplifier Drain Current
Multiplier Drain Current
IVD12_LNA and IVD34_LNA
IVD_AMP
IVD_MULT
66
175
80
mA
mA
mA
1 Measurements taken without external hybrids at the IF ports.
Rev. A | Page 3 of 25
Data Sheet
ADMV7420
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 2.
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Careful attention to
PCB thermal design is required.
Parameter
Rating
VD_AMP
VD_MULT
4.5 V
3 V
VD12_LNA and VD34_LNA
VG_AMP
VG_MULT
VG12_LNA and VG34_LNA
LO Drive
Baseband Input (IF_IP, IF_IN, IF_QP, and IF_QN)
IF Source and Sink Current
Nominal Junction Temperature (TA = 85°C)
4.5 V
θ
JC is the junction to case (or die to package) thermal resistance.
−3 V to +0.2 V
−3 V to +0.2 V
−3 V to +0.2 V
10 dBm
4 dBm
Table 3. Thermal Resistance1
Package Type
θJC
Unit
CE-34-2
52.4
°C/W
1 Thermal impedance simulated values are based on a JEDEC 2S2P test board
with 11 mm × 13 mm thermal vias. Refer to JEDEC standard JESD51-2 for
additional information.
3 mA
137°C
Maximum Junction Temperature (to Maintain 175°C
3 Million Hours Mean Time to Failure
(MTTF))
ESD CAUTION
Operating Temperature Range
Storage Temperature Range
Maximum Peak Reflow Temperature for
Moisture Sensitivity Level 3 (MSL3)
−40°C to +85°C
−55°C to +150°C
260°C
Thermal Humidity Bias (THB)
Thermal Humidity Storage (THS)
Electrostatic Discharge (ESD) Sensitivity
Human Body Model (HBM)
Field Induced Charged Device Model
(FICDM)
JESD22-A1011, 2, 3
JESD22-A1011, 3
300 V
500 V
1 Samples subject to preconditioning (per J-STD-020 Level 3) prior to the start
of the stress test. Level 3 preconditioning consists of the following: bake for
24 hours at 125°C, unbiased soak for 192 hours at 30°C and 60% relative
humidity (RH), and reflow of three passes through an oven with a peak
temperature of 260°C.
2 Results valid for 400 mW of nominal dc power dissipation for all active
devices. Analog Devices, Inc., recommends that users perform their own THB
test for all other bias conditions.
3 Valid for package vent hole solder sealed or unsealed during test.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Rev. A | Page 4 of 25
Data Sheet
ADMV7420
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
34 33 32 31 30 29 28 27 26 25 24 23
1
2
GND
IF_IP
IF_IN
IF_QN
IF_QP
GND
3
ADMV7420
4
TOP VIEW
(TERMINAL SIDE DOWN)
Not to Scale
5
6
PORT 1
RFIN
7
GND
8
GND
9
GND
10
GND
11 12 13 14 15 16 17 18 19 20 21 22
NOTES
1. EXPOSED PADS. THE EXPOSED GROUND PADS
MUST BE CONNECTED TO RF AND DC GROUND.
Figure 2. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
Mnemonic
Description
1, 6 to 12, 14, 16, 17, 19, 21 to 23, 25, 27, 29, 31, 34
GND
Ground Connections. These pins must be connected to RF and
dc ground.
2
IF_IP
Positive IF In Phase Output. This pin is dc-coupled. When
operation to dc is not required, block this pin externally
using a series capacitor with a value chosen to pass the
necessary frequency range. For operation to dc, this pin must
not source or sink more than 3 mA of current or device
malfunction and device failure may result.
3
IF_IN
IF_QN
IF_QP
Negative IF In Phase Output. This pin is dc-coupled. When
operation to dc is not required, block this pin externally
using a series capacitor with a value chosen to pass the
necessary frequency range. For operation to dc, this pin must
not source or sink more than 3 mA of current or device
malfunction and device failure may result.
Negative IF Quadrature Output. This pin is dc-coupled. When
operation to dc is not required, block this pin externally
using a series capacitor with a value chosen to pass the
necessary frequency range. For operation to dc, this pin must
not source or sink more than 3 mA of current or device
malfunction and device failure may result.
Positive IF Quadrature Output. This pin is dc-coupled. When
operation to dc is not required, block this pin externally
using a series capacitor with a value chosen to pass the
necessary frequency range. For operation to dc, this pin must
not source or sink more than 3 mA of current or device
malfunction and device failure may result.
4
5
13
VD34_LNA
Drain Voltage for the Third and Fourth Stage Low Noise
Amplifier. See Figure 75 for the recommended external
components.
Rev. A | Page 5 of 25
Data Sheet
ADMV7420
Pin No.
Mnemonic
Description
15
VG34_LNA
Gate Voltage for the Third and Fourth Stage Low Noise
Amplifier. See Figure 75 for the recommended external
components.
18
20
VD12_LNA
VG12_LNA
Drain Voltage for the First and Second Stage Low Noise
Amplifier. See Figure 75 for the recommended external
components.
Gate Voltage for the First and Second Stage Low Noise
Amplifier. See Figure 75 for the recommended external
components.
24
26
LOIN
VG_MULT
LO Input. This pin is dc-coupled and matched to 50 Ω.
Gate Voltage for the LO Multiplier. See Figure 75 for the
recommended external components.
28
VD_MULT
VG_AMP
VD_AMP
VG_MIXER
RFIN
Drain Voltage for the LO Multiplier. See Figure 75 for the
recommended external components.
Gate Voltage for the LO Amplifier. See Figure 75 for the
recommended external components.
Drain Voltage for the LO Amplifier. See Figure 75 for the
recommended external components.
Gate Voltage for the Field Effect Transistor (FET) Mixer. See
Figure 75 for the recommended external components.
30
32
33
PORT 1
WR-12 Waveguide Port. This port is ac-coupled and matched
to the waveguide input impedance.
EPAD
Exposed Pads. The exposed ground pads must be connected
to RF and dc ground.
INTERFACE SCHEMATICS
GND
VG12_LNA,
VG34_LNA
Figure 3. GND Interface Schematic
Figure 6. VG12_LNA and VG34_LNA Interface Schematic
IF_IP, IF_IN
IF_QN, IF_QP
VD_AMP,
VD_MULT
VG_MIXER
VG_AMP,
VG_MULT
Figure 4. IF_IP, IF_IN, IF_QN, IF_QP, and VG_MIXER Interface Schematic
Figure 7. VG_MULT, VD_MULT, VG_AMP, and VD_AMP Interface
Schematic
VD12_LNA, VD34_LNA
RFIN
Figure 5. VD12_LNA and VD34_LNA Interface Schematic
Figure 8. RFIN Interface Schematic
Rev. A | Page 6 of 25
Data Sheet
ADMV7420
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, IF = 1 GHz, RFIN = −20 dBm combined, LO power = +4 dBm, and upper sideband selected, unless otherwise noted.
18
16
14
12
10
8
18
16
14
12
10
8
0dBm
2dBm
4dBm
6dBm
8dBm
6
6
+85°C
+25°C
–40°C
4
4
2
2
0
0
81.0 81.5 82.0 82.5 83.0 83.5 84.0 84.5 85.0 85.5 86.0
81.0 81.5 82.0 82.5 83.0 83.5 84.0 84.5 85.0 85.5 86.0
RF FREQUENCY (GHz)
RF FREQUENCY (GHz)
Figure 9. Conversion Gain vs. RF Frequency over Temperature
Figure 12. Conversion Gain vs. RF Frequency over LO Power
50
45
40
35
30
25
20
50
45
40
35
30
25
20
15
10
5
0dBm
2dBm
4dBm
6dBm
8dBm
+85°C
15
+25°C
–40°C
10
5
0
0
81.0 81.5 82.0 82.5 83.0 83.5 84.0 84.5 85.0 85.5 86.0
81.0 81.5 82.0 82.5 83.0 83.5 84.0 84.5 85.0 85.5 86.0
RF FREQUENCY (GHz)
RF FREQUENCY (GHz)
Figure 10. Image Rejection vs. RF Frequency over Temperature
Figure 13. Image Rejection vs. RF Frequency over LO Power
10
8
10
8
6
6
4
4
2
2
0
0
–2
–2
–4
–6
–8
–10
0dBm
2dBm
4dBm
6dBm
8dBm
+85°C
–4
+25°C
–40°C
–6
–8
–10
81.0 81.5 82.0 82.5 83.0 83.5 84.0 84.5 85.0 85.5 86.0
81.0 81.5 82.0 82.5 83.0 83.5 84.0 84.5 85.0 85.5 86.0
RF FREQUENCY (GHz)
RF FREQUENCY (GHz)
Figure 11. Input IP3 vs. RF Frequency over Temperature
Figure 14. Input IP3 vs. RF Frequency over LO Power
Rev. A | Page 7 of 25
Data Sheet
ADMV7420
50
45
40
35
30
25
20
50
45
40
35
30
25
20
15
10
5
0dBm
2dBm
4dBm
6dBm
8dBm
+85°C
+25°C
–40°C
15
10
5
0
0
81.0 81.5 82.0 82.5 83.0 83.5 84.0 84.5 85.0 85.5 86.0
81.0 81.5 82.0 82.5 83.0 83.5 84.0 84.5 85.0 85.5 86.0
RF FREQUENCY (GHz)
RF FREQUENCY (GHz)
Figure 15. Input IP2 vs. RF Frequency over Temperature
Figure 18. Input IP2 vs. RF Frequency over LO Power
1.0
1.0
0dBm
2dBm
4dBm
6dBm
8dBm
+85°C
+25°C
–40°C
0.8
0.6
0.8
0.6
0.4
0.4
0.2
0.2
0
0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.2
–0.4
–0.6
–0.8
–1.0
81.0 81.5 82.0 82.5 83.0 83.5 84.0 84.5 85.0 85.5 86.0
81.0 81.5 82.0 82.5 83.0 83.5 84.0 84.5 85.0 85.5 86.0
RF FREQUENCY (GHz)
RF FREQUENCY (GHz)
Figure 16. Amplitude Imbalance vs. RF Frequency over Temperature
Figure 19. Amplitude Imbalance vs. RF Frequency over LO Power
10
8
10
8
6
6
4
4
2
2
0
0
+85°C
+25°C
–40°C
–2
–4
–2
0dBm
–4
–6
2dBm
4dBm
6dBm
8dBm
–6
–8
–8
–10
–10
81.0 81.5 82.0 82.5 83.0 83.5 84.0 84.5 85.0 85.5 86.0
81.0 81.5 82.0 82.5 83.0 83.5 84.0 84.5 85.0 85.5 86.0
RF FREQUENCY (GHz)
RF FREQUENCY (GHz)
Figure 17. Phase Imbalance vs. RF Frequency over Temperature
Figure 20. Phase Imbalance vs. RF Frequency over LO Power
Rev. A | Page 8 of 25
Data Sheet
ADMV7420
10
9
10
9
8
8
6
5
4
3
2
1
0
+85°C
+25°C
–40°C
0dBm
2dBm
4dBm
6dBm
8dBm
8
8
6
5
4
3
2
1
0
81.0 81.5 82.0 82.5 83.0 83.5 84.0 84.5 85.0 85.5 86.0
81.0 81.5 82.0 82.5 83.0 83.5 84.0 84.5 85.0 85.5 86.0
RF FREQUENCY (GHz)
RF FREQUENCY (GHz)
Figure 21. Noise Figure vs. RF Frequency over Temperature
Figure 23. Noise Figure vs. RF Frequency over LO Power
0
+85°C
+25°C
–40°C
–2
–4
–6
–8
–10
–12
–14
–16
–18
–20
81.0 81.5 82.0 82.5 83.0 83.5 84.0 84.5 85.0 85.5 86.0
RF FREQUENCY (GHz)
Figure 22. Input P1dB vs. RF Frequency over Temperature
Rev. A | Page 9 of 25
Data Sheet
ADMV7420
TA = 25°C, IF = 0.1 GHz, RFIN = −20 dBm combined, LO power = +4 dBm, and upper sideband selected, unless otherwise noted.
18
16
14
12
10
8
18
16
14
12
10
8
0dBm
2dBm
4dBm
6dBm
8dBm
6
+85°C
+25°C
–40°C
4
6
2
0
4
81.0 81.5 82.0 82.5 83.0 83.5 84.0 84.5 85.0 85.5 86.0
81.0 81.5 82.0 82.5 83.0 83.5 84.0 84.5 85.0 85.5 86.0
RF FREQUENCY (GHz)
RF FREQUENCY (GHz)
Figure 27. Conversion Gain vs. RF Frequency over LO Power
Figure 24. Conversion Gain vs. RF Frequency over Temperature
50
50
45
40
35
30
25
20
45
40
35
30
25
20
15
10
5
0dBm
2dBm
4dBm
6dBm
8dBm
+85°C
15
+25°C
–40°C
10
5
0
0
81.0 81.5 82.0 82.5 83.0 83.5 84.0 84.5 85.0 85.5 86.0
81.0 81.5 82.0 82.5 83.0 83.5 84.0 84.5 85.0 85.5 86.0
RF FREQUENCY (GHz)
RF FREQUENCY (GHz)
Figure 28. Image Rejection vs. RF Frequency over LO Power
Figure 25. Image Rejection vs. RF Frequency over Temperature
10
10
8
8
6
6
4
4
2
2
0
0
–2
–4
–6
–8
–10
–2
0dBm
2dBm
4dBm
6dBm
8dBm
+85°C
–4
+25°C
–40°C
–6
–8
–10
81.0 81.5 82.0 82.5 83.0 83.5 84.0 84.5 85.0 85.5 86.0
81.0 81.5 82.0 82.5 83.0 83.5 84.0 84.5 85.0 85.5 86.0
RF FREQUENCY (GHz)
RF FREQUENCY (GHz)
Figure 29. Input IP3 vs. RF Frequency over LO Power
Figure 26. Input IP3 vs. RF Frequency over Temperature
Rev. A | Page 10 of 25
Data Sheet
ADMV7420
40
35
30
25
20
15
40
35
30
25
20
15
10
5
0dBm
2dBm
4dBm
6dBm
8dBm
+85°C
+25°C
–40°C
10
5
0
0
81.0 81.5 82.0 82.5 83.0 83.5 84.0 84.5 85.0 85.5 86.0
81.0 81.5 82.0 82.5 83.0 83.5 84.0 84.5 85.0 85.5 86.0
RF FREQUENCY (GHz)
RF FREQUENCY (GHz)
Figure 30. Input IP2 vs. RF Frequency over Temperature
Figure 33. Input IP2 vs. RF Frequency over LO Power
1.0
1.0
0dBm
2dBm
4dBm
6dBm
8dBm
+85°C
+25°C
–40°C
0.8
0.6
0.8
0.6
0.4
0.4
0.2
0.2
0
0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.2
–0.4
–0.6
–0.8
–1.0
81.0 81.5 82.0 82.5 83.0 83.5 84.0 84.5 85.0 85.5 86.0
81.0 81.5 82.0 82.5 83.0 83.5 84.0 84.5 85.0 85.5 86.0
RF FREQUENCY (GHz)
RF FREQUENCY (GHz)
Figure 31. Amplitude Imbalance vs. RF Frequency over Temperature
Figure 34. Amplitude Imbalance vs. RF Frequency over LO Power
10
10
8
+85°C
+25°C
–40°C
8
6
6
4
4
2
2
0
0
0dBm
–2
–4
–6
–8
–10
–2
–4
2dBm
4dBm
6dBm
8dBm
–6
–8
–10
81.0 81.5 82.0 82.5 83.0 83.5 84.0 84.5 85.0 85.5 86.0
81.0 81.5 82.0 82.5 83.0 83.5 84.0 84.5 85.0 85.5 86.0
RF FREQUENCY (GHz)
RF FREQUENCY (GHz)
Figure 32. Phase Imbalance vs. RF Frequency over Temperature
Figure 35. Phase Imbalance vs. RF Frequency over LO Power
Rev. A | Page 11 of 25
Data Sheet
ADMV7420
10
9
10
9
8
8
6
5
4
3
2
1
0
+85°C
+25°C
–40°C
0dBm
2dBm
4dBm
6dBm
8dBm
8
8
6
5
4
3
2
1
0
81.0 81.5 82.0 82.5 83.0 83.5 84.0 84.5 85.0 85.5 86.0
81.0 81.5 82.0 82.5 83.0 83.5 84.0 84.5 85.0 85.5 86.0
RF FREQUENCY (GHz)
RF FREQUENCY (GHz)
Figure 36. Noise Figure vs. RF Frequency over Temperature
Figure 38. Noise Figure vs. RF Frequency over LO Power
0
+85°C
+25°C
–40°C
–2
–4
–6
–8
–10
–12
–14
–16
–18
–20
81.0 81.5 82.0 82.5 83.0 83.5 84.0 84.5 85.0 85.5 86.0
RF FREQUENCY (GHz)
Figure 37. Input P1dB vs. RF Frequency over Temperature
Rev. A | Page 12 of 25
Data Sheet
ADMV7420
TA = 25°C, IF = 0.5 GHz, RFIN = −20 dBm combined, LO power = +4 dBm, and upper sideband selected, unless otherwise noted.
18
16
14
12
10
8
18
16
14
12
10
8
0dBm
2dBm
4dBm
6dBm
8dBm
6
+85°C
+25°C
–40°C
4
6
2
0
4
81.0 81.5 82.0 82.5 83.0 83.5 84.0 84.5 85.0 85.5 86.0
81.0 81.5 82.0 82.5 83.0 83.5 84.0 84.5 85.0 85.5 86.0
RF FREQUENCY (GHz)
RF FREQUENCY (GHz)
Figure 39. Conversion Gain vs. RF Frequency over Temperature
Figure 42. Conversion Gain vs. RF Frequency over LO Power
50
45
40
35
30
25
20
50
45
40
35
30
25
20
15
10
5
0dBm
2dBm
4dBm
6dBm
8dBm
+85°C
15
+25°C
–40°C
10
5
0
0
81.0 81.5 82.0 82.5 83.0 83.5 84.0 84.5 85.0 85.5 86.0
81.0 81.5 82.0 82.5 83.0 83.5 84.0 84.5 85.0 85.5 86.0
RF FREQUENCY (GHz)
RF FREQUENCY (GHz)
Figure 40. Image Rejection vs. RF Frequency over Temperature
Figure 43. Image Rejection vs. RF Frequency over LO Power
10
8
10
8
6
6
4
4
2
2
0
0
–2
–2
–4
–6
–8
–10
0dBm
2dBm
4dBm
6dBm
8dBm
+85°C
–4
+25°C
–40°C
–6
–8
–10
81.0 81.5 82.0 82.5 83.0 83.5 84.0 84.5 85.0 85.5 86.0
81.0 81.5 82.0 82.5 83.0 83.5 84.0 84.5 85.0 85.5 86.0
RF FREQUENCY (GHz)
RF FREQUENCY (GHz)
Figure 41. Input IP3 vs. RF Frequency over Temperature
Figure 44. Input IP3 vs. RF Frequency over LO Power
Rev. A | Page 13 of 25
Data Sheet
ADMV7420
40
35
30
25
20
15
40
35
30
25
20
15
10
5
0dBm
2dBm
4dBm
6dBm
8dBm
+85°C
+25°C
–40°C
10
5
0
0
81.0 81.5 82.0 82.5 83.0 83.5 84.0 84.5 85.0 85.5 86.0
81.0 81.5 82.0 82.5 83.0 83.5 84.0 84.5 85.0 85.5 86.0
RF FREQUENCY (GHz)
RF FREQUENCY (GHz)
Figure 45. Input IP2 vs. RF Frequency over Temperature
Figure 48. Input IP2 vs. RF Frequency over LO Power
1.0
1.0
0dBm
2dBm
4dBm
6dBm
8dBm
+85°C
+25°C
–40°C
0.8
0.6
0.8
0.6
0.4
0.4
0.2
0.2
0
0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.2
–0.4
–0.6
–0.8
–1.0
81.0 81.5 82.0 82.5 83.0 83.5 84.0 84.5 85.0 85.5 86.0
81.0 81.5 82.0 82.5 83.0 83.5 84.0 84.5 85.0 85.5 86.0
RF FREQUENCY (GHz)
RF FREQUENCY (GHz)
Figure 46. Amplitude Imbalance vs. RF Frequency over Temperature
Figure 49. Amplitude Imbalance vs. RF Frequency over LO Power
10
8
10
8
6
6
4
4
2
2
0
0
0dBm
–2
–2
2dBm
4dBm
6dBm
8dBm
–4
–4
–6
+85°C
+25°C
–40°C
–6
–8
–8
–10
–10
81.0 81.5 82.0 82.5 83.0 83.5 84.0 84.5 85.0 85.5 86.0
81.0 81.5 82.0 82.5 83.0 83.5 84.0 84.5 85.0 85.5 86.0
RF FREQUENCY (GHz)
RF FREQUENCY (GHz)
Figure 47. Phase Imbalance vs. RF Frequency over Temperature
Figure 50. Phase Imbalance vs. RF Frequency over LO Power
Rev. A | Page 14 of 25
Data Sheet
ADMV7420
10
9
10
9
8
8
6
5
4
3
2
1
0
+85°C
+25°C
–40°C
0dBm
2dBm
4dBm
6dBm
8dBm
8
7
6
5
4
3
2
1
0
81.0 81.5 82.0 82.5 83.0 83.5 84.0 84.5 85.0 85.5 86.0
81.0 81.5 82.0 82.5 83.0 83.5 84.0 84.5 85.0 85.5 86.0
RF FREQUENCY (GHz)
RF FREQUENCY (GHz)
Figure 51. Noise Figure vs. RF Frequency over Temperature
Figure 53. Noise Figure vs. RF Frequency over LO Power
0
–2
+85°C
+25°C
–40°C
–4
–6
–8
–10
–12
–14
–16
–18
–20
81.0 81.5 82.0 82.5 83.0 83.5 84.0 84.5 85.0 85.5 86.0
RF FREQUENCY (GHz)
Figure 52. Input P1dB vs. RF Frequency over Temperature
Rev. A | Page 15 of 25
Data Sheet
ADMV7420
TA = 25°C, IF = 2 GHz, RFIN = −20 dBm combined, LO power = +4 dBm, and upper sideband selected, unless otherwise noted.
18
16
14
12
10
8
18
16
14
12
10
8
0dBm
2dBm
4dBm
6dBm
8dBm
6
6
+85°C
+25°C
–40°C
4
4
2
2
0
0
81.0 81.5 82.0 82.5 83.0 83.5 84.0 84.5 85.0 85.5 86.0
81.0 81.5 82.0 82.5 83.0 83.5 84.0 84.5 85.0 85.5 86.0
RF FREQUENCY (GHz)
RF FREQUENCY (GHz)
Figure 57. Conversion Gain vs. RF Frequency over LO Power
Figure 54. Conversion Gain vs. RF Frequency over Temperature
50
50
45
40
35
30
25
45
40
35
30
25
20
15
10
5
20
0dBm
2dBm
4dBm
6dBm
8dBm
+85°C
+25°C
–40°C
15
10
5
0
0
81.0 81.5 82.0 82.5 83.0 83.5 84.0 84.5 85.0 85.5 86.0
81.0 81.5 82.0 82.5 83.0 83.5 84.0 84.5 85.0 85.5 86.0
RF FREQUENCY (GHz)
RF FREQUENCY (GHz)
Figure 58. Image Rejection vs. RF Frequency over LO Power
Figure 55. Image Rejection vs. RF Frequency over Temperature
10
10
8
8
6
6
4
4
2
2
0
0
–2
–4
–6
–8
–10
–2
0dBm
2dBm
4dBm
6dBm
8dBm
+85°C
–4
+25°C
–40°C
–6
–8
–10
81.0 81.5 82.0 82.5 83.0 83.5 84.0 84.5 85.0 85.5 86.0
81.0 81.5 82.0 82.5 83.0 83.5 84.0 84.5 85.0 85.5 86.0
RF FREQUENCY (GHz)
RF FREQUENCY (GHz)
Figure 59. Input IP3 vs. RF Frequency over LO Power
Figure 56. Input IP3 vs. RF Frequency over Temperature
Rev. A | Page 16 of 25
Data Sheet
ADMV7420
50
45
40
35
30
25
20
15
50
45
40
35
30
25
20
15
10
5
0dBm
2dBm
4dBm
6dBm
8dBm
+85°C
+25°C
–40°C
10
5
0
0
81.0 81.5 82.0 82.5 83.0 83.5 84.0 84.5 85.0 85.5 86.0
81.0 81.5 82.0 82.5 83.0 83.5 84.0 84.5 85.0 85.5 86.0
RF FREQUENCY (GHz)
RF FREQUENCY (GHz)
Figure 60. Input IP2 vs. RF Frequency over Temperature
Figure 63. Input IP2 vs. RF Frequency over LO Power
1.0
1.0
0dBm
2dBm
4dBm
6dBm
8dBm
+85°C
+25°C
–40°C
0.8
0.6
0.8
0.6
0.4
0.4
0.2
0.2
0
0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.2
–0.4
–0.6
–0.8
–1.0
81.0 81.5 82.0 82.5 83.0 83.5 84.0 84.5 85.0 85.5 86.0
81.0 81.5 82.0 82.5 83.0 83.5 84.0 84.5 85.0 85.5 86.0
RF FREQUENCY (GHz)
RF FREQUENCY (GHz)
Figure 61. Amplitude Imbalance vs. RF Frequency over Temperature
Figure 64. Amplitude Imbalance vs. RF Frequency over LO Power
10
8
10
8
6
6
4
4
2
2
+85°C
+25°C
–40°C
0dBm
0
0
–2
2dBm
4dBm
–2
–4
6dBm
8dBm
–4
–6
–6
–8
–8
–10
–10
81.0 81.5 82.0 82.5 83.0 83.5 84.0 84.5 85.0 85.5 86.0
81.0 81.5 82.0 82.5 83.0 83.5 84.0 84.5 85.0 85.5 86.0
RF FREQUENCY (GHz)
RF FREQUENCY (GHz)
Figure 62. Phase Imbalance vs. RF Frequency over Temperature
Figure 65. Phase Imbalance vs. RF Frequency over LO Power
Rev. A | Page 17 of 25
Data Sheet
ADMV7420
10
9
10
9
8
8
6
5
4
3
2
1
0
+85°C
+25°C
–40°C
0dBm
2dBm
4dBm
6dBm
8dBm
8
8
6
5
4
3
2
1
0
81.0 81.5 82.0 82.5 83.0 83.5 84.0 84.5 85.0 85.5 86.0
81.0 81.5 82.0 82.5 83.0 83.5 84.0 84.5 85.0 85.5 86.0
RF FREQUENCY (GHz)
RF FREQUENCY (GHz)
Figure 66. Noise Figure vs. RF Frequency over Temperature
Figure 68. Noise Figure vs. RF Frequency over LO Power
0
+85°C
+25°C
–40°C
–2
–4
–6
–8
–10
–12
–14
–16
–18
–20
81.0 81.5 82.0 82.5 83.0 83.5 84.0 84.5 85.0 85.5 86.0
RF FREQUENCY (GHz)
Figure 67. Input P1dB vs. RF Frequency over Temperature
Rev. A | Page 18 of 25
Data Sheet
ADMV7420
RETURN LOSS AND 6× LO LEAKAGE
0
0
–2
+85°C
+85°C
+25°C
–40°C
+25°C
–40°C
–2
–4
–4
–6
–6
–8
–8
–10
–12
–14
–16
–18
–20
–10
–12
–14
–16
–18
–20
81.0 81.5 82.0 82.5 83.0 83.5 84.0 84.5 85.0 85.5 86.0
13.4
13.6
13.8
14.0
14.2
14.4
14.6
RF FREQUENCY (GHz)
LO FREQUENCY (GHz)
Figure 69. RF Return Loss vs. RF Frequency over Temperature,
LO Frequency = 14.3 GHz
Figure 71. LO Return Loss vs. LO Frequency over Temperature
0
–50
+85°C
+85°C
+25°C
–40°C
+25°C
–40°C
–5
–10
–15
–20
–25
–30
–35
–40
–45
–50
–54
–58
–62
–66
–80
–84
–88
–82
–86
–90
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
81.0 81.5 82.0 82.5 83.0 83.5 84.0 84.5 85.0 85.5 86.0
IF FREQUENCY (GHz)
RF FREQUENCY (GHz)
Figure 70. IF Return Loss vs. IF Frequency over Temperature,
LO Frequency = 14.3 GHz
Figure 72. 6× LO Leakage at the RF Port over Temperature
Rev. A | Page 19 of 25
Data Sheet
ADMV7420
SPURIOUS PERFORMANCE
TA = 25°C, IF = 1 GHz, RFIN = −20 dBm, and LO input = +4 dBm, unless otherwise noted. Mixer spurious products are measured in dBc
from the IF output power level single-ended for frequencies below 50 GHz, with all other IF ports terminated. Spur values are (M × RF) − (N ×
LO). N/A means not applicable.
M × N Spurious Outputs, RF = 81 GHz, LO = 13.667 GHz
N × LO
0
1
2
3
4
5
6
7
8
12
18
0
1
2
3
4
5
N/A
N/A
N/A
N/A
N/A
N/A
−39
N/A
N/A
N/A
N/A
N/A
−80
−72
N/A
N/A
N/A
N/A
−71
−80
N/A
N/A
N/A
N/A
N/A
−79
N/A
N/A
N/A
N/A
N/A
−85
N/A
N/A
N/A
N/A
N/A
0
N/A
−88
N/A
N/A
N/A
N/A
N/A
−82
N/A
N/A
N/A
N/A
N/A
N/A
−35
N/A
N/A
N/A
N/A
N/A
N/A
−95
N/A
N/A
N/A
N/A
N/A
N/A
M × RF
M × N Spurious Outputs, RF = 83.5 GHz, LO = 14.083 GHz
N × LO
0
1
2
3
4
5
6
7
8
12
18
0
1
2
3
4
5
N/A
N/A
N/A
N/A
N/A
N/A
−33
N/A
N/A
N/A
N/A
N/A
−63
N/A
N/A
N/A
N/A
N/A
−53
−71
N/A
N/A
N/A
N/A
N/A
−78
N/A
N/A
N/A
N/A
N/A
−49
N/A
N/A
N/A
N/A
N/A
0
N/A
−46
N/A
N/A
N/A
N/A
N/A
−80
N/A
N/A
N/A
N/A
N/A
N/A
−32
N/A
N/A
N/A
N/A
N/A
N/A
−55
N/A
N/A
N/A
N/A
N/A
N/A
M × RF
M × N Spurious Outputs, RF = 86 GHz, LO = 14.5 GHz
N × LO
0
1
2
3
4
5
6
7
8
12
18
0
1
2
3
4
5
N/A
N/A
N/A
N/A
N/A
N/A
−35
N/A
N/A
N/A
N/A
N/A
−81
N/A
N/A
N/A
N/A
N/A
−71
−71
N/A
N/A
N/A
N/A
N/A
−81
N/A
N/A
N/A
N/A
N/A
−88
N/A
N/A
N/A
N/A
N/A
0
N/A
−87
N/A
N/A
N/A
N/A
N/A
−83
N/A
N/A
N/A
N/A
N/A
N/A
−37
N/A
N/A
N/A
N/A
N/A
N/A
−96
N/A
N/A
N/A
N/A
N/A
N/A
M × RF
Rev. A | Page 20 of 25
Data Sheet
ADMV7420
THEORY OF OPERATION
The ADMV7420 is a fully integrated SiP, I/Q low noise
downconverter that consists of two functional blocks.
implemented using a cascade of 3× and 2× multipliers. The LO
buffer amplifiers are included on chip to allow a typical LO
drive level of 4 dBm for typical performance. The LO path feeds
a quadrature splitter followed by on-chip baluns that drive the I
and Q mixer cores. The mixer cores comprise singly balanced
passive mixers. The RF input of the I and Q mixers are then
driven through an on-chip Wilkinson power splitter, which is
then fed by the first block of the ADMV7420.
The RFIN port of the ADMV7420 is connected to the gallium
arsenide (GaAs), low noise amplifier that consists of four stages
of low noise amplification that feed into the second block.
The second block is a GaAs, I/Q downconverter with an
integrated LO buffer and 6× multiplier. The 6× multiplier
allows the use of a lower frequency range LO input signal,
typically between 13.2 GHz and 14.6 GHz. The 6× multiplier is
Rev. A | Page 21 of 25
Data Sheet
ADMV7420
APPLICATIONS INFORMATION
POWER-UP BIAS SEQUENCE
POWER-DOWN SEQUENCE
The ADMV7420 functional blocks use active multiple amplifier
and multiplier stages that all use depletion mode pseudomorphic
high electron mobility transistors (pHEMTs). To ensure
transistor damage does not occur, use the following power-up
bias sequence and do not apply RF power to the device on the
LO or IF ports unless otherwise noted:
To power down the ADMV7420, take the following steps:
1. Apply a 0 V bias to VD_MULT, VD_AMP, VD12_LNA,
and VD34_LNA.
2. Apply a 0 V bias to VG_MIXER.
3. Apply a 0 V bias to VG_MULT, VG_AMP, VG12_LNA,
and VG34_LNA.
1. Apply a −2 V bias to VG_MULT, VG_AMP, VG12_LNA,
and VG34_LNA.
2. Apply a −1 V bias to VG_MIXER.
3. Apply a 2 V bias to VD12_LNA.
4. Apply a 1.5 V bias to VD_MULT.
5. Apply a 4 V bias to VD_AMP and VD34_LNA.
6. Adjust VG_AMP between −2 V and 0 V to achieve a total
LAYOUT
Solder the exposed pad on the underside of the ADMV7420 to a
low thermal and electrical impedance ground plane. This pad is
typically soldered to an exposed opening in the solder mask.
Connect these ground vias to all other ground layers to maximize
heat dissipation from the device package.
Figure 73 illustrates the recommended mechanical layout on the
interface plate used to interface to the WR-12 waveguide
opening of the ADMV7420.The recommended PCB land
pattern footprint is shown in Figure 74.
I
VD_AMP current of 175 mA.
7. Adjust VG12_LNA between −2 V and 0 V to achieve a
total IVD12_LNA current of 22 mA.
8. Adjust VG34_LNA between −2 V and 0 V to achieve a
total IVD34_LNA current of 44 mA.
9. Apply a LO input signal on the LO port and adjust
VG_MULT between −2 V and 0 V to achieve a total
I
VD_MULT current of 80 mA.
(Ø0.563)
4× R0.016
2× Ø0.0595±0.0005 THRU
MARKED A
2× Ø0.067±0.003 THRU
MARKED B
0.981
2× 0.899
A
B
A
NOTE: 7
PRESS FIT ALIGNMENT PINS (QTY 2)
TO HEIGHT SHOWN THIS SIDE
0.761
0.639
2× 0.501
0.419
B
0.061 (1.55)
0.122 (3.10)
0.000
0.000
DETAIL A
PART LIST
STOCK NUMBER
VARIOUS PIN, ALIGNMENT, FLANGE, 0.0615 DIA
ITEM QTY VENDOR
DESCRIPTION
1
2
VARIOUS
NOTES:
1. REMOVE BURRS AND BREAK SHARP EDGES.
2. ALL INTERNAL RADII ARE .090 UNLESS OTHERWISE NOTED.
3. SURFACE FINISH 32 RMS UNLESS OTHERWISE SPECIFIED.
4. DIMENSIONS APPLY AFTER PLATING.
5. MATERIAL: ALUMINUM 6061-T6 PER QQ-A-250/11.
6. FINISH: NONE.
7. INSTALL DOWEL PINS.
8. USE ELECTRONIC DATA FOR ALL GEOMETRY THAT IS NOT DIMENSIONED.
Figure 73. Recommended Standard WR-12 Footprint
Rev. A | Page 22 of 25
Data Sheet
ADMV7420
PCB METAL FOOTPRINT
PCB SOLDERMASK KEEPOUT
0.012
0.350
(8.89)
0.098
(2.50)
(0.30)
0.150
(3.80)
0.047
(1.20)
0.071
(1.80)
Ø0.033
(Ø0.85)
0.128
Ø0.028
(0.70)
0.016
(3.24)
(0.40)
0.079
(2.02)
0.185
(4.70)
0.260
(6.60)
0.022
(0.55)
0.165
(4.20)
0.142
(3.60)
0.091
(2.30)
0.124
(3.15)
0.331
(8.40)
0.520
(13.20)
0.085
(2.15)
0.142
(3.60)
SEE DETAIL A
0.073
(1.85)
0.022
(0.55)
0.031
(0.80)
0.173
(4.40)
0.106
(2.69)
PCB SOLDER PASTE MASK
R0.010
(R0.25)
0.150
(3.80)
0.085
0.022
(0.57)
(2.17)
0.220
(5.60)
0.058
(1.47)
Ø0.026
(Ø0.65)
0.122
(3.10)
0.132 0.185
(3.35) (4.70)
DETAIL A
WAVEGUIDE
0.124
(3.14)
0.080
(2.03)
NOTES
1. WAVEGUIDE OPENING TO BE FULLY PLATED.
2. FILL AREA UNDER DEVICE WITH AN ARRAY OF
0.010 VIAS (FILLED, RECOMMENDED 0.025 PITCH).
0.014
(0.35)
0.060
(1.52)
Figure 74. PCB Land Pattern Footprint
Rev. A | Page 23 of 25
Data Sheet
ADMV7420
TYPICAL APPLICATION CIRCUIT
Figure 75 shows the typical application circuit.
VG_AMP
VD_MULT
+
+
4.7µF
4.7µF
4.7µF
4.7µF
+
+
VD_AMP
VG_MULT
LOIN
VG_MIXER
4.7µF
+
1
2
OUT
IFI_OUT
IFOUT
3
ADMV7420
4
IFQ_OUT
5
OUT
90°
HYBRID
RFIN
6
7
180°
HYBRID
8
9
10
VG12_LNA
VD12_LNA
VD34_LNA
VG34_LNA
+
+
4.7µF
4.7µF
4.7µF
+
+
4.7µF
Figure 75. Typical Application Circuit
Rev. A | Page 24 of 25
Data Sheet
ADMV7420
OUTLINE DIMENSIONS
11.15
11.00
10.85
2.75
BSC
4.64
4.00
PIN 1
2.50
INDICATOR
0.38
0.38
PIN 1
CORNER
10.24
0.40 × 0.45°
2.75 BSC
22
34
VENT HOLE
Ø 0.125
0.82
BSC
1
EXPOSED
PAD
EXPOSED
PAD
EXPOSED
PAD
1.80
13.15
13.00
12.85
PORT 1
(See Detail A)
7.50
EXPOSED
PAD
EXPOSED
PAD
0.80
BSC
12.24
1.00
BSC
EXPOSED
PAD
EXPOSED
PAD
6.50
BSC
10
1.80
22
11
1.70
1.55
BOTTOM VIEW
0.36
0.30
TOP VIEW
0.25 BSC
0.48
0.42
0.36
2.04 BSC
2.93
MAX
SIDE VIEW
2.54 REF
0.24
3.15 BSC
0.46 BSC
1.55 BSC
FOR PROPER CONNECTION OF
THE EXPOSED PADS, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.320
0.290
0.260
SEATING
PLANE
4.70
BSC
3.10
BSC
SECTION OF THIS DATA SHEET.
DETAIL A
Figure 76. 34-Terminal Chip Array Small Outline No Lead Cavity [LGA_CAV]
11.00 mm × 13.00 mm Body and 2.93 Maximum mm Package Height
(CE-34-2)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature Range
Package Description
Package Option
ADMV7420BCEZ
ADMV7420-EVALZ
−40°C to +85°C
34-Terminal Chip Array Small Outline No Lead Cavity [LGA_CAV]
Evaluation Board
CE-34-2
1 Z = RoHS Compliant Part.
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D20970-0-10/19(A)
Rev. A | Page 25 of 25
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