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ADMV8818SCCZ-EP-P7 [ADI]

2 GHz to 18 GHz, Digitally Tunable, High-Pass and Low-Pass Filter;
ADMV8818SCCZ-EP-P7
型号： ADMV8818SCCZ-EP-P7
厂家： ADI    ADI
描述：

2 GHz to 18 GHz, Digitally Tunable, High-Pass and Low-Pass Filter
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2 GHz to 18 GHz, Digitally Tunable,  
High-Pass and Low-Pass Filter  
Data Sheet  
ADMV8818  
FEATURES  
GENERAL DESCRIPTION  
Digitally tunable, multioctave, high-pass and low-pass tuning  
Independent 3 dB frequency control for up to 4 GHz of  
bandwidth  
Optimal wideband rejection: 35 dB  
Single chip replacement for discrete filter banks  
Compact 9 mm × 9 mm, 56-terminal LGA package  
The ADMV8818 is a fully monolithic microwave integrated  
circuit (MMIC) that features a digitally selectable frequency of  
operation. The device features four independently controlled high-  
pass filters (HPFs) and four independently controlled low-pass  
filters (LPFs) that span the 2 GHz to 18 GHz frequency range.  
The flexible architecture of the ADMV8818 allows the 3 dB cutoff  
frequency (f3dB) of the high-pass and low-pass filters to be  
controlled independently to generate up to 4 GHz of bandwidth.  
The digital logic control on each filter is 4 bits wide (16 states) and  
controls the on-chip reactive elements to adjust the f3dB. The typical  
insertion loss is 9 dB, and the wideband rejection is 35 dB, which is  
ideally suited for minimizing system harmonics.  
APPLICATIONS  
Test and measurement equipment  
Military radar, electronic warfare, and electronic  
countermeasures  
Satellite communications and space  
Industrial and medical equipment  
This tunable filter can be used as a smaller alternative to large  
switched filter banks and cavity tuned filters, and this device  
provides a dynamically adjustable solution in advanced  
communications applications.  
FUNCTIONAL BLOCK DIAGRAM  
GND  
GND  
GND  
GND  
GND  
GND  
RFIN  
GND  
GND  
GND  
GND  
GND  
GND  
RST  
1
2
3
4
5
6
42  
GND  
ADMV8818  
41  
40  
39  
38  
37  
VSS1 (–2.5V)  
GND  
BYPASS  
1
BYPASS  
1
VDD2 (+3.3V)  
GND  
GND  
7
36 RFOUT  
2
3
4
2
3
4
8
9
35  
34  
33  
32  
31  
30  
29  
GND  
GND  
10  
11  
12  
13  
14  
GND  
GND  
VDD1 (+2.5V)  
GND  
SPI  
GND  
Figure 1.  
Rev. 0  
Document Feedback  
Information furnished by Analog Devices is believed to be accurate and reliable. However, no  
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other  
rights of third parties that may result from its use. Specifications subject to change without notice.  
No license is granted by implication or otherwise under any patent or patent rights of Analog  
Devices. Trademarks and registeredtrademarks are the property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700  
Technical Support  
©2020 Analog Devices, Inc. All rights reserved.  
www.analog.com  
 
 
 
 
 
ADMV8818  
Data Sheet  
TABLE OF CONTENTS  
Features.............................................................................................. 1  
SPI Configuration ...................................................................... 15  
RF Connections.......................................................................... 15  
Mode Selection ........................................................................... 15  
SPI Write Mode.......................................................................... 16  
Switch Positions ......................................................................... 16  
Switch Set .................................................................................... 16  
Filter Settings .............................................................................. 16  
Write Group Priority................................................................. 16  
Frequency Terminology............................................................ 16  
SPI Fast Latch Mode.................................................................. 16  
Chip Reset ................................................................................... 17  
Applications Information ............................................................. 18  
PCB Design Guidelines ............................................................. 18  
Programming Flow Chart............................................................. 19  
Register Summary .......................................................................... 20  
Register Details ............................................................................... 27  
Outline Dimensions....................................................................... 36  
Ordering Guide .......................................................................... 36  
Applications ...................................................................................... 1  
General Description......................................................................... 1  
Functional Block Diagram .............................................................. 1  
Revision History ............................................................................... 2  
Specifications .................................................................................... 3  
Timing Specifications .................................................................. 5  
Absolute Maximum Ratings ........................................................... 7  
Electrostatic Discharge (ESD) Ratings...................................... 7  
ESD Caution.................................................................................. 7  
Pin Configuration and Function Descriptions ............................ 8  
Typical Performance Characteristics............................................. 9  
4 GHz Constant Bandwidth Data.............................................. 9  
Board Loss and Bypass Configuration Data........................... 11  
HPF and LPF Configuration..................................................... 12  
Theory of Operation ...................................................................... 14  
Chip Architecture....................................................................... 14  
Tunable High-Pass Filters......................................................... 14  
Tunable Low-Pass Filters .......................................................... 15  
REVISION HISTORY  
12/2020—Revision 0: Initial Version  
Rev. 0 | Page 2 of 36  
 
Data Sheet  
ADMV8818  
SPECIFICATIONS  
TA = 25°C, unless otherwise noted.  
Table 1.  
Parameter  
Min  
Typ  
Max  
Unit  
Test Conditions/Comments  
FREQUENCY RANGE (f3dB  
Bypass Configuration  
HPF 1  
)
3 dB cutoff  
2
18  
GHz  
State 0  
State 15  
1.75  
3.55  
GHz  
GHz  
HPF 2  
State 0  
State 15  
3.40  
7.25  
GHz  
GHz  
HPF 3  
State 0  
State 15  
6.60  
12.00  
GHz  
GHz  
HPF 4  
State 0  
State 15  
12.50  
19.90  
GHz  
GHz  
LPF 1  
State 0  
State 15  
2.05  
3.85  
GHz  
GHz  
LPF 2  
State 0  
State 15  
3.35  
7.25  
GHz  
GHz  
LPF 3  
State 0  
State 15  
7.00  
13.00  
GHz  
GHz  
LPF 4  
State 0  
State 15  
12.55  
18.85  
GHz  
GHz  
INSERTION LOSS  
Bypass Configuration  
2 GHz  
−3.2  
−4.4  
−6.0  
−7.3  
−8.6  
−11.8  
−14.6  
dB  
dB  
dB  
dB  
dB  
dB  
dB  
10 GHz  
18 GHz  
2 GHz to 6 GHz  
6 GHz to 10 GHz  
10 GHz to 14 GHz  
14 GHz to 18 GHz  
BANDWIDTH (3 dB)  
HPF 1 State 2 and LPF 2 State 11  
HPF 2 State 11 and LPF 3 State 8  
HPF 3 State 10 and LPF 4 State 5  
HPF 4 State 5 and LPF 4 State 13  
Smaller bandwidth possible with more insertion  
loss  
2 GHz to 10 GHz  
10 GHz to 18 GHz  
RESOLUTION  
HPF 1  
HPF 2  
HPF 3  
HPF 4  
LPF 1  
LPF 2  
LPF 3  
0.5 to 4  
1 to 4  
GHz  
GHz  
4 bits per filter (LPF and HPF)  
0.12  
0.26  
0.36  
0.49  
0.12  
0.26  
0.40  
0.42  
GHz  
GHz  
GHz  
GHz  
GHz  
GHz  
GHz  
GHz  
LPF 4  
Rev. 0 | Page 3 of 36  
 
ADMV8818  
Data Sheet  
Parameter  
Min  
Typ  
Max  
Unit  
Test Conditions/Comments  
WIDEBAND REJECTION FREQUENCY OFFSET  
Measured at 35 dB rejection  
HPF 1  
State 0  
State 15  
HPF 2  
−0.65  
−1.25  
ΔGHz  
ΔGHz  
State 0  
State 15  
HPF 3  
−0.85  
−2.00  
ΔGHz  
ΔGHz  
State 0  
State 15  
HPF 4  
−1.15  
−1.90  
ΔGHz  
ΔGHz  
State 0  
State 15  
LPF 1  
−2.35  
−3.10  
ΔGHz  
ΔGHz  
State 0  
State 15  
LPF 2  
0.70  
1.00  
ΔGHz  
ΔGHz  
State 0  
State 15  
LPF 3  
0.90  
1.50  
ΔGHz  
ΔGHz  
State 0  
State 15  
LPF 4  
2.30  
3.20  
ΔGHz  
ΔGHz  
State 0  
2.50  
3.95  
32  
ΔGHz  
ΔGHz  
GHz  
dB  
State 15  
RE-ENTRY FREQUENCY  
RETURN LOSS  
DYNAMIC PERFORMANCE  
≤35 dB  
10  
Input Power for 0.1 dB Compression  
(P0.1dB)  
18  
dBm  
Input Third-Order Intercept (IP3)  
Group Delay Flatness  
Amplitude Settling Time  
Phase Settling Time  
Drift Rate  
45  
<0.8  
1
dBm  
ns  
µs  
Input power (PIN)1 = 5 dBm per tone  
To within ≤1 dB of static insertion loss  
To within ≤2° of static insertion phase  
2
µs  
Amplitude  
Frequency  
−0.018  
−100  
dB/°C  
ppm/°C  
At 8 GHz  
6 GHz to 10 GHz constant bandwidth state  
RESIDUAL PHASE NOISE  
At 1 MHz Offset  
SUPPLY VOLTAGE  
VSS1  
VDD1  
VDD2  
165  
dBc/Hz  
−2.6  
2.4  
3.2  
−2.5  
2.5  
3.3  
−2.4  
2.6  
3.4  
V
V
V
SUPPLY CURRENT (STATIC)  
VSS1  
VDD1  
−50  
µA  
µA  
µA  
200  
50  
VDD2  
SUPPLY CURRENT (DYNAMIC)  
VDD2  
fSCLK/2  
mA  
Where fSCLK is the SCLK toggle frequency in MHz,  
for example, continuous SPI writing at 10 MHz  
yields 5 mA of dynamic supply current  
Rev. 0 | Page 4 of 36  
Data Sheet  
ADMV8818  
Parameter  
Min  
Typ  
Max  
Unit  
Test Conditions/Comments  
LOGIC (RST, CS, SCLK, SDI, SDO, SFL)  
Logic Low  
Logic High  
–0.3  
1.2  
0
3.3  
+0.8  
3.6  
V
V
1 When the insertion loss is less than −20 dB, PIN = 8 dBm per tone.  
TIMING SPECIFICATIONS  
Table 2.  
Parameter  
Min  
10  
10  
20  
2.5  
2.5  
5
Typ  
Max  
Unit  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Test Conditions / Comments  
RST low time to perform reset  
SCLK cycle time (write)  
SCLK cycle time (read)  
SCLK high time  
SCLK low time  
CS falling edge to SCLK rising edge setup time  
SCLK rising edge to CS hold time  
t1  
t2  
t3  
t4  
t5  
t6  
2
t7  
5
Minimum CS high time for latching in data (for multiple SPI transactions)  
CS rising edge to next SCLK rising edge ignore  
SDI data setup time  
t8  
5
t9  
5
2
t10  
t11  
t12  
t13  
t14  
t15  
t16  
t17  
t18  
t19  
SDI data hold time  
10  
10  
10  
10  
2.5  
2.5  
SFL falling edge (exiting SFL mode) to CS falling edge time (start SPI transaction)  
CS rising edge (end SPI transaction) to SFL rising edge time (entering SFL mode)  
SFL rising edge to CS falling edge time  
CS cycle time (SFL mode)  
CS high time (SFL mode)  
CS low time (SFL mode)  
6
5
4
SCLK falling edge to SDO valid (load capacitance (CL) = 10 pF)  
SDO rise and fall time (CL = 10 pF)  
CS rising edge to SDO tristate (CL = 10 pF)  
Rev. 0 | Page 5 of 36  
 
ADMV8818  
Data Sheet  
Timing Diagram  
RST  
t2  
t1  
t3  
t8  
SCLK  
1
2
3
4
5
17  
18  
19  
20  
21  
22  
23  
24  
t14  
t4  
t15  
t7  
CS  
SDI  
SFL  
t6  
t5  
t16  
t10  
t9  
R/W A14  
A13 TO A0  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
t12  
t13  
t11  
t17  
t19  
SDO  
DON’T CARE  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
t18  
NOTES  
1. FOR READ OPERATION THE DATA BITS ON SDI ARE DON’T CARES.  
Figure 2. Timing Diagram  
Rev. 0 | Page 6 of 36  
 
Data Sheet  
ADMV8818  
ABSOLUTE MAXIMUM RATINGS  
ELECTROSTATIC DISCHARGE (ESD) RATINGS  
Table 3.  
The following ESD information is provided for handling of  
ESD-sensitive devices in an ESD protected area only.  
Parameter  
Rating  
SUPPLY  
VDD1  
VDD2  
VSS1  
−0.3 V to +2.8 V  
−0.3 V to +3.6 V  
−3.6 V to +0.3 V  
Human body model (HBM) per ANSI/ESDA/JEDEC JS-001.  
Field induced charged device model (FICDM) per ANSI/ESDA/  
JEDEC JS-002.  
Digital Control Inputs  
Voltage  
Current  
RF Input Power1  
Temperature  
Operating Range  
Storage Range  
Junction to Maintain 1,000,000 Hours  
Mean Time to Failure (MTTF)  
ESD Ratings for ADMV8818  
−0.3 V to VDD2 + 0.3 V  
2 mA  
20 dBm  
Table 4. ADMV8818, 56-Terminal LGA  
ESD Model  
Withstand Threshold (V)  
Class  
2
C3  
HBM  
FICDM  
2000  
250  
−55°C to +105°C  
−65°C to +150°C  
135°C  
ESD CAUTION  
Nominal Junction (TPADDLE = 85°C)  
90°C  
Moisture Sensitivity Level (MSL) Rating  
MSL3  
1 Maximum RF input power valid for frequencies above 1 GHz. For incident  
signals below this frequency, contact Analog Devices, Inc., to discuss the use  
case scenario.  
Stresses at or above those listed under Absolute Maximum  
Ratings may cause permanent damage to the product. This is a  
stress rating only; functional operation of the product at these  
or any other conditions above those indicated in the  
operational section of this specification is not implied.  
Operation beyond the maximum operating conditions for  
extended periods may affect product reliability.  
Rev. 0 | Page 7 of 36  
 
 
 
ADMV8818  
Data Sheet  
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS  
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
42 GND  
GND  
GND  
GND  
GND  
GND  
GND  
RFIN  
GND  
GND  
GND  
GND  
GND  
GND  
RST  
41 VSS1 (–2.5V)  
40 GND  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
VDD2 (+3.3V)  
GND  
GND  
ADMV8818  
TOP VIEW  
(Not to Scale)  
RFOUT  
GND  
GND  
GND  
GND  
VDD1 (+2.5V)  
GND  
GND  
NOTES  
1. EXPOSED PAD. THE EXPOSED PAD MUST BE  
CONNECTED TO THE RF AND DC GROUND.  
Figure 3. Pin Configuration  
Table 5. Pin Function Descriptions  
Pin No.  
Mnemonic Description  
1 to 6, 8 to 13, 15, 17, 19,  
21, 23, 25 to 30, 32 to  
35, 37, 38, 40, 42 to 56  
GND  
Ground. Connect the GND pins to the RF and dc ground.  
7
14  
16  
RFIN  
RST  
RF Input Pin. RFIN is dc-coupled and matched to 50 Ω. Do not apply an external voltage to RFIN.  
Chip Reset. 3.3 V logic. Active low. The RST pin is internally pulled high with a 260 kΩ resistor.  
SCLK  
Serial Peripheral Interface (SPI) Clock. 3.3 V logic. The SCLK pin is internally pulled low with a  
260 kΩ resistor.  
18  
20  
22  
24  
CS  
SPI Chip Select. 3.3 V logic. Active low. The CS pin is internally pulled low with a 260 kΩ resistor.  
SPI Data Output. 3.3 V logic. The SDO pin is internally pulled low with a 260 kΩ resistor.  
SPI Data Input. 3.3 V logic. The SDI pin is internally pulled low with a 260 kΩ resistor.  
SPI Fast Latch Enable. 3.3 V logic. Set SFL high to enable fast latching of filter states on each  
rising edge of CS. While SFL is in this mode, the SCLK, SDO, and SDI pins are not active. The SFL  
pin is internally pulled low with a 260 kΩ resistor.  
SDO  
SDI  
SFL  
31  
36  
39  
41  
VDD1  
RFOUT  
VDD2  
VSS1  
2.5 V Power Supply Pin. Place 0.1 µF and 100 pF decoupling capacitors close to VDD1.  
RF Output Pin. RFOUT is dc-coupled and matched to 50 Ω. Do not apply an external voltage to RFOUT.  
3.3 V Power Supply Pin. Place 0.1 µF and 100 pF decoupling capacitors close to VDD2.  
–2.5 V Power Supply Pin. Place 0.1 µF and 100 pF decoupling capacitors close to VSS1.  
Exposed Pad. The exposed pad must be connected to the RF and dc ground.  
EPAD  
Rev. 0 | Page 8 of 36  
 
Data Sheet  
ADMV8818  
TYPICAL PERFORMANCE CHARACTERISTICS  
4 GHz CONSTANT BANDWIDTH DATA  
0
–2  
0
−55°C  
−40°C  
+25°C  
+85°C  
+105°C  
HPF 1 AND LPF 2  
HPF 1  
AND  
LPF 2  
HPF 2 AND LPF 3  
HPF 3 AND LPF 4  
HPF 4 AND LPF 4  
–5  
–10  
–15  
–20  
–25  
–30  
–35  
–40  
–45  
–50  
–55  
–60  
HPF 2  
AND  
LPF 3  
–4  
HPF 3  
AND  
LPF 4  
–6  
–8  
HPF 4  
AND  
LPF 4  
–10  
–12  
–14  
–16  
–18  
–20  
–22  
–24  
–26  
–28  
–30  
0
2
4
6
8
10  
12  
14  
16  
18  
20  
22  
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40  
RF FREQUENCY (GHz)  
RF FREQUENCY (GHz)  
Figure 4. Insertion Loss vs. RF Frequency at 4 GHz Constant Bandwidth  
Figure 7. Insertion Loss vs. RF Frequency at 4 GHz Constant Bandwidth and  
Various Temperatures  
0
–5  
0
–5  
–10  
–15  
–20  
–10  
–15  
–20  
–25  
–25  
–30  
–35  
–40  
–45  
–50  
–55  
–60  
INPUT RETURN LOSS  
OUTPUT RETURN LOSS  
INSERTION LOSS  
–30  
–35  
–40  
–45  
–50  
–55  
–60  
INPUT RETURN LOSS  
OUTPUT RETURN LOSS  
INSERTION LOSS  
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40  
RF FREQUENCY (GHz)  
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40  
RF FREQUENCY (GHz)  
Figure 5. Input and Output Return Loss and Insertion Loss vs. RF Frequency,  
HPF 1 and LPF 2 Band at 4 GHz Constant Bandwidth  
Figure 8. Input and Output Return Loss and Insertion Loss vs. RF Frequency,  
HPF 3 and LPF 4 Band at 4 GHz Constant Bandwidth  
0
–5  
0
–5  
–10  
–15  
–20  
–10  
–15  
–20  
–25  
–25  
–30  
–35  
–40  
–45  
–50  
–55  
–60  
INPUT RETURN LOSS  
OUTPUT RETURN LOSS  
INSERTION LOSS  
–30  
–35  
–40  
–45  
–50  
–55  
–60  
INPUT RETURN LOSS  
OUTPUT RETURN LOSS  
INSERTION LOSS  
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40  
RF FREQUENCY (GHz)  
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40  
RF FREQUENCY (GHz)  
Figure 9. Input and Output Return Loss and Insertion Loss vs. RF Frequency,  
HPF 4 and LPF 4 Band at 4 GHz Constant Bandwidth  
Figure 6. Input and Output Return Loss and Insertion Loss vs. RF Frequency,  
HPF 2 and LPF 3 Band at 4 GHz Constant Bandwidth  
Rev. 0 | Page 9 of 36  
 
 
ADMV8818  
Data Sheet  
1.80  
1.65  
1.50  
1.35  
1.20  
1.05  
0.90  
0.75  
0.60  
0.45  
0.30  
0.15  
0
0
–5  
1.80  
1.65  
1.50  
1.35  
1.20  
1.05  
0.90  
0.75  
0.60  
0.45  
0.30  
0.15  
0
–5  
INSERTION LOSS  
GROUP DELAY  
–10  
–15  
–20  
–25  
–30  
–35  
–40  
–45  
–50  
–55  
–60  
–10  
–15  
–20  
–25  
–30  
–35  
–40  
–45  
–50  
–55  
–60  
INSERTION LOSS  
GROUP DELAY  
0
0
1
2
3
4
5
6
7
8
7
9
11  
13  
15  
17  
RF FREQUENCY (GHz)  
RF FREQUENCY (GHz)  
Figure 10. Insertion Loss and Group Delay vs. RF Frequency, HPF 1 and LPF 2  
at 4 GHz Constant Bandwidth  
Figure 13. Insertion Loss and Group Delay vs. RF Frequency, HPF 3 and LPF 4  
at 4 GHz Constant Bandwidth  
1.80  
1.80  
1.65  
1.50  
1.35  
1.20  
1.05  
0.90  
0.75  
0.60  
0.45  
0.30  
0.15  
0
0
–5  
0
INSERTION LOSS  
INSERTION LOSS  
GROUP DELAY  
GROUP DELAY  
1.65  
1.50  
1.35  
1.20  
1.05  
0.90  
0.75  
0.60  
0.45  
0.30  
0.15  
0
–5  
–10  
–15  
–20  
–25  
–30  
–35  
–40  
–45  
–50  
–55  
–60  
–10  
–15  
–20  
–25  
–30  
–35  
–40  
–45  
–50  
–55  
–60  
3
5
7
9
11  
13  
9
11  
13  
15  
17  
19  
21  
23  
15  
RF FREQUENCY (GHz)  
RF FREQUENCY (GHz)  
Figure 11. Insertion Loss and Group Delay vs. RF Frequency, HPF 2 and LPF 3  
at 4 GHz Constant Bandwidth  
Figure 14. Insertion Loss and Group Delay vs. RF Frequency, HPF 4 and LPF 4  
at 4 GHz Constant Bandwidth  
60  
55  
50  
45  
40  
–100  
25°C, HPF 1 STATE 2, LPF 2 STATE 11  
–105  
25°C, HPF 2 STATE 11, LPF 3 STATE 8  
25°C, HPF 3 STATE 10, LPF 4 STATE 5  
25°C, HPF 4 STATE 5, LPF 4 STATE 13  
–110  
–115  
–120  
–125  
–130  
–135  
–140  
–145  
–150  
–155  
–160  
–165  
–170  
–175  
–180  
HPF 1  
AND  
HPF 2  
AND  
HPF 3  
AND  
HPF 4  
AND  
35  
30  
25  
20  
15  
10  
5
LPF 2  
LPF 3  
LPF 4  
LPF 4  
−40°C, HPF 1 STATE 2, LPF 2 STATE 11  
+25°C, HPF 1 STATE 2, LPF 2 STATE 11  
+85°C, HPF 1 STATE 2, LPF 2 STATE 11  
−40°C, HPF 2 STATE 11, LPF 3 STATE 8  
+25°C, HPF 2 STATE 11, LPF 3 STATE 8  
+85°C, HPF 2 STATE 11, LPF 3 STATE 8  
−40°C, HPF 3 STATE 10, LPF 4 STATE 5  
+25°C, HPF 3 STATE 10, LPF 4 STATE 5  
+85°C, HPF 3 STATE 10, LPF 4 STATE 5  
−40°C, HPF 4 STATE 5, LPF 4 STATE 13  
+25°C, HPF 4 STATE 5, LPF 4 STATE 13  
+85°C, HPF 4 STATE 5, LPF 4 STATE 13  
0
0
2
4
6
8
10  
12  
14  
16  
18  
20  
1k  
10k  
100k  
1M  
10M  
100M  
RF FREQUENCY (GHz)  
OFFSET FREQUENCY (Hz)  
Figure 12. Input IP3 vs. RF Frequency, 4 GHz, 3 dB Bandwidth Configuration  
at Various Temperatures  
Figure 15. Residual Phase Noise vs. Offset Frequency  
Rev. 0 | Page 10 of 36  
Data Sheet  
ADMV8818  
BOARD LOSS AND BYPASS CONFIGURATION DATA  
0
60  
55  
50  
45  
40  
35  
30  
25  
20  
15  
10  
5
–5  
–10  
–15  
–20  
–25  
–30  
–35  
BOARD LOSS  
BYPASS CONFIGURATION (SWITCHES ONLY)  
BOARD LOSS AND BYPASS CONFIGURATION  
–40°C  
+25°C  
+85°C  
0
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40  
RF FREQUENCY (GHz)  
1
3
5
7
9
11 13 15 17 19 21 23 25  
RF FREQUENCY (GHz)  
Figure 16. Insertion Loss vs. RF Frequency for Board Loss and  
Bypass Configuration  
Figure 18. Input IP3 vs. RF Frequency for Various Temperatures,  
Bypass Configuration  
0
INPUT RETURN LOSS  
OUTPUT RETURN LOSS  
–5  
–10  
–15  
–20  
–25  
–30  
–35  
–40  
–45  
–50  
–55  
–60  
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40  
RF FREQUENCY (GHz)  
Figure 17. Input and Output Return Loss vs. RF Frequency in  
Bypass Configuration  
Rev. 0 | Page 11 of 36  
 
ADMV8818  
Data Sheet  
HPF AND LPF CONFIGURATION  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
10  
9
8
7
6
5
4
3
2
1
22  
LPF 1  
LPF 2  
LPF 3  
LPF 4  
21  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
10  
9
HPF 1  
HPF 2  
HPF 3  
HPF 4  
8
7
6
5
4
3
2
1
0
0
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15  
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15  
LPF STATE  
HPF STATE  
Figure 22. 3 dB Cutoff Frequency vs. LPF State, LPF Configuration  
Figure 19. 3 dB Cutoff Frequency vs. HPF State, HPF Configuration  
0
0
–5  
STATE 0  
STATE 1  
STATE 2  
STATE 3  
STATE 4  
STATE 5  
STATE 6  
STATE 7  
STATE 8  
STATE 9  
STATE 10  
STATE 11  
STATE 12  
STATE 13  
STATE 14  
STATE 15  
–5  
–10  
–15  
–20  
–25  
–30  
–35  
–40  
–45  
–50  
–55  
–60  
–10  
–15  
–20  
–25  
–30  
–35  
STATE 0  
STATE 1  
STATE 2  
STATE 3  
STATE 4  
STATE 5  
STATE 6  
STATE 7  
STATE 8  
STATE 9  
STATE 10  
STATE 11  
STATE 12  
STATE 13  
STATE 14  
STATE 15  
–40  
–45  
–50  
–55  
–60  
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40  
RF FREQUENCY (GHz)  
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40  
RF FREQUENCY (GHz)  
Figure 20. Insertion Loss vs. RF Frequency, HPF 1 Configuration Swept  
HPF State  
Figure 23. Insertion Loss vs. RF Frequency, LPF 1 Configuration Swept  
LPF State  
0
–5  
0
STATE 0  
STATE 1  
STATE 2  
STATE 3  
STATE 4  
STATE 5  
STATE 6  
STATE 7  
STATE 8  
STATE 9  
STATE 10  
STATE 11  
STATE 12  
STATE 13  
STATE 14  
STATE 15  
–5  
–10  
–15  
–20  
–25  
–30  
–35  
–40  
–45  
–50  
–55  
–60  
–10  
–15  
–20  
–25  
–30  
–35  
STATE 0  
STATE 1  
STATE 2  
STATE 3  
STATE 4  
STATE 5  
STATE 6  
STATE 7  
STATE 8  
STATE 9  
STATE 10  
STATE 11  
STATE 12  
STATE 13  
STATE 14  
STATE 15  
–40  
–45  
–50  
–55  
–60  
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40  
RF FREQUENCY (GHz)  
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40  
RF FREQUENCY (GHz)  
Figure 21. Insertion Loss vs. RF Frequency, HPF 2 Configuration Swept  
HPF State  
Figure 24. Insertion Loss vs. RF Frequency, LPF 2 Configuration Swept  
LPF State  
Rev. 0 | Page 12 of 36  
 
Data Sheet  
ADMV8818  
0
–5  
0
–5  
STATE 0  
STATE 1  
STATE 2  
STATE 3  
STATE 4  
STATE 5  
STATE 6  
STATE 7  
STATE 8  
STATE 9  
STATE 10  
STATE 11  
STATE 12  
STATE 13  
STATE 14  
STATE 15  
–10  
–15  
–20  
–25  
–30  
–35  
–40  
–45  
–50  
–55  
–60  
–10  
–15  
–20  
–25  
–30  
–35  
–40  
–45  
–50  
–55  
–60  
STATE 0  
STATE 1  
STATE 2  
STATE 3  
STATE 4  
STATE 5  
STATE 6  
STATE 7  
STATE 8  
STATE 9  
STATE 10  
STATE 11  
STATE 12  
STATE 13  
STATE 14  
STATE 15  
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40  
RF FREQUENCY (GHz)  
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40  
RF FREQUENCY (GHz)  
Figure 28. Insertion Loss vs. RF Frequency, LPF 3 Configuration Swept  
LPF State  
Figure 25. Insertion Loss vs. RF Frequency, HPF 3 Configuration Swept  
HPF State  
0
0
–5  
STATE 0  
STATE 1  
STATE 2  
STATE 3  
STATE 4  
STATE 5  
STATE 6  
STATE 7  
STATE 8  
STATE 9  
STATE 10  
STATE 11  
STATE 12  
STATE 13  
STATE 14  
STATE 15  
–5  
–10  
–15  
–20  
–25  
–30  
–35  
–40  
–45  
–50  
–10  
–15  
–20  
–25  
–30  
–35  
STATE 0  
STATE 1  
STATE 2  
STATE 3  
STATE 4  
STATE 5  
STATE 6  
STATE 7  
STATE 8  
–40  
–45  
–50  
–55  
–60  
STATE 9  
STATE 10  
STATE 11  
STATE 12  
STATE 13  
STATE 14  
STATE 15  
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40  
RF FREQUENCY (GHz)  
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40  
RF FREQUENCY (GHz)  
Figure 29. Insertion Loss vs. RF Frequency, LPF 4 Configuration Swept  
LPF State  
Figure 26. Insertion Loss vs. RF Frequency, HPF 4 Configuration Swept  
HPF State  
0
HPF 3 STATE 2 + LPF 3 STATE 15  
–5  
–10  
–15  
–20  
–25  
–30  
–35  
–40  
–45  
–50  
–55  
–60  
HPF 3 STATE 3 + LPF 3 STATE 14  
HPF 3 STATE 4 + LPF 3 STATE 13  
HPF 3 STATE 5 + LPF 3 STATE 12  
HPF 3 STATE 6 + LPF 3 STATE 11  
HPF 3 STATE 7 + LPF 3 STATE 10  
HPF 3 STATE 8 + LPF 3 STATE 9  
HPF 3 STATE 9 + LPF 3 STATE 8  
HPF 3 STATE 10 + LPF 3 STATE 7  
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40  
RF FREQUENCY (GHz)  
Figure 27. Insertion Loss vs. RF Frequency, Center Frequency (fCENTER) = 10 GHz in  
Various 3 dB Bandwidth for HPF 3 and LPF 3 Configuration  
Rev. 0 | Page 13 of 36  
ADMV8818  
Data Sheet  
THEORY OF OPERATION  
CHIP ARCHITECTURE  
The ADMV8818 is a highly flexible filter that can achieve tunable  
band-pass, high-pass, low-pass, all pass, or all reject responses  
from 2 GHz to 18 GHz. Due to the flexible architecture of the  
ADMV8818 with four SP5T switches coupled with digitally  
tunable high-pass and low-pass filter arrays, the device provides  
full coverage over the frequency band without any dead zones.  
Figure 1 is a conceptual block diagram of the ADMV8818.  
GND  
GND  
GND  
GND  
GND  
GND  
RFIN  
GND  
GND  
GND  
GND  
GND  
GND  
RST  
1
2
3
4
5
6
42  
41  
40  
39  
38  
37  
GND  
VSS1 (–2.5V)  
GND  
BYPASS  
BYPASS  
VDD2 (+3.3V)  
GND  
1
2
3
4
1
2
3
4
GND  
7
36  
RFOUT  
GND  
8
9
35  
34  
33  
32  
31  
30  
29  
The ADMV8818 consists of two sections, the input and the output  
section. The input section has four high-pass filters and an optional  
bypass configuration that is selectable by the two SP5T RFIN  
switches. Similarly, the output section has four low-pass filters  
and an optional bypass configuration that is selectable by the two  
SP5T RFOUT switches. Because the input and output sections  
are independent from one another, the chip can be configured  
for any combination of high-pass filter, low-pass filter, or  
bypass configuration.  
GND  
10  
11  
12  
13  
14  
GND  
GND  
VDD1 (+2.5V)  
GND  
SPI  
GND  
Figure 31. ADMV8818 Configured for LPF 3  
The two SP5T RFIN switches are controlled simultaneously with a  
3-bit digital control. Likewise, the two SP5T RFOUT switches  
are controlled simultaneously with a 3-bit digital control. This  
control scheme creates a total of 25 possible combinations of  
switch settings, achieving many possible filter responses.  
Moreover, any of the high-pass filters can be coupled with any  
of the low-pass filters, achieving virtually no dead zones in the  
2 GHz to 18 GHz frequency range and a wide band-pass response.  
Figure 32 shows the conceptual block diagram of ADMV8818  
when HPF 3 and LPF 2 are selected.  
Figure 30 shows an example of the signal path when the two  
SP5T RFIN and two SP5T RFOUT switches are configured for  
the HPF 1 and LPF 1, respectively. Using this switch setting, a  
band-pass or a no pass response can be created in the 2 GHz to  
3.8 GHz frequency range, depending on the filter settings for  
the HPF 1 and LPF 1.  
GND  
GND  
GND  
GND  
GND  
GND  
RFIN  
GND  
GND  
GND  
GND  
GND  
GND  
RST  
1
2
3
4
5
6
42  
41  
40  
39  
38  
37  
GND  
VSS1 (–2.5V)  
GND  
BYPASS  
BYPASS  
VDD2 (+3.3V)  
GND  
1
2
3
4
1
2
3
4
GND  
7
36  
RFOUT  
GND  
8
9
35  
34  
33  
32  
31  
30  
29  
GND  
GND  
GND  
GND  
GND  
GND  
RFIN  
GND  
GND  
GND  
GND  
GND  
GND  
RST  
1
2
3
4
5
6
42  
41  
40  
39  
38  
37  
GND  
GND  
VSS1 (–2.5V)  
GND  
10  
11  
12  
13  
14  
GND  
BYPASS  
BYPASS  
GND  
VDD2 (+3.3V)  
GND  
VDD1 (+2.5V)  
GND  
1
2
1
2
GND  
SPI  
GND  
7
36  
RFOUT  
GND  
8
9
35  
34  
33  
32  
31  
30  
29  
GND  
3
4
3
4
10  
11  
12  
13  
14  
GND  
GND  
Figure 32. ADMV8818 Configured for HPF 3 and LPF 2  
VDD1 (+2.5V)  
GND  
TUNABLE HIGH-PASS FILTERS  
SPI  
GND  
Figure 33 shows a simplified schematic of the HPF 1, which is a  
Chebyshev type filter. The f3dB can be adjusted by varying  
Capacitor C1 to Capacitor C4. These tunable capacitors are  
constructed with 4-bit digital capacitor arrays, providing 16  
distinct values. The step size of these tunable capacitors is  
adjusted so that each digital binary code increment creates  
Figure 30. ADMV8818 Configured for HPF 1 and LPF 1  
Similarly, any of the filters can be bypassed, creating a low-pass  
or a high-pass response, as shown in Figure 31, where the HPF  
is bypassed and LPF 3 filter is selected. This configuration enables a  
tunable LPF response in the 8 GHz to 12 GHz frequency range.  
approximately the same increment in the f3dB  
.
Rev. 0 | Page 14 of 36  
 
 
 
 
 
 
Data Sheet  
ADMV8818  
C1  
C2  
C3  
C4  
CS  
An active low input on  
CS  
starts and gates a communication  
RFIN  
RFOUT  
cycle. The  
the same serial communications lines. The SDO pin goes to a  
CS  
pin allows more than one device to be used on  
L1  
L2  
L3  
high impedance state when the  
input is high. During the  
Figure 33. HPF 1 Simplified Schematic  
communication cycle, the chip select must stay low. The SPI  
communications protocol follows the Analog Devices SPI  
standard. For more information, see the ADI-SPI Serial  
Control Interface Standard (Rev 1.0).  
The HPF 2, HPF 3, and HPF 4 filters share the same architecture as  
the HPF 1 filter. However, the filter order is increased with respect  
to the frequency to achieve a similar rejection response for all  
filters.  
RF CONNECTIONS  
TUNABLE LOW-PASS FILTERS  
The RFIN and RFOUT pins of the ADMV8818 are dc-coupled  
to on-chip RF switches. If a dc voltage is present on the RFIN  
and RFOUT pins from other components within the system, it  
is recommended to place dc blocking capacitors in series with  
these pins. The dc blocking capacitors must be selected based  
on the operating frequency of the filter. Generally, a value  
greater than 100 pF is sufficient to minimize insertion loss at  
the lower frequencies of operation. At higher frequencies of  
operation, it may be necessary to consider the parasitic elements of  
the selected capacitor. Figure 35 shows a general model of a  
capacitor with the parasitic elements. The parasitic series  
inductance (LESL) is typically of most concern given that its  
impedance can become dominant at frequencies above 10 GHz.  
The other parasitic elements, including the leakage resistance  
(RL), the dielectric absorption resistance (RDA), the dielectric  
Figure 34 shows a simplified schematic of the LPF 1, which is a  
Chebyshev type filter. The f3dB can be adjusted by varying  
Capacitor C1 to Capacitor C4. These tunable capacitors are  
constructed with 4-bit digital capacitor arrays, providing 16  
distinct values. The step size of these tunable capacitors is  
adjusted so that each digital binary code increment creates  
approximately the same increment in the f3dB  
.
L1  
L2  
L3  
RFIN  
RFOUT  
C1  
C2  
C3  
C4  
Figure 34. LPF 1 Simplified Schematic  
The LPF 2, LPF 3, and LPF 4 filters share the same architecture as  
the LPF 1 filter. However, the filter order is increased with respect  
to the frequency to achieve a similar rejection response for all  
filters.  
absorption capacitance (CDA), and electrical series resistance (RESR  
)
are less critical elements for consideration but are shown here for  
completeness.  
R
L
SPI CONFIGURATION  
L
R
ESL  
ESR  
C
The SPI of the ADMV8818 allows configuration of the device  
for specific functions or operations via the 5-pin SPI port. This  
interface provides users with added flexibility and customization.  
The SPI consists of five control lines: SFL, SCLK, SDI, SDO,  
R
DA  
C
DA  
Figure 35. General Model of a Capacitor  
CS  
and . For normal SPI operations, keep the SFL pin low.  
MODE SELECTION  
The SPI protocol consists of an R/W bit followed by 15 register  
address bits and 8 data bits. The address field and data field are  
organized MSB first and end with the LSB.  
The ADMV8818 has two modes of operation: SPI write and SPI  
fast latch. SPI write mode is the normal operating mode,  
whereas SPI fast latch mode is used to sequence through the  
on-chip lookup table (LUT) using the internal state machine.  
To select SPI write mode, set the SFL pin low. For operation in  
SPI fast latch mode, program the on-chip lookup table and fast  
latch parameters with the SFL pin low, and then bring the SFL  
pin high to enter this mode. Figure 36 shows a simplified  
representation of the SPI with the register map and internal  
state machine.  
Set the MSB to 0 for a write operation and set the MSB to 1 for a  
read operation. The write cycle must be sampled on the rising  
edge of SCLK. The 24 bits of the serial write address and data are  
shifted in on the SDI control line, MSB to LSB. The ADMV8818  
input logic level for the write cycle supports a 3.3 V interface.  
For a read cycle, the R/W bit and the 15 register address bits  
shift in on the rising edge of SCLK on the SDI control line. Then,  
8 bits of serial read data shift out on the SDO control line, MSB  
first, on the falling edge of SCLK. The output logic level for a  
read cycle is 3.3 V. The output drivers of the SDO are enabled  
after the last rising edge of SCLK of the instruction cycle and  
remain active until the end of the read cycle. In a read operation,  
REGISTER MAP  
INTERNAL STATE  
MACHINE  
SCLK  
SDO  
SDI  
PARAMETERS AND  
LOOKUP TABLE  
START LOCATION  
...  
STOP LOCATION  
WR  
CS  
FILTERS  
when is deasserted, SDO returns to high impedance until the  
CS  
CS  
next read transaction.  
is active low and must be deasserted  
SFL  
at the end of the write or read sequence.  
Figure 36. Simplified SPI Diagram  
Rev. 0 | Page 15 of 36  
 
 
 
 
 
 
 
 
ADMV8818  
Data Sheet  
An example of the priority order for an SPI streaming transaction  
follows: if the switch set bits are high for both WR1 and WR2, the  
resulting switch positions are the positions programmed in WR1.  
SPI WRITE MODE  
SPI write mode has five write groupings, WR0 through WR4 in  
Register 0x020 through Register 0x029. The groupings can be  
thought of as a small lookup table for SPI write mode. Each  
grouping consists of the following:  
For SPI single instruction transactions, the most recently  
programmed RFIN switch set and RFOUT switch set takes  
effect to move the switch positions. To use SPI single instruction  
transactions, the switch register must be written first followed  
by the filter setting register. For example, to use write grouping  
WR0, Register 0x020 is written first using a 24-bit transaction  
(R/W bit + 15 address bits + 8 data bits, followed by writing  
Register 0x021 also using a 24-bit transaction.  
•
•
•
•
•
•
RFIN switch position  
RFIN switch set  
RFOUT switch position  
RFOUT switch set  
HPF state  
LPF state  
FREQUENCY TERMINOLOGY  
See the Register Details section for an example of the write  
grouping of WR0 (Register 0x020 and Register 0x021).  
Because the ADMV8818 is designed to operate over a wide  
frequency range, there is frequency dependent insertion loss  
that results in a negative slope vs. frequency. Additionally,  
depending upon the selected filter and the state, there may also  
be ripple within the pass band. Given these characteristics, a proper  
SWITCH POSITIONS  
The RFIN switch position dictates where the HPF state bits are  
assigned, and the RFOUT switch position dictates where the  
LPF state bits are assigned. For example, in the WR0_SW write  
group (Register 0x020), when SW_IN_WR0 is set for Band 1 and  
SW_OUT_WR0 is set for Band 2, HPF_WR0 and LPF_WR0  
(Register 0x021) are applied to HPF 1 and LPF 2, respectively.  
definition is necessary to establish a reference frequency (fREF  
)
from which the f3dB for each filter can be computed.  
Analog Devices has found that a consistent methodology  
for determining the fREF and f3dB is to rely on the group delay  
performance of a filter. The following is the methodology used  
for determining the ADMV8818 specifications:  
SWITCH SET  
The RFIN switch set bit is used to determine if the RFIN switch  
position is moved to that setting. Similarly, the RFOUT switch  
set bit is used to determine if the RFOUT switch position is moved  
to that setting. This functionality is useful for configuring a filter to  
a known state and leaving the switch position unchanged (switch  
set bits low). For most applications, the switch set bits are high.  
1. Find the peak group delay (GDPEAK) and peak group delay  
frequency (fPEAK) as the filter insertion loss (S21) begins to  
roll off.  
2. For a low-pass filter, divide fPEAK by 2 to find the average  
frequency (fAVG). For a high-pass filter, multiply fPEAK by 2.  
Once fAVG is calculated, determine the group delay at this  
frequency. Generally, the group delay is flat and approximately  
equal to the average at this particular frequency (fAVG).  
3. Take the mathematical mean of the group delay from Step 1  
and Step 2 to find the reference group delay (GDREF), and  
then find the corresponding fREF and reference insertion  
loss (ILREF) for this group delay.  
FILTER SETTINGS  
Each high-pass filter and low-pass filter contains 16 states (4 bits).  
A value of zero corresponds to setting the f3dB of the filter to its  
lowest possible frequency. Conversely, a value of 15 corresponds to  
setting the f3dB of the filter to its highest possible frequency.  
WRITE GROUP PRIORITY  
4. Subtract 3 dB from the ILREF to find the 3 dB insertion loss  
In SPI write mode, because there are five write groupings, it is  
possible that multiple RFIN switch set bits or RFOUT switch  
set bits are high. The behavior of the switches depends on the  
type of SPI transaction, either streaming or single instruction.  
(IL3dB), and then find the corresponding f3dB  
.
SPI FAST LATCH MODE  
The ADMV8818 has a 128 state lookup table and an internal  
state machine that is useful for quickly changing filter states in  
SPI fast latch mode. When the SFL pin is high, SPI fast latch  
mode is enabled, and the internal state machine sequences on  
In general, there are two types of SPI streaming transactions,  
Endian register ascending order and descending order. The  
ADMV8818 supports the ascending order only. To enable SPI  
streaming with Endian register ascending order, program  
Register 0x000 to 0x3C.  
CS  
each rising edge of the  
pin.  
The lookup table has 128 groupings, LUT0 through LUT127, in  
Register 0x100 through Register 0x1FF. Each grouping consists  
of the same type of parameters as those of SPI write mode.  
For SPI streaming transactions (recommended), the priority  
order for the RFIN switch set bits and the RFOUT switch set  
bits is WR0 to WR4.  
The functionality of the switch positions and filter state bits for  
SPI fast latch mode is similar to those of SPI write mode. That is,  
the filter state bits are assigned based on the switch position bits.  
However, the switch set parameters do not contain any priority.  
The SPI streaming transaction for Register 0x020 to Register 0x029  
then points to Address 0x020 and streams out 10 bytes of data.  
The SPI streaming transaction is 96 bits in total (R/W bit +  
15 address bits + 80 data bits).  
Rev. 0 | Page 16 of 36  
 
 
 
 
 
 
 
Data Sheet  
ADMV8818  
If the RFIN switch set bits and RFOUT switch set bits are  
enabled for a particular LUT, the switch positions change.  
the stop location to the start location and then rolls over to the  
stop location.  
The functionality of the internal state machine is such that on  
The FAST_LATCH_STATE value can fall outside of the start  
and stop locations, which occurs if the start and stop locations  
are updated and the internal pointer is left unchanged from its  
prior value. If this situation occurs, additional LUT groupings  
are selected before the FAST_LATCH_STATE value eventually  
falls within the start and stop locations. For example, if the FAST_  
LATCH_STATE value is 12, the direction is incremental, the start  
location is 15, and the stop location is 31, the LUT groupings  
CS  
each rising edge of the pin, the internal state machine sequences  
a pointer based on the programmed direction. The internal  
state machine has the following parameters:  
•
•
•
•
•
•
FAST_LATCH_POINTER (Register 0x010)  
FAST_LATCH_LOAD (Register 0x010)  
FAST_LATCH_STOP (Register 0x011)  
FAST_LATCH_START (Register 0x012)  
FAST_LATCH_DIRECTION (Register 0x013)  
FAST_LATCH_STATE (Register 0x014)  
CS  
selected on the next six rising edges of the  
pin are the LUT  
grouping numbers, 12, 13, 14, 15, 16, and 17.  
CHIP RESET  
The FAST_LATCH_STATE is the next LUT grouping that is  
There are two methods that can be used to reset the ADMV8818  
registers to their default power-on state, a hard reset and a soft  
CS  
selected on the next rising edge of the pin. The FAST_LATCH_  
STATE is considered the internal pointer location.  
RST  
reset. The hard reset utilizes the  
utilizes Register 0x000.  
pin, and the soft reset  
The internal pointer location can be changed by using the FAST_  
LATCH_LOAD and FAST_LATCH_POINTER bits. When the  
FAST_LATCH_LOAD bit is set high, the FAST_LATCH_  
POINTER value is loaded into the internal pointer. The FAST_  
LATCH_LOAD bit is self resetting after the load operation  
completes.  
RST  
To perform a hard reset, momentarily bring the  
and then high. See Figure 2 for the minimum required duration  
RST  
pin low  
time for the  
pin to be low.  
To perform a soft reset, program Register 0x000 to a value of 0x81.  
This action sets the SOFTRESET and SOFTRESET_ bits high to  
initiate the reset. The SOFTRESET and SOFTRESET_ bits are  
self resetting once the reset operation is complete.  
When the FAST_LATCH_DIRECTION bit is set to zero, the  
sequencing direction is incremental. When the FAST_LATCH_  
DIRECTION bit is set to one, the sequencing direction is  
decremental.  
Regardless of the reset method used, it is recommended to  
perform the following after the chip resets:  
The FAST_LATCH_START and FAST_LATCH_STOP bits are  
used to set the start and stop location, respectively. For incremental  
direction, the internal state machine sequences from the start  
location to the stop location and then rolls over to the start  
location. For the decremental direction, the sequence is from  
•
Program Register 0x000 to 0x3C to enable the SDO pin  
and allow SPI streaming with Endian ascending order.  
Read back all registers on the chip.  
•
Rev. 0 | Page 17 of 36  
 
ADMV8818  
Data Sheet  
APPLICATIONS INFORMATION  
of the transmission lines to the RFIN and RFOUT pins of the  
ADMV8818 must be carefully controlled to 50 Ω to ensure  
optimal RF performance. Connect the GND pins and exposed  
pads of the ADMV8818 directly to the ground plane of the PCB.  
Use a sufficient number of via holes to connect the top and bottom  
ground planes of the PCB.  
PCB DESIGN GUIDELINES  
The PCB used to implement the ADMV8818 must use a high  
quality dielectric material between the top metallization layer  
and internal ground layer, such as the Rogers 4003 or the  
Rogers 4350. All other dielectric layers of the PCB can be standard  
material, such as the Isola 370HR. The characteristic impedance  
Rev. 0 | Page 18 of 36  
 
 
Data Sheet  
ADMV8818  
PROGRAMMING FLOW CHART  
0 5 4 2 5 6  
Figure 37. Programming Flow Chart  
Rev. 0 | Page 19 of 36  
 
ADMV8818  
Data Sheet  
REGISTER SUMMARY  
Table 6. ADMV8818 Register Summary  
Reg  
Name  
Bits  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
Reset  
R/W  
0x000  
ADI_SPI_  
[7:0]  
SOFTRESET_  
LSB_FIRST_  
ENDIAN_  
SDOACTIVE_  
SDOACTIVE  
ENDIAN  
LSB_FIRST  
SOFTRESET  
0x00  
R/W  
CONFIG_A  
0x001  
ADI_SPI_  
CONFIG_B  
[7:0]  
SINGLE_  
INSTRUCTION  
CSB_STALL  
MASTER_  
SLAVE_RB  
RESERVED  
MASTER_  
SLAVE_  
0x00  
R/W  
TRANSFER  
0x003  
0x004  
0x005  
0x010  
CHIPTYPE  
[7:0]  
[7:0]  
[7:0]  
[7:0]  
CHIPTYPE  
0x01  
0x18  
0x88  
0x00  
R
PRODUCT_ID_L  
PRODUCT_ID_H  
PRODUCT_ID_L  
PRODUCT_ID_H  
R
R
FAST_LATCH_  
POINTER  
FAST_  
LATCH_  
LOAD  
FAST_LATCH_POINTER  
R/W  
0x011  
0x012  
0x013  
FAST_LATCH_  
STOP  
[7:0]  
[7:0]  
[7:0]  
RESERVED  
FAST_LATCH_STOP  
FAST_LATCH_START  
0x7F  
0x00  
0x00  
R/W  
R/W  
R/W  
FAST_LATCH_  
START  
RESERVED  
FAST_LATCH_  
DIRECTION  
RESERVED  
FAST_  
LATCH_  
DIRECTION  
0x014  
0x020  
FAST_LATCH_  
STATE  
[7:0]  
[7:0]  
RESERVED  
FAST_LATCH_STATE  
0x00  
0x00  
R
WR0_SW  
SW_IN_  
SET_WR0  
SW_OUT_  
SET_WR0  
SW_IN_WR0  
SW_IN_WR1  
SW_IN_WR2  
SW_IN_WR3  
SW_IN_WR4  
SW_IN_0  
SW_OUT_WR0  
R/W  
0x021  
0x022  
WR0_FILTER  
WR1_SW  
[7:0]  
[7:0]  
HPF_WR0  
LPF_WR0  
SW_OUT_WR1  
0x00  
0x00  
R/W  
R/W  
SW_IN_  
SET_WR1  
SW_OUT_  
SET_WR1  
0x023  
0x024  
WR1_FILTER  
WR2_SW  
[7:0]  
[7:0]  
HPF_WR1  
LPF_WR1  
SW_OUT_WR2  
0x00  
0x00  
R/W  
R/W  
SW_IN_  
SET_WR2  
SW_OUT_  
SET_WR2  
0x025  
0x026  
WR2_FILTER  
WR3_SW  
[7:0]  
[7:0]  
HPF_WR2  
LPF_WR2  
SW_OUT_WR3  
0x00  
0x00  
R/W  
R/W  
SW_IN_  
SET_WR3  
SW_OUT_  
SET_WR3  
0x027  
0x028  
WR3_FILTER  
WR4_SW  
[7:0]  
[7:0]  
HPF_WR3  
LPF_WR3  
SW_OUT_WR4  
0x00  
0x00  
R/W  
R/W  
SW_IN_  
SET_WR4  
SW_OUT_  
SET_WR4  
0x029  
0x100  
WR4_FILTER  
LUT0_SW  
[7:0]  
[7:0]  
HPF_WR4  
LPF_WR4  
SW_OUT_0  
0x00  
0x00  
R/W  
R/W  
SW_IN_  
SET_0  
SW_OUT_  
SET_0  
0x101  
0x102  
LUT0_FILTER  
LUT1_SW  
[7:0]  
[7:0]  
HPF_0  
HPF_1  
HPF_2  
HPF_3  
HPF_4  
HPF_5  
HPF_6  
HPF_7  
HPF_8  
HPF_9  
LPF_0  
SW_OUT_1  
0x00  
0x00  
R/W  
R/W  
SW_IN_  
SET_1  
SW_OUT_  
SET_1  
SW_IN_1  
0x103  
0x104  
LUT1_FILTER  
LUT2_SW  
[7:0]  
[7:0]  
LPF_1  
SW_OUT_2  
0x00  
0x00  
R/W  
R/W  
SW_IN_  
SET_2  
SW_OUT_  
SET_2  
SW_IN_2  
0x105  
0x106  
LUT2_FILTER  
LUT3_SW  
[7:0]  
[7:0]  
LPF_2  
SW_OUT_3  
0x00  
0x00  
R/W  
R/W  
SW_IN_  
SET_3  
SW_OUT_  
SET_3  
SW_IN_3  
0x107  
0x108  
LUT3_FILTER  
LUT4_SW  
[7:0]  
[7:0]  
LPF_3  
SW_OUT_4  
0x00  
0x00  
R/W  
R/W  
SW_IN_  
SET_4  
SW_OUT_  
SET_4  
SW_IN_4  
0x109  
0x10A  
LUT4_FILTER  
LUT5_SW  
[7:0]  
[7:0]  
LPF_4  
SW_OUT_5  
0x00  
0x00  
R/W  
R/W  
SW_IN_  
SET_5  
SW_OUT_  
SET_5  
SW_IN_5  
0x10B  
0x10C  
LUT5_FILTER  
LUT6_SW  
[7:0]  
[7:0]  
LPF_5  
SW_OUT_6  
0x00  
0x00  
R/W  
R/W  
SW_IN_  
SET_6  
SW_OUT_  
SET_6  
SW_IN_6  
0x10D  
0x10E  
LUT6_FILTER  
LUT7_SW  
[7:0]  
[7:0]  
LPF_6  
SW_OUT_7  
0x00  
0x00  
R/W  
R/W  
SW_IN_  
SET_7  
SW_OUT_  
SET_7  
SW_IN_7  
0x10F  
0x110  
LUT7_FILTER  
LUT8_SW  
[7:0]  
[7:0]  
LPF_7  
SW_OUT_8  
0x00  
0x00  
R/W  
R/W  
SW_IN_  
SET_8  
SW_OUT_  
SET_8  
SW_IN_8  
0x111  
0x112  
LUT8_FILTER  
LUT9_SW  
[7:0]  
[7:0]  
LPF_8  
SW_OUT_9  
0x00  
0x00  
R/W  
R/W  
SW_IN_  
SET_9  
SW_OUT_  
SET_9  
SW_IN_9  
0x113  
LUT9_FILTER  
[7:0]  
LPF_9  
0x00  
R/W  
Rev. 0 | Page 20 of 36  
 
 
Data Sheet  
ADMV8818  
Reg  
Name  
Bits  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
SW_IN_10  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
Reset  
R/W  
0x114  
LUT10_SW  
[7:0]  
SW_IN_  
SET_10  
SW_OUT_  
SET_10  
SW_OUT_10  
0x00  
R/W  
0x115  
0x116  
LUT10_FILTER  
LUT11_SW  
[7:0]  
[7:0]  
HPF_10  
LPF_10  
SW_OUT_11  
0x00  
0x00  
R/W  
R/W  
SW_IN_  
SET_11  
SW_OUT_  
SET_11  
SW_IN_11  
SW_IN_12  
SW_IN_13  
SW_IN_14  
SW_IN_15  
SW_IN_16  
SW_IN_17  
SW_IN_18  
SW_IN_19  
SW_IN_20  
SW_IN_21  
SW_IN_22  
SW_IN_23  
SW_IN_24  
SW_IN_25  
SW_IN_26  
SW_IN_27  
SW_IN_28  
SW_IN_29  
SW_IN_30  
SW_IN_31  
SW_IN_32  
0x117  
0x118  
LUT11_FILTER  
LUT12_SW  
[7:0]  
[7:0]  
HPF_11  
LPF_11  
SW_OUT_12  
0x00  
0x00  
R/W  
R/W  
SW_IN_  
SET_12  
SW_OUT_  
SET_12  
0x119  
0x11A  
LUT12_FILTER  
LUT13_SW  
[7:0]  
[7:0]  
HPF_12  
LPF_12  
SW_OUT_13  
0x00  
0x00  
R/W  
R/W  
SW_IN_  
SET_13  
SW_OUT_  
SET_13  
0x11B  
0x11C  
LUT13_FILTER  
LUT14_SW  
[7:0]  
[7:0]  
HPF_13  
LPF_13  
SW_OUT_14  
0x00  
0x00  
R/W  
R/W  
SW_IN_  
SET_14  
SW_OUT_  
SET_14  
0x11D  
0x11E  
LUT14_FILTER  
LUT15_SW  
[7:0]  
[7:0]  
HPF_14  
LPF_14  
SW_OUT_15  
0x00  
0x00  
R/W  
R/W  
SW_IN_  
SET_15  
SW_OUT_  
SET_15  
0x11F  
0x120  
LUT15_FILTER  
LUT16_SW  
[7:0]  
[7:0]  
HPF_15  
LPF_15  
SW_OUT_16  
0x00  
0x00  
R/W  
R/W  
SW_IN_  
SET_16  
SW_OUT_  
SET_16  
0x121  
0x122  
LUT16_FILTER  
LUT17_SW  
[7:0]  
[7:0]  
HPF_16  
LPF_16  
SW_OUT_17  
0x00  
0x00  
R/W  
R/W  
SW_IN_  
SET_17  
SW_OUT_  
SET_17  
0x123  
0x124  
LUT17_FILTER  
LUT18_SW  
[7:0]  
[7:0]  
HPF_17  
LPF_17  
SW_OUT_18  
0x00  
0x00  
R/W  
R/W  
SW_IN_  
SET_18  
SW_OUT_  
SET_18  
0x125  
0x126  
LUT18_FILTER  
LUT19_SW  
[7:0]  
[7:0]  
HPF_18  
LPF_18  
SW_OUT_19  
0x00  
0x00  
R/W  
R/W  
SW_IN_  
SET_19  
SW_OUT_  
SET_19  
0x127  
0x128  
LUT19_FILTER  
LUT20_SW  
[7:0]  
[7:0]  
HPF_19  
LPF_19  
SW_OUT_20  
0x00  
0x00  
R/W  
R/W  
SW_IN_  
SET_20  
SW_OUT_  
SET_20  
0x129  
0x12A  
LUT20_FILTER  
LUT21_SW  
[7:0]  
[7:0]  
HPF_20  
LPF_20  
SW_OUT_21  
0x00  
0x00  
R/W  
R/W  
SW_IN_  
SET_21  
SW_OUT_  
SET_21  
0x12B  
0x12C  
LUT21_FILTER  
LUT22_SW  
[7:0]  
[7:0]  
HPF_21  
LPF_21  
SW_OUT_22  
0x00  
0x00  
R/W  
R/W  
SW_IN_  
SET_22  
SW_OUT_  
SET_22  
0x12D  
0x12E  
LUT22_FILTER  
LUT23_SW  
[7:0]  
[7:0]  
HPF_22  
LPF_22  
SW_OUT_23  
0x00  
0x00  
R/W  
R/W  
SW_IN_  
SET_23  
SW_OUT_  
SET_23  
0x12F  
0x130  
LUT23_FILTER  
LUT24_SW  
[7:0]  
[7:0]  
HPF_23  
LPF_23  
SW_OUT_24  
0x00  
0x00  
R/W  
R/W  
SW_IN_  
SET_24  
SW_OUT_  
SET_24  
0x131  
0x132  
LUT24_FILTER  
LUT25_SW  
[7:0]  
[7:0]  
HPF_24  
LPF_24  
SW_OUT_25  
0x00  
0x00  
R/W  
R/W  
SW_IN_  
SET_25  
SW_OUT_  
SET_25  
0x133  
0x134  
LUT25_FILTER  
LUT26_SW  
[7:0]  
[7:0]  
HPF_25  
LPF_25  
SW_OUT_26  
0x00  
0x00  
R/W  
R/W  
SW_IN_  
SET_26  
SW_OUT_  
SET_26  
0x135  
0x136  
LUT26_FILTER  
LUT27_SW  
[7:0]  
[7:0]  
HPF_26  
LPF_26  
SW_OUT_27  
0x00  
0x00  
R/W  
R/W  
SW_IN_  
SET_27  
SW_OUT_  
SET_27  
0x137  
0x138  
LUT27_FILTER  
LUT28_SW  
[7:0]  
[7:0]  
HPF_27  
LPF_27  
SW_OUT_28  
0x00  
0x00  
R/W  
R/W  
SW_IN_  
SET_28  
SW_OUT_  
SET_28  
0x139  
0x13A  
LUT28_FILTER  
LUT29_SW  
[7:0]  
[7:0]  
HPF_28  
LPF_28  
SW_OUT_29  
0x00  
0x00  
R/W  
R/W  
SW_IN_  
SET_29  
SW_OUT_  
SET_29  
0x13B  
0x13C  
LUT29_FILTER  
LUT30_SW  
[7:0]  
[7:0]  
HPF_29  
LPF_29  
SW_OUT_30  
0x00  
0x00  
R/W  
R/W  
SW_IN_  
SET_30  
SW_OUT_  
SET_30  
0x13D  
0x13E  
LUT30_FILTER  
LUT31_SW  
[7:0]  
[7:0]  
HPF_30  
LPF_30  
SW_OUT_31  
0x00  
0x00  
R/W  
R/W  
SW_IN_  
SET_31  
SW_OUT_  
SET_31  
0x13F  
0x140  
LUT31_FILTER  
LUT32_SW  
[7:0]  
[7:0]  
HPF_31  
LPF_31  
SW_OUT_32  
0x00  
0x00  
R/W  
R/W  
SW_IN_  
SET_32  
SW_OUT_  
SET_32  
0x141  
LUT32_FILTER  
[7:0]  
HPF_32  
LPF_32  
0x00  
R/W  
Rev. 0 | Page 21 of 36  
ADMV8818  
Data Sheet  
Reg  
Name  
Bits  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
SW_IN_33  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
Reset  
R/W  
0x142  
LUT33_SW  
[7:0]  
SW_IN_  
SET_33  
SW_OUT_  
SET_33  
SW_OUT_33  
0x00  
R/W  
0x143  
0x144  
LUT33_FILTER  
LUT34_SW  
[7:0]  
[7:0]  
HPF_33  
LPF_33  
SW_OUT_34  
0x00  
0x00  
R/W  
R/W  
SW_IN_  
SET_34  
SW_OUT_  
SET_34  
SW_IN_34  
SW_IN_35  
SW_IN_36  
SW_IN_37  
SW_IN_38  
SW_IN_39  
SW_IN_40  
SW_IN_41  
SW_IN_42  
SW_IN_43  
SW_IN_44  
SW_IN_45  
SW_IN_46  
SW_IN_47  
SW_IN_48  
SW_IN_49  
SW_IN_50  
SW_IN_51  
SW_IN_52  
SW_IN_53  
SW_IN_54  
SW_IN_55  
0x145  
0x146  
LUT34_FILTER  
LUT35_SW  
[7:0]  
[7:0]  
HPF_34  
LPF_34  
SW_OUT_35  
0x00  
0x00  
R/W  
R/W  
SW_IN_  
SET_35  
SW_OUT_  
SET_35  
0x147  
0x148  
LUT35_FILTER  
LUT36_SW  
[7:0]  
[7:0]  
HPF_35  
LPF_35  
SW_OUT_36  
0x00  
0x00  
R/W  
R/W  
SW_IN_  
SET_36  
SW_OUT_  
SET_36  
0x149  
0x14A  
LUT36_FILTER  
LUT37_SW  
[7:0]  
[7:0]  
HPF_36  
LPF_36  
SW_OUT_37  
0x00  
0x00  
R/W  
R/W  
SW_IN_  
SET_37  
SW_OUT_  
SET_37  
0x14B  
0x14C  
LUT37_FILTER  
LUT38_SW  
[7:0]  
[7:0]  
HPF_37  
LPF_37  
SW_OUT_38  
0x00  
0x00  
R/W  
R/W  
SW_IN_  
SET_38  
SW_OUT_  
SET_38  
0x14D  
0x14E  
LUT38_FILTER  
LUT39_SW  
[7:0]  
[7:0]  
HPF_38  
LPF_38  
SW_OUT_39  
0x00  
0x00  
R/W  
R/W  
SW_IN_  
SET_39  
SW_OUT_  
SET_39  
0x14F  
0x150  
LUT39_FILTER  
LUT40_SW  
[7:0]  
[7:0]  
HPF_39  
LPF_39  
SW_OUT_40  
0x00  
0x00  
R/W  
R/W  
SW_IN_  
SET_40  
SW_OUT_  
SET_40  
0x151  
0x152  
LUT40_FILTER  
LUT41_SW  
[7:0]  
[7:0]  
HPF_40  
LPF_40  
SW_OUT_41  
0x00  
0x00  
R/W  
R/W  
SW_IN_  
SET_41  
SW_OUT_  
SET_41  
0x153  
0x154  
LUT41_FILTER  
LUT42_SW  
[7:0]  
[7:0]  
HPF_41  
LPF_41  
SW_OUT_42  
0x00  
0x00  
R/W  
R/W  
SW_IN_  
SET_42  
SW_OUT_  
SET_42  
0x155  
0x156  
LUT42_FILTER  
LUT43_SW  
[7:0]  
[7:0]  
HPF_42  
LPF_42  
SW_OUT_43  
0x00  
0x00  
R/W  
R/W  
SW_IN_  
SET_43  
SW_OUT_  
SET_43  
0x157  
0x158  
LUT43_FILTER  
LUT44_SW  
[7:0]  
[7:0]  
HPF_43  
LPF_43  
SW_OUT_44  
0x00  
0x00  
R/W  
R/W  
SW_IN_  
SET_44  
SW_OUT_  
SET_44  
0x159  
0x15A  
LUT44_FILTER  
LUT45_SW  
[7:0]  
[7:0]  
HPF_44  
LPF_44  
SW_OUT_45  
0x00  
0x00  
R/W  
R/W  
SW_IN_  
SET_45  
SW_OUT_  
SET_45  
0x15B  
0x15C  
LUT45_FILTER  
LUT46_SW  
[7:0]  
[7:0]  
HPF_45  
LPF_45  
SW_OUT_46  
0x00  
0x00  
R/W  
R/W  
SW_IN_  
SET_46  
SW_OUT_  
SET_46  
0x15D  
0x15E  
LUT46_FILTER  
LUT47_SW  
[7:0]  
[7:0]  
HPF_46  
LPF_46  
SW_OUT_47  
0x00  
0x00  
R/W  
R/W  
SW_IN_  
SET_47  
SW_OUT_  
SET_47  
0x15F  
0x160  
LUT47_FILTER  
LUT48_SW  
[7:0]  
[7:0]  
HPF_47  
LPF_47  
SW_OUT_48  
0x00  
0x00  
R/W  
R/W  
SW_IN_  
SET_48  
SW_OUT_  
SET_48  
0x161  
0x162  
LUT48_FILTER  
LUT49_SW  
[7:0]  
[7:0]  
HPF_48  
LPF_48  
SW_OUT_49  
0x00  
0x00  
R/W  
R/W  
SW_IN_  
SET_49  
SW_OUT_  
SET_49  
0x163  
0x164  
LUT49_FILTER  
LUT50_SW  
[7:0]  
[7:0]  
HPF_49  
LPF_49  
SW_OUT_50  
0x00  
0x00  
R/W  
R/W  
SW_IN_  
SET_50  
SW_OUT_  
SET_50  
0x165  
0x166  
LUT50_FILTER  
LUT51_SW  
[7:0]  
[7:0]  
HPF_50  
LPF_50  
SW_OUT_51  
0x00  
0x00  
R/W  
R/W  
SW_IN_  
SET_51  
SW_OUT_  
SET_51  
0x167  
0x168  
LUT51_FILTER  
LUT52_SW  
[7:0]  
[7:0]  
HPF_51  
LPF_51  
SW_OUT_52  
0x00  
0x00  
R/W  
R/W  
SW_IN_  
SET_52  
SW_OUT_  
SET_52  
0x169  
0x16A  
LUT52_FILTER  
LUT53_SW  
[7:0]  
[7:0]  
HPF_52  
LPF_52  
SW_OUT_53  
0x00  
0x00  
R/W  
R/W  
SW_IN_  
SET_53  
SW_OUT_  
SET_53  
0x16B  
0x16C  
LUT53_FILTER  
LUT54_SW  
[7:0]  
[7:0]  
HPF_53  
LPF_53  
SW_OUT_54  
0x00  
0x00  
R/W  
R/W  
SW_IN_  
SET_54  
SW_OUT_  
SET_54  
0x16D  
0x16E  
LUT54_FILTER  
LUT55_SW  
[7:0]  
[7:0]  
HPF_54  
LPF_54  
SW_OUT_55  
0x00  
0x00  
R/W  
R/W  
SW_IN_  
SET_55  
SW_OUT_  
SET_55  
0x16F  
LUT55_FILTER  
[7:0]  
HPF_55  
LPF_55  
0x00  
R/W  
Rev. 0 | Page 22 of 36  
Data Sheet  
ADMV8818  
Reg  
Name  
Bits  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
SW_IN_56  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
Reset  
R/W  
0x170  
LUT56_SW  
[7:0]  
SW_IN_  
SET_56  
SW_OUT_  
SET_56  
SW_OUT_56  
0x00  
R/W  
0x171  
0x172  
LUT56_FILTER  
LUT57_SW  
[7:0]  
[7:0]  
HPF_56  
LPF_56  
SW_OUT_57  
0x00  
0x00  
R/W  
R/W  
SW_IN_  
SET_57  
SW_OUT_  
SET_57  
SW_IN_57  
SW_IN_58  
SW_IN_59  
SW_IN_60  
SW_IN_61  
SW_IN_62  
SW_IN_63  
SW_IN_64  
SW_IN_65  
SW_IN_66  
SW_IN_67  
SW_IN_68  
SW_IN_69  
SW_IN_70  
SW_IN_71  
SW_IN_72  
SW_IN_73  
SW_IN_74  
SW_IN_75  
SW_IN_76  
SW_IN_77  
SW_IN_78  
0x173  
0x174  
LUT57_FILTER  
LUT58_SW  
[7:0]  
[7:0]  
HPF_57  
LPF_57  
SW_OUT_58  
0x00  
0x00  
R/W  
R/W  
SW_IN_  
SET_58  
SW_OUT_  
SET_58  
0x175  
0x176  
LUT58_FILTER  
LUT59_SW  
[7:0]  
[7:0]  
HPF_58  
LPF_58  
SW_OUT_59  
0x00  
0x00  
R/W  
R/W  
SW_IN_  
SET_59  
SW_OUT_  
SET_59  
0x177  
0x178  
LUT59_FILTER  
LUT60_SW  
[7:0]  
[7:0]  
HPF_59  
LPF_59  
SW_OUT_60  
0x00  
0x00  
R/W  
R/W  
SW_IN_  
SET_60  
SW_OUT_  
SET_60  
0x179  
0x17A  
LUT60_FILTER  
LUT61_SW  
[7:0]  
[7:0]  
HPF_60  
LPF_60  
SW_OUT_61  
0x00  
0x00  
R/W  
R/W  
SW_IN_  
SET_61  
SW_OUT_  
SET_61  
0x17B  
0x17C  
LUT61_FILTER  
LUT62_SW  
[7:0]  
[7:0]  
HPF_61  
LPF_61  
SW_OUT_62  
0x00  
0x00  
R/W  
R/W  
SW_IN_  
SET_62  
SW_OUT_  
SET_62  
0x17D  
0x17E  
LUT62_FILTER  
LUT63_SW  
[7:0]  
[7:0]  
HPF_62  
LPF_62  
SW_OUT_63  
0x00  
0x00  
R/W  
R/W  
SW_IN_  
SET_63  
SW_OUT_  
SET_63  
0x17F  
0x180  
LUT63_FILTER  
LUT64_SW  
[7:0]  
[7:0]  
HPF_63  
LPF_63  
SW_OUT_64  
0x00  
0x00  
R/W  
R/W  
SW_IN_  
SET_64  
SW_OUT_  
SET_64  
0x181  
0x182  
LUT64_FILTER  
LUT65_SW  
[7:0]  
[7:0]  
HPF_64  
LPF_64  
SW_OUT_65  
0x00  
0x00  
R/W  
R/W  
SW_IN_  
SET_65  
SW_OUT_  
SET_65  
0x183  
0x184  
LUT65_FILTER  
LUT66_SW  
[7:0]  
[7:0]  
HPF_65  
LPF_65  
SW_OUT_66  
0x00  
0x00  
R/W  
R/W  
SW_IN_  
SET_66  
SW_OUT_  
SET_66  
0x185  
0x186  
LUT66_FILTER  
LUT67_SW  
[7:0]  
[7:0]  
HPF_66  
LPF_66  
SW_OUT_67  
0x00  
0x00  
R/W  
R/W  
SW_IN_  
SET_67  
SW_OUT_  
SET_67  
0x187  
0x188  
LUT67_FILTER  
LUT68_SW  
[7:0]  
[7:0]  
HPF_67  
LPF_67  
SW_OUT_68  
0x00  
0x00  
R/W  
R/W  
SW_IN_  
SET_68  
SW_OUT_  
SET_68  
0x189  
0x18A  
LUT68_FILTER  
LUT69_SW  
[7:0]  
[7:0]  
HPF_68  
LPF_68  
SW_OUT_69  
0x00  
0x00  
R/W  
R/W  
SW_IN_  
SET_69  
SW_OUT_  
SET_69  
0x18B  
0x18C  
LUT69_FILTER  
LUT70_SW  
[7:0]  
[7:0]  
HPF_69  
LPF_69  
SW_OUT_70  
0x00  
0x00  
R/W  
R/W  
SW_IN_  
SET_70  
SW_OUT_  
SET_70  
0x18D  
0x18E  
LUT70_FILTER  
LUT71_SW  
[7:0]  
[7:0]  
HPF_70  
LPF_70  
SW_OUT_71  
0x00  
0x00  
R/W  
R/W  
SW_IN_  
SET_71  
SW_OUT_  
SET_71  
0x18F  
0x190  
LUT71_FILTER  
LUT72_SW  
[7:0]  
[7:0]  
HPF_71  
LPF_71  
SW_OUT_72  
0x00  
0x00  
R/W  
R/W  
SW_IN_  
SET_72  
SW_OUT_  
SET_72  
0x191  
0x192  
LUT72_FILTER  
LUT73_SW  
[7:0]  
[7:0]  
HPF_72  
LPF_72  
SW_OUT_73  
0x00  
0x00  
R/W  
R/W  
SW_IN_  
SET_73  
SW_OUT_  
SET_73  
0x193  
0x194  
LUT73_FILTER  
LUT74_SW  
[7:0]  
[7:0]  
HPF_73  
LPF_73  
SW_OUT_74  
0x00  
0x00  
R/W  
R/W  
SW_IN_  
SET_74  
SW_OUT_  
SET_74  
0x195  
0x196  
LUT74_FILTER  
LUT75_SW  
[7:0]  
[7:0]  
HPF_74  
LPF_74  
SW_OUT_75  
0x00  
0x00  
R/W  
R/W  
SW_IN_  
SET_75  
SW_OUT_  
SET_75  
0x197  
0x198  
LUT75_FILTER  
LUT76_SW  
[7:0]  
[7:0]  
HPF_75  
LPF_75  
SW_OUT_76  
0x00  
0x00  
R/W  
R/W  
SW_IN_  
SET_76  
SW_OUT_  
SET_76  
0x199  
0x19A  
LUT76_FILTER  
LUT77_SW  
[7:0]  
[7:0]  
HPF_76  
LPF_76  
SW_OUT_77  
0x00  
0x00  
R/W  
R/W  
SW_IN_  
SET_77  
SW_OUT_  
SET_77  
0x19B  
0x19C  
LUT77_FILTER  
LUT78_SW  
[7:0]  
[7:0]  
HPF_77  
LPF_77  
SW_OUT_78  
0x00  
0x00  
R/W  
R/W  
SW_IN_  
SET_78  
SW_OUT_  
SET_78  
0x19D  
LUT78_FILTER  
[7:0]  
HPF_78  
LPF_78  
0x00  
R/W  
Rev. 0 | Page 23 of 36  
ADMV8818  
Data Sheet  
Reg  
Name  
Bits  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
SW_IN_79  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
Reset  
R/W  
0x19E  
LUT79_SW  
[7:0]  
SW_IN_  
SET_79  
SW_OUT_  
SET_79  
SW_OUT_79  
0x00  
R/W  
0x19F  
0x1A0  
LUT79_FILTER  
LUT80_SW  
[7:0]  
[7:0]  
HPF_79  
LPF_79  
SW_OUT_80  
0x00  
0x00  
R/W  
R/W  
SW_IN_  
SET_80  
SW_OUT_  
SET_80  
SW_IN_80  
SW_IN_81  
SW_IN_82  
SW_IN_83  
SW_IN_84  
SW_IN_85  
SW_IN_86  
SW_IN_87  
SW_IN_88  
SW_IN_89  
SW_IN_90  
SW_IN_91  
SW_IN_92  
SW_IN_93  
SW_IN_94  
SW_IN_95  
SW_IN_96  
SW_IN_97  
SW_IN_98  
SW_IN_99  
SW_IN_100  
SW_IN_101  
0x1A1  
0x1A2  
LUT80_FILTER  
LUT81_SW  
[7:0]  
[7:0]  
HPF_80  
LPF_80  
SW_OUT_81  
0x00  
0x00  
R/W  
R/W  
SW_IN_  
SET_81  
SW_OUT_  
SET_81  
0x1A3  
0x1A4  
LUT81_FILTER  
LUT82_SW  
[7:0]  
[7:0]  
HPF_81  
LPF_81  
SW_OUT_82  
0x00  
0x00  
R/W  
R/W  
SW_IN_  
SET_82  
SW_OUT_  
SET_82  
0x1A5  
0x1A6  
LUT82_FILTER  
LUT83_SW  
[7:0]  
[7:0]  
HPF_82  
LPF_82  
SW_OUT_83  
0x00  
0x00  
R/W  
R/W  
SW_IN_  
SET_83  
SW_OUT_  
SET_83  
0x1A7  
0x1A8  
LUT83_FILTER  
LUT84_SW  
[7:0]  
[7:0]  
HPF_83  
LPF_83  
SW_OUT_84  
0x00  
0x00  
R/W  
R/W  
SW_IN_  
SET_84  
SW_OUT_  
SET_84  
0x1A9  
0x1AA  
LUT84_FILTER  
LUT85_SW  
[7:0]  
[7:0]  
HPF_84  
LPF_84  
SW_OUT_85  
0x00  
0x00  
R/W  
R/W  
SW_IN_  
SET_85  
SW_OUT_  
SET_85  
0x1AB  
0x1AC  
LUT85_FILTER  
LUT86_SW  
[7:0]  
[7:0]  
HPF_85  
LPF_85  
SW_OUT_86  
0x00  
0x00  
R/W  
R/W  
SW_IN_  
SET_86  
SW_OUT_  
SET_86  
0x1AD  
0x1AE  
LUT86_FILTER  
LUT87_SW  
[7:0]  
[7:0]  
HPF_86  
LPF_86  
SW_OUT_87  
0x00  
0x00  
R/W  
R/W  
SW_IN_  
SET_87  
SW_OUT_  
SET_87  
0x1AF  
0x1B0  
LUT87_FILTER  
LUT88_SW  
[7:0]  
[7:0]  
HPF_87  
LPF_87  
SW_OUT_88  
0x00  
0x00  
R/W  
R/W  
SW_IN_  
SET_88  
SW_OUT_  
SET_88  
0x1B1  
0x1B2  
LUT88_FILTER  
LUT89_SW  
[7:0]  
[7:0]  
HPF_88  
LPF_88  
SW_OUT_89  
0x00  
0x00  
R/W  
R/W  
SW_IN_  
SET_89  
SW_OUT_  
SET_89  
0x1B3  
0x1B4  
LUT89_FILTER  
LUT90_SW  
[7:0]  
[7:0]  
HPF_89  
LPF_89  
SW_OUT_90  
0x00  
0x00  
R/W  
R/W  
SW_IN_  
SET_90  
SW_OUT_  
SET_90  
0x1B5  
0x1B6  
LUT90_FILTER  
LUT91_SW  
[7:0]  
[7:0]  
HPF_90  
LPF_90  
SW_OUT_91  
0x00  
0x00  
R/W  
R/W  
SW_IN_  
SET_91  
SW_OUT_  
SET_91  
0x1B7  
0x1B8  
LUT91_FILTER  
LUT92_SW  
[7:0]  
[7:0]  
HPF_91  
LPF_91  
SW_OUT_92  
0x00  
0x00  
R/W  
R/W  
SW_IN_  
SET_92  
SW_OUT_  
SET_92  
0x1B9  
0x1BA  
LUT92_FILTER  
LUT93_SW  
[7:0]  
[7:0]  
HPF_92  
LPF_92  
SW_OUT_93  
0x00  
0x00  
R/W  
R/W  
SW_IN_  
SET_93  
SW_OUT_  
SET_93  
0x1BB  
0x1BC  
LUT93_FILTER  
LUT94_SW  
[7:0]  
[7:0]  
HPF_93  
LPF_93  
SW_OUT_94  
0x00  
0x00  
R/W  
R/W  
SW_IN_  
SET_94  
SW_OUT_  
SET_94  
0x1BD  
0x1BE  
LUT94_FILTER  
LUT95_SW  
[7:0]  
[7:0]  
HPF_94  
LPF_94  
SW_OUT_95  
0x00  
0x00  
R/W  
R/W  
SW_IN_  
SET_95  
SW_OUT_  
SET_95  
0x1BF  
0x1C0  
LUT95_FILTER  
LUT96_SW  
[7:0]  
[7:0]  
HPF_95  
LPF_95  
SW_OUT_96  
0x00  
0x00  
R/W  
R/W  
SW_IN_  
SET_96  
SW_OUT_  
SET_96  
0x1C1  
0x1C2  
LUT96_FILTER  
LUT97_SW  
[7:0]  
[7:0]  
HPF_96  
LPF_96  
SW_OUT_97  
0x00  
0x00  
R/W  
R/W  
SW_IN_  
SET_97  
SW_OUT_  
SET_97  
0x1C3  
0x1C4  
LUT97_FILTER  
LUT98_SW  
[7:0]  
[7:0]  
HPF_97  
LPF_97  
SW_OUT_98  
0x00  
0x00  
R/W  
R/W  
SW_IN_  
SET_98  
SW_OUT_  
SET_98  
0x1C5  
0x1C6  
LUT98_FILTER  
LUT99_SW  
[7:0]  
[7:0]  
HPF_98  
LPF_98  
SW_OUT_99  
0x00  
0x00  
R/W  
R/W  
SW_IN_  
SET_99  
SW_OUT_  
SET_99  
0x1C7  
0x1C8  
LUT99_FILTER  
LUT100_SW  
[7:0]  
[7:0]  
HPF_99  
LPF_99  
SW_OUT_100  
0x00  
0x00  
R/W  
R/W  
SW_IN_  
SET_100  
SW_OUT_  
SET_100  
0x1C9  
0x1CA  
LUT100_FILTER  
LUT101_SW  
[7:0]  
[7:0]  
HPF_100  
LPF_100  
SW_OUT_101  
0x00  
0x00  
R/W  
R/W  
SW_IN_  
SET_101  
SW_OUT_  
SET_101  
0x1CB  
LUT101_FILTER  
[7:0]  
HPF_101  
LPF_101  
0x00  
R/W  
Rev. 0 | Page 24 of 36  
Data Sheet  
ADMV8818  
Reg  
Name  
Bits  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
SW_IN_102  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
Reset  
R/W  
0x1CC  
LUT102_SW  
[7:0]  
SW_IN_  
SET_102  
SW_OUT_  
SET_102  
SW_OUT_102  
0x00  
R/W  
0x1CD  
0x1CE  
LUT102_FILTER  
LUT103_SW  
[7:0]  
[7:0]  
HPF_102  
LPF_102  
SW_OUT_103  
0x00  
0x00  
R/W  
R/W  
SW_IN_  
SET_103  
SW_OUT_  
SET_103  
SW_IN_103  
SW_IN_104  
SW_IN_105  
SW_IN_106  
SW_IN_107  
SW_IN_108  
SW_IN_109  
SW_IN_110  
SW_IN_111  
SW_IN_112  
SW_IN_113  
SW_IN_114  
SW_IN_115  
SW_IN_116  
SW_IN_117  
SW_IN_118  
SW_IN_119  
SW_IN_120  
SW_IN_121  
SW_IN_122  
SW_IN_123  
SW_IN_124  
0x1CF  
0x1D0  
LUT103_FILTER  
LUT104_SW  
[7:0]  
[7:0]  
HPF_103  
LPF_103  
SW_OUT_104  
0x00  
0x00  
R/W  
R/W  
SW_IN_  
SET_104  
SW_OUT_  
SET_104  
0x1D1  
0x1D2  
LUT104_FILTER  
LUT105_SW  
[7:0]  
[7:0]  
HPF_104  
LPF_104  
SW_OUT_105  
0x00  
0x00  
R/W  
R/W  
SW_IN_  
SET_105  
SW_OUT_  
SET_105  
0x1D3  
0x1D4  
LUT105_FILTER  
LUT106_SW  
[7:0]  
[7:0]  
HPF_105  
LPF_105  
SW_OUT_106  
0x00  
0x00  
R/W  
R/W  
SW_IN_  
SET_106  
SW_OUT_  
SET_106  
0x1D5  
0x1D6  
LUT106_FILTER  
LUT107_SW  
[7:0]  
[7:0]  
HPF_106  
LPF_106  
SW_OUT_107  
0x00  
0x00  
R/W  
R/W  
SW_IN_  
SET_107  
SW_OUT_  
SET_107  
0x1D7  
0x1D8  
LUT107_FILTER  
LUT108_SW  
[7:0]  
[7:0]  
HPF_107  
LPF_107  
SW_OUT_108  
0x00  
0x00  
R/W  
R/W  
SW_IN_  
SET_108  
SW_OUT_  
SET_108  
0x1D9  
0x1DA  
LUT108_FILTER  
LUT109_SW  
[7:0]  
[7:0]  
HPF_108  
LPF_108  
SW_OUT_109  
0x00  
0x00  
R/W  
R/W  
SW_IN_  
SET_109  
SW_OUT_  
SET_109  
0x1DB  
0x1DC  
LUT109_FILTER  
LUT110_SW  
[7:0]  
[7:0]  
HPF_109  
LPF_109  
SW_OUT_110  
0x00  
0x00  
R/W  
R/W  
SW_IN_  
SET_110  
SW_OUT_  
SET_110  
0x1DD  
0x1DE  
LUT110_FILTER  
LUT111_SW  
[7:0]  
[7:0]  
HPF_110  
LPF_110  
SW_OUT_111  
0x00  
0x00  
R/W  
R/W  
SW_IN_  
SET_111  
SW_OUT_  
SET_111  
0x1DF  
0x1E0  
LUT111_FILTER  
LUT112_SW  
[7:0]  
[7:0]  
HPF_111  
LPF_111  
SW_OUT_112  
0x00  
0x00  
R/W  
R/W  
SW_IN_  
SET_112  
SW_OUT_  
SET_112  
0x1E1  
0x1E2  
LUT112_FILTER  
LUT113_SW  
[7:0]  
[7:0]  
HPF_112  
LPF_112  
SW_OUT_113  
0x00  
0x00  
R/W  
R/W  
SW_IN_  
SET_113  
SW_OUT_  
SET_113  
0x1E3  
0x1E4  
LUT113_FILTER  
LUT114_SW  
[7:0]  
[7:0]  
HPF_113  
LPF_113  
SW_OUT_114  
0x00  
0x00  
R/W  
R/W  
SW_IN_  
SET_114  
SW_OUT_  
SET_114  
0x1E5  
0x1E6  
LUT114_FILTER  
LUT115_SW  
[7:0]  
[7:0]  
HPF_114  
LPF_114  
SW_OUT_115  
0x00  
0x00  
R/W  
R/W  
SW_IN_  
SET_115  
SW_OUT_  
SET_115  
0x1E7  
0x1E8  
LUT115_FILTER  
LUT116_SW  
[7:0]  
[7:0]  
HPF_115  
LPF_115  
SW_OUT_116  
0x00  
0x00  
R/W  
R/W  
SW_IN_  
SET_116  
SW_OUT_  
SET_116  
0x1E9  
0x1EA  
LUT116_FILTER  
LUT117_SW  
[7:0]  
[7:0]  
HPF_116  
LPF_116  
SW_OUT_117  
0x00  
0x00  
R/W  
R/W  
SW_IN_  
SET_117  
SW_OUT_  
SET_117  
0x1EB  
0x1EC  
LUT117_FILTER  
LUT118_SW  
[7:0]  
[7:0]  
HPF_117  
LPF_117  
SW_OUT_118  
0x00  
0x00  
R/W  
R/W  
SW_IN_  
SET_118  
SW_OUT_  
SET_118  
0x1ED  
0x1EE  
LUT118_FILTER  
LUT119_SW  
[7:0]  
[7:0]  
HPF_118  
LPF_118  
SW_OUT_119  
0x00  
0x00  
R/W  
R/W  
SW_IN_  
SET_119  
SW_OUT_  
SET_119  
0x1EF  
0x1F0  
LUT119_FILTER  
LUT120_SW  
[7:0]  
[7:0]  
HPF_119  
LPF_119  
SW_OUT_120  
0x00  
0x00  
R/W  
R/W  
SW_IN_  
SET_120  
SW_OUT_  
SET_120  
0x1F1  
0x1F2  
LUT120_FILTER  
LUT121_SW  
[7:0]  
[7:0]  
HPF_120  
LPF_120  
SW_OUT_121  
0x00  
0x00  
R/W  
R/W  
SW_IN_  
SET_121  
SW_OUT_  
SET_121  
0x1F3  
0x1F4  
LUT121_FILTER  
LUT122_SW  
[7:0]  
[7:0]  
HPF_121  
LPF_121  
SW_OUT_122  
0x00  
0x00  
R/W  
R/W  
SW_IN_  
SET_122  
SW_OUT_  
SET_122  
0x1F5  
0x1F6  
LUT122_FILTER  
LUT123_SW  
[7:0]  
[7:0]  
HPF_122  
LPF_122  
SW_OUT_123  
0x00  
0x00  
R/W  
R/W  
SW_IN_  
SET_123  
SW_OUT_  
SET_123  
0x1F7  
0x1F8  
LUT123_FILTER  
LUT124_SW  
[7:0]  
[7:0]  
HPF_123  
LPF_123  
SW_OUT_124  
0x00  
0x00  
R/W  
R/W  
SW_IN_  
SET_124  
SW_OUT_  
SET_124  
0x1F9  
LUT124_FILTER  
[7:0]  
HPF_124  
LPF_124  
0x00  
R/W  
Rev. 0 | Page 25 of 36  
ADMV8818  
Data Sheet  
Reg  
Name  
Bits  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
SW_IN_125  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
Reset  
R/W  
0x1FA  
LUT125_SW  
[7:0]  
SW_IN_  
SET_125  
SW_OUT_  
SET_125  
SW_OUT_125  
0x00  
R/W  
0x1FB  
0x1FC  
LUT125_FILTER  
LUT126_SW  
[7:0]  
[7:0]  
HPF_125  
LPF_125  
SW_OUT_126  
0x00  
0x00  
R/W  
R/W  
SW_IN_  
SET_126  
SW_OUT_  
SET_126  
SW_IN_126  
SW_IN_127  
0x1FD  
0x1FE  
LUT126_FILTER  
LUT127_SW  
[7:0]  
[7:0]  
HPF_126  
LPF_126  
SW_OUT_127  
0x00  
0x00  
R/W  
R/W  
SW_IN_  
SET_127  
SW_OUT_  
SET_127  
0x1FF  
LUT127_FILTER  
[7:0]  
HPF_127  
LPF_127  
0x00  
R/W  
Rev. 0 | Page 26 of 36  
Data Sheet  
ADMV8818  
REGISTER DETAILS  
Note that the LUT1_SW to LUT127_FILTER bit fields functionality (Register 0x102 to Register 0x1FF) is identical to LUT0_SW and  
LUT0_FILTER bit fields functionality (Register 0x100 and Register 0x101). See Table 6 for the register address information.  
Address: 0x000, Reset: 0x00, Name: ADI_SPI_CONFIG_A  
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7] SOFTRESET_ (R/W)  
Soft Reset  
[0] SOFTRESET (R/W)  
Soft Reset  
[6] LSB_FIRST_ (R/W)  
LSB First  
[1] LSB_FIRST (R/W)  
LSB First  
[5] ENDIAN_ (R/W)  
Endian  
[2] ENDIAN (R/W)  
Endian  
[4] SDOACTIVE_ (R/W)  
SDO Active  
[3] SDOACTIVE (R/W)  
SDO Active  
Table 7. Bit Descriptions for ADI_SPI_CONFIG_A  
Bits  
Bit Name  
Description  
Reset  
Access  
7
SOFTRESET_  
Soft Reset.  
0x0  
R/W  
0: reset asserted.  
1: reset not asserted.  
LSB First.  
0: LSB first.  
1: MSB first.  
Endian.  
0: Little Endian.  
1: Big Endian.  
SDO Active.  
0: SDO inactive.  
1: SDO active.  
SDO Active.  
0: SDO inactive.  
1: SDO active.  
Endian.  
0: Little Endian.  
1: Big Endian.  
LSB First.  
6
5
4
3
2
1
0
LSB_FIRST_  
ENDIAN_  
0x0  
0x0  
0x0  
0x0  
0x0  
0x0  
0x0  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
SDOACTIVE_  
SDOACTIVE  
ENDIAN  
LSB_FIRST  
SOFTRESET  
0: LSB first.  
1: MSB first.  
Soft Reset.  
0: Reset asserted.  
1: Reset not asserted.  
Rev. 0 | Page 27 of 36  
 
ADMV8818  
Data Sheet  
Address: 0x001, Reset: 0x00, Name: ADI_SPI_CONFIG_B  
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7] SINGLE_INSTRUCTION (R/W)  
Single Instruction  
[0] MASTER_SLAVE_TRANSFER (R/W)  
Master Slave Transfer  
[6] CSB_STALL (R/W)  
[4:1] RESERVED  
CS Stall  
[5] MASTER_SLAVE_RB (R/W)  
Master Slave Readback  
Table 8. Bit Descriptions for ADI_SPI_CONFIG_B  
Bits  
Bit Name  
Description  
Reset  
Access  
7
SINGLE_INSTRUCTION  
Single Instruction.  
0x0  
R/W  
0: enable streaming.  
1: disable streaming (regardless of CS).  
CS Stall.  
6
CSB_STALL  
0x0  
0x0  
0x0  
0x0  
R/W  
R/W  
R
5
[4:1]  
0
MASTER_SLAVE_RB  
RESERVED  
MASTER_SLAVE_TRANSFER  
Master Slave Readback.  
Reserved.  
Master Slave Transfer.  
R/W  
Address: 0x003, Reset: 0x01, Name: CHIPTYPE  
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
1
[7:0] CHIPTYPE (R)  
Chip Type, Read Only  
Table 9. Bit Descriptions for CHIPTYPE  
Bits  
[7:0]  
Bit Name  
CHIPTYPE  
Description  
Chip Type, Read Only.  
Reset  
0x1  
Access  
R
Address: 0x004, Reset: 0x18, Name: PRODUCT_ID_L  
7
6
5
4
3
2
1
0
0
0
0
1
1
0
0
0
[7:0] PRODUCT_ID_L (R)  
Product_ID_L, Lower 8 Bits  
Table 10. Bit Descriptions for PRODUCT_ID_L  
Bits  
Bit Name  
Description  
Reset  
Access  
[7:0]  
PRODUCT_ID_L  
Product_ID_L, Lower 8 Bits.  
0x18  
R
Address: 0x005, Reset: 0x88, Name: PRODUCT_ID_H  
7
6
5
4
3
2
1
0
1
0
0
0
1
0
0
0
[7:0] PRODUCT_ID_H (R)  
Product_ID_H, Higher 8 Bits  
Table 11. Bit Descriptions for PRODUCT_ID_H  
Bits  
Bit Name  
Description  
Reset  
Access  
[7:0]  
PRODUCT_ID_H  
Product_ID_H, Higher 8 Bits.  
0x88  
R
Rev. 0 | Page 28 of 36  
Data Sheet  
ADMV8818  
Address: 0x010, Reset: 0x00, Name: FAST_LATCH_POINTER  
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7] FAST_LATCH_LOAD (R/W)  
Fast Latch Load  
[6:0] FAST_LATCH_POINTER (R/W)  
Fast Latch Pointer  
Table 12. Bit Descriptions for FAST_LATCH_POINTER  
Bits Bit Name Description  
FAST_LATCH_LOAD  
Reset Access  
7
Fast Latch Load. Loads the pointer location into the internal state machine for fast  
latch mode. The FAST_LATCH_LOAD bit self resets to zero.  
0x0  
R/W  
[6:0] FAST_LATCH_POINTER Fast Latch Pointer. Determines the pointer location within the fast latch lookup table.  
0x0  
R/W  
Address: 0x011, Reset: 0x7F, Name: FAST_LATCH_STOP  
7
6
5
4
3
2
1
0
0
1
1
1
1
1
1
1
[7] RESERVED  
[6:0] FAST_LATCH_STOP (R/W)  
Fast Latch Stop Index  
Table 13. Bit Descriptions for FAST_LATCH_STOP  
Bits  
7
Bit Name  
RESERVED  
Description  
Reserved.  
Reset  
0x0  
Access  
R
[6:0]  
FAST_LATCH_STOP  
Fast Latch Stop Index. Sets the stop index within the fast latch lookup table.  
0x7F  
R/W  
Address: 0x012, Reset: 0x00, Name: FAST_LATCH_START  
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7] RESERVED  
[6:0] FAST_LATCH_START (R/W)  
Fast Latch Start Index  
Table 14. Bit Descriptions for FAST_LATCH_START  
Bits Bit Name  
Description  
Reset Access  
7
RESERVED  
Reserved.  
0x0  
0x0  
R
R/W  
[6:0] FAST_LATCH_START Fast Latch Start Index. Sets the start index within the fast latch lookup table. Note that,  
when exiting and then re-entering fast latch mode (SFL pin), the internal state machine  
resumes where it left off and not at the start index. If a new start index is programmed, it  
may be necessary to sequence through a number of states from the point at which the  
state machine left off. This action is necessary for a positive incremental direction. For a  
negative decremental direction, this action is necessary for the stop index.  
Address: 0x013, Reset: 0x00, Name: FAST_LATCH_DIRECTION  
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:1] RESERVED  
[0] FAST_LATCH_DIRECTION (R/W)  
Fast Latch Direction  
Table 15. Bit Descriptions for FAST_LATCH_DIRECTION  
Bits Bit Name  
Description  
Reset Access  
[7:1] RESERVED  
Reserved.  
0x0  
0x0  
R
R/W  
0
FAST_LATCH_DIRECTION Fast Latch Direction. Determines which direction to sequence within the fast latch  
lookup table.  
0: increment.  
1: decrement.  
Rev. 0 | Page 29 of 36  
ADMV8818  
Data Sheet  
Address: 0x014, Reset: 0x00, Name: FAST_LATCH_STATE  
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7] RESERVED  
[6:0] FAST_LATCH_STATE (R)  
Fast Latch State  
Table 16. Bit Descriptions for FAST_LATCH_STATE  
Bits Bit Name  
Description  
Reset Access  
7
RESERVED  
Reserved.  
0x0  
0x0  
R
R
[6:0] FAST_LATCH_STATE Fast Latch State. Reads back the internal state machine pointer.  
Address: 0x020, Reset: 0x00, Name: WR0_SW  
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7] SW_IN_SET_WR0 (R/W)  
Write Group 0: RF Input Switch Set  
[2:0] SW_OUT_WR0 (R/W)  
Write Group 0: RF Output Switch Position  
[6] SW_OUT_SET_WR0 (R/W)  
Write Group 0: RF Output Switch Set  
[5:3] SW_IN_WR0 (R/W)  
Write Group 0: RF Input Switch Position  
Table 17. Bit Descriptions for WR0_SW  
Bits Bit Name Description  
Reset Access  
7
6
SW_IN_SET_WR0  
SW_OUT_SET_WR0  
Write Group 0: RF Input Switch Set. Sets the switch position to be as defined in Bits[5:3].  
Write Group 0: RF Output Switch Set. Sets the switch position to be as defined in Bits[2:0].  
Write Group 0: RF Input Switch Position. Defines the RF input switch position, as well as  
which filter band is adjusted by the corresponding HPF state bits.  
0x0  
0x0  
0x0  
R/W  
R/W  
R/W  
[5:3] SW_IN_WR0  
000: bypass.  
001: Band 1.  
010: Band 2.  
011: Band 3.  
100: Band 4.  
[2:0] SW_OUT_WR0  
Write Group 0: RF Output Switch Position. Defines the RF output switch position, as well  
as which filter band is adjusted by the corresponding LPF state bits.  
0x0  
R/W  
000: bypass.  
001: Band 1.  
010: Band 2.  
011: Band 3.  
100: Band 4.  
Address: 0x021, Reset: 0x00, Name: WR0_FILTER  
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:4] HPF_WR0 (R/W)  
Write Group 0: HPF State  
[3:0] LPF_WR0 (R/W)  
Write Group 0: LPF State  
Table 18. Bit Descriptions for WR0_FILTER  
Bits Bit Name  
[7:4] HPF_WR0  
[3:0] LPF_WR0  
Description  
Reset Access  
Write Group 0: HPF State. The selected band is determined by the WR0_SW register, Bits[5:3].  
Write Group 0: LPF State. The selected band is determined by the WR0_SW register, Bits[2:0].  
0x0  
0x0  
R/W  
R/W  
Rev. 0 | Page 30 of 36  
Data Sheet  
ADMV8818  
Address: 0x022, Reset: 0x00, Name: WR1_SW  
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7] SW_IN_SET_WR1 (R/W)  
Write Group 1: RF Input Switch Set  
[2:0] SW_OUT_WR1 (R/W)  
Write Group 1: RF Output Switch Position  
[6] SW_OUT_SET_WR1 (R/W)  
Write Group 1: RF Output Switch Set  
[5:3] SW_IN_WR1 (R/W)  
Write Group 1: RF Input Switch Position  
Table 19. Bit Descriptions for WR1_SW  
Bits Bit Name Description  
Reset Access  
7
6
SW_IN_SET_WR1  
SW_OUT_SET_WR1  
Write Group 1: RF Input Switch Set. Sets the switch position to be as defined in Bits[5:3].  
Write Group 1: RF Output Switch Set. Sets the switch position to be as defined in Bits[2:0].  
Write Group 1: RF Input Switch Position. Defines the RF input switch position, as well as  
which filter band is adjusted by the corresponding HPF state bits.  
0x0  
0x0  
0x0  
R/W  
R/W  
R/W  
[5:3] SW_IN_WR1  
000: Bypass.  
001: Band 1.  
010: Band 2.  
011: Band 3.  
100: Band 4.  
[2:0] SW_OUT_WR1  
Write Group 1: RF Output Switch Position. Defines the RF output switch position, as well  
as which filter band is adjusted by the corresponding LPF state bits.  
0x0  
R/W  
000: bypass.  
001: Band 1.  
010: Band 2.  
011: Band 3.  
100: Band 4.  
Address: 0x023, Reset: 0x00, Name: WR1_FILTER  
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:4] HPF_WR1 (R/W)  
Write Group 1: HPF State  
[3:0] LPF_WR1 (R/W)  
Write Group 1: LPF State  
Table 20. Bit Descriptions for WR1_FILTER  
Bits Bit Name  
[7:4] HPF_WR1  
[3:0] LPF_WR1  
Description  
Reset Access  
Write Group 1: HPF State. The selected band is determined by the WR1_SW register, Bits[5:3].  
Write Group 1: LPF State. The selected band is determined by the WR1_SW register, Bits[2:0].  
0x0  
0x0  
R/W  
R/W  
Rev. 0 | Page 31 of 36  
ADMV8818  
Data Sheet  
Address: 0x024, Reset: 0x00, Name: WR2_SW  
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7] SW_IN_SET_WR2 (R/W)  
Write Group 2: RF Input Switch Set  
[2:0] SW_OUT_WR2 (R/W)  
Write Group 2: RF Output Switch Position  
[6] SW_OUT_SET_WR2 (R/W)  
Write Group 2: RF Output Switch Set  
[5:3] SW_IN_WR2 (R/W)  
Write Group 2: RF Input Switch Position  
Table 21. Bit Descriptions for WR2_SW  
Bits Bit Name Description  
Reset Access  
7
6
SW_IN_SET_WR2  
SW_OUT_SET_WR2  
Write Group 2: RF Input Switch Set. Sets the switch position to be as defined in Bits[5:3].  
Write Group 2: RF Output Switch Set. Sets the switch position to be as defined in Bits[2:0].  
Write Group 2: RF Input Switch Position. Defines the RF input switch position, as well as  
which filter band is adjusted by the corresponding HPF state bits.  
0x0  
0x0  
0x0  
R/W  
R/W  
R/W  
[5:3] SW_IN_WR2  
000: bypass.  
001: Band 1.  
010: Band 2.  
011: Band 3.  
100: Band 4.  
[2:0] SW_OUT_WR2  
Write Group 2: RF Output Switch Position. Defines the RF output switch position, as well  
as which filter band is adjusted by the corresponding LPF state bits.  
0x0  
R/W  
000: bypass.  
001: Band 1.  
010: Band 2.  
011: Band 3.  
100: Band 4.  
Address: 0x025, Reset: 0x00, Name: WR2_FILTER  
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:4] HPF_WR2 (R/W)  
Write Group 2: HPF State  
[3:0] LPF_WR2 (R/W)  
Write Group 2: LPF State  
Table 22. Bit Descriptions for WR2_FILTER  
Bits Bit Name  
[7:4] HPF_WR2  
[3:0] LPF_WR2  
Description  
Reset Access  
Write Group 2: HPF State. The selected band is determined by the WR2_SW register, Bits[5:3].  
Write Group 2: LPF State. The selected band is determined by the WR2_SW register, Bits[2:0].  
0x0  
0x0  
R/W  
R/W  
Rev. 0 | Page 32 of 36  
Data Sheet  
ADMV8818  
Address: 0x026, Reset: 0x00, Name: WR3_SW  
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7] SW_IN_SET_WR3 (R/W)  
Write Group 3: RF Input Switch Set  
[2:0] SW_OUT_WR3 (R/W)  
Write Group 3: RF Output Switch Position  
[6] SW_OUT_SET_WR3 (R/W)  
Write Group 3: RF Output Switch Set  
[5:3] SW_IN_WR3 (R/W)  
Write Group 3: RF Input Switch Position  
Table 23. Bit Descriptions for WR3_SW  
Bits Bit Name Description  
Reset Access  
7
6
SW_IN_SET_WR3  
SW_OUT_SET_WR3  
Write Group 3: RF Input Switch Set. Sets the switch position to be as defined in Bits[5:3].  
Write Group 3: RF Output Switch Set. Sets the switch position to be as defined in Bits[2:0].  
Write Group 3: RF Input Switch Position. Defines the RF input switch position, as well as  
which filter band is adjusted by the corresponding HPF state bits.  
0x0  
0x0  
0x0  
R/W  
R/W  
R/W  
[5:3] SW_IN_WR3  
000: bypass.  
001: Band 1.  
010: Band 2.  
011: Band 3.  
100: Band 4.  
[2:0] SW_OUT_WR3  
Write Group 3: RF Output Switch Position. Defines the RF output switch position, as well  
as which filter band is adjusted by the corresponding LPF state bits.  
0x0  
R/W  
000: bypass.  
001: Band 1.  
010: Band 2.  
011: Band 3.  
100: Band 4.  
Address: 0x027, Reset: 0x00, Name: WR3_FILTER  
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:4] HPF_WR3 (R/W)  
Write Group 3: HPF State  
[3:0] LPF_WR3 (R/W)  
Write Group 3: LPF State  
Table 24. Bit Descriptions for WR3_FILTER  
Bits Bit Name  
[7:4] HPF_WR3  
[3:0] LPF_WR3  
Description  
Reset Access  
Write Group 3: HPF State. The selected band is determined by the WR3_SW register, Bits[5:3].  
Write Group 3: LPF State. The selected band is determined by the WR3_SW register, Bits[2:0].  
0x0  
0x0  
R/W  
R/W  
Rev. 0 | Page 33 of 36  
ADMV8818  
Data Sheet  
Address: 0x028, Reset: 0x00, Name: WR4_SW  
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7] SW_IN_SET_WR4 (R/W)  
Write Group 4: RF Input Switch Set  
[2:0] SW_OUT_WR4 (R/W)  
Write Group 4: RF Output Switch Position  
[6] SW_OUT_SET_WR4 (R/W)  
Write Group 4: RF Output Switch Set  
[5:3] SW_IN_WR4 (R/W)  
Write Group 4: RF Input Switch Position  
Table 25. Bit Descriptions for WR4_SW  
Bits Bit Name Description  
Reset Access  
7
6
SW_IN_SET_WR4  
SW_OUT_SET_WR4  
Write Group 4: RF Input Switch Set. Sets the switch position to be as defined in Bits[5:3].  
Write Group 4: RF Output Switch Set. Sets the switch position to be as defined in Bits[2:0].  
Write Group 4: RF Input Switch Position. Defines the RF input switch position, as well as  
which filter band is adjusted by the corresponding HPF state bits.  
0x0  
0x0  
0x0  
R/W  
R/W  
R/W  
[5:3] SW_IN_WR4  
000: bypass.  
001: Band 1.  
010: Band 2.  
011: Band 3.  
100: Band 4.  
[2:0] SW_OUT_WR4  
Write Group 4: RF Output Switch Position. Defines the RF output switch position, as well  
as which filter band is adjusted by the corresponding LPF state bits.  
0x0  
R/W  
000: bypass.  
001: Band 1.  
010: Band 2.  
011: Band 3.  
100: Band 4.  
Address: 0x029, Reset: 0x00, Name: WR4_FILTER  
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:4] HPF_WR4 (R/W)  
Write Group 4: HPF State  
[3:0] LPF_WR4 (R/W)  
Write Group 4: LPF State  
Table 26. Bit Descriptions for WR4_FILTER  
Bits Bit Name  
[7:4] HPF_WR4  
[3:0] LPF_WR4  
Description  
Reset Access  
Write Group 4: HPF State. The selected band is determined by the WR4_SW register, Bits[5:3].  
Write Group 4: LPF State. The selected band is determined by the WR4_SW register, Bits[2:0].  
0x0  
0x0  
R/W  
R/W  
Rev. 0 | Page 34 of 36  
Data Sheet  
ADMV8818  
Address: 0x100, Reset: 0x00, Name: LUT0_SW  
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7] SW_IN_SET_0 (R/W)  
LUT 000: RF Input Switch Set  
[2:0] SW_OUT_0 (R/W)  
LUT 000: RF Output Switch Position  
[6] SW_OUT_SET_0 (R/W)  
LUT 000: RF Output Switch Set  
[5:3] SW_IN_0 (R/W)  
LUT 000: RF Input Switch Position  
Table 27. Bit Descriptions for LUT0_SW  
Bits Bit Name Description  
Reset Access  
7
6
SW_IN_SET_0  
LUT 000: RF Input Switch Set. Sets the switch position to be as defined in Bits[5:3].  
0x0  
0x0  
0x0  
R/W  
R/W  
R/W  
SW_OUT_SET_0 LUT 000: RF Output Switch Set. Sets the switch position to be as defined in Bits[2:0].  
[5:3] SW_IN_0  
LUT 000: RF Input Switch Position. Defines the RF input switch position, as well as which filter  
band is adjusted by the corresponding HPF state bits.  
000: bypass.  
001: Band 1.  
010: Band 2.  
011: Band 3.  
100: Band 4.  
[2:0] SW_OUT_0  
LUT 000: RF Output Switch Position. Defines the RF output switch position, as well as which  
filter band is adjusted by the corresponding LPF state bits.  
0x0  
R/W  
000: bypass.  
001: Band 1.  
010: Band 2.  
011: Band 3.  
100: Band 4.  
Address: 0x101, Reset: 0x00, Name: LUT0_FILTER  
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:4] HPF_0 (R/W)  
LUT 000: HPF State  
[3:0] LPF_0 (R/W)  
LUT 000: LPF State  
Table 28. Bit Descriptions for LUT0_FILTER  
Bits  
[7:4]  
[3:0]  
Bit Name  
HPF_0  
LPF_0  
Description  
Reset  
0x0  
0x0  
Access  
R/W  
R/W  
LUT 000: HPF State. The selected band is determined by the LUT0_SW register, Bits[5:3].  
LUT 000: LPF State. The selected band is determined by the LUT0_SW register, Bits[2:0].  
Rev. 0 | Page 35 of 36  
ADMV8818  
Data Sheet  
OUTLINE DIMENSIONS  
9.15  
9.00 SQ  
8.85  
3.181  
3.151 SQ  
3.121  
0.28  
0.25  
PIN 1  
INDICATOR  
AREA  
0.22  
PIN 1  
INDICATOR  
43  
56  
42  
1
0.28  
0.25 SQ  
0.22  
6.50 REF  
SQ  
0.50  
BSC  
29  
14  
1.25 REF  
28  
15  
0.68  
0.65  
0.62  
TOP VIEW  
SIDE VIEW  
BOTTOM VIEW  
0.10  
REF  
1.03  
0.97  
0.91  
0.53  
REF  
FOR PROPER CONNECTION OF  
THE EXPOSED PADS, REFER TO  
THE PIN CONFIGURATION AND  
FUNCTION DESCRIPTIONS  
0.478  
0.438  
0.398  
SECTION OF THIS DATA SHEET.  
SEATING  
PLANE  
Figure 38. 56-Terminal Land Grid Array [LGA]  
9 mm × 9 mm Body and 0.97 mm Package Height  
(CC-56-3)  
Dimensions shown in millimeters  
ORDERING GUIDE  
Model1  
Temperature Range  
Package Description  
Package Option  
CC-56-3  
ADMV8818SCCZ-EP  
ADMV8818-EVALZ  
−55°C to +105°C  
56-Terminal Land Grid Array [LGA]  
Evaluation Board  
1 Z = RoHS Compliant Part.  
©2020 Analog Devices, Inc. All rights reserved. Trademarks and  
registered trademarks are the property of their respective owners.  
D25603-12/20(0)  
Rev. 0 | Page 36 of 36  
 
 

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