ADN2530YCPZ-REEL7 [ADI]
11.3 Gbps, Active Back-Termination, Differential VCSEL Driver; 11.3 Gbps的，主动背向端接，差分VCSEL驱动器
| 型号： | ADN2530YCPZ-REEL7 |
| 厂家： | 
ADI |
| 描述： | 11.3 Gbps, Active Back-Termination, Differential VCSEL Driver |
| 文件： | 总20页 (文件大小：424K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
11.3 Gbps, Active Back-Termination,
Differential VCSEL Driver
ADN2530
FEATURES
GENERAL DESCRIPTION
Up to 11.3 Gbps operation
−40°C to +100°C operation
Very low power: ISUPPLY = 65 mA
Typical 26 ps rise/fall times
Full back-termination of output transmission lines
Crosspoint adjust function
PECL-/CML-compatible data inputs
Bias current range: 2 mA to 25 mA
Differential modulation current range: 2.2 mA to 23 mA
Automatic laser shutdown (ALS)
3.3 V operation
Compact 3 mm × 3 mm LFCSP
Voltage-input control for bias and modulation currents
XFP-compliant bias current monitor
The ADN2530 laser diode driver is designed for direct modula-
tion of packaged VCSELs with a differential resistance ranging
from 35 Ω to 140 Ω. The active back-termination technique
provides excellent matching with the output transmission lines
while reducing the power dissipation in the output stage. The
back-termination in the ADN2530 absorbs signal reflections
from the TOSA end of the output transmission lines, enabling
excellent optical eye quality to be achieved even when the
TOSA end of the output transmission lines is significantly
misterminated. The small package provides the optimum
solution for compact modules where laser diodes are packaged
in low pin count optical subassemblies.
The modulation and bias currents are programmable via the
MSET and BSET control pins. By driving these pins with
control voltages, the user has the flexibility to implement
various average power and extinction ratio control schemes,
including closed-loop control and look-up tables. The eye
crosspoint in the output eye diagram is adjustable via the
crosspoint adjust (CPA) control voltage input. The automatic
laser shutdown (ALS) feature allows the user to turn on/off the
bias and modulation currents by driving the ALS pin with the
proper logic levels. The product is available in a space-saving
3 mm × 3 mm LFCSP specified from −40°C to +100°C.
APPLICATIONS
10 Gb Ethernet optical transceivers
10G-BASE-LRM optical transceivers
8× and 10× Fibre Channel optical transceivers
XFP/X2/XENPAK/MSA 300 optical modules
SONET OC-192/SDH STM-64 optical transceivers
FUNCTIONAL BLOCK DIAGRAM
VCC
CPA
ALS
VCC
ADN2530
VCC
IMODP
IMODN
50Ω
50Ω
100Ω
IMOD
VCC
GND
DATAP
DATAN
CROSS
POINT
ADJUST
IBMON
IBIAS
800Ω
800Ω
200Ω
200Ω
200Ω
10Ω
MSET
GND
BSET
Figure 1.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2006 Analog Devices, Inc. All rights reserved.
ADN2530
TABLE OF CONTENTS
Features .............................................................................................. 1
Automatic Laser Shutdown (ALS) ........................................... 11
Modulation Current................................................................... 11
Load Mistermination................................................................. 13
Crosspoint Adjust....................................................................... 13
Power Consumption .................................................................. 13
Applications Information.............................................................. 15
Typical Application Circuit....................................................... 15
Layout Guidelines....................................................................... 15
Design Example.......................................................................... 16
Headroom Calculations ........................................................ 16
BSET and MSET Pin Voltage Calculation .......................... 16
IBIAS Monitor Accuracy Calculations................................ 17
Outline Dimensions....................................................................... 18
Ordering Guide .......................................................................... 18
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Package Thermal Specifications ................................................. 4
Absolute Maximum Ratings............................................................ 5
ESD Caution.................................................................................. 5
Pin Configuration and Function Descriptions............................. 6
Typical Performance Characteristics ............................................. 7
Theory of Operation ...................................................................... 10
Input Stage................................................................................... 10
Bias Current ................................................................................ 10
REVISION HISTORY
8/06—Rev. 0 to Rev. A
Changes to Figure 1.......................................................................... 1
Changes to Table 3............................................................................ 5
Changes to Figure 24...................................................................... 10
Changes to Figure 30...................................................................... 11
Changes to Modulation Current Section .................................... 12
Changes to Typical Application Circuit Section......................... 15
10/05—Revision 0: Initial Version
Rev. A | Page 2 of 20
ADN2530
SPECIFICATIONS
VCC = VCCMIN to VCCMAX, TA = −40°C to +100°C, 100 Ω differential load impedance, crosspoint adjust disabled, unless otherwise noted.
Typical values are specified at 25°C and IMOD = 10 mA with crosspoint adjust disabled, unless otherwise noted.
Table 1.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
BIAS CURRENT (IBIAS)
Bias Current Range
Bias Current While ALS Asserted
Compliance Voltage1
2
25
50
VCC – 1.3
VCC – 0.8
mA
μA
V
ALS = high
IBIAS = 25 mA
IBIAS = 2 mA
0.55
0.55
V
MODULATION CURRENT (IMODP, IMODN)
Modulation Current Range
2.2
2.2
23
19
mA diff
mA diff
μA diff
%
ps
ps
RLOAD = 35 Ω to 100 Ω differential
RLOAD = 140 Ω differential
ALS = high
Modulation Current While ALS Asserted
Crosspoint Adjust (CPA) Range2
Rise Time (20% to 80%)2, 3, 4
250
65
32.5
34.7
32.5
33.7
35
26
26.4
26
26.5
<0.5
<0.5
5.4
5.8
5.4
5.8
−5
CPA disabled
CPA 35% to 65%
CPA disabled
CPA 35% to 65%
CPA disabled
CPA 35% to 65%
10.7 Gbps, CPA disabled
10.7 Gbps, CPA 35% to 65%
11.3 Gbps, CPA disabled
11.3 Gbps, CPA 35% to 65%
5 GHz < f < 10 GHz, Z0 = 100 Ω differential
f < 5 GHz, Z0 = 100 Ω differential
Fall Time (20% to 80%)2, 3, 4
Random Jitter2, 3, 4
ps
ps
ps rms
ps rms
ps p-p
ps p-p
ps p-p
ps p-p
dB
Deterministic Jitter2, 4, 5
Deterministic Jitter 2, 4, 6
Differential |S22|
8.2
8.2
8.2
8.2
−13.6
dB
Compliance Voltage1
DATA INPUTS (DATAP, DATAN)
Input Data Rate
Differential Input Swing
Differential |S11|
Input Termination Resistance
BIAS CONTROL INPUT (BSET)
BSET Voltage to IBIAS Gain
BSET Input Resistance
VCC − 0.7
VCC + 0.7
V
11.3
1.6
Gbps
NRZ
0.4
85
V p-p diff Differential ac-coupled
dB
Ω
−15
100
f < 10 GHz, Z0 = 100 Ω differential
Differential
115
15
800
20
1000
24
1200
mA/V
Ω
MODULATION CONTROL INPUT (MSET)
MSET Voltage to IMOD Gain
MSET Input Resistance
14
800
19
1000
23
1200
mA/V
Ω
BIAS MONITOR (IBMON)
IBMON to IBIAS Ratio
50
μA/mA
Accuracy of IBIAS to IBMON Ratio
−5.0
−4.3
−3.5
−3.0
−2.5
+5.0
+4.3
+3.5
+3.0
+2.5
%
%
%
%
%
IBIAS = 2 mA, RIBMON = 750 Ω
IBIAS = 4 mA, RIBMON = 750 Ω
IBIAS = 8 mA, RIBMON = 750 Ω
IBIAS = 14 mA, RIBMON = 750 Ω
IBIAS = 25 mA, RIBMON = 750 Ω
AUTOMATIC LASER SHUTDOWN (ALS)
VIH
VIL
IIL
2.4
V
V
μA
μA
0.8
+20
200
−20
0
IIH
Rev. A | Page 3 of 20
ADN2530
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
ALS Assert Time
2
μs
Rising edge of ALS to fall of IBIAS and IMOD
below 10% of nominal; see Figure 2
ALS Negate Time
10
μs
Falling edge of ALS to rise of IBIAS and IMOD
above 90% of nominal; see Figure 2
POWER SUPPLY
VCC
3.07
3.3
27
65
3.53
32
76
V
mA
mA
7
ICC
VBSET = VMSET = 0 V
VBSET = VMSET = 0 V
8
ISUPPLY
1 The voltage between the pin with the specified compliance voltage and GND.
2 Specified for TA = −40°C to +85°C due to test equipment limitation. See the Typical Performance Characteristics section for data on performance for TA = −40°C to +100°C.
3 The pattern used is composed of a repetitive sequence of eight 1s followed by eight 0s at 10.7 Gbps.
4 Measured using the high speed characterization circuit shown in Figure 3.
5 The pattern used is K28.5 (00111110101100000101) at 10.7 Gbps rate.
6 The pattern used is K28.5 (00111110101100000101) at 11.3 Gbps rate.
7 Only includes current in the ADN2530 VCC pins.
8 Includes current in ADN2530 VCC pins and dc current in IMODP and IMODN pull-up inductors. See the Power Consumption section for total supply current calculation.
PACKAGE THERMAL SPECIFICATIONS
Table 2.
Parameter
Min
65
2.6
Typ
72.2
5.8
Max
79.4
10.7
125
Unit
°C/W
°C/W
°C
Conditions/Comments
θJ-TOP
θJ-PAD
Thermal resistance from junction to top of package.
Thermal resistance from junction to bottom of exposed pad.
IC Junction Temperature
ALS
NEGATE TIME
ALS
t
IBIAS
AND IMOD
90%
10%
t
ALS
ASSERT TIME
Figure 2. ALS Timing Diagram
VEE
VEE
750Ω
VEE
GND
10Ω
VBSET
10nF
TP1
TP2
GND
BSET IBMON IBIAS GND
GND
VCC
VCC
GND
BIAS TEE
GND
GND
50Ω
ADN2530
Z
= 50Ω
Z
= 50Ω
= 50Ω
Z
Z
= 50Ω
0
0
0
0
DC-BLOCK
DC-BLOCK
ADAPTER ATTENUATOR
ADAPTER ATTENUATOR
J2
DATAP
IMODP
GND
= 50Ω
GND
GND
= 50Ω
GND
OSCILLOSCOPE
Z
Z
0
0
J3
DATAN
VCC
IMODN
VCC
50Ω
GND
GND
GND
GND
GND
BIAS TEE
GND
GND
GND
MSET CPA ALS GND
BIAS TEE: PICOSECOND PULSE LABS MODEL 5542-219
VMSET
GND
VEE
ADAPTER: PASTERNACK PE-9436 2.92mm FEMALE-TO-FEMALE ADAPTER
ATTENUATOR: PASTERNACK PE-7046 2.92mm 10dB ATTENUATOR
DC-BLOCK: AGILENT BLOCKING CAPACITOR 11742A
10nF
VEE
VCPA
VEE
J8
J5
10μF
VEE
GND GND
GND
Figure 3. High Speed Characterization Circuit
Rev. A | Page 4 of 20
ADN2530
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter
Rating
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Supply Voltage—VCC to GND
IMODP, IMODN to GND
DATAP, DATAN to GND
All Other Pins
Junction Temperature
Storage Temperature Range
−0.3 V to +4.2 V
VCC − 1.5 V to +4.5 V
VCC − 1.8 V to VCC − 0.4 V
−0.3 V to VCC + 0.3 V
150°C
−65°C to +150°C
300°C
Soldering Temperature
(Less than 10 sec)
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. A | Page 5 of 20
ADN2530
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
12 BSET
11 IBMON
10 IBIAS
MSET
CPA
ALS
1
2
3
4
PIN 1
INDICATOR
ADN2530
TOP VIEW
(Not to Scale)
GND
9 GND
NOTES:
THERE IS AN EXPOSED PAD ON THE
BOTTOM OF THE PACKAGE THAT MUST BE
CONNECTED TO THE VCC OR GND PLANE.
Figure 4. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
Mnemonic
MSET
CPA
ALS
GND
I/O
Description
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Input
Input
Input
Modulation Current Control Input
Crosspoint Adjust Control Input
Automatic Laser Shutdown
Negative Power Supply
Power
Power
Output
Output
Power
Power
Output
Output
Input
Power
Input
Input
Power
Power
VCC
Positive Power Supply
IMODN
IMODP
VCC
Modulation Current Negative Output
Modulation Current Positive Output
Positive Power Supply
Negative Power Supply
Bias Current Output
Bias Current Monitoring Output
Bias Current Control Input
Positive Power Supply
Data Signal Positive Input
Data Signal Negative Input
Positive Power Supply
GND
IBIAS
IBMON
BSET
VCC
DATAP
DATAN
VCC
Exposed Pad
Pad
Connect to GND or VCC
Rev. A | Page 6 of 20
ADN2530
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VCC = 3.3 V, crosspoint adjust disabled, unless otherwise noted.
30
25
20
15
10
5
10
9
8
7
6
5
4
3
2
1
0
10.7Gbps
11.3Gbps
0
0
0
0
5
10
15
20
25
0
5
10
15
20
25
DIFFERENTIAL MODULATION CURRENT (mA)
DIFFERENTIAL MODULATION CURRENT (mA)
Figure 5. Rise Time vs. IMOD
Figure 8. Deterministic Jitter vs. IMOD
30
25
20
15
10
5
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
JITTER BELOW EQUIPMENT
MEASUREMENT CAPABILITY
0
5
10
15
20
25
0
5
10
15
20
25
DIFFERENTIAL MODULATION CURRENT (mA)
DIFFERENTIAL MODULATION CURRENT (mA)
Figure 6. Fall Time vs. IMOD
Figure 9. Random Jitter vs. IMOD
0
–5
0
–5
–10
–15
–20
–25
–30
–35
–40
–10
–15
–20
–25
–30
–35
–40
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 7. Differential |S11|
Figure 10. Differential |S22|
Rev. A | Page 7 of 20
ADN2530
35
30
25
20
15
10
5
10
9
8
7
6
5
4
3
2
1
0
10.7Gbps
11.3Gbps
0
–40
–20
0
20
40
60
80
100
–40
–20
0
20
40
60
80
100
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 11. Rise Time vs. Temperature (Worse-Case Conditions, CPA Disabled)
Figure 14. Deterministic Jitter vs. Temperature
(Worse-Case Conditions, CPA Disabled)
35
30
25
20
15
10
5
80
70
60
50
40
30
20
VCC = [3.07, 3.3, 3.53]
0
–40
–20
0
20
40
60
80
100
1.00
1.25
1.50
1.75
2.00
2.25
2.50
TEMPERATURE (°C)
CPA VOLTAGE (V)
Figure 12. Fall Time vs. Temperature (Worst-Case Conditions, CPA Disabled)
Figure 15. IMOD Eye Diagram Crosspoint vs. CPA Voltage and VCC
(IMOD = 10 mA)
1.0
80
70
60
50
0.8
0.6
0.4
0.2
0
40
+100°C
–40°C
+85°C
30
20
+25°C
–40
–20
0
20
40
60
80
100
0.75
1.00
1.25
1.50
1.75
2.00
2.25
2.50
TEMPERATURE (°C)
CPA VOLTAGE (V)
Figure 16. IMOD Eye Diagram Crosspoint vs. CPA Voltage and Temperature
(IMOD = 10 mA)
Figure 13. Random Jitter vs. Temperature
(Worst-Case Conditions, CPA Disabled [Worst-Case IMOD = 2.2 mA])
Rev. A | Page 8 of 20
ADN2530
140
120
100
80
IBIAS = 25mA
IBIAS = 10mA
1 LEVEL
1 LEVEL
IBIAS = 2mA
CROSSING
60
40
0 LEVEL
0 LEVEL
20
0
0
5
10
15
20
25
DIFFERENTIAL MODULATION CURRENT (mA)
Figure 17. Total Supply Current vs. IMOD
Figure 20. Electrical Eye Diagram
(IMOD = 10 mA, PRBS31 Pattern at 10.3125 Gbps)
25
20
15
10
5
0
26
27
28
29
30
31
RISE TIME (ps)
Figure 18. Worst-Case Rise Time Distribution
Figure 21. Filtered 10G Ethernet Optical Eye Using AOC HFE6192-562 VCSEL
(PRBS31 Pattern at 10.3125 Gbps, 3 dB Optical Attenuator)
25
20
15
10
5
0
26
27
28
29
30
31
FALL TIME (ps)
Figure 19. Worst-Case Fall Time Distribution
Rev. A | Page 9 of 20
ADN2530
THEORY OF OPERATION
As shown in Figure 1, the ADN2530 consists of an input
stage and two voltage-controlled current sources for bias and
modulation. The bias current is available at the IBIAS pin. It is
controlled by the voltage at the BSET pin and can be monitored
at the IBMON pin. The differential modulation current is
available at the IMODP and IMODN pins. It is controlled by
the voltage at the MSET pin. The output stage implements the
active back-termination circuitry for proper transmission line
matching and power consumption reduction. The ADN2530
can drive a load with differential resistance ranging from 35 Ω
to 140 Ω. The excellent back-termination in the ADN2530
absorbs signal reflections from the TOSA end of the output
transmission lines, enabling excellent optical eye quality to be
achieved even when the TOSA end of the output transmission
lines is significantly misterminated.
ADN2530
50Ω
50Ω
C
C
DATAP
DATAN
DATA SIGNAL SOURCE
Figure 23. AC Coupling the Data Source to the ADN2530 Data Inputs
BIAS CURRENT
The bias current is generated internally using a voltage-to-current
converter consisting of an internal operational amplifier and a
transistor, as shown in Figure 24.
VCC
INPUT STAGE
ADN2530
The input stage of the ADN2530 converts the data signal applied
to the DATAP and DATAN pins to a level that ensures proper
operation of the high speed switch. The equivalent circuit of the
input stage is shown in Figure 22.
IBMON
BSET
IBMON
IBIAS
800Ω
200Ω
IBIAS
VCC
200Ω
10Ω
DATAP
VCC
GND
50Ω
Figure 24. Voltage-to-Current Converter Used to Generate IBIAS
The BSET to IBIAS voltage-to-current conversion factor is
set at 20 mA/V by the internal resistors, and the bias current is
monitored at the IBMON pin using a current mirror with a gain
equal to 1/20. By connecting a 750 Ω resistor between IBMON
and GND, the bias current can be monitored as a voltage across
the resistor. A low temperature coefficient precision resistor
must be used for the IBMON resistor (RIBMON). Any error in
the value of RIBMON due to tolerances or drift in its value over
temperature contributes to the overall error budget for the IBIAS
monitor voltage. If the IBMON voltage is being connected to an
ADC for A/D conversion, RIBMON should be placed close to the
ADC to minimize errors due to voltage drops on the ground
plane. See the Design Example section for example calculations
of the accuracy of the IBIAS monitor as a percentage of the
nominal IBIAS value.
VCC
50Ω
DATAN
Figure 22. Equivalent Circuit of the Input Stage
The DATAP and DATAN pins are terminated internally with a
100 Ω differential termination resistor. This minimizes signal
reflections at the input that could otherwise lead to degradation
in the output eye diagram. It is not recommended to drive the
ADN2530 with single-ended data signal sources.
The ADN2530 input stage must be ac-coupled to the signal
source to eliminate the need for matching between the common-
mode voltages of the data signal source and the input stage of
the driver (see Figure 23). The ac-coupling capacitors should
have an impedance less than 50 Ω over the required frequency
range. Generally, this is achieved using 10 nF to 100 nF
capacitors.
Rev. A | Page 10 of 20
ADN2530
See the Headroom Calculations section for examples.
The equivalent circuits of the BSET, IBIAS, and IBMON pins
are shown in Figure 25 to Figure 27.
The function of Inductor L is to isolate the capacitance of the
IBIAS output from the high frequency signal path. For
recommended components, see Table 6.
VCC
VCC
BSET
AUTOMATIC LASER SHUTDOWN (ALS)
800Ω
The ALS pin is a digital input that enables/disables both the bias
and modulation currents, depending on the logic state applied,
as shown in Table 5.
200Ω
Figure 25. Equivalent Circuit of the BSET Pin
Table 5.
ALS Logic State
IBIAS and IMOD
Disabled
Enabled
IBIAS
VCC
2kΩ
High
Low
VCC
Floating
Enabled
100Ω
The ALS pin is compatible with 3.3 V CMOS and TTL logic
levels. Its equivalent circuit is shown in Figure 29.
10Ω
Figure 26. Equivalent Circuit of the IBIAS Pin
VCC
VCC
100Ω
35kΩ
VCC
VCC
500Ω
ALS
2kΩ
Figure 29. Equivalent Circuit of the ALS Pin
MODULATION CURRENT
100Ω
VCC
The modulation current can be controlled by applying a dc
voltage to the MSET pin. This voltage is converted into a dc
current by using a voltage-to-current converter that uses an
operational amplifier and a bipolar transistor, as shown in
Figure 30.
IBMON
Figure 27. Equivalent Circuit of the IBMON Pin
The recommended configuration for BSET, IBIAS, and IBMON
is shown in Figure 28.
VCC
TO LASER CATHODE
IMODP
L
IBIAS
100Ω IMOD
IMODN
IBIAS
ADN2530
FROM CPA STAGE
BSET
IBMON
MSET
R
IBMON
750Ω
800Ω
GND
VBSET
Figure 28. Recommended Configuration for BSET, IBIAS, and IBMON Pins
200Ω
ADN2530
The circuit used to drive the BSET voltage must be able to drive
the 1 kΩ input resistance of the BSET pin. For proper operation
of the bias current source, the voltage at the IBIAS pin must be
between the compliance voltage specifications for this pin over
supply, temperature, and bias current range (see Table 1). The
maximum compliance voltage is specified for only two bias
current levels (2 mA and 25 mA), but it can be calculated for
any bias current by
GND
Figure 30. Generation of Modulation Current on the ADN2530
This dc current is switched by the data signal applied to the
input stage (DATAP and DATAN pins) and gained up by the
output stage to generate the differential modulation current at
the IMODP and IMODN pins. The output stage also generates
the active back-termination, which provides proper transmission
line termination. Active back-termination uses feedback around
an active circuit to synthesize a broadband termination resistance.
V
COMPLIANCE (V) = VCC (V) − 0.75 − 22 × IBIAS (A)
Rev. A | Page 11 of 20
ADN2530
45
40
35
30
25
20
15
10
This provides excellent transmission line termination while
dissipating less power than a traditional resistor passive back-
termination. No portion of the modulation current flows in the
active back-termination resistance. All of the preset modulation
current IMOD, the range specified in Table 1, flows in the
external load. The equivalent circuits for MSET, IMODP, and
IMODN are shown in Figure 31 and Figure 32. The two 50 Ω
resistors in Figure 32 are not real resistors. They represent the
active back-termination resistance.
MAX
TYP
MIN
VCC
VCC
MSET
800Ω
200Ω
10 20 30 40 50 60 70 80 90 100 110 120 130 140
DIFFERENTIAL LOAD RESISTANCE
Figure 34. MSET Voltage to Modulation Current Ratio vs.
Differential Load Resistance
Figure 31. Equivalent Circuit of the MSET Pin
Using the resistance of the TOSA, the user can calculate the
voltage range that should be applied to the MSET pin to
generate the required modulation current range (see the
example in the Applications Information section).
VCC
50Ω
VCC
50Ω
IMODN
IMODP
The circuit used to drive the MSET voltage must be able to
drive the 1 kΩ resistance of the MSET pin. To be able to drive
23 mA modulation currents through the differential load, the
output stage of the ADN2530 (IMODP and IMODN pins)
must be ac-coupled to the load. The voltages at these pins
have a dc component equal to VCC and an ac component with
single-ended peak-to-peak amplitude of IMOD × 50 Ω. This
is the case when the load impedance (RTOSA) is less than
100 Ω differential because the transmission line characteristic
impedance sets the peak-to-peak amplitude. For the case where
15Ω
15Ω
Figure 32. Equivalent Circuit of the IMODP and IMODN Pins
The recommended configuration of the MSET, IMODP, and
IMODN pins is shown in Figure 33. See Table 6 for recom-
mended components. When the voltage on DATAP is greater
than the voltage on DATAN, the modulation current flows into
the IMODP pin and out of the IMODN pin, generating an
optical Logic 1 level at the TOSA output when the TOSA is
connected as shown in Figure 33.
RTOSA is greater than 100 Ω, the single-ended, peak-to-peak
amplitude is IMOD × RTOSA ÷ 2. For proper operation of the
output stage, the voltages at the IMODP and IMODN pins must
be between the compliance voltage specifications for this pin
over supply, temperature, and modulation current range, as
shown in Figure 35. See the Headroom Calculations section for
examples of headroom calculations.
IBIAS
VCC
L
L
ADN2530
Z
Z
= 50Ω
= 50Ω
Z
Z
= 50Ω
= 50Ω
0
0
C
C
V
V
IMODP, IMODN
IMODP
TOSA
0
0
IMODN
VCC + 0.7V
VCC
MSET
GND
VMSET
L
L
NORMAL OPERATION REGION
VCC VCC
Figure 33. Recommended Configuration for the
MSET, IMODP, and IMODN Pins
VCC – 0.7V
The ratio between the voltage applied to the MSET pin and the
differential modulation current available at the IMODP and
IMODN pins is a function of the load resistance value, as shown
in Figure 34.
Figure 35. Allowable Range for the Voltage at IMODP and IMODN
Rev. A | Page 12 of 20
ADN2530
LOAD MISTERMINATION
POWER CONSUMPTION
Due to its excellent S22 performance, the ADN2530 can drive
differential loads that range from 35 Ω to 140 Ω. In practice,
many TOSAs have differential resistance not equal to 100 Ω. In
this case, with 100 Ω differential transmission lines connecting
the ADN2530 to the load, the load end of the transmission lines
are misterminated. This mistermination leads to signal reflections
back to the driver. The excellent back-termination in the
ADN2530 absorbs these reflections, preventing their reflection
back to the load. This enables excellent optical eye quality to
be achieved even when the load end of the transmission lines is
significantly misterminated. The connection between the load
and the ADN2530 must be made with 100 Ω differential (50 Ω
single-ended) transmission lines so that the driver end of the
transmission lines is properly terminated.
The power dissipated by the ADN2530 is given by
V
⎛
⎜
⎞
⎠
MSET
P = VCC ×
+ ISUPPLY + V
× (IBIAS ×1.2)
IBIAS
⎟
50
⎝
where:
VCC is the power supply voltage.
IBIAS is the bias current generated by the ADN2530.
MSET is the voltage applied to the MSET pin.
SUPPLY is the sum of the current that flows into the VCC,
V
I
IMODP, and IMODN pins of the ADN2530 when IBIAS =
IMOD = 0 expressed in amps (see Table 1).
V
IBIAS is the average voltage on the IBIAS pin.
Considering VBSET/IBIAS = 50 as the conversion factor from
BSET to IBIAS, the dissipated power becomes
CROSSPOINT ADJUST
V
The crossing level in the output electrical eye diagram can be
adjusted between 35% and 65% using the crosspoint adjust (CPA)
control input. This can be used to compensate for asymmetry in
the VCSEL response and optimizes the optical eye mask margin.
The CPA input is a voltage control input, and a plot of eye cross-
point vs. CPA control voltage is shown in Figure 15 and Figure 16
in the Typical Performance Characteristics section. The equivalent
circuit for the CPA pin is shown in Figure 36. To disable the
crosspoint adjust function and set the eye crossing to 50%, the
CPA pin should be tied to VCC.
V
V
BSET
⎛
⎜
⎞
⎠
⎛
⎜
⎞
⎟
MSET
P = VCC ×
+ ISUPPLY +V
×
×1.2
⎟
IBIAS
50
50
⎝
⎝
⎠
To ensure long-term reliable operation, the junction tempera-
ture of the ADN2530 must not exceed 125°C, as specified in
Table 2. For improved heat dissipation, the module’s case can be
used as a heat sink, as shown in Figure 37.
THERMAL COMPOUND
MODULE CASE
T
TOP
DIE
T
100Ω
THERMO-COUPLE
J
PACKAGE
T
PAD
VCC
PCB
CPA
COPPER PLANE
VIAS
Figure 36. Equivalent Circuit for CPA Pin
Figure 37. Typical Optical Module Structure
Rev. A | Page 13 of 20
ADN2530
T
TOP
A compact optical module is a complex thermal environment,
and calculations of device junction temperature using the
package θJA (junction-to-ambient thermal resistance) do not
yield accurate results. The following equation, derived from the
model in Figure 38, can be used to estimate the IC junction
temperature:
T
θJ-TOP
TOP
T
J
P
θJ-PAD
T
PAD
T
PAD
P ×
θJ −PAD × θJ −TOP
+ TTOP × θJ −PAD + TPAD × θJ −TOP
TJ =
θJ −PAD + θJ −TOP
Figure 38. Electrical Model for Thermal Calculations
where:
TTOP and TPAD can be determined by measuring the temperature
at points inside the module, as shown in Figure 37. The thermo-
couples should be positioned to obtain an accurate measurement of
the package top and paddle temperatures. θJ-TOP and θJ-PAD are
given in Table 2.
T
TOP is the temperature at top of package in degrees Celsius.
PAD is the temperature at package exposed paddle in degrees
T
Celsius.
TJ is the IC junction temperature in degrees Celsius.
P is the ADN2530 power dissipation in watts.
θJ-TOP is the thermal resistance from IC junction to package top.
θJ-PAD is the thermal resistance from IC junction to package
exposed pad.
Rev. A | Page 14 of 20
ADN2530
APPLICATIONS INFORMATION
TYPICAL APPLICATION CIRCUIT
LAYOUT GUIDELINES
Figure 39 shows the typical application circuit for the
Due to the high frequencies at which the ADN2530 operates,
care should be taken when designing the PCB layout to obtain
optimum performance. Controlled impedance transmission
lines must be used for the high speed signal paths. The length
of the transmission lines must be kept to a minimum to reduce
losses and pattern-dependent jitter. The PCB layout must be
symmetrical both on the DATAP and DATAN inputs and on
the IMODP and IMODN outputs to ensure a balance between
the differential signals. All VCC and GND pins must be connected
to solid copper planes by using low inductance connections.
When the connections are made through vias, multiple vias can
be connected in parallel to reduce the parasitic inductance.
Each GND pin must be locally decoupled to VCC with high
quality capacitors, see Figure 39. If proper decoupling cannot be
achieved using a single capacitor, the user can use multiple
capacitors in parallel for each GND pin. A 20 μF tantalum
capacitor must be used as the general decoupling capacitor for
the entire module. For recommended PCB layouts, including
those suitable for XFP modules, contact sales. For guidelines on
the surface-mount assembly of the ADN2530, consult the
Amkor Technology® “Application Notes for Surface Mount
Assembly of Amkor’s MicroLeadFrame® (MLF®) Packages.”
ADN2530. The dc voltages applied to the BSET and MSET pins
control the bias and modulation currents. The bias current can
be monitored as a voltage drop across the 750 Ω resistor connected
between the IBMON pin and GND. The dc voltage applied to
the CPA pin controls the crosspoint in the output eye diagram.
By tying the CPA pin to VCC, the CPA function is disabled. The
ALS pin allows the user to turn on/off the bias and modulation
currents depending on the logic level applied to the pin. The
data signal source must be connected to the DATAP and DATAN
pins of the ADN2530 using 50 Ω transmission lines. The
modulation current outputs, IMODP and IMODN, must be
connected to the load (TOSA) using 100 Ω differential (50 Ω
single-ended) transmission lines. Table 6 shows recommended
components for the ac-coupling interface between the ADN2530
and TOSA. For additional application information and optical
eye diagram performance data, see the application notes and
reference design for the ADN2530 at www.analog.com.
Table 6.
Component
Value
110 Ω
300 Ω
100 nF
Description
R1, R2
R3, R4
C3, C4
0603 size resistor
0603 size resistor
0402 size capacitor,
Phycomp 223878719849
L6, L7
160 nH
0603 size inductor,
Murata LQW18ANR16
L2, L3
0603 size chip ferrite bead,
Murata BLM18HG601
L1, L4, L5, L8
10 μH
0805 size inductor,
Murata LQM21FN100M70L
C8
100nF
VCC
GND
R5
V
CC
GND
750Ω
C5
10nF
BSET
TP1
L1
L2
R1 L8
R4
VCC
BSET IBMON IBIAS GND
VCC
= 50Ω
VCC
VCC
VCC
L7
Z
Z
Z
Z
= 50Ω
Z
Z
= 50Ω
= 50Ω
0
0
0
0
DATAP
DATAN
DATAP
IMODP
C1
C4
GND
= 50Ω
ADN2530
TOSA
= 50Ω
0
0
DATAN
VCC
IMODN
VCC
C2
C3
L6
GND
L3
VCC
VCC
MSET CPA ALS GND
VCC
L4
R2 L5
R3
C6
MSET
+3.3V
10nF
VCC
GND
C7
20μF
CPA ALS
VCC
VCC
GND
Figure 39. Typical ADN2530 Application Circuit
Rev. A | Page 15 of 20
ADN2530
Assuming the dc voltage drop across L1, L2, L3, and L4 = 0 V
and IMOD = 10 mA, the minimum voltage at the modulation
output pins is equal to
DESIGN EXAMPLE
This design example covers:
•
•
Headroom calculations for IBIAS, IMODP, and IMODN pins.
VCC − (IMOD × 50)/2 = VCC − 0.25
Calculation of the typical voltage required at the BSET
and MSET pins to produce the desired bias and
modulation currents.
VCC − 0.25 > VCC − 0.7 V, which satisfies the requirement
The maximum voltage at the modulation output pins is equal to
VCC + (IMOD × 50)/2 = VCC + 0.25
•
Calculations of the IBIAS monitor accuracy over the IBIAS
current range.
VCC + 0.25 < VCC + 0.7 V, which satisfies the requirement
This design example assumes that the impedance of the
TOSA is 60 Ω, the forward voltage of the VCSEL at low current
is VF = 1.2 V, IBIAS = 10 mA, IMOD = 10 mA, and VCC = 3.3 V.
Headroom calculations must be repeated for the minimum and
maximum values of the required IBIAS and IMOD ranges to
ensure proper device operation over all operating conditions.
Headroom Calculations
BSET and MSET Pin Voltage Calculation
To ensure proper device operation, the voltages on the IBIAS,
IMODP, and IMODN pins must meet the compliance voltage
specifications in Table 1.
To set the desired bias and modulation currents, the BSET and
MSET pins of the ADN2530 must be driven with the appropriate
dc voltage. The voltage range required at the BSET pin to generate
the required IBIAS range can be calculated using the BSET voltage
to IBIAS gain specified in Table 1. Assuming that IBIAS = 10 mA
and the typical IBIAS/VBSET ratio of 20 mA/V, the BSET voltage
is given by
Considering the typical application circuit shown in Figure 39,
the voltage at the IBIAS pin can be written as
V
IBIAS = VCC − VF − (IBIAS × RTOSA) − VLA
where:
IBIAS(mA)
20 mA/V
10
20
VBSET
=
=
= 0.5 V
VCC is the supply voltage.
VF is the forward voltage across the laser at low current.
The BSET voltage range can be calculated using the required
IBIAS range and the minimum and maximum BSET voltage to
IBIAS gain values specified in Table 1.
R
TOSA is the resistance of the TOSA.
LA is the dc voltage drop across L5, L6, L7, and L8.
V
For proper operation, the minimum voltage at the IBIAS pin
should be greater than 0.55 V, as specified by the minimum
IBIAS compliance specification in Table 1.
The voltage required at the MSET pin to produce the desired
modulation current can be calculated using
IMOD
K
VMSET
=
Assuming that the voltage drop across the 50 Ω transmission lines
is negligible and that VLA = 0 V, VF = 1.2 V, and IBIAS = 10 mA,
where K is the MSET voltage to IMOD ratio.
V
V
IBIAS = 3.3 − 1.2 − (0.01 × 60) = 1.5 V
The value of K depends on the actual resistance of the TOSA
and can be obtained from Figure 34. For a TOSA resistance of
60 Ω, the typical value of K = 24 mA/V. Assuming that IMOD =
10 mA and using the preceding equation, the MSET voltage is
given by
IBIAS = 1.5 V > 0.55 V, which satisfies the requirement
The maximum voltage at the IBIAS pin must be less than the
maximum IBIAS compliance specification as described by
V
COMPLIANCE_MAX = VCC − 0.75 − 22 × IBIAS (A)
For this example,
VCOMPLIANCE_MAX = VCC – 0.75 − 22 × 0.01 = 2.33 V
IBIAS = 1.5 V < 2.33 V, which satisfies the requirement
IMOD (mA)
24 mA/V
10
24
VMSET
=
=
= 0.42 V
The MSET voltage range can be calculated using the required
IMOD range and the minimum and maximum K values. These can
be obtained from the minimum and maximum curves in Figure 34.
V
To calculate the headroom at the modulation current pins
(IMODP and IMODN), the voltage has a dc component equal
to VCC due to the ac-coupled configuration and a swing equal
to IMOD × 50 Ω, as RTOSA < 100 Ω. For proper operation of the
ADN2530, the voltage at each modulation output pin should be
within the normal operation region shown in Figure 35.
Rev. A | Page 16 of 20
ADN2530
Referring to Figure 40, the IBMON output current accuracy is
4.3% for the minimum IBIAS of 4 mA and 3.0% for the
maximum IBIAS value of 14 mA.
IBIAS Monitor Accuracy Calculations
6
5
4
3
2
1
0
The accuracy of the IBMON output current as a percentage of
the nominal IBIAS is given by
4.3 100
100 8 mA
IBMON _ AccuracyMIN = 4 mA
×
= ± 2.15%
for the minimum IBIAS value, and by
3.0 100
100 8 mA
IBMON _ AccuracyMAX = 14 mA
×
= ± 5.25%
for the maximum IBIAS value. This gives a worse-case accuracy
for the IBMON output current of 5.25% of the nominal IBIAS
value over all operating conditions. The IBMON output current
accuracy numbers can be combined with the accuracy numbers
for the 750 Ω IBMON resistor (RIBMON) and any other error
sources to calculate an overall accuracy for the IBMON voltage.
0
5
10
15
20
25
IBIAS (mA)
Figure 40. Accuracy of IBIAS to IBMON Ratio
This example assumes that the nominal value of IBIAS is 8 mA
and that the IBIAS range for all operating conditions is 4 mA to
14 mA. The accuracy of the IBIAS to IBMON ratio is given in
the Table 1 and is plotted in Figure 40.
Rev. A | Page 17 of 20
ADN2530
OUTLINE DIMENSIONS
0.50
0.40
0.30
3.00
BSC SQ
0.60 MAX
PIN 1
INDICATOR
*
1.65
13
12
16
1
0.45
1.50 SQ
1.35
PIN 1
INDICATOR
2.75
BSC SQ
TOP
VIEW
EXPOSED
PAD
(BOTTOM VIEW)
4
9
8
5
0.50
BSC
0.25 MIN
1.50 REF
0.80 MAX
12° MAX
0.65 TYP
0.90
0.85
0.80
0.05 MAX
0.02 NOM
SEATING
PLANE
0.30
0.23
0.18
0.20 REF
*
COMPLIANT TO JEDEC STANDARDS MO-220-VEED-2
EXCEPT FOR EXPOSED PAD DIMENSION.
Figure 41. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
3 mm × 3 mm Body, Very Thin Quad
(CP-16-3)
Dimensions shown in millimeters
ORDERING GUIDE
Model
ADN2530YCPZ-WP1
ADN2530YCPZ-R21
ADN2530YCPZ-REEL71
Temperature Range
−40°C to +100°C
−40°C to +100°C
−40°C to +100°C
Package Description
Package Option
CP-16-3
CP-16-3
Branding
F08
F08
16-Lead LFCSP_VQ, 50-Piece Waffle Pack
16-Lead LFCSP_VQ, 250-Piece Reel
16-Lead LFCSP_VQ, 1500-Piece Reel
CP-16-3
F08
1 Z = Pb-free part.
Rev. A | Page 18 of 20
ADN2530
NOTES
Rev. A | Page 19 of 20
ADN2530
NOTES
©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05457–0–8/06(A)
Rev. A | Page 20 of 20
相关型号：
©2020 ICPDF网 联系我们和版权申明