ADN2811ACP-CML-RL_技术文档

a ^{OC-48/OC-48 FEC Clock and Data Recovery IC}

with Integrated Limiting Amp

ADN2811

FEATURES

PRODUCT DESCRIPTION

Meets SONET Requirements for Jitter Transfer/

Generation/Tolerance

Quantizer Sensitivity: 4 mV Typ

Adjustable Slice Level: ꢀ100 mV

1.9 GHz Minimum Bandwidth

Patented Clock Recovery Architecture

Loss of Signal Detect Range: 3 mV to 15 mV

Single Reference Clock Frequency for Both Native

SONET and 15/14 (7%) Wrapper Rate

Choice of 19.44 MHz, 38.88 MHz, 77.76 MHz, or 155.52 MHz

REFCLK LVPECL/LVDS/LVCMOS/LVTTL

Compatible Inputs (LVPECL/LVDS Only at 155.52 MHz)

19.44 MHz Oscillator On-Chip to Be Used with

External Crystal

The ADN2811 provides the receiver functions of quantization,

signal level detect, and clock and data recovery at OC-48 and

OC-48 FEC rates. All SONET jitter requirements are met,

including jitter transfer, jitter generation, and jitter tolerance.

All specifications are quoted for –40ꢂC to +85ꢂC ambient

temperature, unless otherwise noted.

The device is intended for WDM system applications and can

be used with either an external reference clock or an on-chip

oscillator with external crystal. Both the 2.48 Gb/s and 2.66 Gb/s

digital wrapper rate is supported by the ADN2811, without any

change of reference clock.

This device, together with a PIN diode and a TIA preamplifier,

can implement a highly integrated, low cost, low power, fiber

optic receiver.

Loss of Lock Indicator

Loopback Mode for High Speed Test Data

Output Squelch and Bypass Features

Single-Supply Operation: 3.3 V

Low Power: 540 mW Typical

7 mm ꢁ 7 mm 48-Lead LFCSP

The receiver front end signal detect circuit indicates when the

input signal level has fallen below a user-adjustable threshold.

The signal detect circuit has hysteresis to prevent chatter at

the output.

The ADN2811 is available in a compact 7 mm × 7 mm 48-lead

chip scale package.

APPLICATIONS

SONET OC-48, SDH STM-16, and 15/14 FEC

WDM Transponders

Regenerators/Repeaters

Test Equipment

Backplane Applications

FUNCTIONAL BLOCK DIAGRAM

SLICEP/N

2

VCC

VEE

LOL

CF1

CF2

ADN2811

LOOP

FILTER

2

REFSEL[0..1]

NIN

2

REFCLKP/N

XO1

/n

FREQUENCY

LOCK

DETECTOR

PHASE

SHIFTER

LOOP

FILTER

PHASE

DET.

QUANTIZER

VCO

XTAL

OSC

XO2

FRACTIONAL

DIVIDER

VREF

REFSEL

LEVEL

DETECT

DATA

RETIMING

2

THRADJ

SDOUT

DATAOUTP/N

CLKOUTP/N

RATE

REV. A

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat

may result from its use. No license is granted by implication or otherwise

under any patent or patent rights of Analog Devices. Trademarks and

registered trademarks are the property of their respective companies.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781/329-4700

Fax: 781/326-8703

www.analog.com

(T_A= T_MINto T_MAX, VCC = V_MINto V_MAX, V_EE= 0 V, C_F= 4.7 ꢃF, SLICEP = SLICEN = VCC,

ADN2811–SPECIFICATIONS _{unless otherwise noted.)}

Parameter

Conditions

Min

Typ

Max

Unit

QUANTIZER–DC CHARACTERISTICS

Input Voltage Range

Peak-to-Peak Differential Input

Input Common-Mode Level

Differential Input Sensitivity

Input Overdrive

Input Offset

Input rms Noise

@ PIN or NIN, DC-Coupled

0

1.2

2.4

V

DC-Coupled. (See Figure 22)

PIN–NIN, AC-Coupled¹, BER = 1 ꢁ 10^–10

Figure 4

0.4

4

2

500

244

10

5

mV p-p

µV

BER = 1

ꢁ

10^–10

µV rms

QUANTIZER–AC CHARACTERISTICS

Upper –3 dB Bandwidth

1.9

54

–15

100

0.65

10

GHz

dB

Ω

pF

ps

Small Signal Gain

Differential

@ 2.5 GHz

Differential

S11

Input Resistance

Input Capacitance

Pulsewidth Distortion²

QUANTIZER SLICE ADJUSTMENT

Gain

SliceP–SliceN = ꢀ0.5 V

SliceP–SliceN

0.115

–0.8

1.3

0.200

1.0

0.300

+0.8

VCC

V/V

V

Control Voltage Range

Slice Threshold Offset

@ SliceP or SliceN

mV

LEVEL SIGNAL DETECT (SDOUT)

Level Detect Range (See Figure 2) R_THRESH= 2 kΩ

9.4

2.5

0.7

0.1

5.6

3.9

3.2

13.3

5.3

3.0

0.3

6.6

6.1

6.7

18.0

7.6

5.2

5

7.8

8.5

9.9

mV

µs

dB

R

_THRESH= 20 kΩ

_THRESH= 90 kΩ

Response TimeDC-Coupled

Hysteresis (Electrical), PRBS 2²³

R_THRESH= 2 kΩ

R_THRESH= 20 kΩ

R_THRESH= 90 kΩ

LOSS OF LOCK DETECT (LOL)

LOL Response Time

From f_VCOerror > 1000 ppm

60

µs

POWER SUPPLY VOLTAGE

POWER SUPPLY CURRENT

3.0

3.3

164

3.6

V

150

215

mA

PHASE-LOCKED LOOP

CHARACTERISTICS

Jitter Transfer BW

Jitter Peaking

PIN–NIN = 10 mV p-p

OC-48

590

0.025

880

kHz

dB

UI rms

UI p-p

Jitter Generation

OC-48, 12 kHz–20 MHz

0.003³

0.09

0.05

Jitter Tolerance

OC-48 (See Figure 9)

600 Hz

6 kHz

100 kHz

1 MHz

92³

20³

5.5

1.0³

UI p-p

–2–

REV. A

ADN2811

Parameter

Conditions

Min

Typ

Max

Unit

CML OUTPUTS (CLKOUTP/N, DATAOUTP/N)

Single-Ended Output Swing

Differential Output Swing

Output High Voltage

Output Low Voltage

Rise Time

Fall time

Setup Time

V

_SE(See Figure 3)

300

600

455

910

VCC

600

1200

mV

V

ps

V_DIFF(See Figure 3)

V_OH

V_OL

20%–80%

80%–20%

T_S(See Figure 1)

OC-48

T_H(See Figure 1)

OC-48

VCC – 0.6

VCC – 0.3

150

84

ps

140

150

ps

Hold Time

REFCLK DC INPUT CHARACTERISTICS

Input Voltage Range

Peak-to-Peak Differential Input

Common-Mode Level

@ REFCLKP or REFCLKN

DC-Coupled, Single-Ended

0

100

VCC

V

mV

V

VCC/2

0.8

TEST DATA DC INPUT

CHARACTERISTICS⁴(TDINP/N)

Peak-to-Peak Differential Input Voltage

CML Inputs

V

LVTTL DC INPUT CHARACTERISTICS

Input High Voltage

Input Low Voltage

V_IH

V_IL

2.0

–5

V

0.8

+5

Input Current

V_IN= 0.4 V or V_IN= 2.4 V

LVTTL DC OUTPUT CHARACTERISTICS

Output High Voltage

Output Low Voltage

V_OH, I_OH= –2.0 mA

V_OL, I_OL= +2.0 mA

2.4

V

0.4

NOTES

¹PIN and NIN should be differentially driven, ac-coupled for optimum sensitivity.

²PWD measurement made on quantizer outputs in BYPASS mode.

³Measurement is equipment limited.

⁴TDINP/N are CML inputs. If the drivers to the TDINP/N inputs are anything other than CML, they must be ac-coupled.

Specifications subject to change without notice.

REV. A

–3–

ADN2811

ABSOLUTE MAXIMUM RATINGS*

THERMAL CHARACTERISTICS

Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V

Minimum Input Voltage (All Inputs) . . . . . . . . . . VEE – 0.4 V

Maximum Input Voltage (All Inputs) . . . . . . . . VCC + 0.4 V

Maximum Junction Temperature . . . . . . . . . . . . . . . . . 165ꢂC

Storage Temperature . . . . . . . . . . . . . . . . . . –65ꢂC to +150ꢂC

Lead Temperature (Soldering 10 Sec) . . . . . . . . . . . . . . 300ꢂC

Thermal Resistance

48-Lead LFCSP, four-layer board with exposed paddle

soldered to VCC

θ

_JA= 25ꢂC/W

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the

device at these or any other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect device reliability.

ORDERING GUIDE

Model

Temperature Range Package

Option

ADN2811ACP-CML

ADN2811ACP-CML-RL –40ºC to +85ºC

–40ºC to +85ºC

48-Lead LFCSP

CP-48

Tape-Reel, 2500 pcs

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily

accumulate on the human body and test equipment and can discharge without detection. Although the

ADN2811 features proprietary ESD protection circuitry, permanent damage may occur on devices

subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended

to avoid performance degradation or loss of functionality.

–4–

REV. A

ADN2811

PIN CONFIGURATION

THRADJ

VCC

1

36VCC

35VCC

34VEE

33VEE

32 NC

PIN 1

2

3

4

5

6

7

8

9

INDICATOR

VEE

VREF

ADN2811

NIN

31 NC

SLICEP

SLICEN

VEE

30 RATE

29VEE

28VCC

27VEE

26VCC

25 CF2

TOP VIEW

LOL 10

XO1 11

XO2 12

NC = NO CONNECT

PIN FUNCTION DESCRIPTION

Pin No.

Mnemonic

Type

Description

1

THRADJ

VCC

VEE

AI

P

LOS Threshold Setting Resistor

Analog Supply

Ground

2, 26, 28, Pad

3, 9, 16, 19, 22, 27, 29,

33, 34, 42, 43, 46

4

5

VREF

AO

AI

Internal V_REFVoltage. Decouple to GND with 0.1 µF capacitor.

Differential Data Input. CML.

6

NIN

AI

Differential Data Input. CML.

7

8

10

11

12

13

SLICEP

SLICEN

LOL

XO1

XO2

AI

DO

AO

DI

Differential Slice Level Adjust Input

Loss of Lock Indicator. LVTTL active high.

Crystal Oscillator

REFCLKN

Differential REFCLK Input. LVTTL, LVCMOS, LVPECL, LVDS

(LVPECL, LVDS only at 155.52 MHz).

Differential REFCLK Input. LVTTL, LVCMOS, LVPECL, LVDS

(LVPECL, LVDS only at 155.52 MHz).

Reference Source Select. “0” = on-chip oscillator with external crystal;

“1” = external clock source, LVTTL.

Differential Test Data Input

14

15

REFCLKP

REFSEL

DI

17

TDINP

AI

18

20, 47

21

23

24

25

30

31, 32

35, 36

37

38

39

40

41

44

45

48

TDINN

VCC

CF1

REFSEL1

REFSEL0

CF2

RATE

NC

VCC

DATAOUTN

DATAOUTP

SQUELCH

CLKOUTN

CLKOUTP

BYPASS

SDOUT

LOOPEN

AI

P

Differential Test Data Input

Digital Supply

Frequency Loop Capacitor

Reference Frequency Select (See Table II) LVTTL.

Frequency Loop Capacitor

Data Rate Select (See Table I) LVTTL.

No Connect

AO

DI

AO

DI

P

DO

DI

DO

DI

DO

DI

Output Driver Supply

Differential Retimed Data Output. CML.

Disable Clock and Data Outputs. Active high. LVTTL.

Differential Recovered Clock Output. CML.

Bypass CDR Mode. Active high. LVTTL.

Loss of Signal Detect Output. Active high. LVTTL.

Enable Test Data Inputs. Active high. LVTTL.

Type: P = Power, AI = Analog Input, AO = Analog Output, DI = Digital Input, DO = Digital Output

REV. A

–5–

ADN2811

CLKOUTP

T

H

S

DATAOUTP/N

Figure 1. Output Timing

18

16

14

12

10

8

THRADJ RESISTOR VS. LOSTRIP POINT

6

4

2

0

10

20

30

40

50

60

70

80

90

100

RESISTANCE – k⍀

Figure 2. LOS Comparator Trip Point Programming

OUTP

V

SE

CML

OUTN

OUTP–OUTN

V

SE

V

DIFF

0V

Figure 3. Single-Ended vs. Differential Output Specs

–6–

REV. A

ADN2811

DEFINITION OF TERMS

SINGLE-ENDED VS. DIFFERENTIAL

Maximum, Minimum, and Typical Specifications

AC-coupling is typically used to drive the inputs to the quan-

tizer. The inputs are internally dc biased to a common-mode

potential of ~0.6 V. Driving the ADN2811 single-ended and

observing the quantizer input with an oscilloscope probe at the

point indicated in Figure 5 shows a binary signal with an average

value equal to the common-mode potential and instantaneous

values both above and below the average value. It is convenient

to measure the peak-to-peak amplitude of this signal and call

the minimum required value the quantizer sensitivity. Referring

to Figure 4, since both positive and negative offsets need to be

accommodated, the sensitivity is twice the overdrive.

Specifications for every parameter are derived from statistical

analyses of data taken on multiple devices from multiple wafer

lots. Typical specifications are the mean of the distribution of

the data for that parameter. If a parameter has a maximum (or a

minimum), that value is calculated by adding to (or subtracting

from) the mean six times the standard deviation of the distribu-

tion. This procedure is intended to tolerate production variations.

If the mean shifts by 1.5 standard deviations, the remaining 4.5

standard deviations still provide a failure rate of only 3.4 parts

per million. For all tested parameters, the test limits are guardbanded

to account for tester variation to thus guarantee that no device is

shipped outside of data sheet specifications.

10mV p-p

VREF

INPUT SENSITIVITY AND INPUT OVERDRIVE

SCOPE

Sensitivity and overdrive specifications for the quantizer involve

offset voltage, gain, and noise. The relationship between the

logic output of the quantizer and the analog voltage input is

shown in Figure 4. For sufficiently large positive input voltage,

the output is always Logic 1; similarly for negative inputs, the

output is always Logic 0. However, the transitions between

output Logic Levels 1 and 0 are not at precisely defined input

voltage levels but occur over a range of input voltages. Within

this zone of confusion, the output may be either 1 or 0, or it

may even fail to attain a valid logic state. The width of this zone

is determined by the input voltage noise of the quantizer. The

center of the zone of confusion is the quantizer input offset

voltage. Input overdrive is the magnitude of signal required to

guarantee the correct logic level with 1 × 10^–10confidence level.

PROBE

ADN2811

+

QUANTIZER

50ꢄ 50ꢄ

VREF

Figure 5. Single-Ended Sensitivity Measurement

5mV p-p

VREF

OUTPUT

SCOPE

PROBE

NOISE

1

ADN2811

+

QUANTIZER

NIN

0

50ꢄ 50ꢄ

INPUT (V p-p)

OFFSET

VREF

OVERDRIVE

SENSITIVITY

(2ꢁ OVERDRIVE)

Figure 6. Differential Sensitivity Measurement

Figure 4. Input Sensitivity and Input Overdrive

Driving the ADN2811 differentially (see Figure 6), sensitivity

seems to improve by observing the quantizer input with an

oscilloscope probe. This is an illusion caused by the use of a

single-ended probe. A 5 mV p–p signal appears to drive the

ADN2811 quantizer. However, the single-ended probe mea-

sures only half the signal. The true quantizer input signal is

twice this value since the other quantizer input is a complemen-

tary signal to the signal being observed.

LOS Response Time

The LOS response time is the delay between the removal of

the input signal and the indication of loss of signal (LOS) at

SDOUT. The LOS response time of the ADN2811 is 300 ns

typ when the inputs are dc-coupled. In practice, the time con-

stant of the ac-coupling at the quantizer input determines the

LOS response time.

REV. A

–7–

ADN2811

JITTER SPECIFICATIONS

Jitter Tolerance

The ADN2811 CDR is designed to achieve the best bit-error-rate

(BER) performance and has exceeded the jitter generation, trans-

fer, and tolerance specifications proposed for SONET/SDH

equipment defined in the Telcordia Technologies specification.

The jitter tolerance is defined as the peak-to-peak amplitude of

the sinusoidal jitter applied on the input signal that causes a

1 dB power penalty. This is a stress test that is intended to

ensure no additional penalty is incurred under the operating

conditions (see Figure 8). Figure 9 shows the typical OC-48

jitter tolerance performance of the ADN2811.

Jitter is the dynamic displacement of digital signal edges from

their long-term average positions measured in UI (unit intervals),

where 1 UI = 1 bit period. Jitter on the input data can cause

dynamic phase errors on the recovered clock sampling edge.

Jitter on the recovered clock causes jitter on the retimed data.

15

The following section briefly summarizes the specifications of

the jitter generation, transfer, and tolerance in accordance with

the Telcordia document (GR-253-CORE, Issue 3, September

2000) for the optical interface at the equipment level and the

ADN2811 performance with respect to those specifications.

SLOPE = –20dB/DECADE

1.5

Jitter Generation

0.15

The jitter generation specification limits the amount of jitter

that can be generated by the device with no jitter and wander

applied at the input. For OC-48 devices, the band-pass filter has

a 12 kHz high-pass cutoff frequency with a roll-off of 20 dB/

decade and a low-pass cutoff frequency of at least 20 MHz. The

jitter generated should be less than 0.01 UI rms and less

than 0.1 UI p-p.

f

0

f

1

f

2

f

3

f4

JITTER FREQUENCY – Hz

Figure 8. SONET Jitter Tolerance Mask

1.00E+02

Jitter Transfer

ADN2811

The jitter transfer function is the ratio of the jitter on the output

signal to the jitter applied on the input signal versus the fre-

quency. This parameter measures the limited amount of jitter

on an input signal that can be transferred to the output signal

(see Figure 7).

1.00E+01

1.00E+00

1.00E–01

OC-48 SONET MASK

0.1

1.00E+00

1.00E+02 1.00E+04

1.00E+01 1.00E+03

1.00E+06

1.00E+05

SLOPE = –20dB/DECADE

1.00E+07

ACCEPTABLE

RANGE

MODULATION FREQUENCY – Hz

Figure 9. OC-48 Jitter Tolerance Curve

f_C

JITTER FREQUENCY – kHz

Figure 7. Jitter Transfer Curve

–8–

REV. A

ADN2811

The error transfer, e(s)/X(s), has the same high-pass form as an

ordinary phase-locked loop. This transfer function is free to be

optimized to give excellent wideband jitter accommodation

since the jitter transfer function, Z(s)/X(s), provides the narrow-

band jitter filtering.

THEORY OF OPERATION

The ADN2811 is a delay-locked and phase-locked loop circuit

for clock recovery and data retiming from an NRZ encoded data

stream. The phase of the input data signal is tracked by two

separate feedback loops that share a common control voltage.

A high speed delay-locked loop path uses a voltage controlled

phase shifter to track the high frequency components of the

input jitter. A separate phase control loop, comprised of the

VCO, tracks the low frequency components of the input jitter.

The initial frequency of the VCO is set by yet a third loop, which

compares the VCO frequency with the reference frequency and

sets the coarse tuning voltage. The jitter tracking phase-locked

loop controls the VCO by the fine tuning control.

The delay-locked and phase-locked loops contribute to overall

jitter accommodation. At low frequencies of input jitter on the

data signal, the integrator in the loop filter provides high gain to

track large jitter amplitudes with small phase error. In this case,

the VCO is frequency modulated and jitter is tracked as in an

ordinary phase-locked loop. The amount of low frequency jitter

that can be tracked is a function of the VCO tuning range. A

wider tuning range gives larger accommodation of low fre-

quency jitter. The internal loop control voltage remains small

for small phase errors, so the phase shifter remains close to the

center of its range and thus contributes little to the low fre-

quency jitter accommodation.

The delay-locked and phase-locked loops together track the

phase of the input data signal. For example, when the clock lags

input data, the phase detector drives the VCO to a higher

frequency and also increases the delay through the phase shifter.

Both of these actions both serve to reduce the phase error between

the clock and data. The faster clock picks up phase while the

delayed data loses phase. Since the loop filter is an integrator,

the static phase error will be driven to zero.

At medium jitter frequencies, the gain and tuning range of the

VCO are not large enough to track the input jitter. In this case,

the VCO control voltage becomes large and saturates, and the

VCO frequency dwells at one or the other extreme of its tuning

range. The size of the VCO tuning range therefore has only a

small effect on the jitter accommodation. The delay-locked loop

control voltage is now larger, and so the phase shifter takes on

the burden of tracking the input jitter. The phase shifter range, in

UI, can be seen as a broad plateau on the jitter tolerance curve.

The phase shifter has a minimum range of 2 UI at all data rates.

Another view of the circuit is that the phase shifter implements

the zero required for the frequency compensation of a second-

order phase-locked loop, and this zero is placed in the feedback

path and thus does not appear in the closed-loop transfer func-

tion. Jitter peaking in a conventional second-order phase-locked

loop is caused by the presence of this zero in the closed-loop

transfer function. Since this circuit has no zero in the closed-

loop transfer, jitter peaking is minimized.

The gain of the loop integrator is small for high jitter frequen-

cies, so larger phase differences are needed to make the loop

control voltage big enough to tune the range of the phase

shifter. Large phase errors at high jitter frequencies cannot be

tolerated. In this region, the gain of the integrator determines

the jitter accommodation. Since the gain of the loop integrator

declines linearly with frequency, jitter accommodation is lower

with higher jitter frequency. At the highest frequencies, the loop

gain is very small and little tuning of the phase shifter can be

expected. In this case, jitter accommodation is determined by

the eye opening of the input data, the static phase error, and the

residual loop jitter generation. The jitter accommodation is

roughly 0.5 UI in this region. The corner frequency between the

declining slope and the flat region is the closed loop bandwidth

of the delay-locked loop, which is roughly 5 MHz.

The delay-locked and phase-locked loops together simultaneously

provide wideband jitter accommodation and narrow-band jitter

filtering. The linearized block diagram in Figure 10 shows the

jitter transfer function, Z(s)/X(s), is a second-order low-pass

providing excellent filtering. Note the jitter transfer has no zero,

unlike an ordinary second-order phase-locked loop. This means

that the main PLL loop has low jitter peaking (see Figure 11),

which makes this circuit ideal for signal regenerator applications

where jitter peaking in a cascade of regenerators can contribute

to hazardous jitter accumulation.

psh

X(s)

e(s)

INPUT

DATA

o/s

d/sc

JITTER PEAKING

IN ORDINARY PLL

Z(s)

RECOVERED

CLOCK

JITTER

GAIN

JITTERTRANSFER FUNCTION

d = PHASE DETECTOR GAIN

o = VCO GAIN

c = LOOP INTEGRATOR

psh = PHASE SHIFTER GAIN

n = DIVIDE RATIO

Z(s)

1

ADN2811

(dB)

=

cn

do

n psh

o

Z(s)

X(s)

2

s

+ s

+1

TRACKING ERRORTRANSFER FUNCTION

2

e(s)

X(s)

f (kHz)

s

=

d psh

c

o

d psh

c

do

cn

2

s

+ s

+

n psh

Figure 11. Jitter Response vs. Conventional PLL

Figure 10. PLL/DLL Architecture

REV. A

–9–

ADN2811

FUNCTIONAL DESCRIPTION

Clock and Data Recovery

The ADN2811 will recover clock and data from serial bit streams

at OC-48 as well as the 15/14 FEC rates. The data rate is selected

by the RATE input (see Table I).

LVDS levels via the REFCLKN/P inputs, independent of data

rate. The input buffer accepts any differential signal with a

peak-to-peak differential amplitude of greater than 100 mV

(e.g., LVPECL or LVDS) or a standard single-ended low volt-

age TTL input, providing maximum system flexibility. The

appropriate division ratio can be selected using the REFSEL0/1

pins, according to Table II. Phase noise and duty cycle of the

reference clock are not critical and 100 ppm accuracy is sufficient.

Table I. Data Rate Selection

RATE

Data Rate

Frequency (MHz)

0

1

OC-48

OC-48 FEC

2488.32

2666.06

ADN2811

REFCLKP

Limiting Amplifier

BUFFER

The limiting amplifier has differential inputs (PIN/NIN) that are

internally terminated with 50 Ω to an on-chip voltage reference

(VREF = 0.6 V typically). These inputs are normally ac-coupled,

although dc-coupling is possible as long as the input common-mode

voltage remains above 0.4 V (see Figures 20–22). Input offset is

factory trimmed to achieve better than 4 mV typical sensitivity

with minimal drift. The limiting amplifier can be driven

differentially or single-ended.

REFCLKN

100kꢄ 100kꢄ

VCC/2

XO1

VCC

CRYSTAL

OSCILLATOR

XO2

VCC

Slice Adjust

REFSEL

The quantizer slicing level can be offset by 100 mV to mitigate

the effect of ASE (amplified spontaneous emission) noise by

applying a differential voltage input of 0.8 V to SLICEP/N

inputs. If no adjustment of the slice level is needed, SLICEP/N

should be tied to VCC.

Figure 12. Differential REFCLK Configuration

ADN2811

VCC

REFCLKP

CLK

Loss of Signal (LOS) Detector

The receiver front end level signal detect circuit indicates when

the input signal level has fallen below a user adjustable threshold.

The threshold is set with a single external resistor from Pin 1,

THRADJ, to GND. The LOS comparator trip point versus the

resistor value is illustrated in Figure 2 (this is only valid for

SLICEP = SLICEN = VCC). If the input level to the ADN2811

drops below the programmed LOS threshold, SDOUT (Pin 45)

will indicate the loss of signal condition with a Logic 1. The LOS

response time is ~300 ns by design but will be dominated by the

RC time constant in ac-coupled applications.

OSC

OUT

BUFFER

NC

REFCLKN

100kꢄ 100kꢄ

VCC/2

XO1

XO2

VCC

CRYSTAL

OSCILLATOR

VCC

REFSEL

If the LOS detector is used, the quantizer slice adjust pins must

both be tied to VCC. This is to avoid interaction with the LOS

threshold level.

Figure 13. Single-Ended REFCLK Configuration

Note that it is not expected to use both LOS and slice adjust at

the same time; systems with optical amplifiers need the slice

adjust to evade ASE. However, a loss of signal in an optical link

that uses optical amplifiers causes the optical amplifier output to

be full-scale noise. Under this condition, the LOS would not

detect the failure. In this case, the loss of lock signal will indi-

cate the failure because the CDR circuitry will not be able to

lock onto a signal that is full-scale noise.

ADN2811

VCC

REFCLKP

BUFFER

NC

REFCLKN

100kꢄ 100kꢄ

VCC/2

Reference Clock

There are three options for providing the reference frequency to

the ADN2811: differential clock, single-ended clock, or crystal

oscillator. See Figures 12–14 for example configurations.

XO1

CRYSTAL

19.44MHz

XO2

OSCILLATOR

The ADN2811 can accept any of the following reference clock

frequencies: 19.44 MHz, 38.88 MHz, 77.76 MHz at LVTTL/

LVCMOS/LVPECL/LVDS levels or 155.52 MHz at LVPECL/

REFSEL

Figure 14. Crystal Oscillator Configuration

–10–

REV. A

ADN2811

LOL

An on-chip oscillator to be used with an external crystal is also

provided as an alternative to using the REFCLKN/P inputs.

Details of the recommended crystal are given in Table III.

1

Table II. Reference Frequency Selection

Applied Reference

1000

500

0

500

1000

f

ERROR

VCO

(ppm)

REFSEL

REFSEL[1..0] Frequency (MHz)

Figure 15. Transfer Function of LOL

1

0

00

01

10

11

XX

19.44

38.88

77.76

155.52

The frequency loop requires a single external capacitor between

CF1 and CF2. The capacitor specification is given in Table IV.

Table IV. Recommended C_FCapacitor Specification

REFCLKP/N Inactive. Use

19.44 MHz XTAL oscillator

on Pins XO1, XO2 (Pull

REFCLKP to VCC).

Parameter

Value

Temperature Range

Capacitance

Leakage

–40ꢂC to +85ꢂC

>3.0 µF

<80 nA

Table III. Required Crystal Specifications

Rating

>6.3 V

Parameter

Value

Recommended Manufacturer:

Murata Electronics (770) 436-1300

Part Number: GRM32RR71C475LC01

Mode

Series Resonant

19.44 MHz 100 ppm

100 ppm

Frequency/Overall Stability

Frequency Accuracy

Temperature Stability

Aging

Squelch Mode

When the squelch input is driven to a TTL high state, both the

clock and data outputs are set to the zero state to suppress

downstream processing. If desired, this pin can be directly

driven by the LOS detector output, SDOUT. If the squelch func-

tion is not required, the pin should be tied to VEE.

ESR

20 Ω max

Recommended Manufacturer:

Raltron (305) 593-6033

Part Number: H10S-19.440-S-EXT

Test Modes: Bypass and Loopback

When the bypass input is driven to a TTL high state, the

quantizer output is connected directly to the buffers driving the data

out pins, thus bypassing the clock recovery circuit (see Figure 16).

This feature can help the system to deal with nonstandard bit rates.

REFSEL must be tied to VCC when the REFCLKN/P inputs

are active or tied to VEE when the oscillator is used. No

connection between the XO pin and REFCLK input is necessary

(see Figures 12–14). Note that the crystal should operate in series

resonant mode, which renders it insensitive to external parasitics.

No trimming capacitors are required.

The Loopback Mode can be invoked by driving the LOOPEN

Pin to a TTL high state, which facilitates system diagnostic test-

ing. This will connect the test inputs (TDINP/N) to the clock

and data recovery circuit (per Figure 16). The test inputs have

internal 50 Ω terminations and can be left floating when not in

use. TDINP/N are CML inputs and can only be dc-coupled

when being driven by CML outputs. The TDINP/N inputs must

be ac-coupled if being driven by anything other than CML out-

puts. Bypass and loopback modes are mutually exclusive. Only

one of these modes can be used at any given time. The

ADN2811 will be put into an indeterminate state if both

BYPASS and LOOPEN pins are set to Logic 1 at the same time.

Lock Detector Operation

The lock detector monitors the frequency difference between

the VCO and the reference clock and deasserts the loss of lock

signal when the VCO is within 500 ppm of center frequency

(see Figure 15). This enables the phase loop, which pulls the

VCO frequency in the remaining amount and also acquires

phase lock. Once locked, if the input frequency error exceeds

1000 ppm (0.1%), the loss of lock signal is reasserted and con-

trol returns to the frequency loop, which will reacquire and

maintain a stable clock signal at the output.

REV. A

–11–

ADN2811

+

NIN

0

1

QUANTIZER

CDR

50⍀ 50⍀

RETIMED

FROM

QUANTIZER

OUTPUT

DATA

CLK

VREF

1

0

50⍀ 50⍀

VCC

TDINP/N

LOOPEN BYPASS DATAOUTP/N

CLKOUTP/N SQUELCH

Figure 16. Test Modes

APPLICATIONS INFORMATION

PCB Design Guidelines

Proper RF PCB design techniques must be used for optimal performance.

CLKOUTP/N and DATAOUTP/N output traces are matched

in length. All high speed CML outputs, CLKOUTP/N and

DATAOUTP/N, also require 100 Ω back termination chip

resistors connected between the output pin and VCC. These

resistors should be placed as close as possible to the output

pins. These 100 Ω resistors are in parallel with on-chip 100 Ω

termination resistors to create a 50 Ω back termination (see

Figure 18).

Power Supply Connections and Ground Planes

Use of one low impedance ground plane to both analog and

digital grounds is recommended. The VEE pins should be sol-

dered directly to the ground plane to reduce series inductance.

If the ground plane is an internal plane and connections to the

ground plane are made through vias, multiple vias may be used

in parallel to reduce the series inductance, especially on Pins 33

and 34, which are the ground returns for the output buffers.

The high speed inputs, PIN and NIN, are internally terminated

with 50 Ω to an internal reference voltage (see Figure 19). A 0.1 µF

capacitor is recommended between VREF, Pin 4, and GND to

provide an ac ground for the inputs.

Use of a 10 µF electrolytic capacitor between VCC and GND is

recommended at the location where the 3.3 V supply enters the

PCB. Use of 0.1 µF and 1 nF ceramic chip capacitors should be

placed between IC power supply VCC and GND as close as

possible to the ADN2811 VCC pins. Again, if connections to the

supply and ground are made through vias, the use of multiple vias

in parallel will help to reduce series inductance, especially on Pins 35

and 36, which supply power to the high speed CLKOUTP/N and

DATAOUTP/N output buffers. Refer to the schematic in

Figure 17 for recommended connections.

As with any high speed mixed-signal design, take care to keep

all high speed digital traces away from sensitive analog nodes.

Soldering Guidelines for Chip-Scale Package

The lands on the 48-lead LFCSP are rectangular. The printed

circuit board pad for these should be 0.1 mm longer than the

package land length and 0.05 mm wider than the package land

width. The land should be centered on the pad. This will ensure

that the solder joint size is maximized. The bottom of the chip-

scale package has a central exposed pad. The pad on the printed

circuit board should be at least as large as this exposed pad.

The user must connect the exposed pad to analog VCC.

Transmission Lines

Use of 50 Ω transmission lines are required for all high fre-

quency input and output signals to minimize reflections,

including PIN, NIN, CLKOUTP, CLKOUTN, DATAOUTP,

and DATAOUTN (also REFCLKP, REFCLKN for a

155.2 MHz REFCLK). It is also recommended that the

PIN/NIN input traces are matched in length and that the

If vias are used, they should be incorporated into the pad at

1.2 mm pitch grid. The via diameter should be between 0.3 mm

and 0.33 mm and the via barrel should be plated with 1 oz.

copper to plug the via.

REV. A

–12–

ADN2811

VCC

50ꢄ

TRANSMISSION

LINES

4 ꢁ 100ꢄ

CLKOUTP

CLKOUTN

DATAOUTP

DATAOUTN

VCC

ꢃC

10ꢃF

0.1ꢃF

1nF

48 47 46 45 44 43 42 41 40 39 38 37

R

TH

THRADJ

VCC

36

VCC

1

VCC

VEE

NC

2

35

34

33

32

31

30

29

28

27

26

25

VCC

1nF

0.1ꢃF

1nF

VEE

3

0.1ꢃF

VREF

4

50ꢄ

EXPOSED PAD

TIED OFFTO

VCC PLANE

WITH VIAS

5

TIA

NC

NIN

6

SLICEP

SLICEN

VEE

RATE

VEE

VCC

VEE

VCC

CF2

C

50ꢄ

IN

ꢃC

7

8

VCC

9

0.1ꢃF

LOL

1nF

0.1ꢃF

1nF

10

11

12

ꢃC

19.44MHz

XO1

VCC

ADN2811

13 14 15 16 17 18 19

XO2

20 21 22 23 24

4.7ꢃF

(SEETABLE IV FOR SPECS)

VCC

0.1ꢃF

1nF

Figure 17. Typical Application Circuit

VCC

ADN2811

VCC

C

IN

V

50ꢄ

TERM

NIN

100ꢄ 100ꢄ

50ꢄ

0.1ꢃF

50ꢄ

TIA

C

IN

50ꢄ

0.1ꢃF

50ꢄ

VREF

ADN2811

V

0.1ꢃF

TERM

Figure 18. AC-Coupled Output Configuration

Figure 19. AC-Coupled Input Configuration

–13–

REV. A

ADN2811

Choosing AC-Coupling Capacitors

DC-Coupled Application

The choice of ac-coupling capacitors at the input (PIN, NIN)

and output (DATAOUTP, DATAOUTN) of the ADN2811

must be chosen carefully. When choosing the capacitors, the

time constant formed with the two 50 Ω resistors in the signal

path must be considered. When a large number of consecutive

identical digits (CIDs) are applied, the capacitor voltage can

drop due to baseline wander (see Figure 20), causing pattern

dependent jitter (PDJ).

The inputs to the ADN2811 can also be dc-coupled. This may

be necessary in burst mode applications where there are long

periods of CIDs and baseline wander cannot be tolerated. If the

inputs to the ADN2811 are dc-coupled, care must be taken not

to violate the input range and common-mode level requirements

of the ADN2811 (see Figures 21–23). If dc-coupling is required,

and the output levels of the TIA do not adhere to the levels

shown in Figures 22 and 23, then there will need to be level

shifting and/or an attenuator between the TIA outputs and the

ADN2811 inputs.

For the ADN2811 to work robustly at OC-48, a minimum

capacitor of 0.1 µF to PIN/NIN and 0.1 µF on DATAOUTP/

DATAOUTN should be used. This is based on the assumption

that 1000 CIDs must be tolerated and that the PDJ should be

limited to 0.01 UI p-p.

ADN2811

C

OUT

V1

IN

V2

NIN

+

DATAOUTP

DATAOUTN

50ꢄ

V

LIMAMP

CDR

REF

TIA

C

OUT

V1b

V2b

50ꢄ

IN

2

3

4

1

V1

V1b

V2

V

REF

V2b

VTH

V

DIFF

V

= V2–V2b

DIFF

VTH = ADN2811 QUANTIZERTHRESHOLD

NOTES

1. DURING DATA PATERNSWITH HIGHTRANSITION DENSITY, DIFFERENTIAL DCVOLTAGE AT V1 AND V2 IS ZERO.

2. WHENTHE OUTPUT OFTHE TIA GOESTO CID, V1 AND V1b ARE DRIVENTO DIFFERENT DC LEVELS. V2 AND V2b DISCHARGETOTHEV

EFFECTIVELY INTRODUCES A DIFFERENTIAL DC OFFSET ACROSSTHE AC-COUPLING CAPACITORS.

LEVEL,WHICH

REF

3. WHENTHE BURST OF DATA STARTS AGAIN,THE DIFFERENTIAL DC OFFSET ACROSSTHE AC-COUPLING CAPACITORS IS APPLIEDTOTHE INPUT LEVELS,

CAUSING A DC SHIFT INTHE DIFFERENTIAL INPUT. THIS SHIFT IS LARGE ENOUGH SUCHTHAT ONE OFTHE STATES, EITHER HIGH OR LOW DEPENDING ON

THE LEVELS OF V1 AND V1bWHENTHE TIAWENTTO CID, IS CANCELLED OUT. THE QUANTIZERWILL NOT RECOGNIZETHIS AS AVALID STATE.

4. THE DC OFFSET SLOWLY DISCHARGES UNTILTHE DIFFERENTIAL INPUTVOLTAGE EXCEEDSTHE SENSITIVITY OFTHE ADN2811.THE QUANTIZERWILL BE

ABLETO RECOGNIZE BOTH HIGH AND LOW STATES ATTHIS POINT.

Figure 20. Example of Baseline Wander

REV. A

–14–

ADN2811

INPUT (V)

VCC

ADN2811

50ꢄ

NIN

V p-p = PIN – NIN = 2 ꢁ V = 10mV AT SENSITIVITY

SE

TIA

V

= 5mV MIN

SE

V

= 0.4V MIN

CM

(DC-COUPLED)

NIN

50ꢄ

VREF

0.1ꢃF

Figure 22. Minimum Allowed DC-Coupled Input Levels

Figure 21. ADN2811 with DC-Coupled Inputs

INPUT (V)

V p-p = PIN – NIN = 2 ꢁ V = 2.4V MAX

LOL Toggling during Loss of Input Data

SE

If the input data stream is lost due to a break in the optical link

(or for any reason), the clock output from the ADN2811 will

stay within 1000 ppm of the VCO center frequency as long as

there is a valid reference clock. The LOL pin will toggle at a

rate of several kHz. This is because the LOL pin will toggle

between a Logic 1 and a Logic 0 while the frequency loop and

phase loop swap control of the VCO. The chain of events are as

follows:

V

= 1.2V MAX

SE

V

= 0.6V

CM

(DC-COUPLED)

NIN

• The ADN2811 is locked to the input data stream; LOL = 0.

Figure 23. Maximum Allowed DC-Coupled Input Levels

• The input data stream is lost due to a break in the link. The

VCO frequency drifts until the frequency error is greater

than 1000 ppm. LOL is asserted to a Logic 1 as control of

the VCO is passed back to the frequency loop.

• The frequency loop pulls the VCO to within 500 ppm of its

center frequency. Control of the VCO is passed back to the

phase loop and LOL is deasserted to a Logic 0.

• The phase loop tries to acquire, but there is no input

data present so the VCO frequency drifts.

• The VCO frequency drifts until the frequency error is

greater than 1000 ppm. LOL is asserted to a Logic 1 as

control of the VCO is passed back to the frequency

loop. This process is repeated until a valid input data

stream is re-established.

REV. A

–15–

ADN2811

OUTLINE DIMENSIONS

48-Lead Frame Chip Scale Package [LFCSP]

7 mm ꢀ 7 mm Body

(CP-48)

Dimensions shown in millimeters

0.30

0.23

0.18

7.00

BSC SQ

0.60 MAX

PIN 1

INDICATOR

37

48

36

1

PIN 1

INDICATOR

5.25

5.10

4.95

6.75

BSC SQ

BOTTOM

VIEW

TOP

VIEW

SQ

0.50

0.40

0.30

25

24

12

13

5.50

REF

1.00 MAX

0.65 NOM

1.00

0.90

0.80

12ꢁ MAX

0.05 MAX

0.02 NOM

0.50 BSC

0.20

REF

COPLANARITY

0.08

SEATING

PLANE

COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2

Revision History

Location

Page

12/02—Data Sheet changed from REV. 0 to REV. A.

Change to FUNCTIONAL DESCRIPTION Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

REV. A

–16–


型号：	ADN2811ACP-CML-RL
厂家：	ADI
描述：	OC-48/OC-48 FEC Clock and Data Recovery IC with Integrated Limiting Amp OC- 48 / OC- 48 FEC时钟和数据恢复IC，集成限幅放大器 ATM集成电路 SONET集成电路 SDH集成电路电信集成电路电信电路放大器异步传输模式时钟
文件：	总16页 (文件大小：347K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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