ADN2849SURF_技术文档

10.7 Gbps Electro-Absorption Modulator Driver

Preliminary Technical Data

ADN2849

FEATURES

Data Rates up to 10.709Gb/s

Typical Rise/Fall Time 27ps

Power Dissipation 900mW (at 2V swing, 1V offset)

Programmable Modulation Voltage up to 3V

Programmable Bias Offset Voltage up to 2V

Voltage-input control for offset, modulation

Cross Point Adjust Range 30%- 85%

Selectable Data Retiming

PRODUCT DESCRIPTION

The ADN2849 is a low power 10.7Gbps driver for electro-

absorption modulator (EAM) applications. The modulation

voltage is programmable via an external voltage up to a

maximum swing of 3V when driving 50Ω. The bias offset

voltage and output eye cross point are also programmable. On-

chip 50Ω resistor is provided for back termination of the

output. The ADN2849 is driven by AC coupled differential

CML level data and has selectable data retiming to remove jitter

from data input signal. The modulation voltage can be enabled

or disabled by driving the MOD_ENB pin with the proper logic

levels. It can operate with positive or negative (5.2V or 5.0V)

supply voltage.

PECL/CML Data & Clock Inputs

50Ω on Chip Data & Clock Terminations

Modulation Ebnable/Disable

|S₁₁|<-10dB , |S₂₂|<-8dB at 10GHz

The ADN284949 is available in a compact 4x4mm plastic

package or dice format.

Positive or negative 5.2 or 5.0V single supply operation

Available in dice and 4x4mm 24 Lead LFCSP package

APPLICATIONS

SONET OC-192 Optical Transmitters

SDH STM-64 Optical Transmitters

10Gb Ethernet IEEE802.3

XFP/X2/XENPACK/MSA-300 Optical Modules

CPAP CPAN MOD_SET

BIAS_SET

GND VTERM MODN_TERM

GND

ADN2849

R

50

Ω

DATAP

50

Ω

MODP

CROSS

POINT

ADJUST

DATAN

VBB

MUX

D

Q

CLKP

50

Ω

CLKN

VEE

CLK_SELB

MOD_ENB

Figure 1. Functional Block Diagram

Rev. Pr. G August 2004

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Tel: 781.329.4700

Fax: 781.326.8703

www.analog.com

Preliminary Technical Data

ADN2849

Specifications

(Electrical Specifications (VEE=VEE_MINto VEE_MAX. All specifications T_minto T_max, Z_L=50Ω unless otherwise noted. Typical values

specified at 25⁰C)

Table 1.

Parameter

Min

Typ Max

Unit

Conditions

Bias Offset Voltage(MODP)

Bias offset voltage

-0.25

0.9

-5

-2.0

1.1

5

V

V/V

%

Note 1

BIAS_SET voltage to bias offset voltage gain

Bias offset voltage drift over temperature and VEE

Modulation Voltage(MODP)

Modulation voltage swing

MOD_SET voltage to modulation voltage swing gain

Modulation voltage drift over temperature and VEE

Back termination resistance

Rise time (20% - 80%)

T_a=25⁰C, VEE=-5.2V

0.6

1.5

-5

3.0

1.9

5

V

V/v

%

Note1

T_a=25⁰C, VEE=-5.2V

40

60

Ω

ps

ps RMS

ps_p-p

%

V

27

36

0.75

10

85

5

Fall time (20% - 80%)

Random jitter

Total jitter

Cross point adjust range

Cross point drift over temperature and VEE

Minimum output voltage(single ended)

|S₂₂|

Modulation enable time

Modulation disable time

Data Inputs (DATAP, DATAN)

Differential Input voltage

Termination resistance

30

-5

VEE+1.7

Note1

At 10GHz

-8

dB

ns

100

600

40

1600

60

mV_p-p

Ω

Setup time (see figure 2)

Hold time (see figure 2)

|S₁₁|

25

ps

DB

CLK_SELB=’0’

At 10GHz

-10

Clock Inputs (CLKP, CLKN)

Differential Input voltage

Termination resistance

600

40

1600

60

mV_p-p

Ω

dB

|S₁₁|

At 10GHz

Cross point adjust (CPAN, CPAP)

Input voltage range

CPAP, CPAN differential voltage

Input current

-0.85

85

-1.85

0.6

115

V

V_p-p

µA

Logic Inputs (MOD_ENB, CLK_SELB)

V_IH

V_IL

I_IL

VEE+2

V

VEE+0.8

-400

20

V_I=VEE+0.4V

V_I=VEE+2.4V

V_I=0V

µA

I_IH

200

Supply

VEE

I_EE

-4.75

-5.2 -5.5

52

V

mA

IMOD=0

V_MODP/MODN=0

Notes:

Minimum supply voltage and minimum output voltage determine maximum output swing and maximum bias offset that can be achieved concurrently.

Measured using the characterization circuit shown in figure 3.

Rev. Pr. G | Page 2 of 17

Preliminary Technical Data

ADN2849

SETUP

t_S

HOLD

t_H

DATAP/N

CLKP/N

Figure 2. Setup and hold time

Figure 3. High-speed characterization circuit

Rev. Pr. G | Page 3 of 17

Preliminary Technical Data

ADN2849

ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter

Min Max Units Conditions

VEE to GND

VBB to GND

TBD TBD

V

DATAP, DATAN to GND

CLKP, CLKN to GND

CPAP, CPAN to GND

MOD_SET to GND

BIAS_SET to GND

MOD_ENB to GND

CLK_SELB to GND

Staorage temperature range -60

+150 ⁰C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only;

functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is

not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability

PACKAGE THERMAL SPECIFICATIONS

Table 3.

PARAMETER

θ_J-TOP

θ_J-PAD

MIN

TBD

TYP

TBD

MAX

TBD

UNITS

⁰C/W

CONDITIONS/COMMENTS

Thermal resistance from junction to top of package

Thermal resistance from junction to bottom of exposed pad

ORDERING GUIDE

Table 4.

Model

Temperature range

-40⁰C to +85⁰C

Package description

24 Lead LFCSP

Bare die

ADN2849ACP

ADN2849ACP-RL

ADN2849ACP-RL7

ADN2849SURF

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily

accumulate on the human body and test equipment and can discharge without detection. Although

this product features proprietary ESD protection circuitry, permanent damage may occur on devices

subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are

recommended to avoid performance degradation or loss of functionality.

Rev. Pr. G | Page 4 of 17

Preliminary Technical Data

ADN2849

TYPICAL PERFORMANCE CHARACTERISTICS (T_A=25⁰C, VEE=-5.2V)

000

TBD

000

ALL CAPS (Initial cap)

Figure 4. Rise time vs. Swing

Figure 7. Total jitter vs. Swing

000

TBD

000

ALL CAPS (Initial cap)

Figure 5. Fall time vs. Swing

Figure 8. Cross point vs. differential voltage at CPAP/CPAN pins

000

TBD

000

TBD

000

ALL CAPS (Initial cap)

Figure 9. Differential S11 vs. frequency

Figure 6. Random jitter vs. Swing

Rev. Pr. G | Page 5 of 17

Preliminary Technical Data

ADN2849

000

TBD

000

ALL CAPS (Initial cap)

Figure 10. Single-ended S22 vs. frequency

Figure 13. Electrical eye diagram

(2.5V swing, 0.5V offset, PRBS31 at 10.7Gbps)

000

TBD

000

ALL CAPS (Initial cap)

000

ALL CAPS (Initial cap)

Figure 14. Optical eye diagram using the FLD5F20NP EML

Figure 21. Total supply current vs. Swing with retiming disabled

(Pav=0dBm, ER=10dB, PRBS31 pattern at 9.95328Gbps, SONET

OC192 mask test)

000

TBD

000

ALL CAPS (Initial cap)

Figure 12. Total supply current vs. Swing with retiming enabled

Rev. Pr. G | Page 6 of 17

Preliminary Technical Data

ADN2849

PIN CONFIGURATION AND FUNCTION DESCRIPTION

1

GND

VTERM

GND

DATAP

DATAN

MODP

MODN_TERM

GND

ADN2849

VBB

CLKP

CLKN

VEE

Figure 15. Pin configuration

Note: There is a n exposed pad on the bottom of the package that must be connected to the most negative supply rail of the ADN2849

Table 5.

Pin number

1, 10, 11, 14,17, 20

Mnemonic

GND

Description

Positive power supply

2

3

4

DATAP

DATAN

VBB

AC coupled CML data, positive differential terminal

AC coupled CML data, negative differential terminal

CML termination resistor

5

6

7

8

CLKP

CLKN

MOD_ENB

CLK_SELB

MOD_SET

VEE

AC coupled CML clock, positive differential terminal

AC coupled CML clock, negative differential terminal

Modulation enable logic input

Retiming select logic input

Modulation voltage set input

9

12, 13, 21

Negative power supply

15

16

18, 19

22

23

24

MODN_TERM

MODP

VTERM

BIAS_SET

CPAP

Termination resistor for MODN

Positive modulation voltage output

Back termination voltage output

Bias offset voltage set input

Cross point adjust positive control input

Cross point adjust negative control input

Connect to the most negative supply rail of the ADN2849

CPAN

Pad

Exposed Pad

Rev. Pr. G | Page 7 of 17

Preliminary Technical Data

ADN2849

PAD CONFIGURATION AND FUNCTION DESCRIPTION

25 24 23

22 21 20 19 19

18

17

1

2

16

3

4

ADN2849

4

5

6

15

14

13

26 7

8

9

10

11

12 27

Figure 16. Pad configuration

(Die size 2.05×2.05mm, single bond pad size 84×84µm with 76×76µm glass opening, double bond pad size 184×84µmwith 176×76µm)

Notes:

1. The metallization photograph and the die pad coordinates appear at the end of this document.

2.The pads that have the same number must be bonded together.

3. The back side of the die must be connected to the most negative supply rail of the ADN2849

Table 6.

Pad number

1, 10, 11, 14,17, 20, 25, 26, 27

Mnemonic

GND

Description

Positive power supply

2

3

4

DATAP

DATAN

VBB

AC coupled CML data, positive differential terminal

AC coupled CML data, negative differential terminal

CML termination resistor

5

6

7

8

CLKP

CLKN

MOD_ENB

CLK_SELB

MOD_SET

VEE

AC coupled CML clock, positive differential terminal

AC coupled CML clock, negative differential terminal

Modulation enable logic input

Retiming select logic input

Modulation voltage set input

9

12, 13, 21

Negative power supply

15

16

18, 19

22

23

MODN_TERM

MODP

VTERM

BIAS_SET

CPAP

Termination resistor for MODN

Positive modulation voltage output

Back termination voltage output

Bias offset voltage set input

Cross point adjust positive control input

Cross point adjust negative control input

24

CPAN

Rev. Pr. G | Page 8 of 17

Preliminary Technical Data

ADN2849

THEORY OF OPERATION

GENERAL

GND

Figure 17 shows a typical EA modulator characteristic. Vm

represents the voltage across the modulator and Pout represents

the optical output power. For small voltages across the

modulator it is in its high transmission state. As the voltage

becomes more negative, the modulator becomes less

transparent to the laser light. Fig. 17 also shows a typical drive

signal for an EA modulator. It consists of a modulation signal

with a swing Vs, and a bias offset voltage Vb

DATAP/CLKP

DATAN/CLKN

VBB

VEE

GND

VEE

Pout

VEE

GND

50Ω

Vm

VEE

Figure 18. Equivalent circuit for the data and clock input pins

Vs

Vb

The data and clock input pins are internally terminated with a

100Ω differential termination resistor to minimize signal

reflections at the input pins that could otherwise lead to

degradation in the output eye diagram. The ADN2849 input

pins must be AC-coupled with the signal source to eliminate the

need of matching between the common mode voltages of the

data signal source and the inputs stage of the driver. Also, the

common mode terminal of the internal termination resistors

(VBB) must be externally decoupled. Figure 19 shows the

recommended connection between the data/signal source and

the ADN2849 input pins.

Figure 17. Typical transfer function of an EA modulator

As shown in the functional block diagram (figure 1), the

ADN2849 consists of an input stage for data signals, a cross

point adjust block and the output stage that generates the bias

offset and modulation voltages. The retiming option allows the

user to reduce the jitter by applying a reference clock to the

clock inputs of the ADN2849. The cross point adjust block pre-

distorts the data signal applied to the output stage in order to

compensate for the non-linear transfer function of the EA

modulator as shown in figure 17. The modulation and the bias

offset voltage can be programmed via external DC voltages

applied to the ADN2849. These voltages are converted to

currents internally and applied to the output stage. The single-

ended output stage provides both the bias offset and

modulation voltages at the same pin (MODP) without the need

of any external components. The ADN2849 can operate with

positive or negative (5.0V or 5.2V) supply voltage.

50Ω

C

DATAP/CLKP

C

ADN2849

DATAN/CLKN

VBB

INPUT STAGE

The input stage of the ADN2849 gains the data and clock

signals applied to the DATAP, DATAN and CLKP, CLKN pins

respectively to a level that ensures proper operation of the

ADN2849’s output stage. The data and clock inputs are

PECL/CML compatible and can accept input signal swings in

the range of 600mV to 1600mV peak-to peak differential. The

equivalent circuit for the data and clock input pins is shown in

figure 18.

C

GND

Data/clock signal source

Figure 19. AC-coupling the data/clock signal source to the ADN2849

input pins

Rev. Pr. G | Page 9 of 17

Preliminary Technical Data

ADN2849

The capacitors used AC-coupling and the decoupling of the

VBB pin must have an impedance less than 50Ω over the

required operating frequency range. Generally this is achieved

using values from 10nF to 100nF.

CROSS POINT ADJUST

The cross point adjust function allows the user to move the eye

crossing level in the modulation voltage to compensate for

asymmetry in the EA modulator electrical-to- optical transfer

function. Figure 21 shows an example on how the cross point

adjust can compensate the asymmetry of the EA modulator

transfer function. The 50% cross point in the optical eye can be

obtained in this case by moving the cross point of the signal

applied to the EA modulator away from the 50% point.

The retiming feature of the ADN2849 allows the user to remove

the data dependent jitter present on the DATAP and DATAN

pins by applying the data and clock signals to the ADN2849’s

internal latch. The retiming feature can be enabled or disabled

depending on the logic level applied to the CLK_SELB pin as

described in table 7. Note that any jitter present on the CLKP

and CLKN pins is added to the output.

Optical

Output

Table 7.

CLK_SELB logic level

Retiming function

Disabled

High

Low

Enabled

If the retiming feature is disabled the CLKP and CLKN inputs

can be left floating.

Electrical

Input

The CLK_SELB is a 5V TTL and CMOS compatible digital

input. Its equivalent circuit is shown in figure 20.

GND

Figure 21. Cross point adjust compensation

60K

GND

180K

The cross point is controlled by the differential voltage applied

to the CPAP and CPAN pins. The equivalent circuit of the

CPAP and CPAN pins is shown in figure 22.

CLK_SELB

40K

GND

VEE

CPAP

100Ω

VEE

GND

VEE

Figure 20. Equivalent circuit of the CLK_SELB pin

CPAN

100Ω

100µA

VEE

Figure 22. Equivalent circuit of the CPAP and CPAN pins

Rev. Pr. G | Page 10 of 17

Preliminary Technical Data

ADN2849

The single-ended voltage at CPAP and CPAN pins must be

within the –0.8V to-1.85V range for proper operation of the

cross point adjust block. The cross point will be controlled by

the differential voltage obtained from the single-ended voltages

applied to CPAP and CPAN pins. A simple implementation of a

cross point adjust circuit is shown in figure 23 where a 20KΩ

potentiometer generates the required differential voltage within

the specified input voltage range.

The MOD_ENB pin is a 5V TTL and CMOS compatible logic

input. Its equivalent circuit of the MOD_ENB pin is shown in

figure 24.

GND

180K

GND

60K

GND

MOD_ENB

40K

20kΩ

CPAP

CPAN

VEE

Cross

Point

Adjust

100uA

VEE

Figure 24. Equivalent circuit of the MOD_ENB pin

VEE

Figure 23. Cross point adjust control circuit

An alternative implementation is to use a voltage DAC and a

single-ended to differential conversion amplifier such as the

AD138 that will allow digital control of the cross point. When

designing the circuitry that will drive the voltages at the CPAP

and CPAN pins the user should take in account that each pin is

sinking 100µΑ. If the cross point adjust feature is not required

both the CPAP and CPAN pins should be connected to GND.

This will automatically set the cross point to 50%. Once the

cross point adjust has been calibrated under nominal conditions

it has very low drift over temperature and supply voltage

variations.

OUTPUT STAGE

The output stage of the ADN2849 can provide up to 2V bias

offset and up to 3V modulation voltage across a single-ended

50Ω load. Both the bias offset and the modulation voltage are

made available at a single pin (MODN) eliminating the need for

external bias inductors as shown in figure 25.

GND

+

-

+

-

V

BIAS_SET

100nF

MOD_SET

MODULATION ENABLE

GND

50

Ω

The modulation voltage generated by the ADN2849 can be

enabled or disabled under the control of the MOD_ENB pin.

When the modulation is disabled, the input data is ignored and

the voltage at the output of the ADN2849 will place the EA

modulator in a high absorption (low transparency) state. The

relationship between the logic state of the MOD_ENB input and

the modulation voltage is described in table 8.

ADN2849

R

EAM

50

Ω

MODP

From cross

point adjust

block

IMOD

Table 8.

VEE

MOD_ENB logic level

Modulation voltage

Enabled

Low

High

Disabled

Figure 25. Output stage of the ADN2849

Rev. Pr. G | Page 11 of 17

Preliminary Technical Data

ADN2849

GND

Modulation voltage

VTERM

The modulation voltage is established by switching the

modulation current through the parallel combination of the

modulator terminating impedance (50Ω) and the 50Ω back-

termination resistor on the ADN2849. The modulation set

voltage applied to the MOD_SET pin is converted into current

(IMOD) using a voltage-to-current converter which forces a

voltage equal to V_{MOD_SET}across an internal fixed resistor. For

IMOD range of 24mA to 120mA, the MOD_SET voltage ranges

from 340mV to 1.7V. With its maximum modulation current of

120mA, the ADN2849 is capable of generating a 3V modulation

voltage across the equivalent load resistance (25Ω). The

equivalent circuit of the MOD_SET pin is shown in figure 26.

MODN_TERM

50Ω

10K

MODP

VEE

100Ω

VEE

GND

VEE

BIAS_SET

5K

100Ω

VEE

GND

Figure 27. Equivalent circuit of the BIAS_SET, MODP, MODN_TERM

and VTERM pins

MOD_SET

100Ω

During factory calibration of the optical transmitter, the user

adjusts the BIAS_SET and MOD_SET voltages to achieve the

desired bias offset and modulation voltages. This adjustment

calibrates out BIAS_SET to bias offset voltage and MOD_SET to

modulation voltage gain variations in the ADN2849 due to

resistor process variations and the offset of the internal

amplifiers. The drift in the bias offset and modulation voltages

over temperature and supply voltage variations is very low once

it has been calibrated under nominal conditions.

VEE

Figure 26. Equivalent circuit of the MOD_SET pin

Headroom calculations

The ADN2849 is capable of delivering up to 2V bias offset and

up to 3V modulation voltage on a 50Ω single-ended load.

However, these values for the bias offset and modulation

voltages cannot be obtained at the same time due to headroom

constraints. The minimum supply voltage and the MODP

minimum output voltage specifications determine the

maximum modulation and bias offset voltages that can be

achieved concurrently. In order to guarantee proper operation

of the ADN2849, the bias offset and modulation voltages must

satisfy the following condition:

Bias offset voltage

The bias offset voltage is set by adjusting the voltage between

the BIAS_SET pin and GND. An internal operational amplifier

sets the termination voltage for the internal 50Ω output back-

termination resistors (VTERM) by gaining up the BIAS_SET

voltage by two. This gain of two cancels out the attenuation of

the dividing network formed by the 50Ω back- termination

resistor from the ADN2849 output and the 50Ω load

termination, providing a nominal gain of one from the

BIAS_SET input to the bias offset voltage available at the output

of the ADN2849 (MODP pin). For proper operation, an

external low ESR 100nF decoupling capacitor is required

between the VTERM pin and GND to prevent transient

disturbances on this node. The equivalent circuits of the

BIAS_SET, MODP, MODN_TERM and VTERM pins are

shown in figure27.

V_Modulation+ V_BiasOffset≤ VEE − V_MODPmin

Where,

V_Modulation= the required modulation voltage

V_{Bias Offset}= the required bias offset voltage

VEE = the supply voltage

V_MODPmin= the minimum voltage at the MODP pin (see table 1)

Rev. Pr. G | Page 12 of 17

Preliminary Technical Data

ADN2849

POWER DISSIPATION

For improved heat dissipation the module’s case can be used as

heat sink as shown in figure 29. A compact optical module is a

complex thermal environment, and calculations of device

junction temperature using the package θ_J-A(Junction-to-

Ambient thermal resistance) do not yield accurate results.

The power dissipated by the ADN2849 is a function of the

supply voltage and the level of bias offset and modulation

voltages required. Figure 28 shows the power dissipation of the

ADN2849 vs. modulation voltage for different bias offset

voltages. To ensure long-term reliable operation, the junction

temperature of the ADN2849 must not exceed 125⁰C.

000

TBD

000

ALL CAPS (Initial cap)

Figure 28. Power dissipation of the ADN2849 vs. bias offset and modulation voltage

Thermal Compound

Module Case

Die

T

TO P

T_J

Package

Thermo-couple

T

PAD

PCB

Copper Plane

Filled Vias

Figure 29. Typical optical module structure

Rev. Pr. G | Page 13 of 17

Preliminary Technical Data

ADN2849

The following procedure can be used to estimate the IC

junction temperature.

T_TOPand T_PADcan be determined by measuring the temperature

at points inside the module, as shown in fig. 30. The thermo-

couples should be positioned so as to obtain an accurate

measurement of the package top and paddle temperatures.

Using this model the junction temperature can be calculated

using the formula:

T

_TOP= Temperature at top of package in ⁰C.

T_PAD= Temperature at package exposed paddle in ⁰C.

T_J= IC junction temperature in ⁰C.

P × (θ_{J −PAD}×θ_{J −TOP}) + T_TOP×θ_{J −PAD}+ T_PAD×θ_{J −TOP}

T_J=

P = Power disipation in W.

θ_{J −PAD}+θ_{J −TOP}

θ_J-TOP= Thermal resistance from IC junction to package top.

θ_J-PAD= Thermal resistance from IC junction to package

exposed pad.

Where θ_J-TOPand θ_J-PADare given in table 3 and P is the power

dissipated by the ADN2849 obtained from the graph shown in

figure 28

.

T_TOP

θ_J-TOP

T_J

T_TOP

θ_J-PAD

P

T_PAD

Fig. 32. Electrical model for thermal calculations

Rev. Pr. G | Page 14 of 17

Preliminary Technical Data

ADN2849

the CLKP and CLKN pins must be made using

50Ω transmission lines. The cross point can be adjusted using

the potentiometer R3. The modulation voltage can be enabled

or disabled using the MOD_ENB pin.

APPLICATIONS INFORMATION

TYPICAL APPLICATION CIRCUIT

Figure 31 shows the typical application circuit for the

ADN2849. Applying DC voltages to the BIAS_SET and

MOD_SET pins can control the Modulation and bias offset

voltages. The data signal source must be connected to the

DATAP and DATAN pins using 50Ω impedance transmission

lines. If a reference clock signal is available, the retiming option

can be enabled using the CLK_SELB input. Note that the

connection between the clock signal source and

The ADN2849 can operate with positive or negative (5.0V or

5.2V) supply voltage. Care should be taken to connect the GND

pins to the positive rail of the supply voltage while the VEE and

the exposed pad to the negative rail of the supply voltage.

BIAS_SET

JP1

GND

R4

C15

GND

VEE

C18

C13

R3

JP2

GND

50Ω

BIAS_SET VEE

CPAN CPAP

GND

VTERM

GND

VTERM

GND

C1

GND

Z

DATAP

DATAN

EAM

J1

J2

Z

=50Ω

0

=50Ω

U1

0

Z

0

=50Ω

MODP

C7

C2

C3

GND

ADN2849

GND

VBB

MODN_TERM

GND

C11

J3

J4

CLKP

Z

=50

Ω

0

Z

=50Ω

0

CLKN

VEE

C4

GND

MOD_ENB

CLK_SELB

M OD_SET GND GND VEE

GND

C10

VEE

-5.2V

VEE

C5

MOD_SET

C12

C6

GND

M OD_ENB

CLK_SELB

Figure 31. Typical ADN2849 application circuit

VTERM, VBB, MODN_TERM and VEE pins must be locally

decoupled with high quality capacitors. If proper decoupling

cannot be achieved using a single capacitor, the user can use

multiple capacitors in parallel for each GND pin. A 20µF

tantalum capacitor must be used as general decoupling

capacitor for the entire module The exposed pad should be

connected to the most negative rail of the supply voltage using

filled vias so that solder does not leak through the vias during

reflow. Using filled vias under the package greatly enhances the

reliability of the connectivity of the exposed pad to the GND

plane during reflow.

PCB LAYOUT GUIDELINES

Due to the high frequencies at which the ADN2849 operates,

care should be taken when designing the PCB layout in order to

obtain optimum performance. It is recommended to use

controlled impedance transmission lines for the high-speed

signal paths The length of the transmission lines must be kept

to a minimum to reduce losses and pattern dependant jitter. All

the VEE and GND pins must be connected to solid copper

planes using low inductance connections. When the

connections are made through vias, multiple vias can be

connected in parallel to reduce the parasitic inductance. The

Rev. Pr. G | Page 15 of 17

Preliminary Technical Data

ADN2849

DESIGN EXAMPLE

This section describes a design example that covers the

followings:

MOD_SET voltage range

The voltage range at the MOD_SET pin to generate 2V bias

offset voltage at the MODP pin can be calculated using the

MOD_SET voltage to bias offset voltage gain specification from

table1 using the formulae:

•

Headroom calculation for the required bias offset and

modulation voltages

•

Required voltage range at the BIAS_SET and

MOD_SET pins to generate the required bias offset

and modulation voltages

V_MODULATION

V_{MOD _ SET min}

V_{MOD _ SET max}

=

K_max

V_MODULATION

K_min

This design example assumes a -5.2V supply voltage, 0.5V bias

offset voltage and 2V modulation voltage.

Where K_minand K_maxare the minimum and maximum values of

the MOD_SET voltage to offset bias voltage gain from table1.

Substituting the values the MOD_SET voltage range is 1.05V to

1.33V.

Headroom calculations

In order to operate properly, the bias offset and modulation

voltages must satisfy the following condition:

V_Modulation+ V_BiasOffset≤ VEE − V_MODPmin

Assuming that V_MODPmin=1.7V (see table1), the above condition

became:

2.5V ≤ 5.2 −1.7 = 3.5V

BIAS_SET voltage range

The voltage range at the BIAS_SET pin to generate 0.5V bias

offset voltage at the MODP pin can be calculated using the

BIAS_SET voltage to bias offset voltage gain specification from

table1 using the formulae:

V_{BIAS OFFSET}

V_{BIAS_ SET min}

V_{BIAS_ SET max}

=

K_max

V_{BIAS OFFSET}

K_min

Where K_minand K_maxare the minimum and maximum values of

the BIAS_SET voltage to offset bias voltage gain from table1.

Substituting the values the BIAS_SET voltage range is 0.45V to

0.55V.

Rev. Pr. G | Page 16 of 17

Preliminary Technical Data

ADN2849

OUTLINE DIMENSIONS

0.60 MAX

4.0

BSC SQ

PIN 1

INDICATOR

0.60 MAX

1

19

24

18

PIN 1

INDICATOR

0.50

BSC

2.25

TOP

VIEW

3.75

BSC SQ

BOTTO M

VIEW

SQ

2.10

1.95

0.50

0.40

0.30

6

13

12

7

0.25 MIN

2.50 REF

0.80 MAX

0.65TYP

1. 00

0. 85

0.80

12ꢀ MAX

0.05 MAX

0.02 NOM

0.30

0.23

0.18

COPLANARITY

0.20 REF

0.08

SEATING

PLANE

COMPLIANT TO JEDECSTANDARDS MO-220-VGGD-2

Figure 32. 24-Lead Lead Frame Chip Scale Package (LFCSP) 4mm×4mm Body (CP-24)

Dimensions shown in millimeters

Table 9. Die pad coordinates

Pad Number

X(µm)

-920.50

-609.10

-457.30

-305.50

-103.70

324.85

584.00

920.50

628.00

501.10

349.30

182.40

3.50

Y(µm)

685.00

331.55

103.05

-48.75

1

2

3

4

5

6

7

-220.15

-371.95

-525.55

-920.50

-688.20

-484.20

-271.10

274.50

490.00

694.00

920.50

-920.50

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

-457.30

-609.10

-736.00

738.00

Figure 33. ADN2849 metallization photograph

Note: The coordinates are measured between the center of the die and the center

of the pad.

Rev. Pr. G | Page 17 of 17


型号：	ADN2849SURF
厂家：	ADI
描述：	10.7 Gbps Electro-Absorption Modulator Driver 10.7 Gbps的电吸收调制器驱动器驱动器
文件：	总17页 (文件大小：1043K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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