ADN2890_17 [ADI]
Limiting Amplifier;
| 型号： | ADN2890_17 |
| 厂家： | 
ADI |
| 描述： | Limiting Amplifier |
| 文件： | 总12页 (文件大小：350K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
3.3 V 2.7 Gb/s
Limiting Amplifier
ADN2890
Data Sheet
FEATURES
GENERAL DESCRIPTION
SFP reference design available
Input sensitivity: 3 mV p-p
80 ps rise/fall times
CML outputs: 700 mV p-p differential
Programmable LOS detector: 2 mV to 13 mV
Rx signal strength indicator (RSSI):
SFF-8472 compliant average power measurement
Single-supply operation: 3.3 V
The ADN2890 is a high gain, limiting amplifier optimized for
use in SONET, Gigabit Ethernet (GbE), and Fibre Channel
optical receivers that accept input levels of up to 2.0 V p-p
differential and have 3 mV p-p differential input sensitivity. The
ADN2890 provides the receiver functions of quantization and
loss of signal (LOS) detection. The ADN2890 can easily operate
at up to 3.2 Gb/s to support LX4 transceivers.
The limiting amplifier also measures average received power
based on a direct measurement of the photodiode current with
better than 1 dB of accuracy over the entire input range of the
receiver. This eliminates the need for external average Rx power
detection circuitry in SFF-8472 compliant optical transceivers.
Low power dissipation: 130 mW
Available in space-saving 3 mm × 3 mm 16-lead LFCSP
APPLICATIONS
SFP/SFF/GBIC optical transceivers
OC-3/12/48, GbE, Fibre Channel receivers
10GBASE-LX4 transceivers
The ADN2890 limiting amplifier operates from a single 3.3 V
supply, has low power dissipation, and is available in a space-
saving 3 mm × 3 mm 16-lead lead frame chip scale package
(LFCSP).
WDM transponders
FUNCTIONAL BLOCK DIAGRAM
AVCC
AVEE
DRVCC DRVEE
DRVCC
ADN2890
50Ω
50Ω
C
R
F
PIN
NIN
OUTP
OUTN
+V
F
ADN2880
50Ω
50Ω
3kΩ
V
REF
10k
Ω
LOS
PD_VCC
RSSI/LOS
DETECTOR
ADuC7020
RSSI_OUT
PD_CATHODE
CAZ1
CAZ2
THRADJ SQUELCH
0.01µF
Figure 1.
Rev. B
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rightsof third parties that may result fromits use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks andregisteredtrademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2004–2017 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
ADN2890
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Typical Performance Characteristics ..............................................7
Theory of Operation .........................................................................8
LIMAMP ........................................................................................8
Loss of Signal (LOS) Detector .....................................................8
Received Signal Strength Indicator (RSSI) ................................8
Squelch Mode ................................................................................8
Applications Information .................................................................9
PCB Design Guidelines ................................................................9
Outline Dimensions ....................................................................... 11
Ordering Guide .......................................................................... 11
Applications....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 5
Thermal Resistance ...................................................................... 5
ESD Caution.................................................................................. 5
Pin Configuration and Function Descriptions............................. 6
REVISION HISTORY
4/2017—Rev. A to Rev. B
Changed CP-16-27 to CP-16-22.................................. Throughout
Updated Outline Dimensions....................................................... 11
Changes to Ordering Guide .......................................................... 11
10/2013—Rev. 0 to Rev. A
Change to Output Voltage Swing Parameter, Table 1.................. 3
Change to Figure 2 ........................................................................... 6
Updated Outline Dimensions....................................................... 11
Changes to Ordering Guide .......................................................... 11
5/2004—Revision 0: Initial Version
Rev. B | Page 2 of 12
Data Sheet
ADN2890
SPECIFICATIONS
VCC = VMIN to VMAX, VEE = 0 V, T A = TMIN to TMAX, unless otherwise noted.
Table 1.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
QUANTIZER DC CHARACTERISTICS
Input Voltage Range
Input Common Mode
Peak-to-Peak Differential Input Range
Input Sensitivity
Input Offset Voltage
Input RMS Noise
Input Resistance
1.8
2.1
2.8
2.7
2.0
V p-p
V
V p-p
mV p-p
µV
At PIN or NIN, dc-coupled
DC-coupled
PIN − NIN, ac-coupled
PIN − NIN, BER ≤ 1 × 10−10
4
3
100
235
50
µV rms
Ω
Single-ended
Input Capacitance
QUANTIZER AC CHARACTERISTICS
Input Data Rate
Small Signal Gain
S11
S22
Random Jitter
Deterministic Jitter
Low Frequency Cutoff
0.65
pF
155
2700
Mb/s
dB
dB
57
Differential
−10
−10
2.4
13.7
30
Differential, f < 2.7 GHz
Differential, f < 2.7 GHz
Input ≥ 10 mV p-p, OC-48, PRBS 223 − 1
Input ≥ 10 mV p-p, OC-48, PRBS 223 − 1
CAZ = Open
dB
5
19
ps rms
ps p-p
kHz
kHz
dB
1.0
45
CAZ = 0.0 1 µF
100 kHz < f < 10 MHz
Power Supply Rejection
LOSS OF SIGNAL DETECTOR (LOS)
LOS Assert Level
0.5
7.0
2.5
12.0
3.0
4.0
16.0
6.0
mV p-p
mV p-p
dB
RTHRADJ = 100 kΩ
RTHRADJ = 0 Ω
Hysteresis
OC-3, PRBS 223 − 1, RTHRADJ = 0 Ω
OC-3, PRBS 223 − 1, RTHRADJ = 10 kΩ
OC-48, PRBS 223 − 1, RTHRADJ = 0 Ω
OC-48, PRBS 223 − 1, RTHRADJ = 100 kΩ
DC-coupled
2.0
2.5
3.0
4.5
4.5
600
100
dB
dB
dB
ns
7.5
LOS Assert Time
LOS De-Assert Time
RSSI
ns
DC-coupled
Input Current Range
RSSI Output Accuracy
5
1000
15%
10%
µA
IIN ≤ 20 µA
IIN > 20 µA
IRSSI/IPD
Gain
Offset
Compliance Voltage
POWER SUPPLIES
VCC
1.0
50
mA/mA
nA
V
VCC − 1.05
3.0
VCC − 0.3
At PD_CATHODE
3.3
39
3.6
54
V
mA
°C
ICC
OPERATING TEMPERATURE RANGE
CML OUTPUT CHARACTERISTICS
Output Impedance
Output Voltage Swing
Output Rise and Fall Time
−40
+25
+85
TMIN to TMAX
50
700
80
Ω
Single-ended
Differential
20% to 80%
650
800
100
mV p-p
ps
Rev. B | Page 3 of 12
ADN2890
Data Sheet
Parameter
Min
2.0
Typ
Max
Unit
Test Conditions/Comments
LOGIC INPUTS (SQUELCH)
VIH, Input High Voltage
VIL, Input Low Voltage
Input Current
V
V
nA
nA
0.8
−100
IINH, VIN = 2.4 V
IINL, VIN = 0.4 V
100
LOGIC OUTPUTS (LOS)
VOH, Output High Voltage
2.4
V
V
Open drain output, 4.7 kΩ − 10 kΩ
pull-up resistor to VCC
Open drain output, 4.7 kΩ − 10 kΩ
pull-up resistor to VCC
VOL, Output Low Voltage
0.4
Rev. B | Page 4 of 12
Data Sheet
ADN2890
ABSOLUTE MAXIMUM RATINGS
Table 2.
THERMAL RESISTANCE
θJA is specified for 4-layer PCB with exposed paddle soldered
to GND.
Parameter
Rating
Supply Voltage
4.2 V
Minimum Input Voltage (All Inputs)
Maximum Input Voltage (All Inputs)
Storage Temperature
Operating Temperature Range
Lead Temperature Range (Soldering 10 s)
Junction Temperature
VEE − 0.4 V
VCC + 0.4 V
−65°C to +155°C
−40°C to +85°C
300°C
Table 3.
Package Type
θJA
28
Unit
16-Lead 3 mm × 3 mm LFCSP
°C/W
125°C
ESD CAUTION
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Rev. B | Page 5 of 12
ADN2890
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
AVCC
PIN
1
2
3
4
12 DRVCC
OUTP
11
10 OUTN
DRVEE
ADN2890
TOP VIEW
NIN
(Not To Scale)
AVEE
9
NOTES
1.THE EXPOSED PAD ON THE BOTTOM OF
THE PACKAGE MUST BE CONNECTED
TO THE GND PLANE WITH FILLED VIAS.
Figure 2. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
Mnemonic
I/O
Description
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
AVCC
PIN
NIN
AVEE
THRADJ
CAZ1
CAZ2
LOS
DRVEE
OUTN
Power
Input
Input
Power
Input
Analog Power
Differential Data Input
Differential Data Input
Analog Ground
LOS Threshold Adjust Resistor
Offset Correction Loop Capacitor
Offset Correction Loop Capacitor
LOS Detector Output
Output Buffer Ground
Differential Data Output
Differential Data Output
Output Buffer Power
Output
Power
Output
Output
Power
Input
Output
Power
Output
Power
OUTP
DRVCC
SQUELCH
RSSI_OUT
PD_VCC
PD_CATHODE
Pad
Disable Outputs
Average Current Output
Power Input for RSSI Measurement
Photodiode Bias Voltage
Connect to Ground
Exposed Pad
Rev. B | Page 6 of 12
Data Sheet
ADN2890
TYPICAL PERFORMANCE CHARACTERISTICS
0.96
0.88
0.80
0.72
0.64
0.56
0.48
0.40
0.32
0.24
0.16
0.08
0
VERTICAL SCALE: 100mV/DIV
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
RSSI_IN (mA)
Figure 3. RSSI Output vs. Average PIN Photodiode Current
Figure 6. Eye Diagram at 3.2 Gb/s
0.014
VERTICAL SCALE: 100mV/DIV
0.012
0.010
0.008
0.006
0.004
0.002
0
10
100
1k
(
10k
100k
R
Ω)
TH
Figure 4. LOS Trip Point vs. Threshold Adjust Resistor
Figure 7. Eye Diagram at 2.488 Gb/s
70
60
50
40
30
20
10
0
100k
1M
10M
SUPPLY-NOISE FREQUENCY (Hz)
Figure 5. Typical PSRR vs. Supply-Noise Frequency
Rev. B | Page 7 of 12
ADN2890
Data Sheet
THEORY OF OPERATION
LIMAMP
RECEIVED SIGNAL STRENGTH INDICATOR (RSSI)
Input Buffer
The ADN2890 has an on-chip RSSI circuit that automatically
detects the average received power based on a direct measure-
ment of the PIN photodiode’s current. The photodiode bias is
supplied by the ADN2890, which allows a very accurate, on-
chip, average power measurement based on the amount of
current supplied to the photodiode. The output of the RSSI is a
current that is directly proportional to the average amount of
PIN photodiode current. Placing a resistor between the
RSSI_OUT pin and GND converts the current to a GND
referenced voltage. This function eliminates the need for
external RSSI circuitry in SFF-8472 compliant optical receivers.
The limiting amplifier has differential inputs (PIN/NIN), with
an internal 50 Ω termination. The ROSA (receive optical sub-
assembly) is typically ac-coupled to the ADN2890 inputs,
although dc coupling is possible.
An internal offset correction loop requires that a capacitor be
connected between the CAZ1 and CAZ2 pins. A 0.01 µF
capacitor provides a low frequency cutoff of 2 kHz.
CML Output Buffer
The ADN2890 provides CML outputs, OUTP/OUTN. The
outputs are internally terminated with 50 Ω to VCC.
SQUELCH MODE
The outputs can be kept at a static voltage by driving the
SQUELCH pin to a logic high. The SQUELCH pin can be
driven directly by the LOS pin, which automatically disables
the LIMAMP outputs in situations with no data input.
Driving the SQUELCH input to a logic high disables the
limiting amplifier outputs. The SQUELCH input can be
connected to the LOS output to keep the limiting amplifier
outputs at a static voltage level anytime the input level to the
limiting amplifier drops below the programmed LOS threshold.
LOSS OF SIGNAL (LOS) DETECTOR
The receiver front-end LOS detector circuit indicates when the
input signal level has fallen below the user-adjustable threshold.
The threshold is set by a resistor connected between the
THRADJ pin and VEE. The ADN2890 LOS circuit has a trip
point down to <3.0 mV with >3 dB electrical hysteresis to
prevent chatter at the LOS output. The LOS output is an open-
collector output that must be pulled up externally with a 4.7 kΩ
to 10 kΩ resistor.
Rev. B | Page 8 of 12
Data Sheet
ADN2890
APPLICATIONS INFORMATION
PCB DESIGN GUIDELINES
Proper RF PCB design techniques must be used for optimal
performance.
greatly enhances the reliability of the connectivity of the
exposed pad to the GND plane during reflow.
Power Supply Connections and Ground Planes
Use of a 10 μF electrolytic capacitor between VCC and VEE is
recommended at the location where the 3.3 V supply enters the
PCB. When using 0.1 μF and 1 nF ceramic chip capacitors, they
should be placed between the IC power supply VCC and VEE,
as close as possible to the ADN2890 VCC pins.
Use of one low impedance ground plane is recommended. The
VEE pins should be soldered directly to the ground plane to
reduce series inductance. If the ground plane is an internal
plane and connections to the ground plane are made through
vias, multiple vias can be used in parallel to reduce the series
inductance, especially on Pin 9, which is the ground return for
the output buffers. The exposed pad should be connected to the
GND plane using filled vias so that solder does not leak through
the vias during reflow. Using filled vias under the package
If connections to the supply and ground are made through vias,
the use of multiple vias in parallel helps to reduce series
inductance, especially on Pin 12, which supplies power to the
high speed OUTP/OUTN output buffers. Refer to the schematic
in Figure 8 for recommended connections.
VCC
C9
VCC
RSSI MEASUREMENT
TO ADC
R1
C10
0.1F
200
VCC
VCC
C8
C5
C6
16
15
14
13
C7
AVCC
PIN
DRVCC
1
2
3
4
12
11
10
9
C1
C2
OUTP C3
OUTN C4
DRVEE
CONNECT
EXPOSED
PAD TO
GND
TO HOST
BOARD
NIN
ADN2880
AVEE
5
6
7
8
C1–C4, C11: 0.01F X5R/X7R DIELECTRIC, 0201 CASE
C5, C7, C9, C10, C12: 0.1F X5R/X7R DIELECTRIC, 0402 CASE
C6, C8: 1nF X5R/X7R DIELECTRIC, 0201 CASE
C11
R3
4.7k TO 10k
ON HOST BOARD
C12
R2
VCC
Figure 8. Typical ADN2890 Applications Circuit
Rev. B | Page 9 of 12
ADN2890
Data Sheet
50 Ω resistors connected between the output pin and VCC. The
high speed inputs, PIN and NIN, are internally terminated with
50 Ω to an internal reference voltage.
PCB Layout
Figure 9 shows a recommended PC board layout. Use of 50 Ω
transmission lines is required for all high frequency input and
output signals to minimize reflections: PIN, NIN, OUTP and
OUTN. It is also necessary for the PIN/NIN input traces to be
matched in length, and OUTP/OUTN output traces to be matched
in length to avoid skew between the differential traces. C1, C2,
C3, and C4 are ac-coupling capacitors in series with the high
speed I/O. It is recommended that components be used such
that the pad for the capacitor is the same width as the transmission
line in order to minimize the mismatch in the 50 Ω transmission
line at the capacitor’s pads. It is recommended that the trans-
mission lines not change layers through vias, if possible. For
supply decoupling, the 1 nF decoupling capacitor should be
placed on the same layer as the ADN2890 as close as possible to
the VCC pin. The 0.1 µF capacitor can be placed on the bottom
of the PCB directly underneath the 1 nF decoupling capacitor.
All high speed CML outputs are back-terminated on chip with
As with any high speed mixed-signal design, take care to keep
all high speed digital traces away from sensitive analog nodes.
Soldering Guidelines for Chip Scale Package
The lands on the 16 LFCSP are rectangular. The printed circuit
board pad for these should be 0.1 mm longer than the package
land length and 0.05 mm wider than the package land width.
The land should be centered on the pad. This ensures that the
solder joint size is maximized. The bottom of the chip scale
package has a central exposed pad. The pad on the printed
circuit board should be at least as large as this exposed pad. The
user must connect the exposed pad to VEE using filled vias so
that solder does not leak through the vias during reflow. This
ensures a solid connection from the exposed pad to VEE.
R1, C9, C10 ON BOTTOM
TO ROSA
DOUBLE-VIAS TO REDUCE
INDUCTANCE TO SUPPLY
AND GND
PLACE C7 ON
BOTTOM OF BOARD
UNDERNEATH C8
PLACE C5 ON
BOTTOM OF BOARD
UNDERNEATH C6
1
EXPOSED PAD
C6
C8
C1
C3
PIN
NIN
OUTP
VIAS TO
GND
∼
4mm
OUTN
C2
C4
DOUBLE-VIA TO GND
TO REDUCE INDUCTANCE
VIA TO C12, R2
ON BOTTOM
C11
VIA TO BOTTOM
Figure 9. Recommended ADN2890 PCB Layout
Rev. B | Page 10 of 12
Data Sheet
ADN2890
OUTLINE DIMENSIONS
DETAIL A
(JEDEC 95)
3.10
3.00 SQ
2.90
0.30
0.23
0.18
PIN 1
INDICATOR
PIN 1
13
16
TIONS
INDICATOR AREA OP
(SEE DETAIL A)
0.50
BSC
12
1
1.75
1.60 SQ
1.45
EXPOSED
PAD
9
4
8
5
0.50
0.40
0.30
0.20 MIN
TOP VIEW
TOP VIEW
BOTTOM VIEW
0.80
0.75
0.70
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.05 MAX
0.02 NOM
COPLANARITY
0.08
SECTION OF THIS DATA SHEET.
SEATING
PLANE
0.20 REF
COMPLIANT TOJEDEC STANDARDS MO-220-WEED-6.
Figure 10. 16-Lead Lead Frame Chip Scale Package [LFCSP]
3 mm × 3 mm Body and 0.75 mm Package Height
(CP-16-22)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
ADN2890ACPZ-RL
ADN2890ACPZ-RL7
ADN2890-EVALZ
Temperature Range
–40°C to +85°C
–40°C to +85°C
Package Description
Package Option
CP-16-22
CP-16-22
16-Lead Lead Frame Chip Scale Package [LFCSP]
16-Lead Lead Frame Chip Scale Package [LFCSP]
Evaluation Board
1 Z = RoHS Compliant Part.
Rev. B | Page 11 of 12
ADN2890
NOTES
Data Sheet
©2004–2017 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04509-0-4/17(B)
Rev. B | Page 12 of 12
相关型号：
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IC SPECIALTY TELECOM CIRCUIT, QCC16, 3 X 3 MM, MO-220-VEED-2, LFCSP-16, Telecom IC:Other
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ADN2891ACP-RL7
IC SPECIALTY TELECOM CIRCUIT, QCC16, 3 X 3 MM, MO-220-VEED-2, LFCSP-16, Telecom IC:Other
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