ADN2928 [ADI]
XFP Single Chip Transceiver IC; XFP单芯片收发器IC
| 型号： | ADN2928 |
| 厂家： | 
ADI |
| 描述： | XFP Single Chip Transceiver IC |
| 文件： | 总12页 (文件大小：387K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
XFP Single Chip Transceiver IC
Preliminary Technical Data
ADN2928
FEATURES
PRODUCT OVERVIEW
Fully integrated limiting amplifier and signal conditioner
transceiver IC
The ADN2928 provides the transmit and receive functions of
quantization, loss of signal detect, and clock and data recovery
at rates from 9.953 Gbps to 11.1 Gbps. The part is designed with
the flexibility to allow it to be used in either Telecoms or
Datacoms XFP module applications. The key advantages of this
circuit’s delay and phase-locked loop architecture are that it
provides a low jitter transfer bandwidth of 1 MHz, while also
exceeding the jitter tolerance requirements of XFP, SONET,
Gigabit Ethernet and Fibre Channel. The architecture also
provides fundamentally 0 dB of Jitter peaking.
Meets XFP Telecoms and Datacoms module requirements
Supports OC-192, OC-192-FEC, 10GE, 10GFC, 10GE G.709
Line and system loop-back modes
Integrated Rx limiting amplifier with 10 mV sensitivity
Tx path equalizer for up to 12 inches of FR4
Rx loss of signal (LOS) detector
CML serial data interface
Supply power: 760 mW
3.3 V and 1.8 V power supplies
XFI signalling
Flip-chip, 49-pin BGA, 6 mm × 6 mm package
Temperature range 0°C to 85°C
Power down mode
APPLICATIONS
XFP MSA module receive/transmit signal conditioner
SONET OC-192, (+FEC) transponders
10 gigabit Ethernet optical transceivers
10 gigabit small form factor modules
Test equipment
Serial backplane applications
XFP MODULE
12” FR4
XFP MODULE
12” FR4
TXDATA
OTX
ORX
RXDATA
SERDES/
ASIC
SERDES/
ASIC
ADN2928
ADN2928
12” FR4
12” FR4
RXDATA
ORX
OTX
TXDATA
Figure 1. Typical XFP Application
Rev. PrB
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
Inc. All rights reserved.
© 2005 Analog Devices,
ADN2928
Preliminary Technical Data
TABLE OF CONTENTS
Functional Block Diagram .............................................................. 3
Receive Path Specifications ............................................................. 4
Transmit Path Specifications........................................................... 5
Common Specifications................................................................... 6
Absolute Maximum Ratings............................................................ 7
Pin Configuration and Function Descriptions............................. 8
General Description......................................................................... 9
I2C Interface .................................................................................. 9
Receive Path .................................................................................. 9
Transmit Path................................................................................ 9
System Functions.......................................................................... 9
Applications Information .............................................................. 10
PCB Design Guidelines ............................................................. 10
Outline Dimensions ....................................................................... 11
Ordering Guide........................................................................... 11
REVISION HISTORY
3/05—Revision PrB: Preliminary Version
Rev. PrB | Page 2 of 12
Preliminary Technical Data
ADN2928
FUNCTIONAL BLOCK DIAGRAM
CFT
TxLOL
Equalizer
FLL
TxINP
TxOUTP
TxOUTN
TxIN N
COST
T xCDR
REFCK P
REFCK N
RxLOS
4
4
RxTHR
Limiting Amp
RxOUTP
RxOUTN
RxCDR
RxINP
RxINN
FLL
CDR_NR
TxLOL
RxLOL
COSR
VDDT _1.8
VDDR_1.8
VDD_3.3
1.0V
regulator
SCK
I2C
REGISTERS
SD A
PD N
GN D
CVDD_1.0
CFR
Figure 2. ADN2928 Functional Block Diagram
Rev. PrB | Page 3 of 12
ADN2928
Preliminary Technical Data
RECEIVE PATH SPECIFICATIONS
Table 1.
PARAMETER
Conditions
Min
Typ
1
Max
Unit
QUANTIZER DC CHARACTERISTICS
Peak-to-Peak Differential Input
Input Sensitivity, VSENSE
Input Offset Voltage
Input Current
ac coupled, PIN-NIN
PIN-NIN, BER < 10−12
1.8
V
10
mV
mV
µA
µV
Input RMS Noise
365
QUANTIZER AC CHARACTERISTICS
−3 dB Bandwidth
Input Data Rate
Differential
@ 10 GHz
10
GHz
Gbps
dB
9.953
11.1
Small Signal Gain
45
S11
dB
−12
0.3
100
TBD
60
Random Jitter
Input Resistance
Input Capacitance
Power Supply Rejection
LEVEL DETECT
ps rms
Ω
pF
100 mV p-p @ 100 MHz on VDD
dB
LOS Signal Level
Hysteresis
5
3
mV
dB
PHASE-LOCKED LOOP CHARACTERISTICS
For All Input Data Rates
Jitter Transfer BW - Telecoms
Jitter Transfer BW - Datacoms
Jitter Tolerance - Telecoms
Sinusoidal Jitter Tolerance
Jitter Tolerance - Datacoms
Sinusoidal Jitter Tolerance
Jitter Generation rms
Jitter Peaking
1.2
1.2
3
3
MHz
MHz
Meets SONET mask.
Meets 802.3ae mask
0.7
ps rms
Measured 50 kHz – 80 MHz
< 120 kHz
> 120 kHz
0
0
dB
dB
CML OUTPUTS - RxOUTP/N
Single-Ended Output Swing
Differential Output Swing
Output High Voltage
Output Low Voltage
Rise Time
Vse
Vdiff
Voh
Vol
20% – 80%
80% – 20%
200
400
TBD
425
850
mV
mV
TBD
24
24
ps
ps
Fall Time
Rev. PrB | Page 4 of 12
Preliminary Technical Data
ADN2928
TRANSMIT PATH SPECIFICATIONS
Table 2.
PARAMETER
Conditions
Min
Typ
1
Max
Unit
QUANTIZER DC CHARACTERISTICS
Peak-to-Peak Differential Input
Input Sensitivity, VSENSE
Input Offset Voltage
Input Current
ac coupled, PIN – NIN
PIN – NIN, BER < 10−12
1.8
V
40
mV
mV
µA
µV
Input RMS Noise
QUANTIZER AC CHARACTERISTICS
−3dB Bandwidth
Input Data Rate
Differential
@ 10 GHz
10
GHz
Gbps
dB
9.953
11.1
Small Signal Gain
32
S11
dB
−12
0.3
100
TBD
60
Random Jitter
Input Resistance
Input Capacitance
Power-Supply Rejection
PHASE-LOCKED LOOP CHARACTERISTICS
For All Input Data Rates
Jitter Transfer BW
ps rms
Ω
pF
100 mV p-p @ 100 MHz on VDD
dB
1.2
3
MHz
Jitter Tolerance - Telecoms
Sinusoidal Jitter Tolerance
Jitter Tolerance - Datacoms
Sinusoidal Jitter Tolerance
Jitter Generation rms
Jitter Peaking
Meets SONET mask.
Meets 802.3ae mask
0.7
pS rms
Measured 50 kHz – 80 MHz
< 120 kHz
> 120 kHz
0
0
dB
dB
CML OUTPUTS - TxOUTP/N
Single-Ended Output Swing
Differential Output Swing
Output High Voltage
Output Low Voltage
Rise Time
Vse
Vdiff
Voh
Vol
20% – 80%
80% – 20%
300
700
TBD
500
1000
mV
mV
TBD
24
24
ps
ps
Fall Time
Rev. PrB | Page 5 of 12
ADN2928
Preliminary Technical Data
COMMON SPECIFICATIONS
Table 3.
PARAMETER
Conditions
Min
3
Typ
3.3
Max
3.6
Unit
V
POWER-SUPPLY VOLTAGE, VDD_3.3
POWER-SUPPLY VOLTAGE, VDDx_1.8
POWER SUPPLY CURRENT, VDD_3.3
POWER SUPPLY CURRENT, VDDx_1.8
POWER
1.6
1.8
2.0
V
mA
mA
mW
760
RECEIVE REFERENCE CLOCK INPUTS
Clock Frequency
Clock Frequency
CTRL[0]=0
CTRL[0]=1
155
622
MHz
MHz
V
Input Voltage Range
Rev. PrB | Page 6 of 12
Preliminary Technical Data
ADN2928
ABSOLUTE MAXIMUM RATINGS
Table 4.
Parameter
Supply Voltage
Input Voltage (Pin x or Pin x to Vcc)
Maximum Junction Temperature
Storage Temperature Range
Lead Temperature (Soldering 10 sec)
ESD Rating (Human Body Model)
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rating
5 V
TBD
165°C
−65°C to +150°C
300°C
TBD V
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. PrB | Page 7 of 12
ADN2928
Preliminary Technical Data
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
4 5 6 7
2 3
A
B
C
D
E
F
G
Figure 3. Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
Mnemonic
Type1
Description
A1, A4, B5, B6, D3 to D6, E3,
F2, F6, G4, G7
GND
P
Ground
A7, C6, D7, E5, E6, F7
B1, C2, C3, D1, E4, G1
VDDT_1.8
VDDR_1.8
VDD_3.3
RxINN
RxINP
TxOUTP
TxOUTN
RxTHR
COSR
CVDD_1.0
NC
REFCLKN
REFCLKP
CFT
P
P
P
AI
AI
AO
AO
AI
AO
P
1.8 V transmitter power supply
1.8 V receiver power supply
3.3 V power supply
Negative Differential Rx Data Input
Positive Differential Rx Data Input
Positive Differential Tx Data Output; CML
Negative Differential Tx Data Output; CML
Receiver LOS Threshold Setting Resistor
Receiver Offset Compensation Loop Capacitor
100 nF Decoupling Capacitor for Internal 1 V digital supply
No Connect
Negative Differential Reference Clock Input
Positive Differential Reference Clock Input
Transmitter FLL Loop Filter Capacitor
Receiver Loss of Signal Alarm Output. Active High
Receiver FLL Loop Filter Capacitor
Chip Power Down Input
C1, E7
A2
A3
A5
A6
B2
B3
B4
B7
C4
C5
C7
D2
E1
AI
AI
AO
DO
AO
DI
RxLOS
CFR
PDN
E2
F1
F3
F4
CDR_NR
SDA
SCK
DO
DI/O
DI
CDR Not Ready Alarm. Active High.
I2C Serial Data Input.
I2C Serial Clock Input
F5
COST
AO
AO
AO
AI
Transmitter Offset Compensation Loop Capacitor
Negative Differential Rx Data Output; CML
Positive Differential Rx Data Output; CML
Negative Differential Tx Data Input
Postive Differential Tx Data Input
G2
G3
G5
G6
RxOUTN
RxOUTP
TxINN
TxINP
AI
1Type: P = power, AI = analog input, AO = analog output, DI = digital input, DO = digital output.
Rev. PrB | Page 8 of 12
Preliminary Technical Data
GENERAL DESCRIPTION
ADN2928
The ADN2928 provides the transmit and receive functions of
quantization, loss of signal detect, and clock and data recovery
at rates from 9.953 Gbps to 11.1 Gbps. The part is designed
with the flexibility to allow it to be used in either Telecoms or
Datacoms XFP module applications.
TRANSMIT PATH
Equalizer
An equalizer on the data inputs TxINP/N, of the ADN2928
has differential inputs which are internally terminated with
50 ohms to an on chip reference voltage. The equalizer compen-
sates for the ISI induced signal distortion resulting from up to
12 inches of FR4, plus one connector. This enables the CDR to
retime the data from signals transmitted over standard XFI
interfaces. The equalizer characteristics have been optimized
such that no user programming is required to achieve low
retiming error rates for all data rates and XFI compliant
channels. However for other applications the equalizer boost
characteristics can be programmed through the I2C interface.
I2C INTERFACE
The I2C interface is used to control the following functions:
data invert and squelch, lineside loop-back, XFI system loop-
back, REFCLK divide ratio, status readback, optional equalizer
control, and software reset.
RECEIVE PATH
Limiting Amplifier
A limiting amplifier on the data inputs RxINP/N, of the device
has differential inputs which are internally terminate with
50 Ω to an on-chip reference voltage. The limiting amplifier
quantizes the data, with a sensitivity of better than 10 mV.
Clock and Data Recovery PLL
The transmit path clock and data recovery (CDR) block
recovers the clock from the serial data input and provides
proper timing for the data outputs. This block contains a
synthesizer frequency tracking loop, and a data phase tracking
loop. A synthesizer tracking loop locks the divided down clock
derived from the VCO frequency to a local reference clock
running at 1/ 64 or 1/16 the input data rate. Once it is
determined that the VCO frequency is locked to the reference
clock and valid serial data is present at the input, then the
synthesizer loop is switched off, and the data phase tracking
loop is turned on. The data phase tracking loop is designed in a
manner such that, once locked, the sampling edge of the VCO
clock is automatically aligned with the center of the data input.
A key feature of the Delay and Phase Locked Loop (DPLL)
architecture used is that unlike an ordinary PLL, it provides for
0 dB jitter peaking.
Loss of Signal Detector
The receiver front end signal-level detector indicates when the
input level has dropped below a user-adjustable level, by assert-
ing Pin LOS to logic high. The trip point can be varied by an
external resistor. The signal-level detector circuitry has a com-
parator with a minimum hysteresis of 3 dB to prevent chatter.
Clock and Data Recovery PLL
The receive path clock and data recovery (CDR) block recovers
the clock from the serial data input and provides proper timing
for the data outputs. This block contains a synthesizer-
frequency tracking loop, and a data-phase tracking loop. A
synthesizer tracking loop locks the divided-down clock derived
from the VCO frequency to a local reference clock running at
1/64 or 1/16 the input data rate. Once it is determined that the
VCO frequency is locked to the reference clock and that valid
serial data is present at the input, then the synthesizer loop is
switched off, and the data-phase tracking loop is turned on.
The data-phase tracking loop is designed in a manner such
that, once locked, the sampling edge of the VCO clock is auto-
matically aligned with the center of the data input. A key feature
of the delay and phase-locked loop (DPLL) architecture is that,
unlike an ordinary PLL, it provides for 0 dB jitter peaking.
CML Outputs
The data signal that is retimed by the CDR clock is driven off-
chip by 50 Ω terminated current-mode logic line drivers. The
data polarity can be optionally inverted through the I2C inter-
face, and can be squelched. Output amplitudes can be adjusted.
Lock Detector
The lock detector monitors the frequency difference between
the VCO and the reference clock and asserts a lock signal
(TxLOCK) when the VCO is within 500 ppm of the center
frequency. This enables the phase loop which maintains phase
lock, unless the frequency error exceeds 1000 ppm.
CML Outputs
The data signal that is retimed by the CDR clock is driven off-
chip by 50 Ω terminated current mode logic line drivers. The
data polarity can be optionally inverted through the I2C inter-
face, and can be squelched. Output amplitudes can be adjusted.
SYSTEM FUNCTIONS
XFI System Loopback
In this mode data received on the TxINP/N pins is retimed and
output on the RxOUTP,N pins. The TxINP/N data is not
present on the TxOUTP/N pins.
Lock Detector
The lock detector monitors the frequency difference between
the VCO and the reference clock and asserts a lock signal
(RxLOCK) when the VCO is within 500 ppm of the center
frequency. This enables the phase loop which maintains phase
lock, unless the frequency error exceeds 1000 ppm.
Lineside Loopback
In this mode data received on the RxINP/N pins is retimed and
output on the TxOUTP/N pins. The received data is not present
on the RxOUTP/N pins.
Rev. PrB | Page 9 of 12
ADN2928
Preliminary Technical Data
APPLICATIONS INFORMATION
decouple the IC power supplies between VDD and VEE. These
caps should be placed as close as possible to the ADN2928
VDD pins.
PCB DESIGN GUIDELINES
Proper RF PCB design techniques must be used for optimal
performance. A typical ADN2928 applications circuit is shown
in Figure 4.
If connections to the supply and ground are made through vias,
the use of multiple vias in parallel helps to reduce series
inductance.
Power Supply Connections and Ground Planes
Using one low impedance ground plane is recommended.
Solder the GND pins directly to the ground plane to reduce
series inductance. If the ground plane is an internal plane and
connections to the ground plane are made through vias, mul-
tiple vias can be used in parallel to reduce the series inductance.
Transmission Lines
Use of 50 Ω transmission lines is required for all high frequency
input and output signals to minimize reflections: RxINN/P,
RxOUTN/P, TxINN/P, TxOUTN/P, REFCLKN/P. It is also
necessary for the differential pairs to be matched in length to
avoid skew between the differential traces. As with any high
speed mixed-signal design, take care to keep all high speed
digital traces away from sensitive analog nodes.
Use of a 22 µF electrolytic capacitor between each supply
and GND is recommended at the location where the supply
enters the PCB. Use 0.1 µF and 1 nF ceramic chip capacitors to
VDDT _1.8
1.8V
1n and 100n
decoupling caps
22uF
placed right at DUT
VDDR_1.8
VDD_3.3
22u
22uF
100n
1n
1n
100n
100n
CVDD_1.0
100n
1.0V
regulator
VD DT_1.8
68n
VDDT_1.8
ADN2525 for L D
ADN2530 for VCSEL
ADN2849 for EAM
C7
G6
50 50
CFT
100n
100n
100n
100n
A5
A6
LD D
CM L
EQ
T xCDR
G5
F5
COST
1000p
100n
C5
C4
REFCLK
100n
XFI
PD _VCC
ADN2821
TIA
100n
100n
100n
100n
A3
A2
G3
G2
PA
CM L
RxCDR
COSR
B3
B2
CFR
50 50
VDDR_1.8
68n
1000p
RxT HR
VDDR_1.8
VDD_3.3
4.7k
LOS
E1
(this pull-up
on host PCB)
D2
RxLOS
RT H
VD D_3.3
1.2k
1.2k
SCK
SD A
F4
2
I C
Registers
F3
VDD_3.3
4.7k
ADuC7020
F1
E2
CDR_NR
PDN
Figure 4. Typical ADN2928 Applications Circuit
Rev. PrB | Page 10 of 12
Preliminary Technical Data
OUTLINE DIMENSIONS
ADN2928
A1 CORNER
INDEX AREA
6.00
BSC SQ
7
6
5
4
3
2
1
A
B
C
D
E
F
1.50
SQ
BALL A1
PAD CORNER
4.80
BSC SQ
TOP VIEW
G
BOTTOM
VIEW
0.80
BSC
DETAIL A
1.70
1.56
1.35
1.31
1.21
1.10
DETAILA
0.35
0.25
COPLANARITY
0.12 MAX
*
0.50
0.45
0.40
SEATING
PLANE
BALL DIAMETER
*
COMPLIANT TO JEDEC STANDARDS MO-205
WITH THE EXCEPTION OF BALL DIAMETER.
Figure 5. 49-Lead Chip Scale Package Ball Grid Array [CSP_BGA]
(BC-49-2)
Dimensions shown in millimeters
ORDERING GUIDE
Model
Temperature Range
Package Description
Package Option
ADN2928
0° to 85°C
Rev. PrB | Page 11 of 12
ADN2928
NOTES
Preliminary Technical Data
Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent
Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
©
2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
PR05264–0–3/05(PrB)
Rev. PrB | Page 12 of 12
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