ADN4622 [ADI]

5.7 kV rms/1.5 kV rms、四通道 LVDS 2.5 千兆位隔离器（2 个反转通道）;


型号：	ADN4622
厂家：	ADI
描述：	5.7 kV rms/1.5 kV rms、四通道 LVDS 2.5 千兆位隔离器（2 个反转通道）
文件：	总20页 (文件大小：3458K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

Data Sheet

ADN4624

5.7 kV RMS, Quad-Channel LVDS 2.5 Gigabit Isolator

FEATURES

FUNCTIONAL BLOCK DIAGRAM

► 5.7 kV rms LVDS isolators

► Complies with TIA/EIA-644-A LVDS signal levels

► Quad-channel configuration

► Any data rate up to 2.5 Gbps switching with low jitter

► 10 Gbps total bandwidth across four channels

► 2.15 ns typical propagation delay

► Typical jitter: 0.82 ps rms random, 40 ps total peak

► Lower power 1.8 V supplies

Figure 1.

► ±8 kV IEC 61000-4-2 ESD protection across isolation barrier

► High common-mode transient immunity: 100 kV/μs typical

► Safety and regulatory approvals (28-lead SOIC_W_FP package)

► UL (pending): 5700 V rms for 1 minute per UL 1577

► CSA Component Acceptance Notice 5A (pending)

► VDE certificate of conformity (pending)

► DIN V VDE V 0884-11 (VDE V 0884-11):2017-01

► V_IORM= 849 V_PEAK(working voltage)

► Enable or disable refresh (low speed output correctness check)

► Operating temperature range: −40°C to +125°C

GENERAL DESCRIPTION

The ADN4624¹is a quad-channel, signal isolated, low voltage

differential signaling (LVDS) buffer that operates at up to 2.5 Gbps

with very low jitter. The device integrates Analog Devices, Inc.,

iCoupler technology, enhanced for high speed operation to pro-

vide drop-in galvanic isolation of LVDS signal chains. AC coupling

and/or level shifting to the LVDS receivers and from the LVDS

drivers allows isolation of other high speed signals such as current

mode logic (CML).

► 28-lead, wide body, fine pitch SOIC-FP package with 8.3 mm

creepage and clearance

The ADN4624 includes a refresh mechanism to monitor the input

and output states and ensure they remain the same in the absence

of data transitions (for example, at power-on).

APPLICATIONS

For lower power consumption and high speed operation with low

jitter, the LVDS and isolator circuits rely on 1.8 V supplies. The

ADN4624 is fully specified over a wide industrial temperature range

and is available in a 28-lead, wide body, fine pitch SOIC-FP pack-

age with 8.3 mm creepage and clearance (for 5.7 kV rms or 8

kV_PEAKsurge and impulse voltages and reinforced insulation at AC

mains voltages).

► Isolated video and imaging data

► Analog front-end isolation

► Data plane isolation

► Isolated high speed clock and data links

► Multi-gigabit serialization/deserialization (SERDES)

► Board-to-board optical replacement (for example, short reach

fiber)

Protected by U.S. Patents 5,952,849; 6,873,065; 6,903,578; and 7,075,329. Other patents are pending.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable "as is". However, no responsibility is assumed by Analog

Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to

change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and

registered trademarks are the property of their respective owners.

DOCUMENT FEEDBACK

TECHNICAL SUPPORT

Data Sheet

ADN4624

TABLE OF CONTENTS

Features................................................................ 1

Applications........................................................... 1

Functional Block Diagram......................................1

General Description...............................................1

Specifications........................................................ 3

Receiver Input Threshold Test Voltages.............4

Timing Specifications......................................... 4

Insulation and Safety Related Specifications..... 5

Package Characteristics.....................................5

Regulatory Information.......................................6

DIN V VDE V 0884-11 (VDE V 0884-11)

Insulation Characteristics (Pending).................6

Recommended Operating Conditions................ 7

Absolute Maximum Ratings...................................8

Thermal Resistance........................................... 8

Electrostatic Discharge (ESD) Ratings...............8

ESD Caution.......................................................8

Pin Configuration and Function Descriptions........ 9

Typical Performance Characteristics...................10

Test Circuits and Switching Characteristics.........14

Theory of Operation.............................................15

Isolation and Refresh....................................... 15

Truth Table....................................................... 15

Applications Information...................................... 16

PCB Layout...................................................... 16

Application Examples.......................................16

Magnetic Field Immunity.................................. 17

Insulation Lifetime............................................ 18

Outline Dimensions............................................. 20

Ordering Guide.................................................20

Evaluation Boards............................................ 20

REVISION HISTORY

4/2021—Revision 0: Initial Version

analog.com

Rev. 0 | 2 of 20

Data Sheet

ADN4624

SPECIFICATIONS

For all minimum and maximum specifications, V_DD1= V_DD2= 1.7 V to 1.9 V and T_A= −40°C to +125°C, unless otherwise noted. For all typical

specifications, V_DD1= V_DD2= 1.8 V and T_A= 25°C. For all specifications, REFRESH₁= GND₁and REFRESH₂= GND₂, unless otherwise

noted.

Table 1.

Parameter

Symbol

Min

Typ

Max

Unit

Test Conditions/Comments

INPUTS (RECEIVERS)

Input Threshold

See Figure 28 and Table 2

High

V_TH

V_TL

100

Low

−100

100

Differential Input Voltage

Input Common-Mode Voltage

Input Current, High and Low

Differential Input Capacitance¹

LOGIC INPUTS

|V_ID

See Figure 28 and Table 2

V_IC

0.5|V_ID

2.4 − 0.5|V_ID

See Figure 28 and Table 2

I_IH, I_IL

C_INx±

−5

µA

D_INx±= 2.4 V or 0 V, other input = 1.2 V, V_DDx= 1.8 V or 0 V

D_INx±= 0.4 sin(30 × 10⁶πt) V + 0.5 V, other input = 1.2 V²

V_DDx= V_DD1for REFRESH₁, V_DDx= V_DD2for REFRESH₂

1.7

Input High Voltage

Input Low Voltage

Input Current High

V_INH

V_INL

0.65 V_DDx

0.35 V_DDx

|I_INH

μA

REFRESH_x= V_DDx

REFRESH_x= 1.9 V, V_DDx= 0 V

REFRESH_x= 0 V

Input Current Low

OUTPUTS (DRIVERS)

Differential Output Voltage

V_ODMagnitude Change

Offset Voltage

|I_INL|

|V_OD

250

310

450

See Figure 26 and Figure 27, load resistance (R_L) = 100 Ω

See Figure 26 and Figure 27, R_L= 100 Ω

See Figure 26, R_L= 100 Ω

D_OUTx±= 0 V

Δ|V_OD

V_OS

1.125

1.17

1.375

V_OSMagnitude Change

V_OS, Peak to Peak¹

ΔV_OS

V_OS(PP)

I_OS

150

−20

Output Short-Circuit Current

|V_OD| = 0 V

Differential Output Capacitance¹

C_OUTx±

D_OUTx±= 0.4 sin(30 × 10⁶πt) V + 0.5 V, other input = 1.2 V, V_DD1

or V_DD2= 0 V

POWER SUPPLY

Supply Current Side 1

Supply Current Side 2

I_DD1

I_DD2

140

175

Frequency (f) = 1.25 GHz

115

140

135

f = 1.25 GHz, R_L= 100 Ω

f = 1.25 GHz, R_L= 100 Ω, REFRESH₂= V_DD2

COMMON-MODE TRANSIENT

IMMUNITY³

|CM|

100

kV/µs

Common-mode voltage (V_CM) = 1000 V, transient magnitude =

800 V

These specifications are guaranteed by design and characterization.

t denotes time.

|CM| is the maximum common-mode voltage slew rate that can be sustained while maintaining any D_OUTx+or D_OUTx−pin in the same state as the corresponding D_INx+

or D_INx−pin (no change in output) or producing the expected transition on any D_OUTx+or D_OUTx−pin if the applied common-mode transient edge is coincident with a data

transition on the corresponding D_INx+or D_INx−pin. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges.

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Data Sheet

ADN4624

SPECIFICATIONS

RECEIVER INPUT THRESHOLD TEST VOLTAGES

Table 2. Test Voltages for Receiver Operation

Applied Voltages

D_INx+(V)

D_INx−(V)

Input Voltage, Differential, V_ID(V)

Input Voltage, Common-Mode, V_IC(V)

Driver Output, Differential V_OD(mV)

1.25

1.15

2.4

2.3

0.1

1.15

1.25

2.3

2.4

0.1

1.2

>250

−0.1

0.1

+1.2

2.35

+2.35

0.05

+0.05

1.2

<−250

>250

−0.1

0.1

<−250

>250

0.1

0.9

1.5

1.8

2.4

−0.1

0.6

<−250

>250

1.5

0.9

2.4

1.8

0.6

−0.6

0.6

+1.2

2.1

<−250

>250

−0.6

0.6

+2.1

0.3

<−250

>250

0.6

−0.6

+0.3

<−250

TIMING SPECIFICATIONS

For all minimum and maximum specifications, V_DD1= V_DD2= 1.7 V to 1.9 V and T_A= −40°C to +125°C, unless otherwise noted. For all typical

specifications, V_DD1= V_DD2= 1.8 V and T_A= 25°C. For all specifications, REFRESH₁= V_DD1and REFRESH₂= V_DD2, unless otherwise noted.

Table 3.

Parameter

Symbol

Min

Typ

Max¹

Unit

Test Conditions/Comments

PROPAGATION DELAY

SKEW

t_PLH, t_PHL

2.15

2.8

See Figure 29, from any D_INx+and D_INx−to D_OUTx+and D_OUTx−

See Figure 29, across all D_OUTx+and D_OUTx−

Duty Cycle²

Channel to Channel³

Part to Part⁴

t_SK(D)

t_SK(CH)

t_SK(PP)

150

300

JITTER⁵

See Figure 29, for any D_OUTx+and D_OUTx−

1.25 GHz clock input

2.5 Gbps, 2²³− 1 pseudorandom bit stream (PRBS)

1.25 GHz/2.5 Gbps, 2²³− 1 PRBS⁸

Random Jitter, RMS⁶(1σ)

Deterministic Jitter, Peak to Peak^{6, 7}

t_RJ(RMS)

t_DJ(PP)

t_TJ(PP)

0.82

1.44

ps rms

Total Jitter, Peak to Peak, at Bit Error Rate

(BER) 1 × 10⁻¹²

With Crosstalk

1.25 GHz/2.5 Gbps, 2²³− 1 PRBS all channels⁸

With Crosstalk and Refresh

1.25 GHz/2.5 Gbps, 2²³− 1 PRBS all channels, REFRESH₁= GND₁,

REFRESH₂= GND₂

Additive Phase Jitter

RISE AND FALL TIME

t_ADDJ

225

270

fs rms

100 Hz to 100 kHz, output frequency (f_OUT) = 10 MHz⁹

100 Hz to 100 kHz, f_OUT= 10 MHz, REFRESH₁= GND₁, REFRESH₂

GND₂

fs rms

12 kHz to 20 MHz, f_OUT= 1.25 GHz¹⁰

200

12 kHz to 20 MHz, f_OUT= 1.25 GHz, REFRESH₁= GND₁, REFRESH₂

GND₂

t_R, t_F

180

See Figure 29, 1.25 GHz clock input, any D_OUTx+and D_OUTx−, 20% to

80%, R_L= 100 Ω, load capacitance (C_L) = 5 pF

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Data Sheet

ADN4624

SPECIFICATIONS

Table 3.

Parameter

Symbol

Min

Typ

Max¹

Unit

Test Conditions/Comments

MAXIMUM DATA RATE

2.5

Gbps

These specifications are guaranteed by design and characterization.

Duty cycle or pulse skew is the magnitude of the maximum difference between t_PLHand t_PHLfor any Channel x of a device (where x = 1, 2, 3, or 4), that is, |t_PLHx– t_PHLx|.

Channel to channel or output skew is the difference between the largest and smallest values of t_PLHxwithin a device or the difference between the largest and smallest

values of t_PHLxwithin a device, whichever of the two is greater.

Part to part output skew is the difference between the largest and smallest values of t_PLHxacross multiple devices or the difference between the largest and smallest values

of t_PHLxacross multiple devices, whichever of the two is greater.

Jitter parameters are guaranteed by design and characterization. Values do not include stimulus jitter. V_ID= 400 mV p-p, V_IC= 1.2 V, and t_R/ t_F< 0.05 ns (20% to 80%).

This specification is measured over a population of ~3,000,000 edges.

Peak-to-peak jitter specifications include jitter due to pulse skew (t_SK(D)).

Using the following formula: t_TJ(PP)= 14 × t_RJ(RMS)+ t_DJ(PP)

With input phase jitter of 340 fs rms subtracted.

¹⁰With input phase jitter of 155 fs rms subtracted.

INSULATION AND SAFETY RELATED SPECIFICATIONS

For additional information, see www.analog.com/icouplersafety.

Table 4. RN-28-1 Wide Body with Finer Pitch [SOIC_W_FP] Package

Parameter

Symbol

Value

Unit

Test Conditions/Comments

Rated Dielectric Insulation Voltage

5.7

8.3

kV rms

1 minute duration

Minimum External Air Gap (Clearance)

L (I01)

L (I02)

L (PCB)

mm min

Measured from input terminals to output terminals, shortest distance

through air

Minimum External Tracking (Creepage)

8.3

8.1

mm min

Measured from input terminals to output terminals, shortest distance

path along body

Minimum Clearance in the Plane of the Printed Circuit Board

(PCB Clearance)

Measured from input terminals to output terminals, shortest distance

through air, line of sight, in the PCB mounting plane

Minimum Internal Gap (Internal Clearance)

Tracking Resistance (Comparative Tracking Index)

Material Group

25.5

>600

µm min

Insulation distance through insulation

Tested in accordance to IEC 60112

Material Group per IEC 60664-1

CTI

PACKAGE CHARACTERISTICS

Table 5. RN-28-1 Wide Body with Finer Pitch [SOIC_W_FP] Package

Parameter

Symbol

Min

Typ

Max

Unit

Test Conditions/Comments

Resistance (Input to Output)¹

Capacitance (Input to Output)¹

Input Capacitance²

R_I-O

C_I-O

C_I

10¹³

2.2

Ω

Voltage (input to output) (V_I-O) = 500 VDC

Frequency = 1 MHz

3.4

The device is considered a 2-terminal device: Pin 1 through Pin 14 are shorted together, and Pin 15 through Pin 28 are shorted together.

Input capacitance is from any input data pin to ground.

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Data Sheet

ADN4624

SPECIFICATIONS

REGULATORY INFORMATION

See Table 10 and the Insulation Lifetime section for details regarding the recommended maximum working voltages for specific cross-isolation

waveforms and insulation levels.

Table 6. RN-28-1 Wide Body with Finer Pitch [SOIC_W_FP] Package

Regulatory Agency

Standard Certification/Approval

File

UL (Pending)

To be recognized under UL 1577 Component Recognition Program¹

Single protection, 5700 V rms isolation voltage

E214100

CSA (Pending)²

To be approved under CSA Component Acceptance Notice 5A

CSA 62368-1-19, EN 62368-1:2020 and IEC 62368-1:2018 third edition

Basic insulation at 830 V rms

205078

Reinforced insulation at 415 V rms

CSA 61010-1-12+A1 and IEC 61010-1 third edition

Basic insulation at 600 V rms

Reinforced insulation at 300 V rms

CSA 60601-1:14 and IEC60601-1 third edition+A1

2 means of patient protection (MOPP) for 261 V rms

To be certified according to DIN V VDE V 0884-11 (VDE V 0884-11):2017-01³

Reinforced insulation, V_IORM= 849 V_PEAK, V_IOSM= 8000 V_PEAK

To be certified according to GB4943.1-2011 per CQC11-471543-2015

VDE (Pending)

CQC (Pending)

2471900-4880-0001

Pending

Basic insulation at 820 V rms (1159 V_PEAK

)

Reinforced insulation at 410 V rms (578 V_PEAK

)

In accordance with UL 1577, each ADN4624 is proof tested by applying an insulation test voltage ≥ 6840 V rms for 1 sec.

Working voltages are quoted for Pollution Degree 2, Material Group III. ADN4624 case material has been evaluated by CSA as Material Group I.

In accordance with DIN V VDE V 0884-11, each ADN4624 is proof tested by applying an insulation test voltage ≥ 1592 V_PEAKfor 1 sec (partial discharge detection limit = 5

pC).

DIN V VDE V 0884-11 (VDE V 0884-11) INSULATION CHARACTERISTICS (PENDING)

This isolator is suitable for reinforced electrical isolation only within the safety limit data. Protective circuits ensure the maintenance of the safety

data.

Table 7.

Description

Test Conditions/Comments¹

Symbol

Characteristic

Unit

Installation Classification per DIN VDE 0110

For Rated Mains Voltage ≤ 150 V rms

For Rated Mains Voltage ≤ 300 V rms

For Rated Mains Voltage ≤ 600 V rms

Climatic Classification

I to IV

40/125/21

Pollution Degree per DIN VDE 0110, Table 1

Maximum Working Insulation Voltage

Input to Output Test Voltage, Method B1

V_IORM

849

V_PEAK

V_IORM× 1.875 = V_{PD (M)}, 100% production test, t_INI= t_M= 1

sec, partial discharge < 5 pC

V_{PD (m)}

1592

Input to Output Test Voltage, Method A

After Environmental Tests Subgroup 1

V_{PD (m)}

V_IORM× 1.5 = V_{PD (M)}, t_INI= 60 sec, t_M= 10 sec, partial

discharge < 5 pC

1274

1019

8000

V_PEAK

After Input or Safety Test Subgroup 2 and Subgroup 3 V_IORM× 1.2 = V_{PD (M)}, t_INI= 60 sec, t_M= 10 sec, partial

discharge < 5 pC

Highest Allowable Overvoltage

Surge Isolation Voltage

V_IOTM

Basic

V_PEAK= 16 kV, 1.2 µs rise time, 50 µs, 50% fall time

V_IOSM

16,000

V_PEAK

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Data Sheet

ADN4624

SPECIFICATIONS

Table 7.

Description

Test Conditions/Comments¹

Symbol

Characteristic

Unit

Reinforced

V_PEAK= 16 kV, 1.2 µs rise time, 50 µs, 50% fall time

V_IOSM

10000

V_PEAK

Safety Limiting Values

Maximum value allowed in the event of a failure (see Figure 2)

Maximum Junction Temperature

Total Power Dissipation at 25°C

Insulation Resistance at T_S

T_S

P_S

R_S

150

°C

Ω

2.74

>10⁹

V_IO= 500 V

For information about t_M, t_INI, and V_IO, see DIN V VDE V 0884-11.

Figure 2. Thermal Derating Curve, Dependence of Safety Limiting Values with Ambient Temperature per DIN V VDE V 0884-11

RECOMMENDED OPERATING CONDITIONS

Table 8.

Parameter

Symbol

Rating

Operating Temperature

Supply Voltages

T_A

−40°C to +125°C

1.7 V to 1.9 V

V_DD1, V_DD2

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Data Sheet

ADN4624

ABSOLUTE MAXIMUM RATINGS

Table 9.

THERMAL RESISTANCE

Parameter

Rating

Thermal performance is directly linked to PCB design and operation

environment. Close attention to PCB thermal design is required.

V_DD1to GND₁/V_DD2to GND₂

−0.3 V to +2 V

Input Voltage REFRESH₁to GND₁/REFRESH₂

to GND₂

θ_JAis the natural convection junction to ambient thermal resistance

measured in a one cubic foot sealed enclosure.

Input Voltage (D_INx+, D_INx−) to GND_xon the

Same Side

−0.3 V to +4 V

Table 11. Thermal Resistance

Output Voltage (D_OUTx+, D_OUTx−) to GND_xon the −0.3 V to +2 V

Same Side

Package Type¹

θ_JA

Unit

RN-28-1

43.45

°C/W

Short-Circuit Duration (D_OUTx+, D_OUTx−) to GND_xContinuous

on the Same Side

Test Condition 1: thermal impedance simulated with 4-layer standard JEDEC

PCB.

Operating Temperature Range

Storage Temperature Range

Junction Temperature (T_JMaximum)

Power Dissipation

−40°C to +125°C

−65°C to +150°C

150°C

ELECTROSTATIC DISCHARGE (ESD) RATINGS

(T_Jmaximum − T_A)/θ_JA

The following ESD information is provided for handling of ESD-sen-

sitive devices in an ESD protected area only.

Stresses at or above those listed under Absolute Maximum Ratings

may cause permanent damage to the product. This is a stress

rating only; functional operation of the product at these or any other

conditions above those indicated in the operational section of this

specification is not implied. Operation beyond the maximum operat-

ing conditions for extended periods may affect product reliability.

Human body model (HBM) per ANSI/ESDA/JEDEC JS-001.

International electrotechnical commission (IEC) electromagnetic

compatibility: Part 4-2 (IEC) per IEC 61000-4-2.

Table 10. Maximum Continuous Working Voltage¹, RN-28-1 Wide Body with

Finer Pitch [SOIC_W_FP] Package

ESD Ratings for ADN4624

Table 12. ADN4624, 28-Lead SOIC_W_FP

Parameter

Rating

Constraint

ESD Model

Withstand Threshold (V)

Class

HBM¹

IEC²

±4000

AC Voltage

Bipolar Waveform

Basic Insulation

±8000 (contact discharge)

Level 4

650 V rms

Basic insulation rating per

IEC60747-17. Accumulative failure

rate over lifetime (FROL) ≤ 1000 ppm

at 20 years.

All pins to respective GNDx, 1.5 kΩ, 100 pF.

LVDS pins to isolated GNDx across isolation barrier.

Reinforced Insulation 600 V rms

Unipolar Waveform

Reinforced insulation rating per

IEC60747-17. Accumulative FROL ≤

1 ppm at 26 years.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Charged devi-

ces and circuit boards can discharge without detection. Although

this product features patented or proprietary protection circuitry,

damage may occur on devices subjected to high energy ESD.

Therefore, proper ESD precautions should be taken to avoid

performance degradation or loss of functionality.

Basic Insulation

1782 V_PEAK

Rating limited by AC bipolar

waveform accumulative FROL ≤

1000 ppm at 20 years .

Reinforced Insulation 1330 V_PEAK

Rating limited by package creepage

per IEC 60664-1 in Pollution Degree

2 environment.

DC Voltage

Basic Insulation

1660 VDC

Rating limited by package creepage

per IEC 60664-1 in Pollution Degree

2 environment.

Reinforced Insulation 830 VDC

Rating limited by package creepage

per IEC 60664-1 in Pollution Degree

2 environment.

Maximum continuous working voltage refers to the continuous voltage magnitude

imposed across the isolation barrier in a Pollution Degree 2 environment. See the

Insulation Lifetime section for more details.

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Data Sheet

ADN4624

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

Figure 3. Pin Configuration

Table 13. Pin Function Descriptions

Pin No.

Mnemonic

Description

1, 14

V_DD1

1.8 V Power Supply for Side 1. Connect both pins externally and bypass to GND₁with 0.1 μF capacitors.

2, 3, 13

GND₁

D_IN1+

Ground, Side 1.

Noninverted Differential Input 1.

Inverted Differential Input 1.

Noninverted Differential Input 2.

Inverted Differential Input 2.

Noninverted Differential Input 3.

Inverted Differential Input 3.

Noninverted Differential Input 4.

Inverted Differential Input 4.

D_IN1−

D_IN2+

D_IN2−

D_IN3+

D_IN3−

D_IN4+

D_IN4−

REFRESH₁

Active Low Enable for Side 1 Refresh Function. Short to GND₁for normal operation with refresh enabled, or short to V_DD1for lower power,

lower jitter, and quieter operation with refresh disabled.

15, 28

16, 26, 27

V_DD2

1.8 V Power Supply for Side 2. Connect both pins externally and bypass to GND₂with 0.1 μF capacitors.

Ground, Side 2.

GND₂

REFRESH₂

Active Low Enable for Side 1 Refresh Function. Short to GND₂for normal operation with refresh enabled, or short to V_DD2for lower power,

lower jitter, and quieter operation with refresh disabled.

D_OUT4−

D_OUT4+

D_OUT3−

D_OUT3+

D_OUT2−

D_OUT2+

D_OUT1−

D_OUT1+

Inverted Differential Output 4.

Noninverted Differential Output 4.

Inverted Differential Output 3.

Noninverted Differential Output 3.

Inverted Differential Output 2.

Noninverted Differential Output 2.

Inverted Differential Output 1.

Noninverted Differential Output 1.

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Data Sheet

ADN4624

TYPICAL PERFORMANCE CHARACTERISTICS

V_DD1= V_DD2= 1.8 V, T_A= 25°C, REFRESH₁= GND₁, REFRESH₂= GND₂, R_L= 100 Ω, 1.25 GHz clock input with |V_ID| = 200 mV, V_IC= 1.2 V,

and t_Rand t_F< 0.05 ns, unless otherwise noted.

Figure 4. Supply Current vs. Input Clock Frequency

Figure 5. Supply Current vs. Input Data Rate, 2²³− 1 PRBS

Figure 6. Supply Current vs. Ambient Temperature

Figure 7. Differential Output Voltage, |V_OD| vs. Supply Voltage, V_DD1and V_DD2

Figure 8. Differential Output Voltage, |V_OD| vs. Ambient Temperature

Figure 9. Differential Output Voltage, |V_OD| vs. Input Clock Frequency

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Data Sheet

ADN4624

TYPICAL PERFORMANCE CHARACTERISTICS

Figure 10. Differential Output Voltage, |V_OD| vs. Output Load, R_L(DC Input)

Figure 13. Propagation Delay vs. Differential Input Voltage, |V_ID

Figure 14. Propagation Delay vs. Input Common-Mode Voltage, V_IC

Figure 15. Rise or Fall Time vs. Supply Voltage, V_DD1and V_DD2

Figure 11. Propagation Delay vs. Supply Voltage, V_DD1and V_DD2

Figure 12. Propagation Delay vs. Ambient Temperature

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Data Sheet

ADN4624

TYPICAL PERFORMANCE CHARACTERISTICS

Figure 16. Rise or Fall Time vs. Ambient Temperature

Figure 19. Deterministic Jitter, t_DJ(PP)vs. Data Rate, 2²³− 1 PRBS

Figure 17. Duty Cycle Skew, t_SK(D)vs. Supply Voltage, V_DD1and V_DD2

Figure 20. Deterministic Jitter, t_DJ(PP)vs. Supply Voltage, V_DD1and V_DD2

Figure 18. Duty Cycle Skew, t_SK(D)vs. Ambient Temperature

Figure 21. Deterministic Jitter, t_DJ(PP)vs. Ambient Temperature

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Data Sheet

ADN4624

TYPICAL PERFORMANCE CHARACTERISTICS

Figure 22. Deterministic Jitter, t_DJ(PP)vs. Differential Input Voltage, |V_ID

Figure 24. Time Interval Error (TIE) Histogram for D_OUT1±at 1.25 GHz

Figure 23. Deterministic Jitter, t_DJ(PP)vs. Input Common-Mode Voltage, V_IC

Figure 25. Eye Diagram for D_OUT1±at 1.25 GHz

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Data Sheet

ADN4624

TEST CIRCUITS AND SWITCHING CHARACTERISTICS

Figure 26. Driver Test Circuit

Figure 28. Voltage Definitions

Figure 27. Driver Test Circuit (Full Load Across Common-Mode Range)

Figure 29. Timing Test Circuit

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Data Sheet

ADN4624

THEORY OF OPERATION

The ADN4624 is a high speed differential signal isolator capable

of switching up to 2.5 Gbps with signal levels compliant to TIA/

EIA-644-A. The device couples differential signals applied to the

LVDS receiver inputs across the isolation barrier to the outputs on

the other side and re-transmits the bit stream or clock as LVDS.

This integration allows drop-in isolation of LVDS signal chains and

isolation of other signals such as CML.

ISOLATION AND REFRESH

In response to any change in the input state detected by the

integrated LVDS receiver, an encoder circuit sends narrow (~1 ns)

pulses to a decoder circuit using integrated transformer coils. The

decoder is bistable and is, therefore, either set or reset by the

pulses that indicate input transitions. The decoder state determines

the LVDS driver output state in normal operation, which reflects the

isolated LVDS buffer input state.

The LVDS receiver detects the differential voltage present across a

termination resistor on an LVDS input. An integrated digital isolator

transmits the input state across the isolation barrier, and an LVDS

driver outputs the same state as the input.

For normal operation of the ADN4624, the active low enable pins,

REFRESH₁and REFRESH₂, are shorted to GND₁and GND₂,

respectively, to enable a refresh function. When enabled, this

function means that in the absence of input transitions for more

than approximately 1 µs, a periodic set of refresh pulses, indicative

of the correct input state, ensures dc correctness at the output

(including the fail-safe output state, if applicable).

When there is a positive differential voltage of ≥100 mV across

a termination resistor between any D_INx+pin and a corresponding

D_INx−pin, the corresponding D_OUTx+pin sources current. This cur-

rent flows across the connected transmission line and termination

at the receiver at the far end of the bus, while D_OUTx−sinks the

return current. When there is a negative differential voltage of

≤−100 mV across any D_INx±pin, the corresponding D_OUTx+pin sinks

current with the D_OUTx−pin sourcing the current. Table 14 shows

these input and output combinations.

On power-up, the output state may initially be in the incorrect dc

state if there are no input transitions. The output state is corrected

within 1 µs by the refresh pulses.

If the decoder receives no internal pulses for more than approxi-

mately 1 µs, the device assumes that the input side is unpowered

or nonfunctional, in which case, the output is set to a positive

differential voltage (logic high).

The output drive current is between ±2.5 mA and ±4.5 mA (typically

±3.1 mA), developing between ±250 mV and ±450 mV across a

100 Ω termination resistor (R_T). The received voltage is centered

around 1.2 V. Because the differential voltage (V_ID) reverses polari-

ty, the peak-to-peak voltage swing across R_Tis twice the differential

voltage magnitude (|V_ID|).

For clocks, constant bit streams, or protocols with error correction,

the refresh functionality may not be required. If REFRESH₁and

REFRESH₂are shorted to VDD1 and VDD2, respectively, the

refresh functionality is disabled, allowing for lower power operation

with no internal clock-like signals (potentially reducing conducted or

radiated emissions). In this mode of operation, a new data transition

at the input may be required to correct the output state, either

after power-up or after a common-mode transient event beyond the

guaranteed common-mode transient immunity specification.

TRUTH TABLE

The LVDS standard, TIA/EIA-644-A, defines normal receiver opera-

tion under two conditions: an input differential voltage of ≥+100 mV

corresponding to one logic state, and a voltage of ≤−100 mV for

the other logic state. Between these thresholds, the standard LVDS

receiver operation is undefined (the LVDS receiver can detect either

state), as shown in Table 14.

Table 14. Input and Output Operation

Input (D_INx±

)

Output (D_OUTx±

)

Powered On

V_ID(mV)

Logic

Powered On

V_OD(mV)

Logic

Yes

≥100

High

Yes

≥250

High

≤−100

Low

≤−250

Low

−100 < V_ID< +100

Don’t care

Indeterminate

Don’t care

Indeterminate

≥250

Indeterminate

High

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Data Sheet

ADN4624

APPLICATIONS INFORMATION

data can be isolated using the ADN4624 between components,

between boards, or at a cable interface.

PCB LAYOUT

The ADN4624 can operate with high speed LVDS signals up to

1.25 GHz clock, or 2.5 Gbps nonreturn to zero (NRZ) data. When

operating with such high frequencies, apply best practices for the

LVDS trace layout and termination. Place a 100 Ω termination

resistor as close as possible to the receiver, across the D_INx+and

D_INx−pins.

The ADN4624 provides the galvanic isolation required for robust

external ports, and the low jitter and high drive strength of the

device allow communication along short cable runs of a few

meters. High common-mode immunity ensures communication in-

tegrity even in harsh, noisy environments, and isolation can pro-

tect against electromagnetic compatibility (EMC) transients up to

±8 kV_PEAK, such as ESD, electrical fast transient (EFT), and surge.

Controlled impedance traces (100 Ω differential) are needed on

LVDS signal lines for full signal integrity, reduced system jitter, and

for minimizing electromagnetic interference (EMI) from the PCB.

Trace widths, lateral distance within each pair, and distance to the

ground plane underneath all must be chosen appropriately. Via

fencing to the PCB ground between pairs is also a best practice to

minimize crosstalk between adjacent pairs.

Standard LVDS inputs and outputs allow simple integration into

high speed signal chains using field-programmable gate arrays

(FPGAs), redrivers, or coupling networks to interface to CML and

other physical layers. The ADN4624 can isolate a range of video

and imaging protocols, including protocols that use CML rather than

LVDS for the physical layer.

The ADN4624 pass EN 55032 Class B emissions limits without

extra considerations required for the isolator when operating with

up to 2 Gbps PRBS data. When isolating at higher data rates or for

high speed clocks, specific PCB layout measures may be required

to reduce dipole antenna effects from the isolation gap and provide

sufficient margin below Class B emissions limits.

One example is High-Definition Multimedia Interface (HDMI), where

ac coupling and biasing and termination resistor networks are used,

as shown in Figure 30 to convert between CML (used by the

transition minimized differential signaling (TMDS) data and clock

lanes) and the LVDS levels required by the ADN4624. Additional

Analog Devices isolator components, such as the ADuM2250 and

ADuM2251 I²C isolators, can be used to isolate control signals and

power (ADuM6421A and ADuM6028 isoPower integrated, isolated

dc-to-dc converter). This circuit supports resolutions up to 1080p.

The best practice for high speed PCB design avoids emissions from

traces with high speed LVDS signals. Special care is recommended

for off board connections, where switching transients from high

speed LVDS signals (and clocks in particular) may conduct onto ca-

bling, resulting in radiated emissions. Use common-mode chokes,

ferrites, or other filters as appropriate at LVDS connectors and

power supplies, as well as cable shield or PCB ground connections

to earth or chassis.

Other coupling networks, processing nodes, and translation circuits

can use the ADN4624 as part of an overall signal chain to iso-

late MIPI CSI-2, DisplayPort, and LVDS-based protocols such as

FPD-Link. Use of an FPGA or an application-specific integrated

circuit (ASIC) serializer/deserializer (SERDES) expands bandwidth

through multiple ADN4624 devices to support 1080p or 4K video

resolutions, providing an alternative to short reach fiber links.

The ADN4624 requires appropriate decoupling of the V_DDxpins

with 100 nF capacitors. Power supplies must also have appropriate

filtering to avoid possible radiated emissions due to high frequency

switching noise.

APPLICATION EXAMPLES

High speed LVDS interfaces for the analog front-end (AFE), pro-

cessor to processor serial communication, or video and imaging

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Rev. 0 | 16 of 20

Data Sheet

ADN4624

APPLICATIONS INFORMATION

Figure 30. Example Isolated Video Interface (HDMI) Using the ADN4624

The voltage (V) induced across the receiving coil is given by

MAGNETIC FIELD IMMUNITY

V = (−dβ/dt)∑πr_n²; n = 1, 2, …, N

The limitation on the magnetic field immunity of the device is set

by the condition in which the induced voltage in the transformer

receiving coil is sufficiently large, either to falsely set or reset

the decoder. The following analysis defines such conditions. The

ADN4624 is examined in a 1.7 V operating condition because

this operating condition represents the most susceptible mode of

operation for these products.

where:

dβ is the change in magnetic flux density.

dt is the change in time.

r_nis the radius of the n^thturn in the receiving coil.

The pulses at the transformer output have an amplitude greater

than 0.35 V. The decoder has a sensing threshold of about 0.11 V,

therefore establishing a 0.24 V margin in which induced voltages

are tolerated.

N is the number of turns in the receiving coil.

Given the geometry of the receiving coil in the ADN4624 and an

imposed requirement that the induced voltage be, at most, 50% of

the 0.11 V threshold at the decoder, a maximum allowable external

magnetic flux density is calculated as shown in Figure 31.

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Data Sheet

ADN4624

APPLICATIONS INFORMATION

In combinations of strong magnetic field and high frequency, any

loops formed by PCB traces can induce sufficiently large error

voltages to trigger the thresholds of succeeding circuitry. Avoid PCB

structures that form loops.

INSULATION LIFETIME

All insulation structures eventually break down when subjected to

voltage stress over a sufficiently long period. The rate of insulation

degradation is dependent on the characteristics of the voltage

waveform applied across the insulation as well as on the materials

and material interfaces.

The two types of insulation degradation of primary interest are

breakdown along surfaces exposed to the air and insulation wear

out. Surface breakdown is the phenomenon of surface tracking

and the primary determinant of surface creepage requirements in

system level standards. Insulation wear out is the phenomenon

where charge injection or displacement currents inside the insula-

tion material cause long-term insulation degradation.

Figure 31. Maximum Allowable External Magnetic Flux Density

For example, at a magnetic field frequency of 1 MHz, the maximum

allowable magnetic field of 1.06 kgauss induces a voltage of 0.055

V at the receiving coil. This voltage is about 50% of the sensing

threshold and does not cause a faulty output transition. If such an

event occurs with the worst case polarity during a transmitted pulse,

the applied magnetic field reduces the received pulse from >0.35 V

to 0.295 V. This voltage is still higher than the 0.11 V sensing

threshold of the decoder.

Surface Tracking

Surface tracking is addressed in electrical safety standards by

setting a minimum surface creepage based on the working voltage,

the environmental conditions, and the properties of the insulation

material. Safety agencies perform characterization testing on the

surface insulation of components, which allows the components to

be categorized in different material groups. Lower material group

ratings are more resistant to surface tracking and, therefore, can

provide adequate lifetime with smaller creepage. The minimum

creepage for a given working voltage and material group is in

each system level standard and is based on the total rms voltage

across the isolation barrier, pollution degree, and material group.

The material group and creepage for ADN4624 are detailed in

Table 4.

The preceding magnetic flux density values correspond to specific

current magnitudes at given distances from the ADN4624 trans-

formers. Figure 32 expresses these allowable current magnitudes

as a function of frequency for selected distances. The ADN4624 is

insensitive to external fields. Only extremely large, high frequency

currents that are close to the component can potentially be a

concern. For the 1 MHz example noted, a 2.64 kA current must be

placed 5 mm from the ADN4624 to affect component operation.

Insulation Wear Out

The lifetime of insulation caused by wear out is determined by

the thickness of the insulation, material properties, and the voltage

stress applied. It is important to verify that the product lifetime is

adequate at the application working voltage. The working voltage

supported by an isolator for wear out may not be the same as

the working voltage supported for tracking. The working voltage

applicable to tracking is specified in most standards.

Testing and modeling show that the primary driver of long-term deg-

radation is displacement current in the polyimide insulation causing

incremental damage. The stress on the insulation can be broken

down into broad categories, such as dc stress, which causes little

wear out because there is no displacement current, and an ac

component time varying voltage stress, which causes wear out.

Figure 32. Maximum Allowable Current for Various Current to ADN4624

Spacings

The ratings in certification documents are usually based on 60 Hz

sinusoidal stress because this type of waveform reflects isolation

from line voltage. However, many practical applications have com-

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Data Sheet

ADN4624

APPLICATIONS INFORMATION

binations of 60 Hz ac and dc across the isolation barrier, as shown

in Equation 1. Because only the ac portion of the stress causes

wear out, the equation can be rearranged to solve for the ac rms

voltage, as shown in Equation 2. For insulation wear out with

the polyimide materials used in this product, the ac rms voltage

determines the product lifetime.

This V_RMSvalue is the working voltage used together with the

material group and pollution degree when looking up the creepage

required by a system standard.

To determine if the lifetime is adequate, obtain the time varying

portion of the working voltage. To obtain the ac rms voltage, use

Equation 2.

V_RMS= V_{AC RMS}²+ V_DC(1)

V_{AC RMS}= V_RMS²− V_DC

V_{AC RMS}= 466²− 400²

V_{AC RMS}= V_RMS²− V_DC(2)

V_{AC RMS}= 240 V rms

where:

In this case, the ac rms voltage is simply the line voltage of

240 V rms. This calculation is more relevant when the waveform

is not sinusoidal. Table 10 compares the value to the limits for the

working voltage for the expected lifetime. Note that the dc working

voltage limit in Table 10 is set by the creepage of the package as

specified in IEC 60664-1. This value can differ for specific system

level standards.

V_RMSis the total rms working voltage.

V_{AC RMS}is the time varying portion of the working voltage.

V_DCis the dc offset of the working voltage.

Calculation and Use of Parameters Example

The following example frequently arises in power conversion appli-

cations. Assume that the line voltage on one side of the isolation

is 240 V ac rms and a 400 V dc bus voltage is present on the

other side of the isolation barrier. The isolator material is polyimide.

To establish the critical voltages in determining the creepage, clear-

ance, and lifetime of a device, see Figure 33 and the following

equations.

The working voltage across the barrier from Equation 1 is

V_RMS= V_{AC RMS}²+ V_DC

V_RMS= 240²+ 400²

Figure 33. Critical Voltage Example

V_RMS= 466 V

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Data Sheet

ADN4624

OUTLINE DIMENSIONS

Figure 34. 28-Lead Standard Small Outline, Wide Body, with Finer Pitch [SOIC_W_FP]

(RN-28-1)

Dimensions shown in millimeters

ORDERING GUIDE

Model¹

Temperature Range

Package Description

Packing Quantity

Package Option

ADN4624BRNZ

−40°C to +125°C

28-Lead SOIC (Wide, Finer Pitch)

Tube, 46

RN-28-1

ADN4624BRNZ-RL

Reel, 1000

Z = RoHS Compliant Part.

EVALUATION BOARDS

Model

Description

ADN4624 SOIC_W_FP Evaluation Board

EVAL-ADN4624EB1Z

registered trademarks are the property of their respective owners.

Rev. 0 | 20 of 20

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

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