ADN4652 [ADI]
5 kV/3.75 kV rms、600 Mbps双通道LVDS隔离器 ;
| 型号： | ADN4652 |
| 厂家： | 
ADI |
| 描述： | 5 kV/3.75 kV rms、600 Mbps双通道LVDS隔离器 |
| 文件： | 总24页 (文件大小：795K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
5 kV RMS, 600 Mbps,
Dual-Channel LVDS Isolators
Data Sheet
ADN4650/ADN4651/ADN4652
FEATURES
FUNCTIONAL BLOCK DIAGRAMS
V
V
IN1
IN2
5 kV rms LVDS isolator
ADN4650
Complies with TIA/EIA-644-A LVDS standard
Multiple dual-channel configurations
Up to 600 Mbps switching with low jitter
4.5 ns maximum propagation delay
151 ps maximum peak-to-peak total jitter at 600 Mbps
100 ps maximum pulse skew
600 ps maximum part to part skew
ISOLATION
BARRIER
LDO
LDO
V
D
V
DD2
DD1
D
D
IN1+
IN1–
OUT1+
D
OUT1–
LVDS
DIGITAL ISOLATOR
LVDS
D
D
D
D
IN2+
OUT2+
IN2–
OUT2–
2.5 V or 3.3 V supplies
−75 dBc power supply ripple rejection and glitch immunity
8 kV IEC 61000-4-2 ESD protection across isolation barrier
High common-mode transient immunity: >25 kV/μs
Passes EN55022 Class B radiated emissions limits with
600 Mbps PRBS or 300 MHz clock
GND
GND
2
1
Figure 1.
V
V
IN1
IN2
ADN4651
ISOLATION
BARRIER
LDO
LDO
V
V
DD2
Safety and regulatory approvals
DD1
UL (pending): 5000 V rms for 1 minute per UL 1577
CSA Component Acceptance Notice 5A (pending)
VDE certificate of conformity (pending)
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12
D
D
D
D
IN1+
OUT1+
IN1–
OUT1–
LVDS
DIGITAL ISOLATOR
LVDS
D
D
D
D
OUT2+
IN2+
V
IORM = 424 V peak
OUT2–
IN2–
Fail-safe output high for open, short, and terminated input
conditions (ADN4651/ADN4652)
GND
GND
2
1
Figure 2.
Operating temperature range: −40°C to +125°C
20-lead SOIC with 7.8 mm creepage/clearance
V
V
IN1
IN2
ADN4652
ISOLATION
BARRIER
APPLICATIONS
LDO
LDO
V
V
DD2
DD1
Analog front-end (AFE) isolation
Data plane isolation
Isolated high speed clock and data links
Isolated serial peripheral interface (SPI) over LVDS
D
D
D
D
IN1+
IN1–
OUT1+
OUT1–
LVDS
DIGITAL ISOLATOR
LVDS
D
D
D
OUT2+
OUT2–
IN2+
GENERAL DESCRIPTION
D
IN2–
The ADN4650/ADN4651/ADN46521 are signal isolated, low
voltage differential signaling (LVDS) buffers that operate at up
to 600 Mbps with very low jitter.
GND
GND
2
1
Figure 3.
The devices integrate Analog Devices, Inc., iCoupler® technology,
enhanced for high speed operation, to provide galvanic isolation of
the TIA/EIA-644-A compliant LVDS drivers and receivers. This
technology allows drop-in isolation of an LVDS signal chain.
For high speed operation with low jitter, the LVDS and isolator
circuits rely on a 2.5 V supply. An integrated on-chip low dropout
regulator (LDO) can provide the required 2.5 V from an external
3.3 V power supply. The devices are fully specified over a wide
industrial temperature range and are available in a 20-lead,
wide-body SOIC package with 5 kV rms isolation.
Multiple channel configurations are offered, and the LVDS receiv-
ers on the ADN4651/ADN4652 include a fail-safe mechanism
to ensure a Logic 1 on the corresponding LVDS driver output
when the inputs are floating, shorted, or terminated, but not driven.
1 Protected by U.S. Patents 5,952,849; 6,873,065; 6,903,578; and 7,075,329. Other patents are pending.
Rev. B Document Feedback
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
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Tel: 781.329.4700 ©2015–2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
ADN4650/ADN4651/ADN4652
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Thermal Resistance.......................................................................8
ESD Caution...................................................................................8
Pin Configurations and Function Descriptions............................9
Typical Performance Characteristics ........................................... 12
Test Circuits and Switching Characteristics................................ 17
Theory of Operation ...................................................................... 18
Truth Table and Fail-Safe Receiver .......................................... 18
Isolation ....................................................................................... 19
PCB Layout ................................................................................. 19
Magnetic Field Immunity.......................................................... 19
Insulation Lifetime..................................................................... 20
Applications Information.............................................................. 22
Outline Dimensions....................................................................... 24
Ordering Guide .......................................................................... 24
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagrams............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Receiver Input Threshold Test Voltages .................................... 4
Timing Specifications .................................................................. 4
Insulation and Safety Related Specifications ............................ 5
Package Characteristics ............................................................... 5
Regulatory Information............................................................... 6
DIN V VDE V 0884-10 (VDE V 0884-10) Insulation
Characteristics (Pending)............................................................ 6
Recommended Operating Conditions ...................................... 7
Absolute Maximum Ratings............................................................ 8
REVISION HISTORY
4/16—Rev. A to Rev. B
Changes to Supply Current Parameter, Table 1.............................3
Changes to Skew Parameter and Fail-Safe Delay Parameter,
Table 3 .................................................................................................4
Added Figure 5...................................................................................9
Changes to Table 12 ..........................................................................9
Changes to Figure 30 Caption and Figure 31 Caption .............. 14
Change to Figure 34 ....................................................................... 15
Changes to Truth Table and Fail-Safe Receiver Section............ 16
Added Table 13; Renumbered Sequentially................................ 16
Change to Applications Information Section............................. 20
Added Figure 41 ............................................................................. 20
Changes to Ordering Guide.......................................................... 22
Added ADN4652 ................................................................Universal
Changes to Features Section and General Description Section....... 1
Added Figure 3; Renumbered Sequentially .................................. 1
Changes to Supply Current Parameter, Table 1............................ 3
Changes to Skew Parameter and Fail-Safe Delay Parameter,
Table 3 ................................................................................................ 4
Changes to Table 12.......................................................................... 9
Moved Figure 7 ............................................................................... 10
Added Table 13 ............................................................................... 10
Added Figure 8 and Table 14, Renumbered Sequentially ......... 11
Changes to PCB Layout Section................................................... 19
Changes to Ordering Guide .......................................................... 24
11/15—Revision 0: Initial Version
2/16—Rev. 0 to Rev. A
Added ADN4650 ................................................................Universal
Changes to Features Section and General Description Section........1
Added Figure 1; Renumbered Sequentially .................................. 1
Rev. B | Page 2 of 24
Data Sheet
ADN4650/ADN4651/ADN4652
SPECIFICATIONS
For all minimum/maximum specifications, VDD1 = VDD2 = 2.375 V to 2.625 V, TA = TMIN to TMAX, unless otherwise noted. For all typical
specifications, VDD1 = VDD2 = 2.5 V, TA = 25°C.
Table 1.
Parameter
INPUTS (RECEIVERS)
Input Threshold
High
Symbol
Min
Typ
Max
Unit
Test Conditions/Comments
See Figure 36 and Table 2
VTH
VTL
100
mV
mV
Low
−100
Differential Input Voltage
Input Common-Mode
Voltage
Input Current
Differential Input Capacitance1 CINx
|VID|
VIC
100
0.5|VID|
mV
V
See Figure 36 and Table 2
See Figure 36 and Table 2
2.4 − 0.5|VID|
+5
IIH, IIL
−5
µA
pF
DINx = VDD or 0 V, other input = 1.2 V, VDD = 2.5 V or 0 V
DINx = 0.4 sin(30 × 106πt) V + 0.5 V, other input = 1.2 V
2
OUTPUTS (DRIVERS)
Differential Output Voltage
VOD Magnitude Change
Offset Voltage
VOS Magnitude Change
VOS Peak-to-Peak1
|VOD
|ΔVOD|
VOS
ΔVOS
VOS(PP)
IOS
|
250
310
450
50
mV
mV
V
mV
mV
mA
mA
pF
See Figure 34 and Figure 35, RL = 100 Ω
See Figure 34 and Figure 35, RL = 100 Ω
See Figure 34, RL = 100 Ω
See Figure 34, RL = 100 Ω
See Figure 34, RL = 100 Ω
DOUTx = 0 V
1.125
1.17 1.375
50
150
−20
12
Output Short-Circuit Current
|VOD| = 0 V
Differential Output
Capacitance1
COUTx
5
DOUTx = 0.4 sin(30 × 106πt) V + 0.5 V, other input =
1.2 V, VDD1 or VDD2 = 0 V
POWER SUPPLY
Supply Current
IDD1, IIN1,
IDD2, or IIN2
ADN4651/ADN4652 Only
ADN4650 Only
55
mA
mA
mA
mA
V
No output load, inputs with 100 Ω, no applied |VID|
All outputs loaded, RL = 100 Ω, f = 300 MHz
No output load, inputs with 100 Ω, |VID| = 200 mV
All outputs loaded, RL = 100 Ω, f = 300 MHz
No external supply on VDD1 or VDD2
58
50
60
3.3
80
65
72
3.6
LDO Input Range
VIN1 or
VIN2
3.0
LDO Output Range
VDD1 or
VDD2
2.375
2.5
2.625
V
Power Supply Ripple Rejection, PSRR
Phase Spur Level
−75
dBc
Phase spur level on DOUTx with 300 MHz clock on
DINx and applied ripple of 100 kHz, 100 mV p-p on
a 2.5 V supply to VDD1 or VDD2
COMMON-MODE TRANSIENT
IMMUNITY2
|CM|
25
50
kV/µs VCM = 1000 V, transient magnitude = 800 V
1 These specifications are guaranteed by design and characterization.
2 |CM| is the maximum common-mode voltage slew rate that can be sustained while maintaining any DOUTx+/DOUTx− pin in the same state as the corresponding DINx+/DINx−
pin (no change on output), or producing the expected transition on any DOUTx+/DOUTx− pin if the applied common-mode transient edge is coincident with a data
transition on the corresponding DINx+/DINx− pin. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges.
Rev. B | Page 3 of 24
ADN4650/ADN4651/ADN4652
Data Sheet
RECEIVER INPUT THRESHOLD TEST VOLTAGES
Table 2. Test Voltages for Receiver Operation
Applied Voltages
DINx+ (V)
1.25
1.15
2.4
2.3
0.1
0
1.5
0.9
2.4
DINx− (V)
1.15
1.25
2.3
2.4
0
0.1
0.9
1.5
1.8
Input Voltage, Differential (VID) (V)
Input Voltage, Common-Mode (VIC) (V)
Driver Output (VOD) (mV)
>+250
<−250
>+250
<−250
>+250
<−250
>+250
<−250
>+250
<−250
>+250
<−250
+0.1
−0.1
+0.1
−0.1
+0.1
−0.1
+0.6
−0.6
+0.6
−0.6
+0.6
−0.6
1.2
1.2
2.35
2.35
0.05
0.05
1.2
1.2
2.1
2.1
0.3
1.8
0.6
0
2.4
0
0.6
0.3
TIMING SPECIFICATIONS
For all minimum/maximum specifications, VDD1 = VDD2 = 2.375 V to 2.625 V, TA = TMIN to TMAX, unless otherwise noted. All typical
specifications, VDD1 = VDD2 = 2.5 V, T A = 25°C.
Table 3.
Parameter
Symbol
Min Typ Max1 Unit
Test Conditions/Comments
PROPAGATION DELAY
tPLH, tPHL
4
4.5
ns
See Figure 37, from any DINx+/DINx− to DOUTx+/DOUTx−
See Figure 37, across all DOUTx+/DOUTx−
SKEW
Duty Cycle2
Channel to Channel3
tSK(D)
tSK(CH)
100
ps
ps
ps
ps
ps
200 500
150 300
600
ADN4650 only
ADN4650, ADN4651, ADN4652, or combinations
ADN4650 to ADN4650 only
Part to Part4
tSK(PP)
500
JITTER5
See Figure 37, for any DOUTx+/DOUTx−
Random Jitter, RMS6 (1σ)
Deterministic Jitter7, 8
With Crosstalk
Total Jitter at BER 1 × 10−12
Additive Phase Jitter
tRJ(RMS)
tDJ(PP)
tDJC(PP)
tTJ(PP)
2.6
30
30
70
387
376
4.8
96
ps rms 300 MHz clock input
ps
ps
600 Mbps, 223 − 1 PRBS
600 Mbps, 223 − 1 PRBS
151
ps
300 MHz/600 Mbps, 223 − 1 PRBS9
100 Hz to 100 kHz, fOUT = 10 MHz10
12 kHz to 20 MHz, fOUT = 300 MHz11
See Figure 37, any DOUTx+/DOUTx−, 20% to 80%, RL = 100 Ω, CL = 5 pF
tADDJ
fs rms
fs rms
ps
RISE/FALL TIME
FAIL-SAFE DELAY12
tR, tF
350
1.2
tFSH, tFSL
1
µs
ADN4651/ADN4652 only; see Figure 37 and Figure 4, any
DOUTx+/DOUTx−, RL = 100 Ω
MAXIMUM DATA RATE
600
Mbps
1 These specifications are guaranteed by design and characterization.
2 Duty cycle or pulse skew is the magnitude of the maximum difference between tPLH and tPHL for any channel of a device, that is, |tPHLx – tPHLx|.
3 Channel to channel or output skew is the difference between the largest and smallest values of tPLHx within a device or the difference between the largest and smallest
values of tPHLx within a device, whichever of the two is greater.
4 Part to part output skew is the difference between the largest and smallest values of tPLHx across multiple devices or the difference between the largest and smallest
values of tPHLx across multiple devices, whichever of the two is greater.
5 Jitter parameters are guaranteed by design and characterization. Values do not include stimulus jitter. VID = 400 mV p-p, tR = tF = 0.3 ns (20% to 80%).
6 This specification is measured over a population of ~7,000,000 edges.
7 Peak-to-peak jitter specifications include jitter due to pulse skew (tSK(D)).
8 This specification is measured over a population of ~3,000,000 edges.
9 Using the formula tTJ(PP) = 14 × tRJ(RMS) + tDJ(PP)
.
10 With input phase jitter of 250 fs rms subtracted.
11 With input phase jitter of 100 fs rms subtracted.
12 The fail-safe delay is the delay before DOUTx is switched high to reflect idle input to DINx (|VID| < 100 mV, open or short/terminated input condition).
Rev. B | Page 4 of 24
Data Sheet
ADN4650/ADN4651/ADN4652
Timing Diagram
>1.3V
1.2V
D
INx+
(D
= 1.2V)
INx–
<1.1V
+0.1V
V
0V
ID
–0.1V
D
D
OUTx+
~1.3V
OUTx–
~1.0V
~ +0.3V
+0.1V
+0.1V
V
0V
OD
~ –0.3V
tFSH
tFSL
Figure 4. Fail-Safe Timing Diagram
INSULATION AND SAFETY RELATED SPECIFICATIONS
For additional information, see www.analog.com/icouplersafety.
Table 4.
Parameter
Symbol Value Unit
Test Conditions/Comments
Rated Dielectric Insulation Voltage
Minimum External Air Gap (Clearance)
5000
7.8
V rms
1-minute duration
L (I01)
L (I02)
L (PCB)
mm min Measured from input terminals to output terminals,
shortest distance through air
mm min Measured from input terminals to output terminals,
shortest distance path along body
mm min Measured from input terminals to output terminals,
shortest distance through air, line of sight, in the PCB
mounting plane
Minimum External Tracking (Creepage)
7.8
8.1
Minimum Clearance in the Plane of the Printed
Circuit Board (PCB Clearance)
Minimum Internal Gap (Internal Clearance)
Tracking Resistance (Comparative Tracking Index)
Material Group
17
>400
II
µm min
V
Insulation distance through insulation
DIN IEC 112/VDE 0303 Part 1
Material Group (DIN VDE 0110, 1/89, Table 1)
CTI
PACKAGE CHARACTERISTICS
Table 5.
Parameter
Symbol Min Typ Max Unit Test Conditions/Comments
Resistance (Input to Output)1
Capacitance (Input to Output)1
Input Capacitance2
RI-O
CI-O
CI
1013
Ω
pF
pF
2.2
3.7
f = 1 MHz
IC Junction to Ambient Thermal Resistance
θJA
45.7
°C/W Thermal simulation with 4-layer standard JEDEC PCB
1 The device is considered a 2-terminal device: Pin 1 through Pin 10 are shorted together, and Pin 11 through Pin 20 are shorted together.
2 Input capacitance is from any input data pin to ground.
Rev. B | Page 5 of 24
ADN4650/ADN4651/ADN4652
Data Sheet
REGULATORY INFORMATION
See Table 11 and the Insulation Lifetime section for details regarding recommended maximum working voltages for specific cross-
isolation waveforms and insulation levels.
Table 6.
UL (Pending)
CSA (Pending)
VDE (Pending)
To Be Recognized Under UL 1577
Component Recognition Program1
To be approved under CSA
To be certified according to DIN V VDE V 0884-10
Component Acceptance Notice 5A (VDE V 0884-10):2006-122
Single Protection, 5000 V rms Isolation
Voltage
Reinforced insulation, VIORM = 424 V peak, VIOSM
6000 V peak
=
Basic insulation, VIORM = 424 V peak, VIOSM = 10,000 V peak
File 2471900-4880-0001
File E214100
File 205078
1 In accordance with UL 1577, each ADN4650/ADN4651/ADN4652 is proof tested by applying an insulation test voltage ≥ 6000 V rms for 1 sec.
2 In accordance with DIN V VDE V 0884-10, each ADN4650/ADN4651/ADN4652 is proof tested by applying an insulation test voltage ≥ 795 V peak for 1 sec (partial discharge
detection limit = 5 pC).
DIN V VDE V 0884-10 (VDE V 0884-10) INSULATION CHARACTERISTICS (PENDING)
This isolator is suitable for reinforced electrical isolation only within the safety limit data. Protective circuits ensure the maintenance of
the safety data.
Table 7.
Description
Test Conditions/Comments
Symbol Characteristic Unit
Installation Classification per DIN VDE 0110
For Rated Mains Voltage ≤ 150 V rms
For Rated Mains Voltage ≤ 300 V rms
For Rated Mains Voltage ≤ 600 V rms
Climatic Classification
Pollution Degree per DIN VDE 0110, Table 1
Maximum Working Insulation Voltage
Input to Output Test Voltage, Method B1
I to IV
I to IV
I to III
40/125/21
2
VIORM
Vpd (m)
424
795
V peak
V peak
VIORM × 1.875 = Vpd (m), 100% production test,
t
ini = tm = 1 sec, partial discharge < 5 pC
Input to Output Test Voltage, Method A
After Environmental Tests Subgroup 1
Vpd (m)
VIORM × 1.5 = Vpd (m), tini = 60 sec, tm = 10 sec,
partial discharge < 5 pC
VIORM × 1.2 = Vpd (m), tini = 60 sec, tm = 10 sec,
partial discharge < 5 pC
636
V peak
V peak
V peak
After Input and/or Safety Test Subgroup 2
and Subgroup 3
Highest Allowable Overvoltage
Surge Isolation Voltage
Basic
509
VIOTM
5000
VPEAK = 12.8 kV, 1.2 µs rise time, 50 µs, 50% fall time
VPEAK = 10 kV, 1.2 µs rise time, 50 µs, 50% fall time
VIOSM
VIOSM
10,000
6000
V peak
V peak
Reinforced
Safety Limiting Values
Maximum value allowed in the event of a failure
(see Figure 5)
Maximum Junction Temperature
Total Power Dissipation at 25°C
Insulation Resistance at TS
TS
PS
RS
150
2.78
>109
°C
W
Ω
VIO = 500 V
Rev. B | Page 6 of 24
Data Sheet
ADN4650/ADN4651/ADN4652
3.0
2.5
2.0
1.5
1.0
0.5
RECOMMENDED OPERATING CONDITIONS
Table 8.
Parameter
Symbol
Rating
Operating Temperature
Supply Voltages
Supply to LDO
TA
−40°C to +125°C
VIN1, VIN2
3.0 V to 3.6 V
LDO Bypass, VINx Shorted to VDDx VDD1, VDD2 2.375 V to 2.625 V
0
0
50
100
150
200
AMBIENT TEMPERATURE (°C)
Figure 5. Thermal Derating Curve, Dependence of Safety Limiting Values
with Ambient Temperature per DIN V VDE V 0884-10
Rev. B | Page 7 of 24
ADN4650/ADN4651/ADN4652
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 9.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Parameter
Rating
VIN1 to GND1/VIN2 to GND2
VDD1 to GND1/VDD2 to GND2
Input Voltage (DINx+, DINx−) to GNDx on
the Same Side
−0.3 V to +6.5 V
−0.3 V to +2.8 V
−0.3 V to VDD + 0.3 V
Table 10. Thermal Resistance
Package Type
θJA
Unit
20-Lead SOIC
45.7
°C/W
Output Voltage (DOUTx+, DOUTx−) to
GNDx on the Same Side
Short-Circuit Duration (DOUTx+, DOUTx−
−0.3 V to VDD + 0.3 V
Continuous
)
ESD CAUTION
to GNDx on the Same Side
Operating Temperature Range
Storage Temperature Range
Junction Temperature (TJ Maximum)
−40°C to +125°C
−65°C to +150°C
150°C
Power Dissipation
ESD
(TJ maximum − TA)/θJA
Human Body Model (All Pins to
Respective GNDx, 1.5 kΩ, 100 pF)
IEC 61000-4-2 (LVDS Pins to Isolated
GNDx Across Isolation Barrier)
4 kV
8 kV
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Table 11. Maximum Continuous Working Voltage1
Parameter
Rating
Constraint
AC Voltage
Bipolar Waveform
Basic Insulation
Reinforced Insulation
Unipolar Waveform
Basic Insulation
Reinforced Insulation
DC Voltage
495 V peak
495 V peak
50-year minimum insulation lifetime for 1% failure
50-year minimum insulation lifetime for 1% failure
990 V peak
875 V peak
50-year minimum insulation lifetime for 1% failure
Lifetime limited by package creepage, maximum approved working voltage
Basic Insulation
Reinforced Insulation
1079 V peak Lifetime limited by package creepage, maximum approved working voltage
536 V peak Lifetime limited by package creepage, maximum approved working voltage
1 The maximum continuous working voltage refers to the continuous voltage magnitude imposed across the isolation barrier. See the Insulation Lifetime section for
more details.
Rev. B | Page 8 of 24
Data Sheet
ADN4650/ADN4651/ADN4652
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
V
1
2
3
4
5
6
7
8
9
20
V
IN2
IN1
GND
19 GND
1
2
V
18
V
DD2
DD1
GND
17 GND
1
IN1+
IN1–
IN2+
IN2–
2
ADN4650
TOP VIEW
(Not to Scale)
D
D
D
D
16
15
14
13
12
D
D
D
D
OUT1+
OUT1–
OUT2+
OUT2–
DD2
V
V
DD1
GND 10
11 GND
1
2
Figure 6. ADN4650 Pin Configuration
Table 12. ADN4650 Pin Function Descriptions
Pin No.
Mnemonic
Description
1
VIN1
Optional 3.3 V Power Supply/LDO Input for Side 1. Bypass VIN1 to GND1 using a 1 μF capacitor. Alternatively, if
using a 2.5 V supply, connect VIN1 directly to VDD1
Ground, Side 1.
.
2, 4, 10
3, 9
GND1
VDD1
2.5 V Power Supply for Side 1. Connect both pins externally and bypass to GND1 with 0.1 μF capacitors. If
supplying 3.3 V to VIN1, connect a 1 μF capacitor between Pin 3 and GND1 for proper regulation of the 2.5 V
output of the internal LDO.
5
6
7
8
DIN1+
DIN1−
DIN2+
DIN2−
GND2
VDD2
Noninverted Differential Input 1.
Inverted Differential Input 1.
Noninverted Differential Input 2.
Inverted Differential Input 2.
Ground, Side 2.
2.5 V Power Supply for Side 2. Connect both pins externally and bypass to GND2 with 0.1 μF capacitors. If
supplying 3.3 V to VIN2, connect a 1 μF capacitor between Pin 18 and GND2 for proper regulation of the 2.5 V
output of the internal LDO.
11, 17, 19
12, 18
13
14
15
16
20
DOUT2−
DOUT2+
DOUT1−
DOUT1+
VIN2
Inverted Differential Output 2.
Noninverted Differential Output 2.
Inverted Differential Output 1.
Noninverted Differential Output 1.
Optional 3.3 V Power Supply/LDO Input for Side 2. Bypass VIN2 to GND2 using a 1 μF capacitor. Alternatively, if
using a 2.5 V supply, connect VIN2 directly to VDD2
.
Rev. B | Page 9 of 24
ADN4650/ADN4651/ADN4652
Data Sheet
V
1
2
3
4
5
6
7
8
9
20
V
IN2
IN1
GND
19 GND
1
2
V
18 V
DD2
DD1
GND
17 GND
1
IN1+
IN1–
2
OUT1+
OUT1–
IN2+
ADN4651
TOP VIEW
(Not to Scale)
D
D
16
15
14
13
12
D
D
D
D
D
D
OUT2+
OUT2–
IN2–
V
V
DD2
DD1
GND 10
11 GND
1
2
Figure 7. ADN4651 Pin Configuration
Table 13. ADN4651 Pin Function Descriptions
Pin No.
Mnemonic
Description
1
VIN1
Optional 3.3 V Power Supply/LDO Input for Side 1. Bypass VIN1 to GND1 using a 1 μF capacitor. Alternatively, if
using a 2.5 V supply, connect VIN1 directly to VDD1
Ground, Side 1.
.
2, 4, 10
3, 9
GND1
VDD1
2.5 V Power Supply for Side 1. Connect both pins externally and bypass to GND1 with 0.1 μF capacitors. If
supplying 3.3 V to VIN1, connect a 1 μF capacitor between Pin 3 and GND1 for proper regulation of the 2.5 V
output of the internal LDO.
5
6
7
8
DIN1+
DIN1−
DOUT2+
DOUT2−
GND2
VDD2
Noninverted Differential Input 1.
Inverted Differential Input 1.
Noninverted Differential Output 2.
Inverted Differential Output 2.
Ground, Side 2.
2.5 V Power Supply for Side 2. Connect both pins externally and bypass to GND2 with 0.1 μF capacitors. If
supplying 3.3 V to VIN2, connect a 1 μF capacitor between Pin 18 and GND2 for proper regulation of the 2.5 V
output of the internal LDO.
11, 17, 19
12, 18
13
14
15
16
20
DIN2−
DIN2+
DOUT1−
DOUT1+
VIN2
Inverted Differential Input 2.
Noninverted Differential Input 2.
Inverted Differential Output 1.
Noninverted Differential Output 1.
Optional 3.3 V Power Supply/LDO Input for Side 2. Bypass VIN2 to GND2 using a 1 μF capacitor. Alternatively, if
using a 2.5 V supply, connect VIN2 directly to VDD2
.
Rev. B | Page 10 of 24
Data Sheet
ADN4650/ADN4651/ADN4652
V
1
2
3
4
5
6
7
8
9
20
V
IN2
IN1
GND
19 GND
1
2
2
V
18
V
DD2
DD1
GND
17 GND
1
ADN4652
TOP VIEW
(Not to Scale)
D
D
16
15
14
13
12
D
D
D
D
OUT1+
OUT1–
IN1+
IN1–
D
D
IN2+
OUT2+
OUT2–
DD2
IN2–
V
V
DD1
GND 10
11 GND
1
2
Figure 8. ADN4652 Pin Configuration
Table 14. ADN4652 Pin Function Descriptions
Pin No.
Mnemonic
Description
1
VIN1
Optional 3.3 V Power Supply/LDO Input for Side 1. Bypass VIN1 to GND1 using a 1 μF capacitor. Alternatively, if
using a 2.5 V supply, connect VIN1 directly to VDD1
Ground, Side 1.
.
2, 4, 10
3, 9
GND1
VDD1
2.5 V Power Supply for Side 1. Connect both pins externally and bypass to GND1 with 0.1 μF capacitors. If
supplying 3.3 V to VIN1, connect a 1 μF capacitor between Pin 3 and GND1 for proper regulation of the 2.5 V
output of the internal LDO.
5
6
7
8
DOUT1+
DOUT1−
DIN2+
DIN2−
GND2
VDD2
Noninverted Differential Output 1.
Inverted Differential Output 1.
Noninverted Differential Input 2.
Inverted Differential Input 2.
Ground, Side 2.
2.5 V Power Supply for Side 2. Connect both pins externally and bypass to GND2 with 0.1 μF capacitors. If
supplying 3.3 V to VIN2, connect a 1 μF capacitor between Pin 18 and GND2 for proper regulation of the 2.5 V
output of the internal LDO.
11, 17, 19
12, 18
13
14
15
16
20
DOUT2−
DOUT2+
DIN1−
DIN1+
VIN2
Inverted Differential Output 2.
Noninverted Differential Output 2.
Inverted Differential Input 1.
Noninverted Differential Input 1.
Optional 3.3 V Power Supply/LDO Input for Side 2. Bypass VIN2 to GND2 using a 1 μF capacitor. Alternatively, if
using a 2.5 V supply, connect VIN2 directly to VDD2
.
Rev. B | Page 11 of 24
ADN4650/ADN4651/ADN4652
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
VDD1 = VDD2 = 2.5 V, T A = 25°C, RL = 100 Ω, 300 MHz input with |VID| = 200 mV, and VIC = 1.1 V, unless otherwise noted.
70
60
50
40
30
20
10
0
70
60
50
40
30
20
10
0
I
I
I
I
I
I
I
I
DD1
DD2
IN1
DD1
DD2
IN1
IN2
IN2
0
50
100
150
200
250
300
–50
–25
0
25
50
75
100
125
INPUT CLOCK FREQUENCY (MHz)
AMBIENT TEMPERATURE (°C)
Figure 9. IDD1/IDD2 or IIN1/IIN2 Supply Current vs. DIN1 Input Clock Frequency
(DIN2 Not Switching)
Figure 12. IDD1/IDD2 or IIN1/IIN2 Supply Current vs. Ambient Temperature (TA)
(DIN2 with 300 MHz Clock Input, DIN1 Not Switching)
70
60
50
40
30
20
70
60
50
40
30
20
I
I
I
I
(D
(D
(D
(D
ACTIVE)
ACTIVE)
ACTIVE)
ACTIVE)
I
I
I
I
DD1
DD2
DD1
DD2
IN2
IN2
IN1
IN1
DD1
DD2
IN1
10
0
10
0
IN2
2.35
2.40
2.45
2.50
2.55
/V
2.60
2.65
0
50
100
150
200
250
300
SUPPLY VOLTAGE, V
(V)
DD1 DD2
INPUT CLOCK FREQUENCY (MHz)
Figure 10. IDD1/IDD2 or IIN1/IIN2 Supply Current vs. DIN2 Input Clock Frequency
(DIN1 Not Switching)
Figure 13. IDD1/IDD2 Supply Current vs. Supply Voltage, VDD1/VDD2
70
60
50
40
30
20
70
60
50
40
30
20
I
I
I
I
(D
(D
ACTIVE)
ACTIVE)
ACTIVE)
ACTIVE)
I
I
I
I
IN1
IN2
IN2
DD1
DD2
IN1
10
0
IN2
10
0
1 (D
IN
IN1
IN1
(D
IN2
IN2
3.00
3.15
3.30
3.45
(V)
3.60
–50
–25
0
25
50
75
100
125
SUPPLY VOLTAGE, V /V
IN1 IN2
AMBIENT TEMPERATURE (°C)
Figure 11. IDD1/IDD2 or IIN1/IIN2 Supply Current vs. Ambient Temperature (TA)
(DIN1 with 300 MHz Clock Input, DIN2 Not Switching)
Figure 14. IIN1/IIN2 Supply Current vs. Supply Voltage, VIN1/VIN2
Rev. B | Page 12 of 24
Data Sheet
ADN4650/ADN4651/ADN4652
2.65
2.60
2.55
2.50
2.45
2.40
2.35
1.60
1.55
1.50
1.45
1.40
1.35
1.30
1.25
V
V
V
V
CHANNEL 1
CHANNEL 2
DD1
DD2
OH
OH
3.0
3.1
3.2
3.3
3.4
3.5
3.6
2.35
2.40
2.45
2.50
2.55
2.60
2.65
LDO INPUT VOLTAGE, V /V
(V)
SUPPLY VOLTAGE, V
/V
(V)
IN1 IN2
DD1 DD2
Figure 15. LDO Output Voltage, VDD1/VDD2 vs. LDO Input Voltage, VIN1/VIN2
Figure 18. Driver Output High Voltage (VOH) vs. Supply Voltage, VDD1/VDD2
1.25
1.20
1.15
1.10
1.05
1.00
0.95
350
340
330
320
310
300
290
280
270
V
V
CHANNEL 1
CHANNEL 2
OL
OL
V
V
CHANNEL 1
CHANNEL 2
260
250
OD
OD
0.90
2.35
2.40
2.45
2.50
2.55
/V
2.60
2.65
0
50
100
150
200
250
300
350
SUPPLY VOLTAGE, V
(V)
DD1 DD2
INPUT CLOCK FREQUENCY (MHz)
Figure 16. Driver Differential Output Voltage (VOD) vs. Input Clock Frequency
Figure 19. Driver Output Low Voltage (VOL) vs. Supply Voltage, VDD1/VDD2
1.375
450
400
350
300
250
200
150
100
1.325
1.275
1.225
1.175
V
V
CHANNEL 1
CHANNEL 2
OS
OS
50
V
V
CHANNEL 1
CHANNEL 2
OD
OD
1.125
2.35
0
50
2.40
2.45
2.50
2.55
/V
2.60
2.65
75
100
OUTPUT LOAD, R (Ω)
125
150
SUPPLY VOLTAGE, V
(V)
DD1 DD2
L
Figure 17. Driver Differential Output Voltage (VOD) vs. Output Load (RL)
Figure 20. Driver Output Offset Voltage (VOS) vs. Supply Voltage, VDD1/VDD2
Rev. B | Page 13 of 24
ADN4650/ADN4651/ADN4652
Data Sheet
3.60
3.60
3.55
3.50
3.45
3.40
3.35
3.30
tPHL CHANNEL 2
tPHL CHANNEL 2
tPLH CHANNEL 2
tPHL CHANNEL 1
tPLH CHANNEL 1
tPLH CHANNEL 2
tPHL CHANNEL 1
tPLH CHANNEL 1
3.55
3.50
3.45
3.40
3.35
3.30
2.35
2.40
2.45
2.50
2.55
2.60
2.65
0
0.5
1.0
1.5
2.0
2.5
SUPPLY VOLTAGE, V
AND V
(V)
RECEIVER INPUT OFFSET VOLTAGE, V (V)
DD1
DD2
IC
Figure 21. Differential Propagation Delay vs. Supply Voltage, VDD1 and VDD2
Figure 24. Differential Propagation Delay vs. Receiver Input Offset Voltage (VIC)
4.0
3.9
3.8
3.7
3.6
3.5
3.4
3.3
240
tF CHANNEL 2
tR CHANNEL 2
tF CHANNEL 1
tR CHANNEL 1
220
200
180
160
140
120
tPHL CHANNEL 2
tPLH CHANNEL 2
tPHL CHANNEL 1
tPLH CHANNEL 1
3.2
3.1
3.0
2.35
2.40
2.45
2.50
2.55
/V
2.60
2.65
–50
–25
0
25
50
75
100
125
SUPPLY VOLTAGE, V
(V)
AMBIENT TEMPERATURE (°C)
DD1 DD2
Figure 22. Differential Propagation Delay vs. Ambient Temperature (TA)
Figure 25. Differential Output Transition Time vs. Supply Voltage, VDD1/VDD2
3.60
3.55
3.50
3.45
240
220
200
180
3.40
160
tPHL CHANNEL 2
tPLH CHANNEL 2
tPHL CHANNEL 1
tF CHANNEL 2
tR CHANNEL 2
tF CHANNEL 1
tR CHANNEL 1
3.35
140
tPLH CHANNEL 1
1.0 1.2
DIFFERENTIAL INPUT VOLTAGE, V (V)
3.30
120
–50
0
0.2
0.4
0.6
0.8
1.4
–25
0
25
50
75 100 125
ID
AMBIENT TEMPERATURE (°C)
Figure 23. Differential Propagation Delay vs. Receiver Differential Input
Voltage (VID)
Figure 26. Differential Output Transition Time vs. Ambient Temperature (TA)
Rev. B | Page 14 of 24
Data Sheet
ADN4650/ADN4651/ADN4652
30
25
20
15
10
5
40
35
30
25
20
15
10
5
tSK(D) CHANNEL 2
tSK(D) CHANNEL 1
CHANNEL 1
CHANNEL 2
0
2.35
0
2.40
2.45
2.50
2.55
AND V
2.60
(V)
DD2
2.65
0
100
200
300
400
500
600
SUPPLY VOLTAGE, V
DD1
DATA RATE (Mbps)
Figure 27. Duty Cycle Skew (tSK(D)) vs. Supply Voltage, VDD1 and VDD2
Figure 29. Deterministic Jitter (tDJ(PP)) vs. Data Rate
50
45
40
35
30
25
20
15
10
5
30
25
20
15
10
5
CHANNEL 1
CHANNEL 2
tSK(D) CHANNEL 2
tSK(D) CHANNEL 1
75 100 125
AMBIENT TEMPERATURE (°C)
0
2.35
0
–50
2.40
2.45
2.50
2.55
/V
2.60
2.65
–25
0
25
50
SUPPLY VOLTAGE, V
(V)
DD1 DD2
Figure 28. Duty Cycle Skew (tSK(D)) vs. Ambient Temperature (TA)
Figure 30. Deterministic Jitter (tDJ(PP)) vs. Supply Voltage, VDD1/VDD2
Rev. B | Page 15 of 24
ADN4650/ADN4651/ADN4652
Data Sheet
60
50
40
30
20
10
0
CHANNEL 1
CHANNEL 2
–50
–25
0
25
50
75
100
125
CH1 50mV CH2 50mV
CH3 10mV CH4 10mV
300ps/DIV
DELAY 61.0828ns
AMBIENT TEMPERATURE (°C)
Figure 31. Deterministic Jitter (tDJ(PP)) vs. Ambient Temperature
Figure 33. ADN4651 Eye Diagram for DOUT2
CH1 50mV CH2 50mV
CH3 10mV CH4 10mV
300ps/DIV
DELAY 61.0828ns
Figure 32. ADN4651 Eye Diagram for DOUT1
Rev. B | Page 16 of 24
Data Sheet
ADN4650/ADN4651/ADN4652
TEST CIRCUITS AND SWITCHING CHARACTERISTICS
D
D
D
INx+
OUTx+
R
V
V
OD
ID
V
V
OUT+
IN+
D
D
OUTx–
INx–
V
V
OUT–
IN–
D
D
INx+
INx–
OUTx+
D
R /2
L
NOTES
1. V = V
– V
IN–
R
ID
IN+
2. V = (V
+ V )/2
IC
IN+
IN–
V
V
OD
V
V
OS
R /2
L
3. V
= V
– V
OD
OUT+ OUT–
D
D
OUTx–
4. V = (V
+ V
)/2
OS
OUT+
OUT–
Figure 34. Driver Test Circuit
Figure 36. Voltage Definitions
D
D
D
D
D
D
C
INx+
OUTx+
INx+
OUTx+
L
3.75kΩ
3.75kΩ
R
V
L
TEST
V
SIGNAL
GENERATOR
R
D
R
D
R
L
V
V
OD
D
INx–
C
50Ω
50Ω
L
D
OUTx–
INx–
OUTx–
NOTES
NOTES
1. V
= 0V TO 2.4V
1. C INCLUDES PROBE AND JIG CAPACITANCE.
TEST
L
Figure 35. Driver Test Circuit (Full Load Across Common-Mode Range)
Figure 37. Timing Test Circuit
Rev. B | Page 17 of 24
ADN4650/ADN4651/ADN4652
Data Sheet
THEORY OF OPERATION
The ADN4650/ADN4651/ADN4652 are TIA/EIA-644-A LVDS
compliant isolated buffers. LVDS signals applied to the inputs are
transmitted on the outputs of the buffer, and galvanic isolation
is integrated between the two sides of the device. This integration
allows drop-in isolation of LVDS signal chains.
ADN4651/ADN4652 incorporate a fail-safe circuit to ensure
the LVDS outputs are in a known state (logic high) when the
input state is undefined (−100 mV < VID < +100 mV), as shown
in Table 16.
This input state can occur when the inputs are floating (uncon-
nected, no termination resistor), when the inputs are shorted,
and when there is no active driver connected to the inputs (but
with a termination resistor). Open-circuit, short-circuit, and
terminated/idle bus fail-safes, respectively, ensure a known output
state for these conditions, as implemented by the
The LVDS receiver detects the differential voltage present across
a termination resistor on an LVDS input. An integrated digital
isolator transmits the input state across the isolation barrier,
and an LVDS driver outputs the same state as the input.
With a positive differential voltage of ≥100 mV across any DINx pin,
the corresponding DOUTx+ pin sources current. This current flows
across the connected transmission line and termination at the
receiver at the far end of the bus, while DOUTx− sinks the return
current. With a negative differential voltage of ≤−100 mV across
any DINx pin, the corresponding DOUTx+ pin sinks current, with
ADN4651/ADN4652.
After the fail-safe circuit is triggered by these input states
(−100 mV < VID < +100 mV), there is a delay of up to 1.2 µs
before the output is guaranteed to be high (VOD ≥ 250 mV).
During this time, the output may transition to or stay in a logic
low state (VOD ≤ −250 mV).
DOUTx− sourcing the current. Table 15 and Table 16 show these
input/output combinations.
The fail-safe circuit triggers as soon as the input differential voltage
remains between +100 mV and −100 mV for some nanoseconds.
This means that very slow rise and fall times on the input signal,
outside typical LVDS operation (350 ps maximum tR/tF), can poten-
tially trigger the fail-safe circuit on a high to low crossover.
The output drive current is between 2.5 mA and 4.5 mA
(typically 3.1 mA), developing between 250 mV and 450 mV
across a 100 Ω termination resistor (RT). The received voltage is
centered around 1.2 V. Note that because the differential voltage
(VID) reverses polarity, the peak-to-peak voltage swing across RT
is twice the differential voltage magnitude (|VID|).
At the minimum |VID| of 100 mV for normal operation, the
rise/fall time must be ≤5 ns to avoid triggering a fail-safe state.
Increasing |VID| to 200 mV correspondingly allows an input
rise/fall time of up to 10 ns without triggering a fail-safe state.
For very low speed applications where slow high to low transitions
in excess of this limit are expected, using external biasing resistors
is an option to introduce a minimum |VID| of 100 mV (that is,
the fail-safe cannot trigger).
TRUTH TABLE AND FAIL-SAFE RECEIVER
The LVDS standard, TIA/EIA-644-A, defines normal receiver
operation under two conditions: an input differential voltage
of ≥+100 mV corresponding to one logic state, and a voltage of
≤−100 mV for the other logic state. Between these thresholds,
standard LVDS receiver operation is undefined (it may detect
either state), as shown in Table 15 for the ADN4650. The
Table 15. ADN4650 Input/Output Operation
Input (DINx
)
Output (DOUTx
VOD (mV)
≥250
≤−250
Indeterminate
≥250
)
Powered On
VID (mV)
≥100
≤−100
Logic
Powered On
Logic
Yes
Yes
Yes
No
High
Low
Indeterminate
Don’t care
Yes
Yes
Yes
Yes
High
Low
Indeterminate
High
−100 < VID < +100
Don’t care
Table 16. ADN4651/ADN4652 Input/Output Operation
Input (DINx
)
Output (DOUTx
VOD (mV)
≥250
)
Powered On
VID (mV)
≥100
Logic
Powered On
Logic
High
Low
High
High
Yes
Yes
Yes
No
High
Yes
Yes
Yes
Yes
≤−100
Low
≤−250
≥250
≥250
−100 < VID < +100
Don’t care
Indeterminate
Don’t care
Rev. B | Page 18 of 24
Data Sheet
ADN4650/ADN4651/ADN4652
The ADN4650/ADN4651/ADN4652 require appropriate
decoupling of the VDDx pins with 100 nF capacitors. If the
integrated LDO is not used, and a 2.5 V supply is connected
directly, connect the appropriate VINx pin to the supply as well, as
shown in Figure 38, using the ADN4651 as an example.
ISOLATION
In response to any change in the input state detected by the
integrated LVDS receiver, an encoder circuit sends narrow (~1 ns)
pulses to a decoder circuit using integrated transformer coils.
The decoder is bistable and is, therefore, either set or reset by
the pulses that indicate input transitions. The decoder state
determines the LVDS driver output state in normal operation,
and this in turn reflects the isolated LVDS buffer input state.
100nF
100nF
1
2
20
19
18
17
16
15
14
13
12
11
V
V
V
IN2
IN1
GND
GND
1
2
V
3
DD1
DD2
In the absence of input transitions for more than approximately
1 μs, a periodic set of refresh pulses, indicative of the correct
input state, ensures dc correctness at the output (including the
fail-safe output state, if applicable). These periodic refresh
pulses also correct the output state within 1 μs in the event of a
fault condition or set the ADN4651/ADN4652 output to the fail-
safe state.
4
GND
D
GND
D
1
2
ADN4651
5
IN1+
IN1–
OUT1+
OUT1–
IN2+
TOP VIEW
100Ω
6
D
D
D
(Not to Scale)
D
D
D
7
OUT2+
OUT2–
100Ω
8
IN2–
V
9
V
DD2
DD1
10
GND
GND
2
1
100nF
100nF
Figure 38. Required PCB Layout When Not Using the LDO (2.5 V Supply)
On power-up, the output state may initially be in the incorrect
dc state if there are no input transitions. The output state is
corrected within 1 μs by the refresh pulses.
1µF 100nF
100nF1µF
1µF
1µF
1
2
20
19
18
17
16
15
14
13
12
11
V
V
IN2
IN1
GND
GND
1
2
If the decoder receives no internal pulses for more than
approximately 1 μs, the device assumes that the input side is
unpowered or nonfunctional, in which case, the output is set to
a positive differential voltage (logic high).
V
3
V
DD2
DD1
4
GND
D
GND
2
1
ADN4651
5
D
D
D
D
IN1+
OUT1+
OUT1–
IN2+
TOP VIEW
100Ω
6
D
D
D
(Not to Scale)
IN1–
7
OUT2+
OUT2–
100Ω
8
PCB LAYOUT
IN2–
V
9
V
DD2
DD1
The ADN4650/ADN4651/ADN4652 can operate with high
speed LVDS signals up to 300 MHz clock, or 600 Mbps nonreturn
to zero (NRZ) data. With such high frequencies, it is particularly
important to apply best practices for the LVDS trace layout and
termination. Locate a 100 Ω termination resistor as close as
possible to the receiver, across the DINx+ and DINx− pins.
10
GND
GND
2
1
100nF
100nF
Figure 39. Required PCB Layout When Using the LDO (3.3 V Supply)
When the integrated LDO is used, bypass capacitors of 1 ꢀF are
required on the VINx pins and on the nearest VDDx pins (LDO
output), as shown in Figure 39, using the ADN4651 as an
example.
Controlled 50 Ω impedance traces are needed on LVDS signal lines
for full signal integrity, reduced system jitter, and minimizing elec-
tromagnetic interference (EMI) from the PCB. Trace widths, lateral
distance within each pair, and distance to the ground plane
underneath all must be chosen appropriately. Via fencing to the
PCB ground between pairs is also a best practice to minimize
crosstalk between adjacent pairs.
MAGNETIC FIELD IMMUNITY
The limitation on the magnetic field immunity of the device is
set by the condition in which the induced voltage in the
transformer receiving coil is sufficiently large, either to falsely
set or reset the decoder. The following analysis defines such
conditions. The ADN4650/ADN4651/ADN4652 are examined
in a 2.375 V operating condition because it represents the most
susceptible mode of operation for this product.
The ADN4650/ADN4651/ADN4652 pass EN55022 Class B
emissions limits without extra considerations required for the
isolator when operating with up to 600 Mbps PRBS data. When
isolating high speed clocks (for example, 300 MHz), a reduced
PCB clearance (isolation gap) may be required to reduce dipole
antenna effects and provide sufficient margin below Class B
emissions limits.
The pulses at the transformer output have an amplitude greater
than 0.5 V. The decoder has a sensing threshold of about 0.25 V,
therefore establishing a 0.25 V margin in which induced voltages
are tolerated. The voltage induced across the receiving coil is
given by
The best practice for high speed PCB design avoids any other emis-
sions from PCBs in applications that use the ADN4650/ADN4651/
ADN4652. Special care is recommended for off board connections,
where switching transients from high speed LVDS signals (and
clocks in particular) may conduct onto cabling, resulting in
radiated emissions. Use common-mode chokes, ferrites, or other
filters as appropriate at the LVDS connectors, as well as cable
shield or PCB ground connections to earth/chassis.
2
V = (−dβ/dt)∑πrn ; n = 1, 2, …, N
where:
β is the magnetic flux density.
rn is the radius of the nth turn in the receiving coil.
N is the number of turns in the receiving coil.
Rev. B | Page 19 of 24
ADN4650/ADN4651/ADN4652
Data Sheet
Given the geometry of the receiving coil in the ADN4650/
ADN4651/ADN4652, and an imposed requirement that the
induced voltage be, at most, 50% of the 0.25 V margin at the
decoder, a maximum allowable magnetic field is calculated as
shown in Figure 40.
Note that at combinations of strong magnetic field and high
frequency, any loops formed by PCB traces can induce
sufficiently large error voltages to trigger the thresholds of
succeeding circuitry. Avoid PCB structures that form loops.
INSULATION LIFETIME
1k
All insulation structures eventually break down when subjected
to voltage stress over a sufficiently long period. The rate of
insulation degradation is dependent on the characteristics of the
voltage waveform applied across the insulation as well as on the
materials and material interfaces.
100
10
1
The two types of insulation degradation of primary interest are
breakdown along surfaces exposed to the air and insulation wear
out. Surface breakdown is the phenomenon of surface tracking
and the primary determinant of surface creepage requirements
in system level standards. Insulation wear out is the phenomenon
where charge injection or displacement currents inside the
insulation material cause long-term insulation degradation.
0.1
0.01
0.001
1k
10k
100k
1M
10M
100M
MAGNETIC FIELD FREQUENCY (Hz)
Surface Tracking
Figure 40. Maximum Allowable External Magnetic Flux Density
Surface tracking is addressed in electrical safety standards by
setting a minimum surface creepage based on the working voltage,
the environmental conditions, and the properties of the insulation
material. Safety agencies perform characterization testing on the
surface insulation of components that allows the components to be
categorized in different material groups. Lower material group
ratings are more resistant to surface tracking and, therefore, can
provide adequate lifetime with smaller creepage. The minimum
creepage for a given working voltage and material group is in each
system level standard and is based on the total rms voltage across
the isolation barrier, pollution degree, and material group. The
material group and creepage for ADN4650/ADN4651/ADN4652
are presented in Table 4.
For example, at a magnetic field frequency of 1 MHz, the maxi-
mum allowable magnetic field of 0.92 kgauss induces a voltage
of 0.125 V at the receiving coil. This voltage is about 50% of the
sensing threshold and does not cause a faulty output transition.
If such an event occurs with the worst case polarity during a
transmitted pulse, it reduces the received pulse from >0.5 V to
0.375 V. This voltage is still higher than the 0.25 V sensing
threshold of the decoder.
The preceding magnetic flux density values correspond to specific
current magnitudes at given distances from the ADN4650/
ADN4651/ADN4652 transformers. Figure 41 expresses these
allowable current magnitudes as a function of frequency for
selected distances. The ADN4650/ADN4651/ADN4652 are
very insensitive to external fields. Only extremely large, high
frequency currents, very close to the component, can potentially
be a concern. For the 1 MHz example noted, a 2.29 kA current must
be placed 5 mm from the ADN4650/ADN4651/ADN4652 to
affect component operation.
Insulation Wear Out
The lifetime of insulation caused by wear out is determined by
its thickness, material properties, and the voltage stress applied.
It is important to verify that the product lifetime is adequate at
the application working voltage. The working voltage supported
by an isolator for wear out may not be the same as the working
voltage supported for tracking. It is the working voltage applica-
ble to tracking that is specified in most standards.
10k
DISTANCE = 1m
1k
Testing and modeling show that the primary driver of long-term
degradation is displacement current in the polyimide insulation
causing incremental damage. The stress on the insulation can be
broken down into broad categories, such as dc stress, which causes
very little wear out because there is no displacement current,
and an ac component time varying voltage stress, which causes
wear out.
100
DISTANCE = 100mm
10
DISTANCE = 5mm
1
0.1
0.01
1k
10k
100k
1M
10M
100M
MAGNETIC FIELD FREQUENCY (Hz)
Figure 41. Maximum Allowable Current for Various Current to
ADN4650/ADN4651/ADN4652 Spacings
Rev. B | Page 20 of 24
Data Sheet
ADN4650/ADN4651/ADN4652
The ratings in certification documents are usually based on
60 Hz sinusoidal stress because this reflects isolation from line
voltage. However, many practical applications have combinations
of 60 Hz ac and dc across the isolation barrier, as shown in
Equation 1. Because only the ac portion of the stress causes
wear out, the equation can be rearranged to solve for the ac rms
voltage, as shown in Equation 2. For insulation wear out with the
polyimide materials used in this product, the ac rms voltage
determines the product lifetime.
The working voltage across the barrier from Equation 1 is
2
VRMS
VRMS
=
VAC RMS2 +VDC
=
2402 + 4002
VRMS = 466 V
This VRMS value is the working voltage used together with the
material group and pollution degree when looking up the
creepage required by a system standard.
2
(1)
To determine if the lifetime is adequate, obtain the time varying
portion of the working voltage. To obtain the ac rms voltage,
use Equation 2.
VRMS
=
VAC RMS2 +VDC
or
2
(2)
VAC RMS
=
VRMS2 −VDC
2
VAC RMS
VAC RMS
=
=
VRMS2 −VDC
where:
4662 − 4002
V
V
V
RMS is the total rms working voltage.
AC RMS is the time varying portion of the working voltage.
DC is the dc offset of the working voltage.
VAC RMS = 240 V rms
In this case, the ac rms voltage is simply the line voltage of
240 V rms. This calculation is more relevant when the waveform is
not sinusoidal. The value is compared to the limits for the working
voltage in Table 11 for the expected lifetime, less than a 60 Hz
sine wave, and it is well within the limit for a 50-year service life.
Calculation and Use of Parameters Example
The following example frequently arises in power conversion
applications. Assume that the line voltage on one side of the
isolation is 240 V ac rms and a 400 V dc bus voltage is present
on the other side of the isolation barrier. The isolator material is
polyimide. To establish the critical voltages in determining the
creepage, clearance, and lifetime of a device, see Figure 42 and
the following equations.
Note that the dc working voltage limit in Table 11 is set by the
creepage of the package as specified in IEC 60664-1. This value
can differ for specific system level standards.
V
AC RMS
V
V
V
DC
PEAK
RMS
TIME
Figure 42. Critical Voltage Example
Rev. B | Page 21 of 24
ADN4650/ADN4651/ADN4652
Data Sheet
APPLICATIONS INFORMATION
High speed LVDS interfaces can be isolated using the
ADN4650/ADN4651/ADN4652 either between components,
between boards, or at a cable interface. The ADN4650/ADN4651/
ADN4652 offer full LVDS compliant inputs and outputs, allowing
increased LVDS output drive strength compared to built-in reduced
specification LVDS interfaces on other components. The LVDS
compliant receiver inputs on the ADN4650/ADN4651/ADN4652
also ensure full compatibility with any LVDS source being
isolated.
Newer programmable logic controller (PLC) and input/output
modules communicate across an LVDS backplane, illustrating a
board to board LVDS interface, as shown in Figure 45. With a
daisy-chain type topology for transmit and receive to either
adjacent node, two ADN4651 (or ADN4652) devices on each
node can isolate four LVDS channels. The addition of galvanic
isolation allows a much more robust backplane interface port
on the PLC or input/output modules.
With galvanic isolation, even LVDS ports can be treated as full
external ports, and transmitted along cable runs (see Figure 46),
even in harsh environments where high common-mode voltages
may be induced on the cable. The low jitter of the
ADN4651/ADN4652 ensures that more of the jitter budget can
be used to account for the cable effects, allowing the cable to be
as long as possible. The ADN4651/ADN4652 offer a high drive
strength, fully LVDS compliant output, capable of driving short
cable runs of a few meters. This is in contrast to alternative
isolation methods that degrade the LVDS signal quality. The
data rate can be chosen as appropriate for the cable length; the
ADN4651/ADN4652 operate not only at 600 Mbps but also at
any arbitrary data rate down to dc.
Isolated analog front-end applications provide an example of
the ADN4650/ADN4651 isolating an LVDS interface between
components. As shown in Figure 43, two ADN4650 components
isolate the LVDS interface of the AD7960 analog-to-digital
converter (ADC), including 600 Mbps data, a 300 MHz echoed
clock, and a 5 MHz sample clock. Isolation of the AD7960 using
two ADN4651 components is shown in Figure 44. The ADN4651
additive phase jitter is sufficiently low that it does not affect the
ADC performance even when isolating the sample clock. In
addition, implementing the galvanic isolation improves ADC
performance by removing digital and power supply noise from
the field-programmable gate array (FPGA) circuit.
ADN4650
D±
D±
100Ω
100Ω
100Ω
100Ω
DCO±
DCO±
AD7960
FPGA/ASIC
100Ω
100Ω
CLK± 100Ω
CNV± 100Ω
CLK±
CNV±
ADN4650
Figure 43. Example Isolated Analog Front-End Implementation (Isolated AD7960 Using the ADN4650)
ADN4651
D±
D±
100Ω
100Ω
100Ω
100Ω
CLK±
CLK±
AD7960
FPGA/ASIC
DCO±
CNV±
100Ω
100Ω DCO±
100Ω
100Ω
CNV±
ADN4651
Figure 44. Example Isolated Analog Front-End Implementation (Isolated AD7960 Using the ADN4651)
Rev. B | Page 22 of 24
Data Sheet
ADN4650/ADN4651/ADN4652
MCU 1
MCU 2
MCU 3
100Ω
100Ω
100Ω
100Ω
100Ω
100Ω
100Ω
100Ω
100Ω
100Ω
100Ω
100Ω
ISOLATION
ISOLATION
ISOLATION
ISOLATION
ISOLATION
ISOLATION
100Ω
100Ω
100Ω
100Ω
100Ω
100Ω
MODULE 1
MODULE 2
MODULE 3
Figure 45. Example Isolated Backplane Implementation for PLCs and Input/Output Modules Using the ADN4651
SHIELDED
TWISTED PAIR
CABLE
ADN4651
ADN4651
100Ω
100Ω
FPGA/
ASIC
FPGA/
ASIC
100Ω
100Ω
Figure 46. Example Isolated LVDS Cable Application Using the ADN4651
Rev. B | Page 23 of 24
ADN4650/ADN4651/ADN4652
OUTLINE DIMENSIONS
Data Sheet
13.00 (0.5118)
12.60 (0.4961)
20
11
10
7.60 (0.2992)
7.40 (0.2913)
1
10.65 (0.4193)
10.00 (0.3937)
0.75 (0.0295)
0
.25 (0.0098)
45°
2.65 (0.1043)
2.35 (0.0925)
0.30 (0.0118)
0.10 (0.0039)
8°
0°
COPLANARITY
SEATING
PLANE
0.51 (0.0201)
0.31 (0.0122)
1.27 (0.0500)
0.40 (0.0157)
0.10
1.27
(0.0500)
BSC
0.33 (0.0130)
0.20 (0.0079)
COMPLIANT TO JEDEC STANDARDS MS-013-AC
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 47. 20-Lead Standard Small Outline Package [SOIC_W]
Wide Body (RW-20)
Dimensions shown in millimeters and (inches)
ORDERING GUIDE
Model1
ADN4650BRWZ
ADN4650BRWZ-RL7
ADN4651BRWZ
ADN4651BRWZ-RL7
ADN4652BRWZ
ADN4652BRWZ-RL7
EVAL-ADN4650EB1Z
EVAL-ADN4651EB1Z
EVAL-ADN4652EB1Z
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Package Description
Package Option
RW-20
RW-20
20-Lead Standard Small Outline Package [SOIC_W]
20-Lead Standard Small Outline Package [SOIC_W]
20-Lead Standard Small Outline Package [SOIC_W]
20-Lead Standard Small Outline Package [SOIC_W]
20-Lead Standard Small Outline Package [SOIC_W]
20-Lead Standard Small Outline Package [SOIC_W]
ADN4650 SOIC_W Evaluation Board
RW-20
RW-20
RW-20
RW-20
RW-20
RW-20
RW-20
ADN4651 SOIC_W Evaluation Board
ADN4652 SOIC_W Evaluation Board
1 Z = RoHS Compliant Part.
©2015–2016 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D13677-0-4/16(B)
Rev. B | Page 24 of 24
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