ADN4654BRWZ [ADI]
5 kV RMS and 3.75 kV RMS, Dual-Channel LVDS Gigabit Isolators;
| 型号： | ADN4654BRWZ |
| 厂家： | 
ADI |
| 描述： | 5 kV RMS and 3.75 kV RMS, Dual-Channel LVDS Gigabit Isolators |
| 文件： | 总25页 (文件大小：732K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
5 kV RMS and 3.75 kV RMS,
Dual-Channel LVDS Gigabit Isolators
Data Sheet
ADN4654/ADN4655/ADN4656
FEATURES
FUNCTIONAL BLOCK DIAGRAMS
V
V
IN1
IN2
5 kV rms and 3.75 kV rms LVDS isolators
Complies with TIA/EIA-644-A LVDS standard
Multiple dual-channel configurations
Any data rate up to 1.1 Gbps switching with low jitter
4 ns typical propagation delay
ADN4654
ISOLATION
BARRIER
LDO
LDO
V
D
V
DD2
DD1
D
D
IN1+
IN1–
OUT1+
OUT1–
D
2.6 ps rms typical random jitter, rms
LVDS
DIGITAL ISOLATOR
LVDS
90 ps typical peak-to-peak total jitter at 1.1 Gbps
2.5 V or 3.3 V supplies
D
D
D
D
IN2+
OUT2+
OUT2–
IN2–
−75 dBc power supply ripple rejection, phase spur level
Glitch immunity
GND
GND
2
1
8 kV IEC 61000-4-2 ESD protection across isolation barrier
High common-mode transient immunity: >25 kV/μs
Passes EN 55022 Class B radiated emissions limits with
1.1 Gbps PRBS
Safety and regulatory approvals (20-lead SOIC_W package)
UL (pending): 5000 V rms for 1 minute per UL 1577
CSA Component Acceptance Notice 5A (pending)
VDE certificate of conformity (pending)
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12
Figure 1.
V
V
IN2
IN1
ADN4655
ISOLATION
BARRIER
LDO
LDO
V
D
V
DD2
DD1
D
D
IN1+
IN1–
OUT1+
OUT1–
D
LVDS
DIGITAL ISOLATOR
LVDS
D
D
D
D
OUT2+
IN2+
IN2–
OUT2–
V
IORM = 424 VPEAK
Fail-safe output high for open, short, and terminated input
conditions (ADN4655/ADN4656)
GND
1
GND
2
Figure 2.
Operating temperature range: −40°C to +125°C
7.8 mm minimum creepage and clearance
V
V
IN1
IN2
ADN4656
ISOLATION
BARRIER
LDO
LDO
APPLICATIONS
V
V
DD1
DD2
Isolated video and imaging data
Analog front-end isolation
D
D
D
IN1+
OUT1+
D
OUT1–
IN1–
LVDS
DIGITAL ISOLATOR
LVDS
Data plane isolation
Isolated high speed clock and data links
D
D
D
OUT2+
IN2+
D
OUT2–
IN2–
GND
GND
2
1
Figure 3.
GENERAL DESCRIPTION
The ADN4654/ADN4655/ADN46561 are signal isolated, low
voltage differential signaling (LVDS) buffers that operate at up
to 1.1 Gbps with low jitter. The devices integrate Analog Devices,
Inc., iCoupler® technology, enhanced for high speed operation to
provide galvanic isolation of the TIA/EIA-644-A compliant LVDS
drivers and receivers. This integration allows drop-in isolation of
an LVDS signal chain.
the corresponding LVDS driver output when the inputs are
floating, shorted, or terminated but not driven.
For high speed operation with low jitter, the LVDS and isolator
circuits rely on a 2.5 V supply. An integrated on-chip low dropout
(LDO) regulator can provide the required 2.5 V from an external
3.3 V power supply. The devices are fully specified over a wide
industrial temperature range and come in a 20-lead, wide body
SOIC_W package with 5 kV rms isolation or in a 20-lead SSOP
package with 3.75 kV rms isolation.
The ADN4654/ADN4655/ADN4656 comprise multiple channel
configurations, and the LVDS receivers on the ADN4655 and
ADN4656 include a fail-safe mechanism to ensure a Logic 1 on
1 Protected by U.S. Patents 5,952,849; 6,873,065; 6,903,578; and 7,075,329. Other patents are pending.
Rev. C Document Feedback
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rightsof third parties that may result fromits use. Specifications subject to change without notice. No
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Tel: 781.329.4700 ©2018–2019 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
ADN4654/ADN4655/ADN4656
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
ESD Caution...................................................................................8
Pin Configurations and Function Descriptions............................9
Typical Performance Characteristics ........................................... 12
Test Circuits and Switching Characteristics................................ 17
Theory of Operation ...................................................................... 18
Truth Table and Fail-Safe Receiver .......................................... 18
Isolation ....................................................................................... 19
Applications Information .............................................................. 20
PCB Layout ................................................................................. 20
Application Examples ................................................................ 20
Magnetic Field Immunity.......................................................... 22
Insulation Lifetime..................................................................... 22
Outline Dimensions....................................................................... 24
Ordering Guide .......................................................................... 25
Applications....................................................................................... 1
Functional Block Diagrams............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Receiver Input Threshold Test Voltages .................................... 4
Timing Specifications .................................................................. 4
Insulation and Safety Related Specifications ............................ 5
Package Characteristics ............................................................... 6
Regulatory Information............................................................... 6
DIN V VDE V 0884-10 (VDE V 0884-10) Insulation
Characteristics (Pending)............................................................ 7
Recommended Operating Conditions ...................................... 7
Absolute Maximum Ratings............................................................ 8
Thermal Resistance ...................................................................... 8
REVISION HISTORY
6/2019—Rev. B to Rev. C
Added ADN4656................................................................Universal
Changes to Features Section............................................................ 1
Added Figure 3; Renumbered Sequentially .................................. 1
Added Note 1, Table 8...................................................................... 7
Added Figure 8 and Table 15; Renumbered Sequentially ......... 11
Changes to Magnetic Field Immunity Section ........................... 22
Changes to Ordering Guide .......................................................... 25
1/2019—Rev. 0 to Rev. A
Added ADN4655................................................................Universal
Added Figure 2; Renumbered Sequentially ...................................1
Changes to General Description Section .......................................1
Changes to Table 1.............................................................................3
Changes to Table 3.............................................................................4
Added Timing Diagram Section and Figure 3 ..............................5
Changes to Figure 5 Caption and Table 12 Title ...........................9
Added Figure 6 and Table 13; Renumbered Sequentially......... 10
Changes to Theory of Operation Section and Truth Table and
Fail Safe Receiver Section .............................................................. 17
Added Table 15 ............................................................................... 17
Moved Isolation Section ................................................................ 18
Moved PCB Layout Section .......................................................... 19
Changes to PCB Layout Section................................................... 19
Changes to Ordering Guide.......................................................... 23
3/2019—Rev. A to Rev. B
Changes to Title, Features Section, General Description Section,
and Figure 2....................................................................................... 1
Changes to Table 4............................................................................ 5
Added Table 5.................................................................................... 5
Changes to Table 7............................................................................ 6
Changes to Table 8 and Figure 4..................................................... 7
Changes to Table 10, Table 11, and Table 12................................. 8
Added Figure 44.............................................................................. 23
Changes to Ordering Guide .......................................................... 23
11/2018—Revision 0: Initial Version
Rev. C | Page 2 of 25
Data Sheet
ADN4654/ADN4655/ADN4656
SPECIFICATIONS
For all minimum and maximum specifications, VDD1 = VDD2 = 2.375 V to 2.625 V, TA = −40°C to +125°C, unless otherwise noted. For all
typical specifications, VDD1 = VDD2 = 2.5 V, TA = 25°C, unless otherwise noted.
Table 1.
Parameter
INPUTS (RECEIVERS)
Input Threshold
High
Symbol
Min
Typ
Max
Unit
Test Conditions/Comments
See Figure 38 and Table 2
VTH
VTL
100
mV
mV
Low
−100
Differential Input Voltage
Input Common-Mode Voltage
Input Current, High and Low
|VID|
VIC
IIH, IIL
100
0.5|VID|
−5
mV
V
µA
See Figure 38 and Table 2
See Figure 38 and Table 2
2.4 − 0.5|VID|
+5
DINx = VDDx or 0 V, other input = 1.2 V, VDDx
2.5 V or 0 V
=
Differential Input Capacitance1 CINx
2
pF
DINx = 0.4 sin(30 × 106πt) V + 0.5 V, other input =
1.2 V2
OUTPUTS (DRIVERS)
Differential Output Voltage
|VOD
|
250
310
450
50
mV
See Figure 36 and Figure 37, load resistance (RL) =
100 Ω
VOD Magnitude Change
Offset Voltage
VOS Magnitude Change
VOS, Peak to Peak1
|ΔVOD|
VOS
ΔVOS
VOS(PP)
IOS
mV
V
See Figure 36 and Figure 37, RL = 100 Ω
See Figure 36, RL = 100 Ω
See Figure 36, RL = 100 Ω
See Figure 36, RL = 100 Ω
DOUTx = 0 V
1.125
1.17 1.375
50
150
−20
12
mV
mV
mA
mA
pF
Output Short-Circuit Current
|VOD| = 0 V
Differential Output
Capacitance1
COUTx
5
DOUTx = 0.4 sin(30 × 106πt) V + 0.5 V, other input =
1.2 V, VDD1 or VDD2 = 0 V
POWER SUPPLY
Supply Current
IDD1, IIN1,
IDD2, or IIN2
ADN4655/ADN4656 only
ADN4654 only
55
mA
mA
mA
mA
V
No output load, inputs with 100 Ω, no applied |VID|
All outputs loaded, RL = 100 Ω, frequency = 0.55 GHz
No output load, inputs with 100 Ω, |VID| = 200 mV
All outputs loaded, RL = 100 Ω, frequency = 0.55 GHz
No external supply on VDD1 or VDD2
58
50
60
3.3
82
65
80
3.6
LDO Input Range
VIN1 or
VIN2
3.0
LDO Output Range
VDD1 or
VDD2
2.375
2.5
2.625
V
Power Supply Ripple Rejection, PSRR
Phase Spur Level
−75
dBc
Phase spur level on DOUTx with 0.55 GHz clock on
DINx and applied ripple of 100 kHz, 100 mV p-p on
a 2.5 V supply to VDD1 or VDD2
COMMON-MODE TRANSIENT
IMMUNITY3
|CM|
25
50
kV/µs Common-mode voltage (VCM) = 1000 V, transient
magnitude = 800 V
1 These specifications are guaranteed by design and characterization.
2 t denotes time.
3 |CM| is the maximum common-mode voltage slew rate that can be sustained while maintaining any DOUTx+/DOUTx− pin in the same state as the corresponding DINx+/DINx−
pin (no change in output), or producing the expected transition on any DOUTx+/DOUTx− pin if the applied common-mode transient edge is coincident with a data
transition on the corresponding DINx+/DINx− pin. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges.
Rev. C | Page 3 of 25
ADN4654/ADN4655/ADN4656
Data Sheet
RECEIVER INPUT THRESHOLD TEST VOLTAGES
Table 2. Test Voltages for Receiver Operation
Applied Voltages
DINx+ (V)
1.25
1.15
2.4
2.3
0.1
DINx− (V)
1.15
1.25
2.3
2.4
0
Input Voltage, Differential, VID (V) Input Voltage, Common-Mode, VIC (V)
Driver Output, Differential VOD (mV)
0.1
1.2
>250
<−250
>250
<−250
>250
<−250
>250
−0.1
0.1
−0.1
0.1
−0.1
0.6
+1.2
2.35
+2.35
0.05
+0.05
1.2
0
1.5
0.1
0.9
0.9
2.4
1.5
1.8
−0.6
0.6
+1.2
2.1
<−250
>250
1.8
0.6
2.4
0
−0.6
0.6
+2.1
0.3
<−250
>250
0
0.6
−0.6
+0.3
<−250
TIMING SPECIFICATIONS
For all minimum and maximum specifications, VDD1 = VDD2 = 2.375 V to 2.625 V, TA = TMIN to TMAX, unless otherwise noted. All typical
specifications, VDD1 = VDD2 = 2.5 V, T A = 25°C, unless otherwise noted.
Table 3.
Parameter
Symbol
Min Typ Max1 Unit
Test Conditions/Comments
PROPAGATION DELAY
tPLH, tPHL
4
4.5
ns
See Figure 39, from any DINx+/DINx− to DOUTx+/DOUTx−
See Figure 39, across all DOUTx+/DOUTx−
SKEW
Duty Cycle2
Channel to Channel3
tSK(D)
tSK(CH)
100
ps
ps
ps
ps
ps
150 300
200 500
500
ADN4654 only
ADN4655 and ADN4656 only
ADN4654 to ADN4654 only
ADN4654, ADN4655, ADN4656, or combinations
See Figure 39, for any DOUTx+/DOUTx−
Part to Part4
tSK(PP)
600
JITTER5
Random Jitter, RMS6 (1σ)
Deterministic Jitter, Peak to tDJ(PP)
Peak7, 8
With Crosstalk
tRJ(RMS)
2.6
50
4.8
116
ps rms 0.55 GHz clock input
ps
1.1 Gbps, 223 − 1 pseudorandom bit stream (PRBS)
tDJC(PP)
tTJ(PP)
50
90
ps
ps
1.1 Gbps, 223 − 1 PRBS
0.55 GHz, 1.1 Gbps, 223 − 1 PRBS9
Total Jitter at Bit Error Rate
(BER) 1 × 10−12
171
Additive Phase Jitter
tADDJ
387
288
fs rms
fs rms
ps
100 Hz to 100 kHz, output frequency (fOUT) = 10 MHz10
12 kHz to 20 MHz, fOUT = 0.55 GHz11
RISE AND FALL TIME
FAIL-SAFE DELAY12
tR, tF
350
1.2
See Figure 39, any DOUTx+/DOUTx−, 20% to 80%, RL = 100 Ω, load
capacitance (CL) = 5 pF
ADN4655 and ADN4656 only; see Figure 39 and Figure 4,
any DOUTx+/DOUTx−, RL = 100 Ω
tFSH, tFSL
1
µs
MAXIMUM DATA RATE
1.1
1.25
Gbps
1 These specifications are guaranteed by design and characterization.
2 Duty cycle or pulse skew is the magnitude of the maximum difference between tPLH and tPHL for any channel of a device, that is, |tPLHx – tPHLx|, where x denotes either
Channel 1 or Channel 2 propagation delay.
3 Channel to channel or output skew is the difference between the largest and smallest values of tPLHx within a device or the difference between the largest and smallest
values of tPHLx within a device, whichever of the two is greater.
4 Part to part output skew is the difference between the largest and smallest values of tPLHx across multiple devices or the difference between the largest and smallest
values of tPHLx across multiple devices, whichever of the two is greater.
5 Jitter parameters are guaranteed by design and characterization. Values do not include stimulus jitter. VID = 400 mV p-p, tR = tF = 0.3 ns (20% to 80%).
6 This specification is measured over a population of ~7,000,000 edges.
7 Peak-to-peak jitter specifications include jitter due to pulse skew (tSK(D)).
8 This specification is measured over a population of ~3,000,000 edges.
9 Using the formula: tTJ(PP) = 14 × tRJ(RMS) + tDJ(PP)
.
10 With input phase jitter of 250 fs rms subtracted.
11 With input phase jitter of 100 fs rms subtracted.
12 The fail-safe delay is the delay before DOUTx is switched high to reflect an idle input to DINx (|VID| < 100 mV, with open, short, or terminated input condition).
Rev. C | Page 4 of 25
Data Sheet
ADN4654/ADN4655/ADN4656
Timing Diagram
>1.3V
1.2V
D
INx+
(D
= 1.2V)
INx–
<1.1V
+0.1V
V
0V
ID
–0.1V
D
OUTx+
OUTx–
~1.3V
D
~1.0V
~ +0.3V
+0.1V
+0.1V
V
0V
OD
~ –0.3V
tFSH
tFSL
Figure 4. Fail-Safe Timing Diagram
INSULATION AND SAFETY RELATED SPECIFICATIONS
For additional information, see www.analog.com/icouplersafety.
Table 4. 20-Lead SOIC_W Package
Parameter
Symbol Value Unit
Test Conditions/Comments
Rated Dielectric Insulation Voltage
Minimum External Air Gap (Clearance)
5
7.8
kV rms
1 minute duration
L (I01)
L (I02)
L (PCB)
mm min Measured from input terminals to output terminals,
shortest distance through air
mm min Measured from input terminals to output terminals,
shortest distance path along body
mm min Measured from input terminals to output terminals,
shortest distance through air, line of sight, in the PCB
mounting plane
Minimum External Tracking (Creepage)
7.8
8.1
Minimum Clearance in the Plane of the Printed
Circuit Board (PCB Clearance)
Minimum Internal Gap (Internal Clearance)
Tracking Resistance (Comparative Tracking Index)
Material Group
22
>400
II
µm min
V
Insulation distance through insulation
DIN IEC 112/VDE 0303 Part 1
Material Group (DIN VDE 0110, 1/89, Table 1)
CTI
Table 5. 20-Lead SSOP Package
Parameter
Symbol Value Unit
Test Conditions/Comments
Rated Dielectric Insulation
Voltage
3.75
kV rms
1 minute duration
Minimum Clearance
Minimum Creepage
Minimum PCB Clearance
L (I01)
L (I02)
L (PCB)
5.3
mm min
mm min
mm min
Measured from input terminals to output terminals, shortest distance
through air
Measured from input terminals to output terminals, shortest distance path
along body
Measured from input terminals to output terminals, shortest distance
through air, line of sight, in the PCB mounting plane
5.3
5.6
Minimum Internal Clearance
Comparative Tracking Index
Material Group
22
>400
II
µm min
V
Insulation distance through insulation
DIN IEC 112/VDE 0303 Part 1
Material Group (DIN VDE 0110, 1/89, Table 1)
CTI
Rev. C | Page 5 of 25
ADN4654/ADN4655/ADN4656
Data Sheet
PACKAGE CHARACTERISTICS
Table 6.
Parameter
Symbol Min Typ Max Unit Test Conditions/Comments
Resistance (Input to Output)1
Capacitance (Input to Output)1
Input Capacitance2
RI-O
1013
Ω
CI-O
CI
2.2
3.7
pF
pF
Frequency = 1 MHz
1 The device is considered a 2-terminal device: Pin 1 through Pin 10 are shorted together, and Pin 11 through Pin 20 are shorted together.
2 Input capacitance is from any input data pin to ground.
REGULATORY INFORMATION
See Table 12 and the Insulation Lifetime section for details regarding recommended maximum working voltages for specific cross-
isolation waveforms and insulation levels.
Table 7.
UL (Pending)
CSA (Pending)
VDE (Pending)
To Be Recognized Under UL 1577
To be approved under CSA
To be certified according to DIN V VDE V 0884-10
(VDE V 0884-10):2006-122
Reinforced insulation, VIORM = 424 VPEAK, VIOSM = 8000 VPEAK
File 2471900-4880-0001
Component Recognition Program1 Component Acceptance Notice 5A
Single Protection, Isolation Voltage
20-Lead SOIC, 5000 V rms
20-Lead SSOP, 3750 V rms
File E214100
File 205078
1 In accordance with UL 1577, each ADN4654/ADN4655/ADN4656 is proof tested by applying an insulation test voltage ≥ 6000 V rms (20-lead SOIC_W) or ≥ 4500 V rms (20-lead
SSOP) for 1 sec.
2 In accordance with DIN V VDE V 0884-10, each ADN4654/ADN4655/ADN4656 is proof tested by applying an insulation test voltage ≥ 795 VPEAK for 1 sec (partial discharge
detection limit = 5 pC).
Rev. C | Page 6 of 25
Data Sheet
ADN4654/ADN4655/ADN4656
DIN V VDE V 0884-10 (VDE V 0884-10) INSULATION CHARACTERISTICS (PENDING)
This isolator is suitable for reinforced electrical isolation only within the safety limit data. Protective circuits ensure the maintenance of
the safety data.
Table 8.
Description
Test Conditions/Comments1
Symbol Characteristic Unit
Installation Classification per DIN VDE 0110
For Rated Mains Voltage ≤ 150 V rms
For Rated Mains Voltage ≤ 300 V rms
For Rated Mains Voltage ≤ 600 V rms
Climatic Classification
Pollution Degree per DIN VDE 0110, Table 1
Maximum Working Insulation Voltage
Input to Output Test Voltage, Method B1
I to IV
I to IV
I to III
40/125/21
2
VIORM
VPD (M)
424
795
VPEAK
VPEAK
VIORM × 1.875 = VPD (M), 100% production test,
tINI = tM = 1 sec, partial discharge < 5 pC
Input to Output Test Voltage, Method A
After Environmental Tests Subgroup 1
VPD (M)
VIORM × 1.5 = VPD (M), tINI = 60 sec, tM = 10 sec,
partial discharge < 5 pC
VIORM × 1.2 = VPD (M), tINI = 60 sec, tM = 10 sec,
partial discharge < 5 pC
636
VPEAK
VPEAK
VPEAK
After Input or Safety Test Subgroup 2 and
Subgroup 3
Highest Allowable Overvoltage
Surge Isolation Voltage
Basic
509
VIOTM
7000
VPEAK = 12.8 kV, 1.2 μs rise time, 50 μs, 50% fall time
VPEAK = 12.8 kV, 1.2 μs rise time, 50 μs, 50% fall time
VIOSM
VIOSM
10,000
8000
VPEAK
VPEAK
Reinforced
Safety Limiting Values
Maximum value allowed in the event of a failure
(see Figure 5)
Maximum Junction Temperature
Total Power Dissipation at 25°C
20-Lead SOIC
20-Lead SSOP
Insulation Resistance at TS
TS
PS
150
°C
2.78
1.8
>109
W
W
Ω
VIO = 500 V
RS
1 For information about tM, tINI, and VIO, see DIN V VDE V 0884-10.
3.0
RECOMMENDED OPERATING CONDITIONS
20-LEAD SOIC
2.5
Table 9.
Parameter
Symbol
Rating
2.0
Operating Temperature
Supply Voltages
TA
−40°C to +125°C
20-LEAD SSOP
1.5
1.0
0.5
0
Supply to LDO Regulator
LDO Bypass, VINx Shorted to VDDx VDD1, VDD2 2.375 V to 2.625 V
VIN1, VIN2
3.0 V to 3.6 V
0
50
100
150
200
AMBIENT TEMPERATURE (°C)
Figure 5. Thermal Derating Curve, Dependence of Safety Limiting Values
with Ambient Temperature per DIN V VDE V 0884-10
Rev. C | Page 7 of 25
ADN4654/ADN4655/ADN4656
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 10.
THERMAL RESISTANCE
Thermal performance is directly linked to PCB design and
operation environment. Close attention to PCB thermal design
is required.
Parameter
Rating
VIN1 to GND1/VIN2 to GND2
VDD1 to GND1/VDD2 to GND2
Input Voltage (DINx+, DINx−) to GNDx on
the Same Side
−0.3 V to +6.5 V
−0.3 V to +2.8 V
−0.3 V to VDD + 0.3 V
θ
JA is the natural convection junction to ambient thermal
resistance measured in a one-cubic foot sealed enclosure.
Output Voltage (DOUTx+, DOUTx−) to
GNDx on the Same Side
Short-Circuit Duration (DOUTx+, DOUTx−
−0.3 V to VDD + 0.3 V
Continuous
Table 11. Thermal Resistance
Package Type1
RW-20
θJA
Unit
°C/W
°C/W
)
to GNDx on the Same Side
45.7
69.6
Operating Temperature Range
Storage Temperature Range
Junction Temperature (TJ Maximum)
Power Dissipation
−40°C to +125°C
−65°C to +150°C
150°C
RS-20
1 Test Condition 1: thermal impedance simulated with 4-layer standard JEDEC PCB.
ESD CAUTION
(TJ maximum − TA)/θJA
Electrostatic Discharge (ESD)
Human Body Model (All Pins to
Respective GNDx, 1.5 kΩ, 100 pF)
4 kV
IEC 61000-4-2 (LVDS Pins to Isolated
GNDx Across Isolation Barrier)
20-Lead SOIC
20-Lead SSOP
8 kV
7 kV
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Table 12. Maximum Continuous Working Voltage1
Rating
Parameter
RW-20
RS-20
Constraint
AC Voltage
Bipolar Waveform
Basic Insulation
Reinforced Insulation
Unipolar Waveform
Basic Insulation
Reinforced Insulation
DC Voltage
424 VPEAK
424 VPEAK
424 V PEAK
424 V PEAK
50-year minimum insulation lifetime for 1% failure
50-year minimum insulation lifetime for 1% failure
848 VPEAK
875 VPEAK
848 V PEAK
620 V PEAK
50-year minimum insulation lifetime for 1% failure
Lifetime limited by package creepage, maximum approved working voltage
Basic Insulation
Reinforced Insulation
1079 VPEAK
536 VPEAK
754 V PEAK
380 V PEAK
Lifetime limited by package creepage, maximum approved working voltage
Lifetime limited by package creepage, maximum approved working voltage
1 The maximum continuous working voltage refers to the continuous voltage magnitude imposed across the isolation barrier. See the Insulation Lifetime section for
more details.
Rev. C | Page 8 of 25
Data Sheet
ADN4654/ADN4655/ADN4656
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
V
1
2
3
4
5
6
7
8
9
20
V
IN1
IN2
GND
19 GND
1
2
V
18
V
DD2
DD1
GND
17 GND
1
IN1+
IN1–
IN2+
IN2–
2
ADN4654
D
D
D
D
16
15
14
13
12
D
D
D
D
OUT1+
OUT1–
OUT2+
OUT2–
DD2
TOP VIEW
(Not to Scale)
V
V
DD1
GND 10
11 GND
1
2
Figure 6. ADN4654 Pin Configuration
Table 13. ADN4654 Pin Function Descriptions
Pin No.
Mnemonic Description
1
VIN1
Optional 3.3 V Power Supply and LDO Input for Side 1. Bypass VIN1 to GND1 using a 1 μF capacitor. Alternatively, if using
a 2.5 V supply, connect VIN1 directly to VDD1
.
2, 4, 10
3, 9
GND1
VDD1
Ground, Side 1.
2.5 V Power Supply for Side 1. Connect both pins externally and bypass to GND1 with 0.1 μF capacitors. If supplying
3.3 V to VIN1, connect a 1 μF capacitor between Pin 3 and GND1 for proper regulation of the 2.5 V output of the
internal LDO regulator.
5
6
7
8
DIN1+
DIN1−
DIN2+
DIN2−
GND2
VDD2
Noninverted Differential Input 1.
Inverted Differential Input 1.
Noninverted Differential Input 2.
Inverted Differential Input 2.
Ground, Side 2.
2.5 V Power Supply for Side 2. Connect both pins externally and bypass to GND2 with 0.1 μF capacitors. If supplying
3.3 V to VIN2, connect a 1 µF capacitor between Pin 18 and GND2 for proper regulation of the 2.5 V output of the
internal LDO regulator.
11, 17, 19
12, 18
13
14
15
16
20
DOUT2−
DOUT2+
DOUT1−
DOUT1+
VIN2
Inverted Differential Output 2.
Noninverted Differential Output 2.
Inverted Differential Output 1.
Noninverted Differential Output 1.
Optional 3.3 V Power Supply and LDO Input for Side 2. Bypass VIN2 to GND2 using a 1 μF capacitor. Alternatively, if using
a 2.5 V supply, connect VIN2 directly to VDD2
.
Rev. C | Page 9 of 25
ADN4654/ADN4655/ADN4656
Data Sheet
V
1
2
3
4
5
6
7
8
9
20
V
IN2
IN1
GND
19 GND
1
2
V
18 V
DD2
DD1
GND
17 GND
1
IN1+
IN1–
2
OUT1+
OUT1–
IN2+
ADN4655
D
D
16
15
14
13
12
D
D
D
D
TOP VIEW
(Not to Scale)
D
D
OUT2+
OUT2–
IN2–
V
V
DD2
DD1
GND 10
11 GND
1
2
Figure 7. ADN4655 Pin Configuration
Table 14. ADN4655 Pin Function Descriptions
Pin No.
Mnemonic Description
1
VIN1
Optional 3.3 V Power Supply and LDO Input for Side 1. Bypass VIN1 to GND1 using a 1 μF capacitor. Alternatively, if using
a 2.5 V supply, connect VIN1 directly to VDD1
.
2, 4, 10
3, 9
GND1
VDD1
Ground, Side 1.
2.5 V Power Supply for Side 1. Connect both pins externally and bypass to GND1 with 0.1 μF capacitors. If supplying
3.3 V to VIN1, connect a 1 μF capacitor between Pin 3 and GND1 for proper regulation of the 2.5 V output of the
internal LDO regulator.
5
6
7
8
DIN1+
DIN1−
DOUT2+
DOUT2−
Noninverted Differential Input 1.
Inverted Differential Input 1.
Noninverted Differential Output 2.
Inverted Differential Output 2.
Ground, Side 2.
11, 17, 19 GND2
12, 18
VDD2
2.5 V Power Supply for Side 2. Connect both pins externally and bypass to GND2 with 0.1 μF capacitors. If supplying
3.3 V to VIN2, connect a 1 μF capacitor between Pin 18 and GND2 for proper regulation of the 2.5 V output of the
internal LDO regulator.
13
14
15
16
20
DIN2−
DIN2+
DOUT1−
DOUT1+
VIN2
Inverted Differential Input 2.
Noninverted Differential Input 2.
Inverted Differential Output 1.
Noninverted Differential Output 1.
Optional 3.3 V Power Supply and LDO Input for Side 2. Bypass VIN2 to GND2 using a 1 μF capacitor. Alternatively, if using
a 2.5 V supply, connect VIN2 directly to VDD2
.
Rev. C | Page 10 of 25
Data Sheet
ADN4654/ADN4655/ADN4656
V
1
2
3
4
5
6
7
8
9
20
V
IN2
IN1
GND
19 GND
1
2
2
V
18
V
DD2
DD1
GND
17 GND
1
ADN4656
TOP VIEW
(Not to Scale)
D
D
16
15
14
13
12
D
D
D
D
OUT1+
OUT1–
IN1+
IN1–
D
D
IN2+
OUT2+
OUT2–
DD2
IN2–
V
V
DD1
GND 10
11 GND
1
2
Figure 8. ADN4656 Pin Configuration
Table 15. ADN4656 Pin Function Descriptions
Pin No.
Mnemonic Description
1
VIN1
Optional 3.3 V Power Supply and LDO Input for Side 1. Bypass VIN1 to GND1 using a 1 μF capacitor. Alternatively, if using
a 2.5 V supply, connect VIN1 directly to VDD1
.
2, 4, 10
3, 9
GND1
VDD1
Ground, Side 1.
2.5 V Power Supply for Side 1. Connect both pins externally and bypass to GND1 with 0.1 μF capacitors. If supplying
3.3 V to VIN1, connect a 1 μF capacitor between Pin 3 and GND1 for proper regulation of the 2.5 V output of the
internal LDO regulator.
5
6
7
8
DOUT1+
DOUT1−
DIN2+
Noninverted Differential Output 1.
Inverted Differential Output 1.
Noninverted Differential Input 2.
Inverted Differential Input 2.
Ground, Side 2.
DIN2−
11, 17, 19 GND2
12, 18
VDD2
2.5 V Power Supply for Side 2. Connect both pins externally and bypass to GND2 with 0.1 μF capacitors. If supplying
3.3 V to VIN2, connect a 1 μF capacitor between Pin 18 and GND2 for proper regulation of the 2.5 V output of the
internal LDO regulator.
13
14
15
16
20
DOUT2−
DOUT2+
DIN1−
DIN1+
VIN2
Inverted Differential Output 2.
Noninverted Differential Output 2.
Inverted Differential Input 1.
Noninverted Differential Input 1.
Optional 3.3 V Power Supply and LDO Input for Side 2. Bypass VIN2 to GND2 using a 1 μF capacitor. Alternatively, if using
a 2.5 V supply, connect VIN2 directly to VDD2
.
Rev. C | Page 11 of 25
ADN4654/ADN4655/ADN4656
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
VDD1 = VDD2 = 2.5 V, T A = 25°C, RL = 100 Ω, 0.55 GHz input with |VID| = 200 mV, and VIC = 1.1 V for ADN4654, unless otherwise noted.
70
60
50
40
30
20
10
0
90
80
70
60
50
40
30
20
10
0
I
I
I
I
I
I
I
I
DD1
DD2
IN1
DD1
DD2
IN1
IN2
IN2
0
50 100 150 200 250 300 350 400 450 500 550
INPUT CLOCK FREQUENCY (MHz)
–50
–25
0
25
50
75
100
125
AMBIENT TEMPERATURE (°C)
Figure 9. Supply Current vs. Input Clock Frequency
(DIN1 Switching, DIN2 Not Switching)
Figure 12. Supply Current vs. Ambient Temperature
(DIN1 and DIN2 with 550 MHz Clock Inputs)
70
60
50
40
30
20
10
0
80
70
60
50
40
30
20
10
0
I
I
I
I
(D
(D
(D
(D
ACTIVE)
ACTIVE)
ACTIVE)
ACTIVE)
I
IN1
IN2
IN1
IN2
IN1±
IN1±
IN2±
IN2±
DD1
DD2
IN1
IN2
I
I
I
3.00
3.15
3.30
3.45
(V)
3.60
0
50 100 150 200 250 300 350 400 450 500 550
INPUT CLOCK FREQUENCY (MHz)
SUPPLY VOLTAGE, V /V
IN1 IN2
Figure 10. Supply Current vs. Input Clock Frequency
(DIN1 and DIN2 Switching)
Figure 13. Supply Current vs. Supply Voltage, VIN1/VIN2
70
60
50
40
30
20
10
0
70
60
50
40
30
20
10
0
I
I
I
I
DD1
DD2
IN1
I
I
I
I
(D
(D
(D
(D
ACTIVE)
ACTIVE)
ACTIVE)
ACTIVE)
DD1
DD2
DD1
DD2
IN1±
IN1±
IN2±
IN2±
IN2
–50
–25
0
25
50
75
100
125
2.35
2.50
SUPPLY VOLTAGE, V
2.65
AMBIENT TEMPERATURE (°C)
/V
(V)
DD1 DD2
Figure 11. Supply Current vs. Ambient Temperature
(DIN1 with 550 MHz Clock Input, DIN2 Not Switching)
Figure 14. Supply Current vs. Supply Voltage, VDD1/VDD2
Rev. C | Page 12 of 25
Data Sheet
ADN4654/ADN4655/ADN4656
2.65
2.60
2.55
2.50
2.45
2.40
2.35
1.60
1.55
1.50
1.45
1.40
1.35
1.30
1.25
V
V
V
V
CHANNEL 1
CHANNEL 2
DD1
DD2
OH
OH
3.0
3.1
3.2
3.3
3.4
3.5
3.6
2.35
2.40
2.45
2.50
2.55
/V
2.60
2.65
LDO INPUT VOLTAGE, V /V
(V)
SUPPLY VOLTAGE, V
(V)
IN1 IN2
DD1 DD2
Figure 15. LDO Output Voltage, VDD1/VDD2 vs. LDO Input Voltage, VIN1/VIN2
Figure 18. Driver Output High Voltage, VOH vs. Supply Voltage, VDD1/VDD2
1.25
1.20
1.15
1.10
1.05
1.00
0.95
350
340
330
320
310
300
290
280
270
V
V
CHANNEL 1
CHANNEL 2
V
V
CHANNEL 1
CHANNEL 2
260
250
OD
OD
OL
OL
0.90
2.35
0
50 100 150 200 250 300 350 400 450 500 550
INPUT CLOCK FREQUENCY (MHz)
2.40
2.45
2.50
2.55
2.60
2.65
SUPPLY VOLTAGE, V
/V
(V)
DD1 DD2
Figure 19. Driver Output Low Voltage, VOL vs. Supply Voltage, VDD1/VDD2
Figure 16. Driver Differential Output Voltage vs. Input Clock Frequency
1.375
450
400
350
300
250
200
150
100
1.325
1.275
1.225
1.175
V
V
CHANNEL 1
CHANNEL 2
OS
OS
50
0
V
V
CHANNEL 1
CHANNEL 2
OD
OD
1.125
2.35
2.40
2.45
2.50
2.55
/V
2.60
2.65
50
75
100
OUTPUT LOAD, R (Ω)
125
150
SUPPLY VOLTAGE, V
(V)
DD1 DD2
L
Figure 20. Driver Output Offset Voltage, VOS vs. Supply Voltage, VDD1/VDD2
Figure 17. Driver Differential Output Voltage, VOD vs. Output Load, RL
Rev. C | Page 13 of 25
ADN4654/ADN4655/ADN4656
Data Sheet
3.60
3.60
3.55
3.50
3.45
3.40
3.35
3.30
tPHL CHANNEL 2
tPHL CHANNEL 2
tPLH CHANNEL 2
tPHL CHANNEL 1
tPLH CHANNEL 1
tPLH CHANNEL 2
tPHL CHANNEL 1
tPLH CHANNEL 1
3.55
3.50
3.45
3.40
3.35
3.30
2.35
2.40
2.45
2.50
2.55
2.60
2.65
0
0.5
1.0
1.5
2.0
2.5
SUPPLY VOLTAGE, V
AND V
(V)
RECEIVER INPUT OFFSET VOLTAGE, V (V)
DD1
DD2
IC
Figure 21. Differential Propagation Delay vs. Supply Voltage, VDD1 and VDD2
Figure 24. Differential Propagation Delay vs. Receiver Input Offset Voltage, VIC
4.0
3.9
3.8
3.7
3.6
3.5
3.4
3.3
240
tF CHANNEL 2
tR CHANNEL 2
tF CHANNEL 1
tR CHANNEL 1
220
200
180
160
140
120
tPHL CHANNEL 2
tPLH CHANNEL 2
tPHL CHANNEL 1
tPLH CHANNEL 1
3.2
3.1
3.0
–50
–25
0
25
50
75
100
125
2.35
2.40
2.45
2.50
2.55
/V
2.60
2.65
AMBIENT TEMPERATURE (°C)
SUPPLY VOLTAGE, V
(V)
DD1 DD2
Figure 25. Differential Output Transition Time vs. Supply Voltage, VDD1/VDD2
Figure 22. Differential Propagation Delay vs. Ambient Temperature
240
220
200
180
3.60
3.55
3.50
3.45
160
3.40
tF CHANNEL 2
tR CHANNEL 2
tF CHANNEL 1
tR CHANNEL 1
tPHL CHANNEL 2
tPLH CHANNEL 2
tPHL CHANNEL 1
140
3.35
tPLH CHANNEL 1
1.0 1.2
DIFFERENTIAL INPUT VOLTAGE, V (V)
120
–50
3.30
–25
0
25
50
75 100 125
0
0.2
0.4
0.6
0.8
1.4
AMBIENT TEMPERATURE (°C)
ID
Figure 23. Differential Propagation Delay vs. Differential Input Voltage, VID
Figure 26. Differential Output Transition Time vs. Ambient Temperature
Rev. C | Page 14 of 25
Data Sheet
ADN4654/ADN4655/ADN4656
30
25
20
15
10
5
90
80
70
60
50
40
30
20
10
0
tSK(D) CHANNEL 2
tSK(D) CHANNEL 1
CHANNEL 1
CHANNEL 2
0
2.35
2.35
2.40
2.45
2.50
2.55
2.60
2.65
2.40
2.45
2.50
2.55
AND V
2.60
(V)
DD2
2.65
SUPPLY VOLTAGE, V
SUPPLY VOLTAGE, V
/V
(V)
DD1
DD1 DD2
Figure 30. Deterministic Jitter vs. Supply Voltage, VDD1/VDD2
Figure 27. Duty Cycle Skew, tSK(D) vs. Supply Voltage, VDD1 and VDD2
30
25
20
15
10
5
90
CHANNEL 1
CHANNEL 2
80
70
60
50
40
30
20
10
0
tSK(D) CHANNEL 2
tSK(D) CHANNEL 1
75 100 125
AMBIENT TEMPERATURE (°C)
0
–50
-40 -25 -10
5
20
35
50
65
80
95 110 125
–25
0
25
50
AMBIENT TEMPERATURE (°C)
Figure 31. Deterministic Jitter vs. Ambient Temperature
Figure 28. Duty Cycle Skew, tSK(D) vs. Ambient Temperature
90
80
70
60
50
40
30
20
10
0
CHANNEL 1
CHANNEL 2
200k
180k
160k
140k
120k
100k
80k
60k
40k
20k
0
0
200
400
600
800
1000
1200
–80
–60
–40
–20
0
20
40
60
TIME (ps)
DATA RATE (Mbps)
Figure 29. Deterministic Jitter vs. Data Rate
Figure 32. Time Interval Error (TIE) Histogram for DOUT1 at 550 MHz
Rev. C | Page 15 of 25
ADN4654/ADN4655/ADN4656
Data Sheet
CH1 50mV CH2 50mV
300ps/DIV
CH1 50mV CH2 50mV
300ps/DIV
DELAY 61.0828ns
DELAY 61.0828ns
Figure 33. Eye Diagram for DOUT1 at 300 MHz
Figure 35. Eye Diagram for DOUT2 at 300 MHz
400
300
200
100
0
–100
–200
–300
–400
–600
–400
–200
0
200
400
600
TIME (ps)
Figure 34. Eye Diagram for DOUT1 at 550 MHz
Rev. C | Page 16 of 25
Data Sheet
ADN4654/ADN4655/ADN4656
TEST CIRCUITS AND SWITCHING CHARACTERISTICS
D
D
D
INx+
OUTx+
R
V
V
OD
ID
V
V
OUT+
IN+
D
D
D
D
INx+
OUTx+
D
R /2
D
D
OUTx–
L
INx–
V
V
OUT–
IN–
R
V
V
OD
V
V
OS
R /2
L
NOTES
1. V = V
INx–
OUTx–
– V
ID
IN+
IN–
2. V = (V
+ V )/2
IC
IN+
IN–
3. V
= V
– V
OD
OUT+ OUT–
4. V = (V
+ V
)/2
OS
OUT+
OUT–
Figure 36. Driver Test Circuit
Figure 38. Voltage Definitions
D
D
C
L
D
D
D
D
INx+
OUTx+
D
INx+
OUTx+
3.75kΩ
R
L
V
TEST
V
SIGNAL
R
R
D
R
L
GENERATOR
V
V
OD
3.75kΩ
D
C
L
50Ω
50Ω
INx–
D
OUTx–
INx–
OUTx–
NOTES
NOTES
1. V
= 0V TO 2.4V
1. C INCLUDES PROBE AND JIG CAPACITANCE.
TEST
L
Figure 37. Driver Test Circuit (Full Load Across Common-Mode Range)
Figure 39. Timing Test Circuit
Rev. C | Page 17 of 25
ADN4654/ADN4655/ADN4656
Data Sheet
THEORY OF OPERATION
The ADN4654/ADN4655/ADN4656 are TIA/EIA-644-A LVDS
compliant isolated buffers. LVDS signals applied to the inputs are
transmitted on the outputs of the buffer, and galvanic isolation
is integrated between the two sides of the device. This integration
allows drop-in isolation of the LVDS signal chains.
can detect either state), as shown in Table 16 for the ADN4654. The
ADN4655/ADN4656 incorporates a fail-safe circuit to ensure
that the LVDS outputs are in a known state (logic high) when
the input state is undefined (−100 mV < VID < +100 mV), as
shown in Table 17.
The LVDS receiver detects the differential voltage present across
a termination resistor on an LVDS input. An integrated digital
isolator transmits the input state across the isolation barrier,
and an LVDS driver outputs the same state as the input.
This input state occurs when the inputs are floating (unconnected
with no termination resistor), shorted, or when there is no
active driver connected to the inputs with a termination resistor
present. Open-circuit, short-circuit, and terminated or idle bus
fail-safes, respectively, ensure a known output state for these
conditions, as implemented by the ADN4655/ADN4656.
When there is a positive differential voltage of ≥100 mV across
any DINx pin, the corresponding DOUTx+ pin sources current.
This current flows across the connected transmission line and
termination at the receiver at the far end of the bus, while
DOUTx− sinks the return current. When there is a negative
differential voltage of ≤−100 mV across any DINx pin, the
corresponding DOUTx+ pin sinks current and the DOUTx− pin
sources current. Table 16 and Table 17 show these input and
output combinations.
After these input states (−100 mV < VID < +100 mV) trigger
the fail-safe circuit, there is a delay of up to 1.2 µs before the
output is guaranteed to be high (VOD ≥ 250 mV). During this
time, the output may transition to, or stay in, a logic low state
(VOD ≤ −250 mV).
The fail-safe circuit triggers as soon as the input differential voltage
remains between +100 mV and −100 mV for some nanoseconds.
Therefore, very slow rise and fall times on the input signal,
outside typical LVDS operation (350 ps maximum tR/tF), can
potentially trigger the fail-safe circuit on a high to low crossover.
The output drive current is between 2.5 mA and 4.5 mA
(typically 3.1 mA), developing between 250 mV and 450 mV
across a 100 Ω termination resistor (RT). The received voltage is
centered around 1.2 V. Because the differential voltage (VID)
reverses polarity, the peak-to-peak voltage swing across RT is
twice the differential voltage magnitude (|VID|).
At the minimum |VID| of 100 mV for normal operation, the rise
and fall time must be ≤5 ns to avoid triggering a fail-safe state.
Increasing |VID| to 200 mV allows an input rise and fall time of
up to 10 ns without triggering a fail-safe state. For speed applica-
tions with restricting data rates less than 30 Mbps, where slow
high to low transitions in excess of this limit are expected, use
external biasing resistors to introduce a minimum |VID| of
100 mV if the fail-safe cannot trigger.
TRUTH TABLE AND FAIL-SAFE RECEIVER
The LVDS standard, TIA/EIA-644-A, defines normal receiver
operation under two conditions: an input differential voltage
of ≥+100 mV corresponding to one logic state, and a voltage of
≤−100 mV for the other logic state. Between these thresholds,
standard LVDS receiver operation is undefined (the LVDS receiver
Table 16. ADN4654 Input and Output Operation
Input (DINx
)
Output (DOUTx
VOD (mV)
≥250
≤−250
Indeterminate
≥250
)
Powered On
VID (mV)
≥100
≤−100
Logic
Powered On
Logic
Yes
Yes
Yes
No
High
Low
Indeterminate
Don’t care
Yes
Yes
Yes
Yes
High
Low
Indeterminate
High
−100 < VID < +100
Don’t care
Table 17. ADN4655/ADN4656 Input and Output Operation
Input (DINx
)
Output (DOUTx )
Powered On
VID (mV)
≥100
≤−100
−100 < VID < +100
Don’t care
Logic
Powered On
VOD (mV)
≥250
≤−250
≥250
Logic
High
Low
High
High
Yes
Yes
Yes
No
High
Low
Indeterminate
Don’t care
Yes
Yes
Yes
Yes
≥250
Rev. C | Page 18 of 25
Data Sheet
ADN4654/ADN4655/ADN4656
On power-up, the output state may initially be in the incorrect
dc state if there are no input transitions. The output state is
corrected within 1 µs by the refresh pulses.
ISOLATION
In response to any change in the input state detected by the
integrated LVDS receiver, an encoder circuit sends narrow (~1 ns)
pulses to a decoder circuit using integrated transformer coils.
The decoder is bistable and is, therefore, either set or reset by
the pulses that indicate input transitions. The decoder state
determines the LVDS driver output state in normal operation,
which reflects the isolated LVDS buffer input state.
If the decoder receives no internal pulses for more than
approximately 1 µs, the device assumes that the input side is
unpowered or nonfunctional, in which case, the output is set to
a positive differential voltage (logic high).
In the absence of input transitions for more than approximately
1 µs, a periodic set of refresh pulses, indicative of the correct input
state, ensures dc correctness at the output (including the fail-safe
output state, if applicable).
Rev. C | Page 19 of 25
ADN4654/ADN4655/ADN4656
Data Sheet
APPLICATIONS INFORMATION
When the integrated LDO regulator is used, bypass capacitors
of 1 µF are required on the VINx pins and on the nearest VDDx
pins (LDO output), as shown in Figure 41.
PCB LAYOUT
The ADN4654/ADN4655/ADN4656 can operate with high
speed LVDS signals up to 0.55 GHz clock, or 1.1 Gbps nonreturn to
zero (NRZ) data. When operating with such high frequencies,
apply best practices for the LVDS trace layout and termination.
Place a 100 Ω termination resistor as close as possible to the
receiver, across the DINx+ and DINx− pins.
100nF
100nF
1µF
1µF
1µF
1µF
1
2
20
19
18
17
16
15
14
13
12
11
V
IN2
V
IN1
GND
GND
1
2
V
3
V
DD2
DD1
4
GND
D
GND
2
1
ADN4654
5
D
Controlled 50 Ω impedance traces are needed on LVDS signal
lines for full signal integrity, reduced system jitter, and minimizing
electromagnetic interference (EMI) from the PCB. Trace widths,
lateral distance within each pair, and distance to the ground plane
underneath all must be chosen appropriately. Via fencing to the
PCB ground between pairs is also a best practice to minimize
crosstalk between adjacent pairs.
IN1+
IN1–
IN2+
OUT1+
OUT1–
OUT2+
OUT2–
TOP VIEW
100Ω
100Ω
6
D
D
(Not to Scale)
D
D
D
7
8
D
IN2–
V
9
V
DD2
DD1
10
GND
GND
2
1
100nF
100nF
Figure 41. Required PCB Layout When Using LDO Regulator (3.3 V Supply)
APPLICATION EXAMPLES
The ADN4654/ADN4655/ADN4656 pass EN 55022 Class B
emissions limits without extra considerations required for the
isolator when operating with up to 1.1 Gbps PRBS data. When
isolating high speed clocks (for example, 0.55 GHz), a reduced
PCB clearance (isolation gap) may be required with the 20-lead
SOIC_W model to reduce dipole antenna effects and provide
sufficient margin below Class B emissions limits.
High speed LVDS interfaces for the analog front-end (AFE),
processor to processor communication, or video and imaging data
can be isolated using the ADN4654, as an example, between
components, between boards, or at a cable interface. The ADN4654
provides the galvanic isolation required for robust external ports,
and the low jitter and high drive strength of the device allow
communication along short cable runs of a few meters. High
common-mode immunity ensures communication integrity
even in harsh, noisy environments, and isolation can protect
against electromagnetic compatibility (EMC) transients up to
8 kV peak, such as ESD, electrical fast transient (EFT), and
surge. The ADN4654 can isolate a range of video and imaging
protocols, including protocols that use current mode logic
(CML) rather than LVDS for the physical layer. One example is
High-Definition Multimedia Interface (HDMI), where
ac coupling and biasing and termination resistor networks are
used as shown in Figure 42 to convert between CML (used by
the transition minimized differential signaling (TMDS) data
and clock lanes) and the LVDS levels required by the ADN4654.
Additional Analog Devices isolator components, such as the
ADuM1250/ADuM1251 I2C isolators, can be used to isolate
control signals and power (ADuM5020 isoPower integrated,
isolated dc-to-dc converter). This circuit supports resolutions
up to 720p.
The best practice for high speed PCB design avoids any other
emissions from PCBs in applications that use the ADN4654/
ADN4655/ADN4656. Take care when configuring off-board
connections, where switching transients from high speed LVDS
signals (clocks in particular) can conduct onto cabling, resulting
in radiated emissions. Use common-mode chokes, ferrites, or
other filters as appropriate at the LVDS connectors, as well as
cable shield or PCB ground connections to earth or chassis.
The ADN4654/ADN4655/ADN4656 require appropriate
decoupling of the VDDx pins with 100 nF capacitors. If the
integrated LDO regulator is not used, and a 2.5 V supply is
connected directly, connect the appropriate VINx pin to the supply
as well, as shown in Figure 40, using the ADN4654 as an
example.
100nF
100nF
1
2
3
4
5
6
7
8
9
20
V
V
IN2
IN1
19
18
17
16
15
14
13
12
11
GND
GND
GND
GND
1
2
V
V
DD1
DD2
1
IN1+
IN1–
IN2+
IN2–
2
Other circuits can use the ADN4654 for isolating MIPI CSI-2,
DisplayPort, and LVDS-based protocols such as FPD-Link. Use
of a field-programmable gate array (FPGA) or an application-
specific integrated circuit (ASIC) serializer/deserializer (SERDES)
expands bandwidth through multiple ADN4654 devices to
support 1080p or 4K video resolutions, providing an alternative
to short reach fiber links.
ADN4654
D
D
D
D
D
D
D
D
OUT1+
OUT1–
OUT2+
OUT2–
TOP VIEW
100Ω
100Ω
(Not to Scale)
V
V
DD1
DD2
10
GND
GND
2
1
100nF
100nF
Figure 40. Required PCB Layout When Not Using LDO Regulator (2.5 V Supply)
Rev. C | Page 20 of 25
Data Sheet
ADN4654/ADN4655/ADN4656
1
3
2
4
1
TMDS D0+
TMDS D0–
ADN4654 (×2)
TMDS D0+
TMDS D0–
TMDS D1+
TMDS D1–
TMDS D1+
TMDS D1–
2
TMDS D2+
TMDS D2–
TMDS D2+
TMDS D2–
TMDS CLK+
TMDS CLK–
TMDS CLK+
TMDS CLK–
ADuM1250
SDA
SCK
SDA
SCK
ADuM1251
CEC
HPD
CEC
HPD
ADuM5020 (×2)
V
V
OSC
REC
DDP
REG
V
(3.3V)
ISO
SUPPLY FOR ISOLATORS
OSC
REC
REG
DDP
V
(5V, 100mA)
ISO
+5V
NOTES
1. SUPPLY BIASED TERMINATION
2. AC COUPLING
3. COMMON-MODE BIASING
4. DIFFERENTIAL TERMINATION
Figure 42. Example Isolated Video Interface (HDMI) Using the ADN4654
Rev. C | Page 21 of 25
ADN4654/ADN4655/ADN4656
Data Sheet
insensitive to external fields. Only extremely large, high frequency
currents that are close to the component can potentially be a
concern. For the 1 MHz example noted, a 2.29 kA current must be
placed 5 mm from the ADN4654/ADN4655/ADN4656 to affect
component operation.
MAGNETIC FIELD IMMUNITY
The limitation on the magnetic field immunity of the device is
set by the condition in which the induced voltage in the trans-
former receiving coil is sufficiently large, either to falsely set or
reset the decoder. The following analysis defines such conditions.
The ADN4654/ADN4655/ADN4656 are examined in a 2.375 V
operating condition because this operating condition represents
the most susceptible mode of operation for these products.
10k
DISTANCE = 1m
1k
100
The pulses at the transformer output have an amplitude greater
than 0.5 V. The decoder has a sensing threshold of about 0.25 V,
therefore establishing a 0.25 V margin in which induced voltages
are tolerated. The voltage (V) induced across the receiving coil
is given by
DISTANCE = 100mm
10
DISTANCE = 5mm
1
2
V = (−dβ/dt)∑πrn ; n = 1, 2, …, N
0.1
where:
dβ is the change in magnetic flux density.
dt is the change in time.
0.01
1k
10k
100k
1M
10M
100M
MAGNETIC FIELD FREQUENCY (Hz)
rn is the radius of the nth turn in the receiving coil.
N is the number of turns in the receiving coil.
Figure 44. Maximum Allowable Current for Various Current to ADN4654
Spacings
Given the geometry of the receiving coil in the ADN4654/
ADN4655/ADN4656 and an imposed requirement that the
induced voltage be, at most, 50% of the 0.25 V margin at the
decoder, a maximum allowable external magnetic flux density is
calculated as shown in Figure 43.
In combinations of strong magnetic field and high frequency,
any loops formed by PCB traces can induce sufficiently large
error voltages to trigger the thresholds of succeeding circuitry.
Avoid PCB structures that form loops.
INSULATION LIFETIME
1k
All insulation structures eventually break down when subjected
to voltage stress over a sufficiently long period. The rate of
insulation degradation is dependent on the characteristics of
the voltage waveform applied across the insulation as well as on
the materials and material interfaces.
100
10
1
The two types of insulation degradation of primary interest are
breakdown along surfaces exposed to the air and insulation wear
out. Surface breakdown is the phenomenon of surface tracking
and the primary determinant of surface creepage requirements
in system level standards. Insulation wear out is the phenomenon
where charge injection or displacement currents inside the
insulation material cause long-term insulation degradation.
0.1
0.01
0.001
1k
10k
100k
1M
10M
100M
MAGNETIC FIELD FREQUENCY (Hz)
Surface Tracking
Figure 43. Maximum Allowable External Magnetic Flux Density
Surface tracking is addressed in electrical safety standards by
setting a minimum surface creepage based on the working voltage,
the environmental conditions, and the properties of the insulation
material. Safety agencies perform characterization testing on the
surface insulation of components, which allows the components to
be categorized in different material groups. Lower material group
ratings are more resistant to surface tracking and, therefore, can
provide adequate lifetime with smaller creepage. The minimum
creepage for a given working voltage and material group is in each
system level standard and is based on the total rms voltage across
the isolation barrier, pollution degree, and material group. The
material group and creepage for ADN4654/ADN4655/ADN4656
are detailed in Table 4 and Table 5.
For example, at a magnetic field frequency of 1 MHz, the
maximum allowable magnetic field of 0.92 kgauss induces a
voltage of 0.125 V at the receiving coil. This voltage is about
50% of the sensing threshold and does not cause a faulty output
transition. If such an event occurs with the worst case polarity
during a transmitted pulse, the applied magnetic field reduces
the received pulse from >0.5 V to 0.375 V. This voltage is still
higher than the 0.25 V sensing threshold of the decoder.
The preceding magnetic flux density values correspond to specific
current magnitudes at given distances from the ADN4654/
ADN4655/ADN4656 transformers. Figure 44 expresses these
allowable current magnitudes as a function of frequency for
selected distances. The ADN4654/ADN4655/ADN4656 are
Rev. C | Page 22 of 25
Data Sheet
ADN4654/ADN4655/ADN4656
Insulation Wear Out
creepage, clearance, and lifetime of a device, see Figure 45 and
the following equations.
The lifetime of insulation caused by wear out is determined by
the thickness of the insulation, material properties, and the voltage
stress applied. It is important to verify that the product lifetime
is adequate at the application working voltage. The working
voltage supported by an isolator for wear out may not be the
same as the working voltage supported for tracking. The working
voltage applicable to tracking is specified in most standards.
The working voltage across the barrier from Equation 1 is
2
VRMS
=
VAC RMS2 +VDC
VRMS
=
2402 + 4002
VRMS = 466 V
This VRMS value is the working voltage used together with the
material group and pollution degree when looking up the creepage
required by a system standard.
Testing and modeling show that the primary driver of long-term
degradation is displacement current in the polyimide insulation
causing incremental damage. The stress on the insulation can be
broken down into broad categories, such as dc stress, which causes
little wear out because there is no displacement current, and an
ac component time varying voltage stress, which causes wear out.
To determine if the lifetime is adequate, obtain the time varying
portion of the working voltage. To obtain the ac rms voltage,
use Equation 2.
The ratings in certification documents are usually based on
60 Hz sinusoidal stress because this type of waveform reflects
isolation from line voltage. However, many practical applications
have combinations of 60 Hz ac and dc across the isolation barrier,
as shown in Equation 1. Because only the ac portion of the
stress causes wear out, the equation can be rearranged to solve
for the ac rms voltage, as shown in Equation 2. For insulation
wear out with the polyimide materials used in this product, the
ac rms voltage determines the product lifetime.
2
VAC RMS
VAC RMS
=
=
VRMS2 −VDC
4662 − 4002
VAC RMS = 240 V rms
In this case, the ac rms voltage is simply the line voltage of
240 V rms. This calculation is more relevant when the waveform is
not sinusoidal. Table 12 compares the value to the limits for the
working voltage for the expected lifetime. Note that the dc
working voltage limit in Table 12 is set by the creepage of the
package as specified in IEC 60664-1. This value can differ for
specific system level standards.
2
(1)
VRMS
=
VAC RMS2 +VDC
or
2
=
VRMS2 −VDC
(2)
VAC RMS
where:
V
V
V
RMS is the total rms working voltage.
AC RMS is the time varying portion of the working voltage.
DC is the dc offset of the working voltage.
V
AC RMS
V
V
V
DC
PEAK
RMS
Calculation and Use of Parameters Example
The following example frequently arises in power conversion
applications. Assume that the line voltage on one side of the
isolation is 240 V ac rms and a 400 V dc bus voltage is present
on the other side of the isolation barrier. The isolator material is
polyimide. To establish the critical voltages in determining the
TIME
Figure 45. Critical Voltage Example
Rev. C | Page 23 of 25
ADN4654/ADN4655/ADN4656
OUTLINE DIMENSIONS
Data Sheet
7.50
7.20
6.90
11
20
5.60
5.30
5.00
8.20
7.80
7.40
1
10
PIN 1
INDICATOR
TOP VIEW
SIDE VIEW
0.25
0.09
1.85
1.75
1.65
2.00 MAX
END VIEW
8°
4°
0°
0.95
0.75
0.55
0.38
0.22
0.05 MIN
SEATING
PLANE
COPLANARITY
0.65 BSC
0.10
COMPLIANT TO JEDEC STANDARDS MO-150-AE
Figure 46. 20-Lead Shrink Small Outline Package [SSOP]
(RS-20)
Dimensions shown in millimeters
13.00 (0.5118)
12.60 (0.4961)
20
1
11
7.60 (0.2992)
7.40 (0.2913)
10.65 (0.4193)
10
10.00 (0.3937)
0.75 (0.0295)
45°
(0.0098)
2.65 (0.1043)
0.25
2.35 (0.0925)
8°
0.30 (0.0118)
0.10 (0.0039)
0°
COPLANARITY
0.10
SEATING
PLANE
0.51 (0.0201)
0.31 (0.0122)
1.27 (0.0500)
0.40 (0.0157)
1.27
(0.0500)
BSC
0.33 (0.0130)
0.20 (0.0079)
COMPLIANT TO JEDEC STANDARDS MS-013-AC
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 47. 20-Lead Standard Small Outline Package [SOIC_W]
Wide Body
(RW-20)
Dimensions shown in millimeters and (inches)
Rev. C | Page 24 of 25
Data Sheet
ADN4654/ADN4655/ADN4656
ORDERING GUIDE
Model1
ADN4654BRSZ
ADN4654BRSZ-RL7
ADN4654BRWZ
ADN4654BRWZ-RL7
ADN4655BRWZ
ADN4655BRWZ-RL7
ADN4656BRWZ
ADN4656BRWZ-RL7
EVAL-ADN4654EB1Z
EVAL-ADN4655EB1Z
EVAL-ADN4656EB1Z
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Package Description
Package Option
20-Lead Shrink Small Outline Package [SSOP]
20-Lead Shrink Small Outline Package [SSOP]
20-Lead Wide Body, Standard Small Outline Package [SOIC_W]
20-Lead Wide Body, Standard Small Outline Package [SOIC_W]
20-Lead Wide Body, Standard Small Outline Package [SOIC_W]
20-Lead Wide Body, Standard Small Outline Package [SOIC_W]
20-Lead Wide Body, Standard Small Outline Package [SOIC_W]
20-Lead Wide Body, Standard Small Outline Package [SOIC_W]
Evaluation Board
RS-20
RS-20
RW-20
RW-20
RW-20
RW-20
RW-20
RW-20
Evaluation Board
Evaluation Board
1 Z = RoHS Compliant Part.
I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).
©2018–2019 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D17011-0-6/19(C)
Rev. C | Page 25 of 25
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