ADN4662BRZ [ADI]
Single, 3 V, CMOS, LVDS Differential Line Receiver;
| 型号： | ADN4662BRZ |
| 厂家： | 
ADI |
| 描述： | Single, 3 V, CMOS, LVDS Differential Line Receiver 光电二极管 接口集成电路 |
| 文件： | 总13页 (文件大小：258K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Single, 3 V, CMOS, LVDS
Differential Line Receiver
Data Sheet
ADN4662
FEATURES
FUNCTIONAL BLOCK DIAGRAM
V
CC
15 kV ESD protection on input pins
400 Mbps (200 MHz) switching rates
Flow-through pinout simplifies PCB layout
2.5 ns maximum propagation delay
ADN4662
R
R
IN+
R
OUT
IN–
3.3 V power supply
High impedance outputs on power-down
Low power design: typically 18 mW (quiescent)
Interoperable with existing 5 V LVDS drivers
Accepts small swing (310 mV typical) differential signal
levels
GND NC
NC
NC
Figure 1.
Supports open, short, and terminated input fail-safe
0 V to −100 mV threshold region
Conforms to TIA/EIA-644 LVDS standard
Industrial operating temperature range: −40°C to +85°C
Available in surface-mount (SOIC) package
APPLICATIONS
Point-to-point data transmission
Multidrop buses
Clock distribution networks
Backplane receivers
GENERAL DESCRIPTION
The ADN4662 is a single, CMOS, low voltage differential
signaling (LVDS) line receiver offering data rates of over
400 Mbps (200 MHz), and ultralow power consumption.
It features a flow-through pinout for easy PCB layout and
separation of input and output signals.
The ADN4662 and its companion driver, the ADN4661, offer a
new solution to high speed, point-to-point data transmission,
and a low power alternative to emitter-coupled logic (ECL) or
positive emitter-coupled logic (PECL).
The device accepts low voltage (310 mV typical) differential
input signals and converts them to a single-ended 3 V TTL/
CMOS logic level.
Rev. A
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Technical Support
www.analog.com
ADN4662* PRODUCT PAGE QUICK LINKS
Last Content Update: 02/23/2017
COMPARABLE PARTS
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DESIGN RESOURCES
• ADN4662 Material Declaration
• PCN-PDN Information
EVALUATION KITS
• AD-FMCMOTCON2-EBZ Evaluation Board
• Quality And Reliability
• Symbols and Footprints
DOCUMENTATION
Application Notes
DISCUSSIONS
View all ADN4662 EngineerZone Discussions.
• AN-1176: Component Footprints and Symbols in the
Binary .Bxl File Format
SAMPLE AND BUY
Visit the product page to see pricing options.
• AN-1177: LVDS and M-LVDS Circuit Implementation Guide
• AN-1179: Junction Temperature Calculation for Analog
Devices RS-485/RS-422, CAN, and LVDS/M-LVDS
Transceivers
TECHNICAL SUPPORT
Submit a technical question or find your regional support
number.
Data Sheet
• ADN4662: Single, 3 V, CMOS, LVDS Differential Line
Receiver Data Sheet
DOCUMENT FEEDBACK
Submit feedback for this data sheet.
TOOLS AND SIMULATIONS
• ADN4662 IBIS Model
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ADN4662
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
ESD Caution...................................................................................6
Pin Configuration and Function Descriptions..............................7
Typical Performance Characteristics ..............................................8
Theory of Operation ...................................................................... 11
Applications Information.......................................................... 11
Outline Dimensions....................................................................... 12
Ordering Guide .......................................................................... 12
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
AC Characteristics........................................................................ 4
Absolute Maximum Ratings............................................................ 6
REVISION HISTORY
10/13—Rev. 0 to Rev. A
Change to Features Section ............................................................. 1
1/09—Revision 0: Initial Version
Rev. A | Page 2 of 12
Data Sheet
ADN4662
SPECIFICATIONS
VDD = 3.0 V to 3.6 V; CL = 15 pF to GND; all specifications TMIN to TMAX, unless otherwise noted.
Table 1.
Parameter1
Symbol
Min
Typ2
Max
Unit
Conditions/Comments
LVDS INPUT
High Threshold at RIN+, RIN−
Low Threshold at RIN+, RIN−
3
VTH
VTL
IIN
+100
mV
mV
μA
μA
μA
VCM = 1.2 V, 0.05 V, 2.95 V
VCM = 1.2 V, 0.05 V, 2.95 V
VIN = 2.8 V, VCC = 3.6 V or 0 V
VIN = 0 V, VCC = 3.6 V or 0 V
VIN = 3.6 V, VCC = 0 V
3
−100
−10
−10
−20
Input Current at RIN+, RIN−
1
1
1
+10
+10
+20
OUTPUT
Output High Voltage
VOH
2.7
2.7
2.7
3.1
3.1
3.1
0.3
−47
−0.8
V
V
V
V
mA
V
IOH = −0.4 mA, VID = +200 mV
IOH = −0.4 mA, input terminated
IOH = −0.4 mA, input shorted
IOL = 2 mA, VID = −200 mV
Enabled, VOUT = 0 V
Output Low Voltage
VOL
IOS
VCL
0.5
−100
Output Short-Circuit Current4
Input Clamp Voltage
POWER SUPPLY
−15
−1.5
ICL = −18 mA
No Load Supply Current
ESD PROTECTION
ICC
5.4
9
mA
Inputs open
RIN+, RIN− Pins
All Pins Except RIN+, RIN−
15
4
kV
kV
Human body model
Human body model
1 Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground, unless otherwise specified.
2 All typicals are given for: VCC = +3.3 V, TA = 25°C.
3 VCC is always higher than RIN+ and RIN− voltage. RIN− and RIN+ are allowed to have a voltage range of −0.2 V to VCC − VID/2. However, to be compliant with ac specifications,
the common voltage range is 0.1 V to 2.3 V.
4 Output short-circuit current (IOS) is specified as magnitude only; the minus sign indicates direction only. Only one output should be shorted at a time. Do not exceed
maximum junction temperature specification.
Rev. A | Page 3 of 12
ADN4662
Data Sheet
AC CHARACTERISTICS
VDD = 3.0 V to 3.6 V; CL1 = 15 pF to GND; all specifications TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter
Symbol Min Typ2 Max Unit Conditions/Comments3
Differential Propagation Delay High to Low
Differential Propagation Delay Low to High
tPHLD
tPLHD
tSKD1
tSKD3
tSKD4
tTLH
1.0
1.0
0
2.15 2.5
2.03 2.5
ns
ns
ps
ns
ns
ps
ps
CL = 15 pF, VID = 200 mV (see Figure 2 and Figure 3)
CL = 15 pF, VID = 200 mV (see Figure 2 and Figure 3)
CL = 15 pF, VID = 200 mV (see Figure 2 and Figure 3)
CL = 15 pF, VID = 200 mV (see Figure 2 and Figure 3)
CL = 15 pF, VID = 200 mV (see Figure 2 and Figure 3)
CL = 15 pF, VID = 200 mV (see Figure 2 and Figure 3)
CL = 15 pF, VID = 200 mV (see Figure 2 and Figure 3)
4
Differential Pulse Skew |tPHLD − tPLHD
Differential Part-to-Part Skew5
Differential Part-to-Part Skew6
Rise Time
|
80
400
1.0
1.5
510
445
800
800
Fall Time
Maximum Operating Frequency7
tTHL
fMAX
200 250
MHz All channels switching
1 CL includes probe and jig capacitance.
2 All typicals are given for VCC = 3.3 V, TA = 25°C.
3 Generator waveform for all tests unless otherwise specified: f = 1 MHz, ZO = 50 Ω, tTLH and tTHL (0% to 100%) ≤ 3 ns for RIN+/RIN−
.
4 tSKD1 is the magnitude difference in differential propagation delay time between the positive going edge and the negative going edge of the same channel.
5 tSKD3, part-to-part skew, is the differential channel-to-channel skew of any event between devices. This specification applies to devices at the same VCC and within 5°C
of each other within the operating temperature range.
6 tSKD4, part-to-part skew, is the differential channel-to-channel skew of any event between devices. This specification applies to devices over recommended operating
temperature and voltage ranges, and across process distribution. tSKD4 is defined as |maximum − minimum| differential propagation delay.
7 fMAX generator input conditions: f = 200 MHz, tTLH = tTHL < 1 ns (0% to 100%), 50% duty cycle, differential (1.05 V to 1.35 V peak-to-peak). Output criteria: 60%/40% duty
cycle, VOL (maximum 0.4 V), VOH (minimum 2.7 V), load = 15 pF (stray plus probes).
Rev. A | Page 4 of 12
Data Sheet
ADN4662
Test Circuits and Timing Diagrams
V
CC
R
IN+
SIGNAL
GENERATOR
R
R
OUT
IN–
50Ω 50Ω
C
L
C
= LOAD AND TEST JIG CAPACITANCE
L
Figure 2. Test Circuit for Receiver Propagation Delay and Transition Time
R
1.3V
1.1V
IN–
0V (DIFFERENTIAL)
V
= 200mV
1.2V
ID
R
IN+
tPLHD
tPHLD
V
OH
80%
80%
R
1.5V
1.5V
OUT
20%
20%
V
OL
tTLH
tTHL
Figure 3. Receiver Propagation Delay and Transition Time Waveforms
Rev. A | Page 5 of 12
ADN4662
Data Sheet
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Table 3.
Parameter
Rating
VCC to GND
−0.3 V to +4 V
−0.3 V to VCC + 3.9 V
−0.3 V to VCC + 0.3 V
Input Voltage (RIN+, RIN−) to GND
Output Voltage (ROUT) to GND
Operating Temperature Range
Industrial Temperature Range
Storage Temperature Range
Junction Temperature (TJ max)
Power Dissipation
−40°C to +85°C
−65°C to +150°C
150°C
ESD CAUTION
(TJ max − TA)/θJA
SOIC Package
θJA Thermal Impedance
Reflow Soldering Peak Temperature
Pb-Free
149.5°C/W
260°C 5°C
Rev. A | Page 6 of 12
Data Sheet
ADN4662
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
R
R
1
2
3
4
8
7
6
5
V
CC
IN–
ADN4662
R
IN+
OUT
NC
NC
NC
TOP VIEW
(Not to Scale)
GND
NC = NO CONNECT
Figure 4. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Mnemonic Description
1
RIN−
Receiver Channel 1 Inverting Input. When this input is more negative than RIN+, ROUT is high. When this input is
more positive than RIN+, ROUT is low.
2
RIN+
Receiver Channel 1 Noninverting Input. When this input is more positive than RIN−, ROUT is high. When this input is
more negative than RIN−, ROUT is low.
3
4
5
6
7
NC
NC
GND
NC
ROUT
No Connect.
No Connect.
Ground reference point for all circuitry on the part.
No Connect.
Receiver Output (3 V TTL/CMOS). If the differential input voltage between RIN+ and RIN− is positive, this output is
high. If the differential input voltage is negative, this output is low.
8
VCC
Power Supply Input. This part can be operated from 3.0 V to 3.6 V.
Rev. A | Page 7 of 12
ADN4662
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
0
–5
3.6
V
= 0V
OUT
= 25°C
I
= –400µA
LOAD
T = 25°C
A
T
A
3.5
3.4
3.3
3.2
3.1
3.0
2.9
V
= 200mV
–10
–15
–20
–25
–30
–35
–40
–45
–50
ID
3.0
3.1
3.2
3.3
3.4
CC
3.5
3.6
3.0
3.1
3.2
3.3
3.4
CC
3.5
3.6
POWER SUPPLY VOLTAGE, V (V)
POWER SUPPLY VOLTAGE, V (V)
Figure 5. Output High Voltage vs. Power Supply Voltage
Figure 8. Threshold Voltage vs. Power Supply Voltage
33.60
33.55
33.50
33.45
33.40
33.35
33.30
33.25
50
45
40
35
30
25
20
15
10
5
T
V
V
= 25°C
A
I
T
V
= 2mA
LOAD
= 25°C
= 3.3V
CC
A
= 200mV
= 15pF
ID
= –200mV
ID
C
L
0
0.01
0.1
1
10
100
1000
3.0
3.1
3.2
3.3
3.4
CC
3.5
3.6
FREQUENCY (MHz)
POWER SUPPLY VOLTAGE, V (V)
Figure 9. Power Supply Current vs. Frequency
Figure 6. Output Low Voltage vs. Power Supply Voltage
–35
–37
–39
–41
–43
–45
–47
–49
–51
–53
–55
10
9
8
7
6
5
4
3
2
1
0
V
= 0V
OUT
= 25°C
V
V
C
= 3.3V
= 200mV
= 15pF
CC
T
A
ID
L
FREQUENCY = 1MHz
–40
–15
10
35
60
85
3.0
3.1
3.2
3.3
3.4
CC
3.5
3.6
AMBIENT TEMPERATURE (°C)
POWER SUPPLY VOLTAGE, V (V)
Figure 7. Output Short-Circuit Current vs. Power Supply Voltage
Figure 10. Power Supply Current vs. Ambient Temperature
Rev. A | Page 8 of 12
Data Sheet
ADN4662
2.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
V
V
= 3.3V
= 200mV
V
C
= 3.3V
= 15pF
CC
CC
ID
FREQUENCY = 200MHz
= 15pF
L
2.4
FREQUENCY = 200MHz
= 1.2V
V
C
CM
L
2.3
2.2
tPHLD
2.1
tPLHD
tPLHD
tPHLD
2.0
1.9
1.8
–40
–15
10
35
60
85
0
0.5
1.0
1.5
2.0
2.5
3.0
AMBIENT TEMPERATURE, T (°C)
A
DIFFERENTIAL INPUT VOLTAGE, V (V)
ID
Figure 14. Differential Propagation Delay vs. Differential Input Voltage
Figure 11. Differential Propagation Delay vs. Ambient Temperature
250
4.0
T
V
= 25°C
= 200mV
A
T
= 25°C
A
ID
FREQUENCY = 200MHz
= 15pF
FREQUENCY = 200MHz
V
C
200
150
100
50
= 200mV
ID
C
3.5
3.0
2.5
2.0
1.5
L
= 15pF
L
tPLHD
0
tPHLD
–50
–100
3.0
3.1
3.2
3.3
3.4
3.5
3.6
0
0.5
1.0
1.5
2.0
2.5
3.0
POWER SUPPLY VOLTAGE, V (V)
COMMON-MODE VOLTAGE, V
(V)
CC
CM
Figure 15. Differential Skew vs. Power Supply Voltage
Figure 12. Differential Propagation Delay vs. Common-Mode Voltage
160
140
120
100
80
2.30
V
V
= 3.3V
CC
= 200mV
T
V
= 25°C
= 200mV
A
ID
2.25
2.20
2.15
2.10
2.05
2.00
1.95
1.90
1.85
ID
FREQUENCY = 200MHz
= 15pF
FREQUENCY = 200MHz
= 15pF
C
L
C
L
tPHLD
60
40
tPLHD
20
0
–40
–15
10
35
60
85
3.0
3.1
3.2
3.3
3.4
3.5
3.6
AMBIENT TEMPERATURE, T (°C)
POWER SUPPLY VOLTAGE, V (V)
A
CC
Figure 16. Differential Skew vs. Ambient Temperature
Figure 13. Differential Propagation Delay vs. Power Supply Voltage
Rev. A | Page 9 of 12
ADN4662
Data Sheet
600
580
560
540
520
500
480
460
440
420
1800
1600
1400
1200
1000
800
V
V
= 3.3V
CC
= 200mV
T
V
V
= 25°C
A
ID
= 3.3V
CC
= 200mV
FREQUENCY = 25MHz
= 15pF
ID
C
FREQUENCY = 1MHz
L
tTLH
tTLH
tTHL
tTHL
600
400
400
3.0
200
3.1
3.2
3.3
3.4
3.5
3.6
10
15
20
25
30
35
40
45
POWER SUPPLY VOLTAGE, V (V)
CC
LOAD (pF)
Figure 20. Transition Time vs. Load
Figure 17. Transition Time vs. Power Supply Voltage
600
550
500
450
400
350
2.9
2.7
2.5
2.3
2.1
1.9
1.7
1.5
V
V
= 3.3V
CC
= 200mV
ID
FREQUENCY = 200MHz
= 15pF
C
L
tPHLD
tTLH
tPLHD
tTHL
T
V
V
= 25°C
A
= 3.3V
CC
= 200mV
ID
FREQUENCY = 200MHz
–40
–15
10
35
60
85
10
15
20
25
30
35
40
45
AMBIENT TEMPERATURE, T (°C)
A
LOAD (pF)
Figure 18. Transition Time vs. Ambient Temperature
Figure 21. Differential Propagation Delay vs. Load at 200 MHz
1800
3.1
2.9
2.7
2.5
2.3
2.1
1.9
1.7
1.5
T
= 25°C
A
1600
1400
1200
1000
800
600
400
200
0
V
V
= 3.3V
CC
= 200mV
ID
FREQUENCY = 200MHz
tPHLD
tPLHD
tTLH
tTHL
T
V
V
= 25°C
A
= 3.3V
CC
= 200mV
ID
FREQUENCY = 1MHz
10
15
20
25
30
35
40
45
10
15
20
25
30
35
40
45
LOAD (pF)
LOAD (pF)
Figure 19. Differential Propagation Delay vs. Load at 1 MHz
Figure 22. Transition Time vs. Load at 200 MHz
Rev. A | Page 10 of 12
Data Sheet
ADN4662
THEORY OF OPERATION
(1.2 V + [310 mV/2]) = 1.355 V, and the inverting receiver input
(1.2 V − [310 mV/2]) = 1.045 V for Logic 1. For Logic 0, the
inverting and noninverting input voltages are reversed. Note that
because the differential voltage reverses polarity, the peak-to-peak
voltage swing across RT is twice the differential voltage.
The ADN4662 is a single line receiver for low voltage
differential signaling. It takes a differential input signal of
310 mV typically and converts it into a single-ended 3 V
TTL/CMOS logic signal.
A differential current input signal, received via a transmission
medium, such as a twisted pair cable, develops a voltage across
a terminating resistor, RT. This resistor is chosen to match the
characteristic impedance of the medium, typically around
100 Ω. The differential voltage is detected by the receiver and
converted back into a single-ended logic signal.
Current mode signalling offers considerable advantages over
voltage mode signalling, such as RS-422. The operating current
remains fairly constant with increased switching frequency,
whereas with voltage mode drivers the current increases
exponentially in most cases. This is caused by the overlap as
internal gates switch between high and low, which causes currents
to flow from VCC to ground. A current mode device simply reverses
a constant current between its two outputs, with no significant
overlap currents.
When the noninverting receiver input, RIN+, is positive with
respect to the inverting input RIN− (current flows through RT
from RIN+ to RIN−), then ROUT is high. When the noninverting
receiver input RIN+ is negative with respect to the inverting
input RIN− (current flows through RT from RIN− to RIN+), then
This is similar to emitter-coupled logic (ECL) and positive emitter-
coupled logic (PECL), but without the high quiescent current of
ECL and PECL.
ROUT is low.
The ADN4662 differential line receiver is capable of receiving
signals of 100 mV over a 1 V common-mode range centered
around 1.2 V. This relates to the typical driver offset voltage
value of 1.2 V. The signal originating from the driver is centered
around 1.2 V and may shift 1 V around this center point. This
1 V shifting may be caused by a difference in the ground
potential of the driver and receiver, the common-mode effect of
coupled noise, or both.
APPLICATIONS INFORMATION
Figure 23 shows a typical application for point-to-point data
transmission using the ADN4663 as the driver.
3.3V
10µF
TANTALUM
3.3V
10µF
TANTALUM
+
+
0.1µF
0.1µF
V
V
CC
CC
ADN4661
ADN4662
D
D
R
OUT+
IN+
R
100Ω
R
T
Using the ADN4663 as a driver, the received differential current
is between 2.5 mA and 4.5 mA (typically 3.1 mA), developing
between 250 mV and 450 mV across a 100 Ω termination resis-
tor. The received voltage is centered around the receiver offset of
1.2 V. In other words, the noninverting receiver input is typically
D
R
OUT
IN
OUT–
IN–
GND
GND
Figure 23. Typical Application Circuit
Rev. A | Page 11 of 12
ADN4662
Data Sheet
OUTLINE DIMENSIONS
5.00 (0.1968)
4.80 (0.1890)
8
1
5
4
6.20 (0.2441)
5.80 (0.2284)
4.00 (0.1574)
3.80 (0.1497)
0.50 (0.0196)
0.25 (0.0099)
1.27 (0.0500)
BSC
45°
1.75 (0.0688)
1.35 (0.0532)
0.25 (0.0098)
0.10 (0.0040)
8°
0°
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
1.27 (0.0500)
0.40 (0.0157)
0.25 (0.0098)
0.17 (0.0067)
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MS-012-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 24. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
ORDERING GUIDE
Model1
Temperature Range Package Description
Package Option
ADN4662BRZ
ADN4662BRZ-REEL7
1 Z = RoHS Compliant Part.
−40°C to +85°C
−40°C to +85°C
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Standard Small Outline Package [SOIC_N]
R-8
R-8
©2009–2013 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07960-0-10/13(A)
Rev. A | Page 12 of 12
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SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
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