ADN4663BRZ-REEL7 [ADI]
Dual, 3 V, CMOS, LVDS High Speed Differential Driver; 双通道， 3 V ， CMOS ， LVDS高速差分驱动器
| 型号： | ADN4663BRZ-REEL7 |
| 厂家： | 
ADI |
| 描述： | Dual, 3 V, CMOS, LVDS High Speed Differential Driver |
| 文件： | 总12页 (文件大小：201K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Dual, 3 V, CMOS, LVDS
High Speed Differential Driver
ADN4663
FUNCTIONAL BLOCK DIAGRAM
FEATURES
V
CC
15 kV ESD protection on output pins
600 Mbps (300 MHz) switching rates
Flow-through pinout simplifies PCB layout
300 ps typical differential skew
700 ps maximum differential skew
1.5 ns maximum propagation delay
3.3 V power supply
ADN4663
D
D
OUT1+
D
IN1
IN2
OUT1–
D
D
OUT2+
D
OUT2–
355 mV differential signaling
Low power dissipation: 23 mW typical
Interoperable with existing 5 V LVDS receivers
Conforms to TIA/EIA-644 LVDS standard
Industrial operating temperature range (−40°C to +85°C)
Available in surface-mount (SOIC) package
GND
Figure 1.
APPLICATIONS
Backplane data transmission
Cable data transmission
Clock distribution
GENERAL DESCRIPTION
The ADN4663 is a dual, CMOS, low voltage differential
signaling (LVDS) line driver offering data rates of over
600 Mbps (300 MHz), and ultralow power consumption.
It features a flow-through pinout for easy PCB layout and
separation of input and output signals.
twisted-pair cable. The transmitted signal develops a differential
voltage of typically 3ꢁꢁ mV across a termination resistor at the
receiving end, and this is converted back to a TTL/CMOS logic
level by a line receiver.
The ADN4663 and a companion receiver offer a new solution
to high speed point-to-point data transmission, and a low
power alternative to emitter-coupled logic (ECL) or positive
emitter-coupled logic (PECL).
The device accepts low voltage TTL/CMOS logic signals and
converts them to a differential current output of typically
3.ꢀ mA for driving a transmission medium such as a
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2009 Analog Devices, Inc. All rights reserved.
ADN4663
TABLE OF CONTENTS
Features .............................................................................................. ꢀ
ESD Caution...................................................................................6
Pin Configuration and Function Descriptions..............................7
Typical Performance Characteristics ..............................................8
Theory of Operation ...................................................................... ꢀꢀ
Applications Information.......................................................... ꢀꢀ
Outline Dimensions....................................................................... ꢀ2
Ordering Guide .......................................................................... ꢀ2
Applications....................................................................................... ꢀ
Functional Block Diagram .............................................................. ꢀ
General Description......................................................................... ꢀ
Revision History ............................................................................... 2
Specifications..................................................................................... 3
AC Characteristics........................................................................ 4
Absolute Maximum Ratings............................................................ 6
REVISION HISTORY
1/09—Revision 0: Initial Version
Rev. 0 | Page 2 of 12
ADN4663
SPECIFICATIONS
VCC = 3.0 V to 3.6 V; RL = ꢀ00 Ω; CL = ꢀꢁ pF to GND; all specifications TMIN to TMAX, unless otherwise noted.
Table 1.
Parameter1, 2
Symbol Min
Typ Max
Unit Test Conditions
LVDS OUTPUTS (DOUTx+, DOUTx−
)
Differential Output Voltage
Change in Magnitude of VOD for
Complementary Output States
VOD
ΔVOD
250
355
1
450
35
mV
See Figure 2 and Figure 4
|mV| See Figure 2 and Figure 4
Offset Voltage
Change in Magnitude of VOS for
Complementary Output States
VOS
ΔVOS
1.125 1.2
3
1.375
25
V
See Figure 2 and Figure 4
|mV| See Figure 2 and Figure 4
Output High Voltage
Output Low Voltage
VOH
VOL
1.4
1.1
1.6
V
V
See Figure 2 and Figure 4
See Figure 2 and Figure 4
0.90
INPUTS (DIN1, DIN2
)
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
VIH
VIL
IIH
IIL
VCL
2.0
VCC
0.8
+10
+10
V
V
μA
μA
V
GND
−10
−10
−1.5
2
1
−0.6
VIN = 3.3 V or 2.4 V
VIN = GND or 0.5 V
ICL = −18 mA
Input Clamp Voltage
LVDS OUTPUT PROTECTION (DOUTx+, DOUTx−
)
Output Short-Circuit Current3
IOS
−5.7 −8.0
mA
μA
DINx = VCC, DOUTx+ = 0 V or DINx = GND, DOUTx− = 0 V
VOUT = VCC or GND, VCC = 0 V
LVDS OUTPUT LEAKAGE (DOUTx+, DOUTx−
)
Power-Off Leakage
IOFF
−10
1
+10
POWER SUPPLY
Supply Current, Unloaded
Supply Current, Loaded
ESD PROTECTION
ICC
ICCL
8
10
14
20
mA
mA
No load, DINx = VCC or GND
DINx = VCC or GND
DOUTx+, DOUTx− Pins
All Pins Except DOUTx+, DOUTx−
15
4
kV
kV
Human body model
Human body model
1 Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground except VOD, ΔVOD, and ΔVOS
2 The ADN4663 is a current mode device and functions within data sheet specifications only when a resistive load is applied to the driver outputs. Typical range is
90 Ω to 110 Ω.
.
3 Output short-circuit current (IOS) is specified as magnitude only; minus sign indicates direction only.
Rev. 0 | Page 3 of 12
ADN4663
AC CHARACTERISTICS
ꢀ
VCC = 3.0 V to 3.6 V; RL = ꢀ00 Ω; CL = ꢀꢁ pF to GND; all specifications TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter2
Symbol
tPHLD
tPLHD
tSKD1
tSKD2
tSKD3
tSKD4
tTLH
Min
0.3
0.3
0
0
0
0
0.2
0.2
Typ
0.8
1.1
0.3
0.4
Max
1.5
1.5
0.7
0.8
1.0
1.2
1.0
1.0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
Conditions/Comments3, 4
See Figure 3 and Figure 4
See Figure 3 and Figure 4
See Figure 3 and Figure 4
See Figure 3 and Figure 4
See Figure 3 and Figure 4
See Figure 3 and Figure 4
See Figure 3 and Figure 4
See Figure 3 and Figure 4
See Figure 3
Differential Propagation Delay High to Low
Differential Propagation Delay Low to High
5
Differential Pulse Skew |tPHLD − tPLHD
Channel-to-Channel Skew6
Differential Part-to-Part Skew7
Differential Part-to-Part Skew8
Rise Time
|
0.5
0.5
350
Fall Time
Maximum Operating Frequency9
tTHL
fMAX
MHz
1 CL includes probe and jig capacitance.
2 AC parameters are guaranteed by design and characterization.
3 Generator waveform for all tests, unless otherwise specified: f = 50 MHz, ZO = 50 Ω, tTLH ≤ 1 ns, and tTHL ≤ 1 ns.
4 All input voltages are for one channel, unless otherwise specified. Other inputs are set to GND.
5 tSKD1 = |tPHLD − tPLHD| is the magnitude difference in differential propagation delay time between the positive going edge and the negative going edge of the
same channel.
6 tSKD2 is the differential channel-to-channel skew of any event on the same device.
7 tSKD3, differential part-to-part skew, is defined as the difference between the minimum and maximum specified differential propagation delays. This specification
applies to devices at the same VCC and within 5°C of each other within the operating temperature range.
8 tSKD4, differential part-to-part skew, is the differential channel-to-channel skew of any event between devices. This specification applies to devices over recommended
operating temperatures and voltage ranges, and across process distribution. tSKD4 is defined as |maximum − minimum| differential propagation delay.
9 fMAX generator input conditions: tTLH = tTHL < 1 ns (0% to 100%), 50% duty cycle, 0 V to 3 V. Output criteria: duty cycle = 45% to 55%, VOD > 250 mV, all channels
switching.
Rev. 0 | Page 4 of 12
ADN4663
Test Circuits and Timing Diagrams
D
OUTx+
V
CC
V
CC
R /2
L
D
INx
V
V
OD
OS
V
V
R /2
L
D
OUTx–
Figure 2. Test Circuit for Driver VOD and VOS
D
V
OUTx+
CC
C
L
L
R
L
D
INx
SIGNAL
GENERATOR
D
OUTx–
50Ω
C
C
INCLUDES LOAD AND TEST JIG CAPACITANCE.
L
Figure 3. Test Circuit for Driver Propagation Delay, Transition Time, and Maximum Operating Frequency
3V
D
1.5V
1.5V
INx
0V
tPHLD
tPLHD
V
D
D
OH
OUTx–
V
0V (DIFFERENTIAL)
0V
OD
V
OUTx+
OL
80%
80%
V
DIFF
0V
V
= D
OUT+
– D
OUT–
0V
DIFF
20%
20%
tTHL
tTHL
Figure 4. Driver Propagation Delay and Transition Time Waveforms
Rev. 0 | Page 5 of 12
ADN4663
ABSOLUTE MAXIMUM RATINGS
TA = 2ꢁ°C, unless otherwise noted. All voltages are relative to
their respective ground.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Table 3.
Parameter
Rating
VCC to GND
Input Voltage (DINx) to GND
Output Voltage (DOUTx+, DOUTx−) to GND
−0.3 V to +4 V
−0.3 V to VCC + 0.3 V
−0.3 V to VCC + 0.3 V
Short-Circuit Duration (DOUTx+, DOUTx−) to GND Continuous
Operating Temperature Range
ESD CAUTION
Industrial
−40°C to +85°C
−65°C to +150°C
150°C
Storage Temperature Range
Junction Temperature (TJ max)
Power Dissipation
(TJ max − TA)/θJA
SOIC Package
θJA Thermal Impedance
Reflow Soldering Peak Temperature
Pb-Free
149.5°C/W
260°C 5°C
Rev. 0 | Page 6 of 12
ADN4663
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
V
D
8
7
6
5
D
D
D
D
1
2
3
4
CC
OUT1–
OUT1+
OUT2+
OUT2–
ADN4663
IN1
IN2
TOP VIEW
D
(Not to Scale)
GND
Figure 5. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Mnemonic Description
1
VCC
Power Supply Input. The part can be operated from 3.0 V to 3.6 V, and the supply should be decoupled with a
10 μF solid tantalum capacitor in parallel with a 0.1 μF capacitor to GND.
2
3
4
5
DIN1
DIN2
GND
DOUT2−
Driver Channel 1 Logic Input.
Driver Channel 2 Logic Input.
Ground reference point for all circuitry on the part.
Channel 2 Inverting Output Current Driver. When DIN2 is high, current flows into DOUT2−. When DIN2 is low, current
flows out of DOUT2−
Channel 2 Noninverting Output Current Driver. When DIN2 is high, current flows out of DOUT2+. When DIN2 is low,
current flows into DOUT2+
Channel 1 Noninverting Output Current Driver. When DIN1 is high, current flows out of DOUT1+. When DIN1 is low,
current flows into DOUT1+
Channel 1 Inverting Output Current Driver. When DIN1 is high, current flows into DOUT1−. When DIN1 is low, current
flows out of DOUT1−
.
6
7
8
DOUT2+
DOUT1+
DOUT1−
.
.
.
Rev. 0 | Page 7 of 12
ADN4663
TYPICAL PERFORMANCE CHARACTERISTICS
325.0
324.8
324.6
324.4
324.2
324.0
1.415
T
R
= 25°C
= 100Ω
T
R
= 25°C
= 100Ω
A
A
L
L
1.414
1.413
1.412
3.0
3.1
3.2
3.3
3.4
CC
3.5
3.6
3.6
3.6
3.0
3.1
3.2
3.3
3.4
CC
3.5
3.6
POWER SUPPLY VOLTAGE, V (V)
POWER SUPPLY VOLTAGE, V (V)
Figure 6. Output High Voltage vs. Power Supply Voltage
Figure 9. Differential Output Voltage vs. Power Supply Voltage
500
1.090
1.089
1.088
1.087
T
= 25°C
= 100Ω
T
= 25°C
= 3.3V
A
A
R
V
L
CC
450
400
350
300
250
3.0
3.1
3.2
3.3
3.4
3.5
90
100
110
120
130
140
150
POWER SUPPLY VOLTAGE, V (V)
LOAD RESISTOR, R (Ω)
CC
L
Figure 7. Output Low Voltage vs. Power Supply Voltage
Figure 10. Differential Output Voltage vs. Load Resistor
1.252
1.251
1.250
1.249
–3.9
–4.0
–4.1
–4.2
T
R
= 25°C
= 100Ω
A
T
= 25°C
A
L
V
= GND OR V
IN
CC
= 0V
V
OUT
3.0
3.1
3.2
3.3
3.4
CC
3.5
3.0
3.1
3.2
3.3
3.4
CC
3.5
3.6
POWER SUPPLY VOLTAGE, V (V)
POWER SUPPLY VOLTAGE, V (V)
Figure 8. Output Short-Circuit Current vs. Power Supply Voltage
Figure 11. Offset Voltage vs. Power Supply Voltage
Rev. 0 | Page 8 of 12
ADN4663
1200
1100
1000
900
T
C
V
V
R
= 25°C
= 15pF
T = 25°C
A
f = 1MHz
C = 15pF
L
A
19
17
15
13
11
9
L
= 3.3V
CC
= 0V TO 3.3V
R = 100Ω PER DRIVER
IN
L
= 100Ω PER DRIVER
L
BOTH CHANNELS SWITCHING
t
PHLD
t
PLHD
ONE CHANNEL SWITCHING
7
5
3.0
3.1
3.2
3.3
3.4
3.5
3.6
0.01
0.1
1
10
100
1k
POWER SUPPLY VOLTAGE, V (V)
SWITCHING FREQUENCY (MHz)
CC
Figure 12. Power Supply Current vs. Switching Frequency
Figure 15. Differential Propagation Delay vs. Power Supply Voltage
12.5
12.0
11.5
11.0
10.5
10.0
1200
T
= 25°C
V
= 3.3V
A
CC
f = 1MHz
f = 1MHz
C
V
= 15pF
C
R
= 15pF
= 100Ω PER DRIVER
L
L
L
= 0V TO 3.3V
= 100Ω PER DRIVER
IN
R
L
t
PLHD
1100
1000
900
t
PHLD
3.0
3.1
3.2
3.3
3.4
CC
3.5
3.6
–40
–20
0
20
40
60
80
100
POWER SUPPLY VOLTAGE, V (V)
AMBIENT TEMPERATURE, T (°C)
A
Figure 13. Power Supply Current vs. Power Supply Voltage
Figure 16. Differential Propagation Delay vs. Ambient Temperature
100
15
T
= 25°C
V
= 3.3V
A
CC
f = 1MHz
f = 1MHz
C
R
= 15pF
= 100Ω PER DRIVER
C
V
R
= 15pF
= 0V TO 3V
= 100Ω PER DRIVER
L
L
L
80
60
40
20
0
14
13
12
11
10
IN
L
3.0
3.1
3.2
3.3
3.4
3.5
3.6
–40
–15
10
35
60
85
POWER SUPPLY VOLTAGE, V (V)
TEMPERATURE (°C)
CC
Figure 14. Power Supply Current vs. Ambient Temperature
Figure 17. Differential Skew vs. Power Supply Voltage
Rev. 0 | Page 9 of 12
ADN4663
50
400
380
360
340
320
V
= 3.3V
V
= 3.3V
CC
f = 1MHz
CC
f = 1MHz
C
R
= 15pF
= 100Ω PER DRIVER
C
R
= 15pF
= 100Ω PER DRIVER
L
L
L
L
40
30
20
10
t
TLH
t
THL
0
–40
–20
0
20
40
60
80
100
–40
–20
0
20
40
60
80
100
AMBIENT TEMPERATURE, T (°C)
AMBIENT TEMPERATURE, T (°C)
A
A
Figure 18. Differential Skew vs. Ambient Temperature
Figure 20. Transition Time vs. Ambient Temperature
400
380
T
= 25°C
A
f = 1MHz
= 15pF
C
L
R
= 100Ω PER DRIVER
L
t
TLH
360
340
320
t
THL
3.0
3.1
3.2
3.3
3.4
3.5
3.6
POWER SUPPLY VOLTAGE, V (V)
CC
Figure 19. Transition Time vs. Power Supply Voltage
Rev. 0 | Page 10 of 12
ADN4663
THEORY OF OPERATION
The ADN4663 is a dual line driver for low voltage differential
signaling. It takes a single-ended 3 V logic signal and converts
it to a differential current output. The data can then be transmitted
for considerable distances, over media such as a twisted-pair cable
or PCB backplane, to an LVDS receiver, where it develops a voltage
across a terminating resistor, RT. This resistor is chosen to match
the characteristic impedance of the medium, typically around
ꢀ00 ꢂ. The differential voltage is detected by the receiver and
converted back into a single-ended logic signal.
A current mode device simply reverses a constant current
between its two outputs, with no significant overlap currents.
This is similar to emitter-coupled logic (ECL) and positive
emitter-coupled logic (PECL), but without the high quiescent
current of ECL and PECL.
APPLICATIONS INFORMATION
Figure 2ꢀ shows a typical application for point-to-point data
transmission using the ADN4663 as the driver and a LVDS
receiver.
When DINx is high (Logic ꢀ), current flows out of the DOUTx+ pin
(current source) through RT and back into the DOUTx− pin (current
sink). At the receiver, this current develops a positive differential
voltage across RT (with respect to the inverting input) and results
in a Logic ꢀ at the receiver output. When DINx is low, DOUTx+
sinks current and DOUTx− sources current; a negative differential
voltage across RT results in a Logic 0 at the receiver output.
+3.3V
10µF
TANTALUM
+3.3V
+
+
0.1µF
V
V
CC
CC
LVDS RECEIVER
ADN4663
D
D
IN+
OUTx+
R
T
100Ω
OUTx–
D
OUT
D
INx
D
D
IN–
The output drive current is between 2.ꢁ mA and 4.ꢁ mA
(typically 3.ꢁꢁ mA), developing between 2ꢁ0 mV and 4ꢁ0 mV
across a ꢀ00 ꢂ termination resistor. The received voltage is centered
around the receiver offset of ꢀ.2 V. Therefore, the noninverting
receiver input is typically (ꢀ.2 V + [3ꢁꢁ mV/2]) = ꢀ.377 V, and
the inverting receiver input is (ꢀ.2 V − [3ꢁꢁ mV/2]) = ꢀ.023 V
for Logic ꢀ. For Logic 0, the inverting and noninverting output
voltages are reversed. Note that because the differential voltage
reverses polarity, the peak-to-peak voltage swing across RT is
twice the differential voltage.
GND
GND
Figure 21. Typical Application Circuit
Current mode drivers offer considerable advantages over
voltage mode drivers such as RS-422 drivers. The operating
current remains fairly constant with increased switching
frequency, whereas that of voltage mode drivers increase
exponentially in most cases. This is caused by the overlap
as internal gates switch between high and low, which causes
currents to flow from the device power supply to ground.
Rev. 0 | Page 11 of 12
ADN4663
OUTLINE DIMENSIONS
5.00 (0.1968)
4.80 (0.1890)
8
1
5
4
6.20 (0.2441)
5.80 (0.2284)
4.00 (0.1574)
3.80 (0.1497)
0.50 (0.0196)
0.25 (0.0099)
1.27 (0.0500)
BSC
45°
1.75 (0.0688)
1.35 (0.0532)
0.25 (0.0098)
0.10 (0.0040)
8°
0°
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
1.27 (0.0500)
0.40 (0.0157)
0.25 (0.0098)
0.17 (0.0067)
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MS-012-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 22. 8-Lead Standard Small Outline Package [SOIC(N)]
(R-8)
Dimensions shown in millimeters and (inches)
ORDERING GUIDE
Model
Temperature Range
Package Description
Package Option
ADN4663BRZ1
−40°C to +85°C
−40°C to +85°C
8-Lead Standard Small Outline Package [SOIC-N]
8-Lead Standard Small Outline Package [SOIC-N]
R-8
R-8
ADN4663BRZ-REEL71
1 Z = RoHS Compliant Part.
©2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07927-0-1/09(0)
Rev. 0 | Page 12 of 12
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500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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