ADN8830ACP_技术文档

Thermoelectric Cooler Controller

ADN8830

FEATURES

GENERAL DESCRIPTION

High Efficiency

The ADN8830 is a monolithic controller that drives a thermo-

electric cooler (TEC) to stabilize the temperature of a laser diode

or a passive component used in telecommunications equipment.

Small Size: 5 mm

؋

5 mm LFCSP

Low Noise: <0.5% TEC Current Ripple

Long-Term Temperature Stability: ؎0.01؇C

Temperature Lock Indication

Temperature Monitoring Output

Oscillator Synchronization with an External Signal

Clock Phase Adjustment for Multiple Controllers

Programmable Switching Frequency up to 1 MHz

Thermistor Failure Alarm

This device relies on a negative temperature coefficient (NTC)

thermistor to sense the temperature of the object attached to the

TEC. The target temperature is set with an analog input voltage

either from a DAC or an external resistor divider.

The loop is stabilized by a PID compensation amplifier with

high stability and low noise. The compensation network can be

adjusted by the user to optimize temperature settling time. The

component values for this network can be calculated based on

the thermal transfer function of the laser diode or obtained

from the lookup table given in the Application Notes section.

Maximum TEC Voltage Programmability

APPLICATIONS

Thermoelectric Cooler (TEC) Temperature Control

Resistive Heating Element Control

Temperature Stabilization Substrate (TSS) Control

Voltage outputs are provided to monitor both the temperature of

the object and the voltage across the TEC. A voltage reference

of 2.5 V is also provided.

FUNCTIONAL BLOCK DIAGRAM

PID COMPENSATION

NETWORK

P-CHANNEL

FROM

(UPPER MOSFET)

THERMISTOR

TEMPERATURE

MEASUREMENT

AMPLIFIER

PWM

N-CHANNEL

CONTROLLER

TEMPERATURE

SET

MOSFET

DRIVERS

INPUT

P-CHANNEL

(LOWER MOSFET)

VOLTAGE

REFERENCE

OSCILLATOR

V

REF

N-CHANNEL

FREQUENCY/PHASE

CONTROL

D

REV.

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reliable. However, no responsibility is assumed by Analog Devices for its

use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat

may result from its use. No license is granted by implication or otherwise

under any patent or patent rights of Analog Devices. Trademarks and

registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781/329-4700

781/461-3113

www.analog.com

2012

Fax:

©

(@ V_DD= 3.3 V to 5.0 V, V_GND= 0 V, T_A= 25؇C, T_SET= 25؇C, using typical application

ADN8830–SPECIFICATIONS ^{configuration as shown in Figure 1, unless otherwise noted.)}

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

TEMPERATURE STABILITY

Long-Term Stability

Using 10 kΩ thermistor with

ꢀ = –4.4% at 25°C

0.01

°C

PWM OUTPUT DRIVERS

Output Transition Time

Nonoverlapping Clock Delay

Output Resistance

Output Voltage Swing

Output Voltage Ripple

Output Current Ripple

t_R, t_F

C_L= 3,300 pF

20

65

6

ns

Ω

50

0

R_O(N1, P1) I_L= 50 mA

OUT A

ꢁOUT A

ꢁI_TEC

V_LIM= 0 V

_CLK= 1 MHz

V_DD

V

f

0.2

%

f_CLK= 1 MHz

LINEAR OUTPUT AMPLIFIER

Output Resistance

R_{O, P2}

R_{O, N2}

OUT B

I_OUT= 2 mA

85

178

Ω

V

Output Voltage Swing

0

V_DD

5.5

POWER SUPPLY

Power Supply Voltage

Power Supply Rejection Ratio

V_DD

PSRR

3.0

80

60

V

_DD= 3.3 V to 5 V, V_TEC= 0 V

92

8

dB

mA

μA

V

–40°C ≤ T_A≤ +85°C

PWM not switching

–40°C ≤ T_A≤ +85°C

Pin 10 = 0 V

Supply Current

I_SY

12

15

Shutdown Current

Soft-Start Charging Current

Undervoltage Lockout

I_SD

I_SS

V_OLOCK

5

15

2.0

Low-to-high threshold

V_CM= 1.5 V

2.7

ERROR AMPLIFIER

Input Offset Voltage

Gain

Input Voltage Range

Common-Mode Rejection Ratio

V_OS

A_{V, IN}

V_CM

50

20

250

2.0

μV

V/V

V

dB

0.2

58

55

CMRR

0.2 V < V_CM< 2.0 V

–40°C ≤ T_A≤ +85°C

68

Open-Loop Input Impedance

Gain-Bandwidth Product

R_IN

GBW

1

2

GΩ

MHz

REFERENCE VOLTAGE

Reference Voltage

V_REF

I_REF< 2 mA

2.37

2.47

2.57

V

OSCILLATOR

Synchronization Range

Oscillator Frequency

f_CLK

Pin 25 connected to external clock

Pin 24 = V_DD; (R = 150 kΩ;

Pin 25 = GND)

200

800

1,000

1,250

kHz

1,000

LOGIC CONTROL*

Logic Low Input Threshold

Logic High Input Threshold

Logic Low Output Level

Logic High Output Threshold

0.2

V

3

V_DD– 0.2

*Logic inputs meet typical CMOS I/O conditions for source/sink current (~1 μA).

Specifications subject to change without notice.

D

REV.

–2–

ADN8830

ABSOLUTE MAXIMUM RATINGS*

Package Type

␪_JA*

␪

Unit

JC

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 V

Input Voltage . . . . . . . . . . . . . . . . . . . . . . . GND to V_S+ 0.3 V

Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C

Operating Temperature Range . . . . . . . . . . . . –40°C to +85°C

Operating Junction Temperature . . . . . . . . . . . . . . . . . . 125°C

Lead Temperature Range (Soldering, 10 sec) . . . . . . . . 300°C

32-Lead LFCSP (ACP)

35

10

°C/W

*ꢂ_JAis specified for worst-case conditions, i.e., ꢂ_JAis specified for a device

soldered in a 4-layer circuit board for surface-mount packages.

ESD RATINGS

883 (Human Body) Model . . . . . . . . . . . . . . . . . . . . . . 1.0 kV

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the

device at these or any other conditions above those listed in the operational

sections of this specification is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect device reliability.

PIN CONFIGURATION

THERMFAULT 1

THERMIN 2

SD 3

TEMPSET 4

TEMPLOCK 5

NC 6

24 COMPOSC

23 PGND

22 N1

21 P1

20 PVDD

19 OUT A

18 COMPSWIN

17 COMPSWOUT

PIN 1

INDICATOR

ADN8830

TOP VIEW

VREF 7

AVDD 8

NC = NO CONNECT

THE EXPOSED PAD ON THE BOTTOM OF THE

PACKAGE MUST BE CONNECTED TO V_CCOR

THE GND PLANE.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily

accumulate on the human body and test equipment and can discharge without detection. Although the

ADN8830 features proprietary ESD protection circuitry, permanent damage may occur on devices

subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended

to avoid performance degradation or loss of functionality.

D

REV.

–3–

ADN8830

PIN FUNCTION DESCRIPTIONS

Description

Pin No.

Mnemonic

Type

1

2

3

4

5

THERMFAULT

THERMIN

SD

Digital Output

Analog Input

Digital Input

Analog Input

Digital Output

Indicates an Open or Short-Circuit Condition from Thermistor.

Thermistor Feedback Input.

Puts Device into Low Current Shutdown Mode. Active low.

Target Temperature Input.

TEMPSET

TEMPLOCK

Indicates when Thermistor Temperature is within 0.1°C of Target Tem-

perature as Set by TEMPSET Voltage.

6

NC

No Connection, except as Noted in the Application Notes Section.

2.5 V Reference Voltage.

7

VREF

AVDD

OUT B

N2

Analog Output

Power

8

Power for Nondriver Sections. 3.0 V min; 5.5 V max.

Linear Output Feedback. Will typically connect to TEC+ pin of TEC.

Drives Linear Output External NMOS Gate.

9

Analog Input

Analog Output

10

11

12

P2

Drives Linear Output External PMOS Gate.

TEMPCTL

Output of Error Amplifier. Connects to COMPFB through feedforward

section of compensation network.

13

14

COMPFB

Analog Input

Feedback Summing Node of Compensation Amplifier. Connects to

TEMPCTL and COMPOUT through compensation network.

COMPOUT

Analog Output

Output of Compensation Amplifier. Connects to COMPFB through feed-

back section of compensation network.

15

16

VLIM

VTEC

Analog Input

Sets Maximum Voltage across TEC.

Analog Output

Indicates Relative Voltage across the TEC. The 1.5 V corresponds to 0 V

across TEC. The 3.0 V indicates maximum output voltage, maximum heat

transfer through TEC.

17

18

COMPSWOUT

COMPSWIN

Analog Output

Analog Input

Compensation for Switching Amplifier.

Compensation for Switching Amplifier. Capacitor connected between

COMPSWIN and COMPSWOUT.

19

20

21

22

23

OUT A

PVDD

P1

Analog Input

Power

PWM Output Feedback. Will typically connect to TEC– pin of TEC.

Power for Output Driver Sections. 3.0 V min; 5.5 V max.

Drives PWM Output External PMOS Gate.

Digital Output

Ground

N1

Drives PWM Output External NMOS Gate.

PGND

Power Ground. External NMOS devices connect to PGND. Can be

connected to digital ground as noise sensitivity at this node is not critical.

24

25

26

27

28

COMPOSC

SYNCIN

Analog Input

Digital Input

Analog Input

Digital Output

Connect as Indicated in the Application Notes Section.

Optional Clock Input. If not connected, clock frequency set by FREQ pin.

Sets Switching Frequency.

FREQ

SOFTSTART

SYNCOUT

Controls Initialization Time for ADN8830 with Capacitor to Ground.

Phase Adjusted Clock Output. Phase set from PHASE pin. Can be used to

drive SYNCIN of other ADN8830 devices.

29

30

31

32

PHASE

AGND

TEMPOUT

NC

Analog Input

Ground

Sets Switching and SYNCOUT Clock Phase Relative to SYNCIN Clock.

Analog Ground. Should be low noise for highest accuracy.

Indication of Thermistor Temperature.

Analog Output

No Connection.

EP

Exposed Pad

The exposed pad on the bottom of the package must be connected to V_CCor the

GND plane.

D

REV.

–4–

Typical Performance Characteristics–ADN8830

360

SYNC IN = 200kHz

V

= 5V

= 25؇C

DD

T

A

= 25؇C

320

280

240

200

160

120

80

T

A

P1

N1

40

0

0.4

0.8

1.2

1.6

2.0

2.4

0

TIME (20ns/DIV)

VPHASE (V)

TPC 4. Clock Phase Shift vs. Phase Voltage

TPC 1. N1 and P1 Rise Time

2.480

2.475

2.470

2.465

2.460

2.455

V

= 5V

= 25؇C

DD

T

A

P1

N1

0

–40

–15

10

35

60

85

0

TEMPERATURE (؇C)

TIME (20ns/DIV)

TPC 5. V_REFvs. Temperature

TPC 2. N1 and P1 Fall Time

1,000

800

600

400

200

0

360

320

280

240

200

160

120

80

SYNC IN = 1MHz

V

= 5V

= 25؇C

DD

T

A

= 25؇C

T

A

40

0

250

500

750

(k⍀)

1,000

1,250

1,500

0.4

0.8

1.2

1.6

2.0

2.4

0

R

VPHASE (V)

FREQ

TPC 3. Clock Phase Shift vs. Phase Voltage

TPC 6. Switching Frequency vs. R_FREQ

D

REV.

–5–

ADN8830

1,000

45

40

35

30

25

20

15

10

5

V

= 5V

V

DD

= 5V

DD

R

= 150k⍀

T

A

= 25؇C

990

980

970

960

950

FREQ

USING CIRCUIT SHOWN IN FIGURE 1

940

930

920

0

–40

–15

10

35

60

85

200

300

400

500

600

700

800

900

1,000

TEMPERATURE (؇C)

SWITCHING FREQUENCY (kHz)

TPC 7. Switching Frequency vs. Temperature

TPC 10. Supply Current vs. Switching Frequency

70

65

60

55

50

45

40

35

30

2.06

2.05

2.04

2.03

2.02

–40

–15

10

35

60

85

–40

–15

10

35

60

85

TEMPERATURE (؇C)

TPC 8. Offset Voltage vs. Temperature

TPC 11. Open Thermistor Fault Threshold vs. Temperature

200

100

0.26

0

–100

–200

–300

–400

0.25

0.24

0.23

–40

–15

10

35

60

85

0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

TEMPERATURE (؇C)

COMMON-MODEVOLTAGE (V)

TPC 9. Offset Voltage vs. Common-Mode Voltage

TPC 12. Short Thermistor Fault Threshold vs.

Temperature

D

–6–

REV.

ADN8830

APPLICATION NOTES

Principle of Operation

In addition, an effective controller should operate down to 3.3 V

and have an indication of when the target temperature has been

reached. The ADN8830 accomplishes all of these requirements

with a minimum of external components. Figure 1 shows a

reference design for a typical application.

The ADN8830 is a controller for a TEC and is used to set and

stabilize the temperature of the TEC. A voltage applied to the

input of the ADN8830 corresponds to a target temperature

setpoint. The appropriate current is then applied to the TEC

to pump heat either to or away from the object whose tem-

perature is being regulated. The temperature of the object is

measured by a thermistor and is fed back to the ADN8830 to

correct the loop and settle the TEC to the appropriate final

temperature. For best stability, the thermistor should be mounted

in close proximity to the object. In most laser diode modules,

the TEC and thermistor are already mounted in the unit and

are used to regulate the temperature of the laser diode.

Temperature is monitored by connecting the measurement

thermistor to a precision amplifier, called the error amplifier,

with a simple resistor divider. This voltage is compared against

the temperature set input voltage, creating an error voltage that

is proportional to their difference. To maintain accurate wave-

length and power from the laser diode, this difference voltage

must be as accurate as possible. For this reason, self-correction

auto-zero amplifiers are used in the input stage of the ADN8830,

providing a maximum offset voltage of 250 μV over time and

temperature. This results in final temperature accuracy within

0.01°C in typical applications, eliminating the ADN8830 as an

error source in the temperature control loop. A logic output is

provided at TEMPLOCK to indicate when the target temperature

has been reached.

A complete TEC controller solution requires:

• A precision input amplifier stage to accurately measure the

difference between the target and object temperatures.

• A compensation amplifier to optimize the stability and

temperature settling time.

• A high output current stage. Because of the high output

currents involved, a TEC controller should operate with

high efficiency to minimize the heat generated from

power dissipation.

The output of the error amplifier is then fed into a compensa-

tion amplifier. An external network consisting of a few resistors

and capacitors is connected around the compensation amplifier.

This network can be adjusted by the user to optimize the step

SYNCOUT

TEMPOUT

C1

0.1␮F

R1

150k⍀

L1

4.7␮H

3.3V

32

1

31

30

29

28

27

26

25

24

COILCRAFT

DO3316-472

THERMFAULT

THERMIN

TEC–

C2

RTH

10k⍀

@25؇C

R2

7.68k⍀

0.1%

22␮F

CDE ESRD

2

3

4

5

6

7

23

22

21

20

19

18

Q1

FDW2520C-B

VREF

3.3V

TEMPSET

Q2

FDW2520C-A

R3

10k⍀

0.1%

ADN8830

TEMPLOCK

3.3V

C3

10␮F

C4

R4

7.68k⍀

0.1%

22␮F

CDE ESRD

3.3V

VREF

C5

10nF

C7

10␮F

8

9

17

16

3.3V

C8

10␮F

12

13

14

15

10

11

Q3

R5

205k⍀

C9

10␮F

FDW2520C-A

C6

2.2nF

R6

100k⍀

C10

330pF

TEC+

C12

3.3nF

C11

1␮F

R7

1M⍀

Q4

VTEC

FDW2520C-B

Figure 1. Typical Application Schematic

–7–

D

REV.

ADN8830

response of the TEC’s temperature either in terms of settling time

or maximum current change. Details of how to adjust the compen-

sation network are given in the Compensation Loop section.

simple integrator or PID loop, the dc forward gain of the

compensation section is equal to the open-loop gain of the

compensation amplifier, which is over 80 dB or 10,000. The

output from the compensation loop at COMPOUT is then fed

to the linear amplifier. The output of the linear amplifier at

OUT B is fed with COMPOUT into the PWM amplifier whose

output is OUT A. These two outputs provide the voltage drive

directly to the TEC. Including the external transistors, the gain of

the differential output section is fixed at 4. Details on the output

amplifiers can be found in the Output Driver Amplifiers section.

The ADN8830 can be easily integrated with a wavelength locker

for fine-tune temperature adjustment of the laser diode for a

specific wavelength. This is a useful topology for tunable wave-

length lasers. Details are highlighted in the Using the TEC

Controller ADN8830 with a Wave Locker section.

The TEC is driven differentially using an H-bridge configura-

tion to maximize the output voltage swing. The ADN8830

drives external transistors that are used to provide current to the

TEC. These transistors can be selected by the user based on the

maximum output current required for the TEC. The maximum

voltage across the TEC can be set through use of the VLIM pin

on the ADN8830.

1.5V

COMPENSATION PWM/LINEAR

INPUT

AMPLIFIER

AMPLIFIERS

4

2

TEMPSET

THERMIN

19

9

OUT A

OUT B

1.5V

A

= 20

V

To further improve the power efficiency of the system, one side

of the H-bridge uses a switched output. Only one inductor and

one capacitor are required to filter out the switching frequency.

The output voltage ripple is a function of the output inductor

and capacitor and the switching frequency. For most applica-

tions, a 4.7 μH inductor, 22 μF capacitor, and switching frequency

of 1 MHz maintains less than 0.5% worst-case output voltage

ripple across the TEC. The other side of the H-bridge does not

require any additional circuitry.

A

= Z2/Z1

Z2

A = 4

V

12

13

COMPFB

14

COMPOUT

Z1

TEMPCTL

Figure 2. Signal Flow Block Diagram of the ADN8830

Thermistor Setup

The temperature of the thermal object, such as a laser diode, is

detected with a negative temperature coefficient (NTC) thermistor.

The thermistor’s resistance exhibits an exponential relationship to

the inverse of temperature, meaning the resistance decreases at

higher temperatures. Thus, by measuring the thermistor resistance,

temperature can be ascertained. Betatherm is a leading supplier

of NTC thermistors. Thermistor information and details can be

found at www.betatherm.com.

The oscillator section of the ADN8830 controls the switched

output section. A single resistor sets the switching frequency

from 100 kHz to 1 MHz. The clock output is available at the

SYNCOUT pin and can be used to drive another ADN8830

device by connecting to its SYNCIN pin. The phase of the

clock is adjusted by a voltage applied to the PHASE pin, which

can be set by a simple resistor divider. Phase adjustment allows

two or more ADN8830 devices to operate from the same clock

frequency and not have all outputs switch simultaneously, which

could create an excessive power supply ripple. Details of how to

adjust the clock frequency and phase are given in the Setting the

Switching Frequency section.

For this application, the resistance is measured using a voltage

divider. The thermistor is connected between THERMIN (Pin 2)

and AGND (Pin 30). Another resistor (R_X) is connected between

VREF (Pin 7) and THERMIN (Pin 2), creating a voltage divider

for the VREF voltage. Figure 3 shows the schematic for this

configuration.

For effective indication of a catastrophic system failure, the

ADN8830 alerts to open-circuit or short-circuit conditions from the

thermistor, preventing an erroneous and potentially damaging

temperature correction from occurring. With some additional

external circuitry, output overcurrent detection can be imple-

mented to provide warning in the event of a TEC short-circuit

failure. This circuit is highlighted in the Setting Maximum

Output Current and Short-Circuit Protection section.

V

DD

8

7

R

X

2

ADN8830

Signal Flow Diagram

R

THERM

Figure 2 shows the signal flow diagram through the ADN8830.

The input amplifier is fixed with a gain of 20. The voltage at

TEMPCTL can be expressed as

30

Figure 3. Connecting a Thermistor to the ADN8830

TEMPCTL = 20 × TEMPSET – THERMIN + 1.5

(1)

(

)

With the thermistor connected from THERMIN to AGND, the

voltage at THERMIN will decrease as temperature increases.

To maintain the proper input-to-output polarity in this configu-

ration, OUT A (Pin 19) should connect to the TEC– pin on the

TEC, and OUT B (Pin 9) should connect to the VTEC+ pin.

When the temperature is settled, the thermistor voltage will be

equal to the TEMPSET voltage, and the output of the input

amplifier will be 1.5 V.

The voltage at TEMPCTL is then fed into the compensation

amplifier whose frequency response is dictated by the compen-

sation network. Details on the compensation amplifier can be

found in the Compensation Loop section. When configured as a

The thermistor can also be connected from VREF to THERMIN

with R_Xconnecting to ground. In this case, OUT A must connect to

TEC+ with OUT B connected to TEC– for proper operation.

D

REV.

–8–

ADN8830

Although the thermistor has a nonlinear relationship to tem-

perature, near optimal linearity over a specified temperature

range can be achieved with the proper value of R_X. First, the

resistance of the thermistor must be known, where

The setpoint voltage can be driven from a DAC or another

voltage source, as shown in Figure 4. The reference voltage

for the DAC should be connected to VREF (Pin 7) on the

ADN8830 to ensure best accuracy from device to device.

For a fixed target temperature, a voltage divider network can be

used as shown in Figure 5. R1 is set equal to R_X, and R2 is

equal to the value of R_THERMat the target temperature.

R_THERM= R_T1@T = T_LOW

= R_T2@T = T_MID

(2)

= R_T3@T = T_HIGH

3.3V

7

3.3V

8

T

_LOWand T_HIGHare the endpoints of the temperature range and

T_MIDis the average. These resistances can be found in most

thermistor data sheets. In some cases, only the coefficients

corresponding to the Steinhart-Hart equation are given. The

Steinhart-Hart equation is

1–4

6

4

7

AD7390

5

8

ADN8830

3

1

T

= a + b1n R + c 1n R

( )

(3)

[

]

␮C

where T is the absolute temperature of the thermistor in Kelvin

(K = °C + 273.15), and R is the resistance of the thermistor at

that temperature. Based on the coefficients a, b, and c, R_THERM

can be calculated for a given T, albeit somewhat tediously, by

solving the cubic roots of this equation

30

Figure 4. Using a DAC to Control the Temperature

Setpoint

1

3

1

3

⎡

⎤

⎥

3.3V

1

2

1

2

⎛

⎞

⎛

⎞

⎢

2

ψ³

27

ψ³

27

⎛

⎞

⎛

⎞

(4)

8

χ

2

χ

2

χ

⎜

⎟

⎜

+ –

⎜

⎟

R_THERM= exp

–

+

–

+

⎢

⎜

⎟

⎜

⎟

⎜

⎟

7

4

⎝

⎠

⎝

⎠

⎜

⎟

⎠

⎜

⎝

⎟

⎠

⎢

⎝

⎢

⎥

⎦

R1

⎣

4

ADN8830

where

1

T

a –

R2

b

c

ψ =

and

X =

c

30

R_Xis then found as

Figure 5. Using a Voltage Divider to Set a Fixed

Temperature Setpoint

R_T1R_T2+ R_T2R_T3– 2R_T1R_T3

R_T1+ R_T3– 2R_T2

R_X

=

(5)

Design Example 1

A laser module requires a constant temperature of 25°C. From

the manufacturer’s data sheet, we find the thermistor in the laser

module has a value of 10 kΩ at 25°C. Because the laser is not

required to operate at a range of temperatures, the value of R_X

can be set to 10 kΩ. TEMPSET can be set by a simple resistor

divider as shown in Figure 5, with R1 and R2 both equal to 10 kΩ.

For the best accuracy as well as the widest selection range for

resistances, R_Xshould be 0.1% tolerance. Naturally, the smaller

the temperature range required for control, the more linear

the voltage divider will be with respect to temperature. The

voltage at THERMIN is

R_THERM

R_THERM+ R_X

Design Example 2

V_X=VREF

(6)

A laser module requires a continuous temperature control from

5°C to 45°C. The manufacturer’s data sheet shows the thermistor

has a value of 10 kΩ at 25°C, 25.4 kΩ at 5°C, and 4.37 kΩ at

45°C. Using Equation 5, R_Xis calculated to be 7.68 kΩ to yield

the most linear temperature-to-voltage conversion. A DAC

will be used to set the TEMPSET voltage.

where VREF has a typical value of 2.47 V.

The ADN8830 control loop will adjust the temperature of the

TEC until V_Xequals the voltage at TEMPSET (Pin 4), which

we define as V_SET. Target temperature can be set by

V_SET= m T – T

+V

(7)

DAC Resolution for TEMPSET

(

)

MID

XMID

The temperature setpoint voltage to THERMIN can be set from

a DAC. The DAC must have a sufficient number of bits to achieve

adequate temperature resolution from the system. The voltage

range for THERMIN is found by multiplying the variable m

from Equation 8 by the temperature range.

where T equals the target temperature, and

V_{X , HIGH}–V_{X , LOW}

m =

(8)

T_HIGH–T_LOW

V_Xfor high, mid, and low are found by using Equation 6 and

THERMIN Voltage Range = m × T

– T_MIN

(9)

(

)

MAX

substituting R_T3, R_T2, and R_T1, respectively, for R_THERM. The

variable m is the change in V_Xwith respect to temperature and

is expressed in V/°C.

From Design Example 2, 40°C of the control temperature range

is achieved with a voltage range of only 1 V.

D

REV.

–9–

ADN8830

To eliminate the resolution of the DAC as the principal source

of system error, the step size of each bit, V_STEP, should be lower

than the desired system resolution. A practical value for absolute

DAC resolution is the equivalent of 0.05°C. The value of V_STEP

should be less than the value of m from Equation 8 multiplied

by the desired temperature resolution, or

Table I. Switching Frequencies vs. R_FREQ

f_SWITCH

R_FREQ

100 kHz

250 kHz

500 kHz

750 kHz

1 MHz

1.5 MΩ

600 kΩ

300 kΩ

200 kΩ

150 kΩ

(10)

V_STEP< 0.05°C × m

where m is the slope of the voltage-to-temperature conversion

line, as found from Equation 8. From Design Example 2, where

m = 25 mV/°C, we see the DAC should have resolution better

than 1.25 mV per step.

For other frequencies, the value for this resistor, R_FREQ, should

be set to

150 ×10⁹

f_SWITCH

R_FREQ

=

The minimum number of bits required is then given as

(12)

log V

– log V

(

)

(

)

FS

STEP

where f_SWITCHis the switching frequency in Hz.

Number of Bits =

(11)

log 2

( )

Higher switching frequencies reduce the voltage ripple across

the TEC. However, high switch frequencies will create more

power dissipation in the external transistors. This is due to the

more frequent charging and discharging of the transistors’ gate

capacitances. If large transistors are needed for a high output

current application, faster switching frequencies could reduce

the overall power efficiency of the circuit. This is covered in

detail in the Calculating Power Dissipation and Efficiency section.

where V_FSis the full-scale output voltage from the DAC, which

should be equal to the reference voltage from the ADN8830,

VREF = 2.47 V as given in the Specifications table for the

Reference Voltage. In this example, the minimum resolution is

11 bits. A 12-bit DAC, such as the AD7390, can be readily

found.

It is important that the full-scale voltage input to the DAC is tied

to the ADN8830 reference voltage, as shown in Figure 4. This

eliminates errors from slight variances of VREF.

The switching frequency of the ADN8830 can be synchronized

with an external clock by connecting the clock signal to SYNCIN

(Pin 25). Pin 24 should also be connected to an R-C network, as

shown in Figure 6. This network is simply used to compensate a

PLL to lock on to the external clock. To ensure the quickest

synchronization lock-in time, R_FREQshould be set to 1.5 MΩ.

Thermistor Fault and Temperature Lock Indications

Both the THERMFAULT (Pin 1) and TEMPLOCK (Pin 5)

outputs are CMOS compatible outputs that are active high.

THERMFAULT will be a logic low while the thermistor is

operating normally and will go to a logic high if a short or

open is detected at THERMIN (Pin 2). The trip voltage for

THERMFAULT is when THERMIN falls below 0.2 V or

exceeds 2.0 V. THERMFAULT provides only an indication of

a fault condition and does not activate any shutdown or protec-

tion circuitry on the ADN8830. To shut down the ADN8830, a

logic low voltage must be asserted on Pin 3, as described in the

Shutdown Mode section.

1nF

ADN8830

COMPOSC

24

1k⍀

0.1␮F

FREQ

26

1.5M⍀

TEMPLOCK will output a logic high when the voltage at

THERMIN is within 2.5 mV of TEMPSET. This voltage can

be related to temperature by solving for m from Equation 8. For

most laser diode applications, 2.5 mV is equivalent to 0.1°C.

If the voltage difference between THERMIN and TEMPSET is

greater than 2.5 mV, then TEMPLOCK will output a logic low.

The input offset voltage of the ADN8830 is guaranteed to within

250 μV, which for most applications is within 0.01°C.

Figure 6. Using an R-C Network on Pin 24 with

an External Clock

The relative phase of the ADN8830 internal oscillator compared

to the external clock signal can be adjusted. This is accomplished

by adjusting the voltage to PHASE (Pin 29) according to TPCs 3

and 4. The phase shift versus voltage can be approximated as

V_PHASE

VREF

Setting the Switching Frequency

Phase Shift° = 360° ×

(13)

The ADN8830 has an internal oscillator to generate the switch-

ing frequency for the output stage. This oscillator can be either

set in free-run mode or synchronized to an external clock

signal. For free-run operation, SYNCIN (Pin 25) should be

connected to ground and COMPOSC (Pin 24) should be

connected to AVDD. The switching frequency is then set by a

single resistor connected from FREQ (Pin 26) to ground.

Table I shows R_FREQfor some common switching frequencies.

where V_PHASEis the voltage at Pin 29, and VREF has a typical

value of 2.47 V.

To ensure the oscillator operates correctly, V_PHASEshould remain

higher than 100 mV and lower than 2.3 V. This is required for

either internal clock or external synchronization operation. A

resistor divider from VREF to ground can establish this voltage

easily, although any voltage source, such as a DAC, could be used

as well. If phase is not a consideration, for example with a single

ADN8830 being used, Pin 29 can be tied to Pin 6, which pro-

vides a 1.5 V reference voltage.

D

REV.

–10–

ADN8830

The phase adjusted output from the ADN8830 is available at

SYNCOUT (Pin 28). This pin can be used as a master clock

signal for driving other ADN8830 devices. Multiple ADN8830

devices can be either driven from a single master ADN8830

device by connecting its SYNCOUT pin to each slave’s SYNCIN

pin or daisy-chained by connecting each device’s SYNCOUT to

the next device’s SYNCIN pin.

Soft Start on Power-Up

The ADN8830 can be programmed to ramp up for a specified

time after the power supply is applied or after shutdown is

de-asserted. This feature, known as soft start, is useful for

gradually increasing the duty cycle of the PWM amplifier. The

soft start time is set with a single capacitor connected from Pin 27

to ground according to Equation 14.

Phase shifting is useful in systems that use more than one

ADN8830 TEC controller. It ensures the ADN8830 devices

will not switch at the same time, which could create excessive

ripple on the power supply voltage. By adjusting the phase of

each device, the switching transients can be spaced equally over

the clock period, reducing potential supply ripple and easing the

instantaneous current demand from the supply.

(14)

τ_SS= 150 ×C_SS

where C_SSis the value of the capacitor in microfarads, and ꢃ_SSis

the soft start time in milliseconds. To set a soft start time of 15 ms,

_SSshould equal 0.1 μF. A minimum soft start time of 10 ms is

recommended to ensure proper initialization of the ADN8830

on power-up.

C

Shutdown Mode

Using a single master clock, each slave ADN8830 should have a

different value phase shift. For example, with four TEC con-

trollers, one slave device should be set for 90° of phase shift,

another for 180°, and the last for 270°. In a daisy-chain configu-

ration, each slave device would be set with equal phase. Using

the previous example, each slave would be set to 90° with its

SYNCOUT pin connected to the next device’s SYNCIN pin.

Examples are shown in Figures 7 and 8.

The ADN8830 has a shutdown mode that deactivates the output

stage and puts the device into a low current standby state. The

current draw for the ADN8830 in shutdown is less than 100 μA.

The shutdown input, Pin 3, is active low. To shut down the

device, Pin 3 should be driven to logic low. Once a logic high is

applied, the ADN8830 will reactivate after the delay set by the

soft start circuitry. Refer to the Soft Start on Power-Up section

for more details on this feature.

Pin 3 should not be left floating as there are no internal pull-up

or pull-down resistors. If the shutdown function is not required,

Pin 3 should be tied to V_DDto ensure the device is always active.

25

7

28

24

ADN8830

NC

SLAVE

50k⍀

1k⍀

1nF

29

26

Compensation Loop

0.1␮F

The ADN8830 TEC controller has a built-in amplifier dedicated

for loop compensation. The exact compensation network is set

by the user and can vary from a simple integrator to PI, PID, or

any other type of network. The type of compensation and com-

ponent values should be determined by the user since it will

depend on the thermal response of the object and the TEC. One

method for determining these values empirically is to input a step

function to TEMPSET, thus changing the target temperature,

and adjusting the compensation network to minimize the set-

tling time of the object’s temperature.

150k⍀

V

DD

24

25

6

28

25

7

28

24

ADN8830

NC

MASTER

SLAVE

100k⍀

1k⍀

1nF

29

26

0.1␮F

R

FREQ

100k⍀

1.5M⍀

A typical compensation network used for temperature control

of a laser module is a PID loop, which consists of a very low

frequency pole and two separate zeros at higher frequencies.

Figure 9 shows a simple network for implementing PID com-

pensation. An additional pole is added at a higher frequency

than the zeros to reduce the noise sensitivity of the control loop.

The bode plot of the magnitude is shown in Figure 10.

25

7

28

24

ADN8830

NC

SLAVE

150k⍀

1k⍀

0.1␮F

1nF

29

26

1.5M⍀

50k⍀

Figure 7. Multiple ADN8830 Devices Driven from

a Master Clock

1nF

V

DD

1k⍀

0.1␮F

24

25

6

28

25

7

25

7

25

7

28

ADN8830

NC

MASTER

SLAVE

150k⍀

29

26

R

29

26

29

26

29

26

50k⍀

1.5M⍀

50k⍀

1.5M⍀

50k⍀

1.5M⍀

FREQ

Figure 8. Multiple ADN8830 Devices Using a Daisy Chain

–11–

D

REV.

ADN8830

The unity-gain crossover frequency of the feedforward amplifier

is given as

0dB

1

f_0dB

=

× 80 ×TEC GAIN

(15)

2πR3C1

R1

To ensure stability, the unity-gain crossover frequency should be

lower than the thermal time constant of the TEC and thermistor.

However, this thermal time constant may not be specified and

can be difficult to characterize.

R2||R3

R1

R3

There are many texts written on loop stabilization, and it is beyond

the scope of this data sheet to discuss all methods and trade-offs

in optimizing compensation networks. A simple method that

can be used to empirically determine a PID compensation loop

as shown in Figure 9 involves the following procedure:

1

2␲R3C1

2␲R1C1

2␲C2(R2+R3)

2␲R2C2

FREQUENCY (Hz LOG SCALE)

Figure 10. Bode Plot for PID Compensation

1. Connect thermistor and TEC to the ADN8830 application

circuit. Power does not need to be applied to the laser diode

for this procedure. Monitor output voltage across the TEC

with an oscilloscope.

2. Short C1 and open C2, leaving just R1 and R3 as a simple

proportional-only compensation loop.

3. While maintaining a constant TEMPSET voltage, increase

the ratio of R1/R3, thus increasing the gain until loop oscilla-

tion starts to occur. Decrease this ratio by a factor of 2 from

the point of oscillation. The R1/R3 ratio will likely be less

than unity for most laser modules.

4. Add C1 capacitor and decrease value until oscillation starts,

then increase by a factor of 2. A good initial starting value for

C1 is to create a unity-gain crossover of 0.1 Hz based on

Equation 15.

5. Short R2 and increase C2 until oscillation starts. At this point,

either C2 can be decreased or R2 can be added to regain

stability. Generally speaking, R2 will be greater than R3 and

C2 will be one or more orders of magnitude less than C1.

6. TEMPSET should be adjusted with a step change while

observing the output voltage settling time. A step change of

100 mV should suffice. From here, C2, R2, and even C1 can

be decreased to minimize settling time at the expense of

additional output voltage overshoot.

7. An additional feedback capacitor, CF, in parallel with R1

and C1, can be added to add another high frequency pole. In

many cases, this improves the stability of the system without

increasing the settling time as out-of-band noise is filtered

out of the control signal. A 330 pF to 1 nF capacitor should

suffice, if required.

Using the TEC Controller ADN8830 with a Wave Locker

Many optical applications require precision control of laser

wavelength. The wavelength of the laser diode can be adjusted

by changing its temperature, which is done through temperature

control of the TEC. Wavelength control can be done by feeding

a wave locker or etalon output back to the microprocessor and

using the microprocessor to calculate and reinstruct the TEC

controller with a new target temperature. However, this method

is computationally expensive and has time delays before the

adjustment is done. A faster responding and simpler method is

to feed the wave locker signal back to the TEC controller for

direct temperature control.

The ADN8830 is designed to be compatible with a wave locker

controller. Figure 11 shows the basic schematic. The TEMPCTL

output from ADN8830 is proportional to the object’s actual

temperature. This voltage is fed to the wave locker controller.

Also fed to the wave locker controller are the photodiode out-

puts from the wave locker, as well as the laser diode power and

a digital signal indicating a functional laser diode, both of which

come from the CW controller. The output of the wave locker

controller is then connected to the input of the compensation

network. This allows the wave locker controller to adjust the

TEC temperature based on the current temperature of the

object, the current wavelength of the laser diode, and the target

wavelength. Once the target wavelength is reached, the wave

locker controller sends a signal to the microcontroller indicating

that the laser signal is good.

␭ LOCKER

PD1

FROM ␭

LOCKER

The typical values shown in the typical application circuit in

Figure 1 have R1 = 100 kΩ, R2 = 1 MΩ, R3 = 205 kΩ, C1 = 10 μF

␭ LOCKER

PD2

,

C2 = 1 μF, and an additional feedback capacitor of 330 pF. For

most pump laser modules, this results in a 10°C TEMPSET step

settling time to within 0.1°C in less than 5 seconds.

WAVE LOCKER

GOOD

TO

ADN8830

LASER DIODE MICRO-

POWER

PROCESSOR

FROM CW

CONTROLLER

LASER DIODE

ADN8830

GOOD

TEC

CONTROL

TEMP IN

REFERENCE

VOLTAGE

TEMPCTL

12

COMPFB

13

COMPOUT

14

COMPOUT

TEMPCTL

12

COMPFB

13

R3

14

COMPENSATION

NETWORK

C1

R1

R2

C2

CF

Figure 11. Using the ADN8830 with a Wave Locker

Figure 9. Implementing a PID Compensation Loop

D

REV.

–12–

ADN8830

Using TEMPOUT to Measure Temperature

The TEMPOUT pin is a voltage that is proportional to the

difference between the target temperature and the measured

thermistor temperature. The full equation for the voltage at

TEMPOUT is

where V_{OUT A}and V_{OUT B}are the voltages at Pins 19 and 9, respec-

tively. The ripple voltage at Pin 19 is filtered out internally and

does not appear at VTEC, leaving it as an accurate dc output of

the TEC voltage.

The TEC is driven with a differential voltage, allowing current

to flow in either direction through the TEC. This can provide

heat transfer either to or from the object being regulated without

the use of a negative voltage rail. The maximum output voltage

across the TEC is set by the voltage at VLIM (Pin 15). Refer to

the Setting the Maximum TEC Voltage and Current section for

details on this operation. With VLIM set to ground, the maximum

TEMPOUT = 1.5 + 3 × THERMIN – TEMPSET

(16)

(

)

The voltage range of TEMPOUT is 0 V to 3.0 V and is inde-

pendent of power supply voltage.

Setting the Maximum TEC Voltage and Current

The ADN8830 can be programmed for a maximum output volt-

age to protect the TEC. A voltage from 0 V to 1.5 V applied to

the VLIM (Pin 15) input to the ADN8830 sets the maximum

TEC voltage, V_{TEC, MAX}. This voltage can be set with either a

resistor divider or from a DAC. Because the output of the

ADN8830 is bidirectional, this voltage sets both the upper

and lower limits of the TEC voltage. The equation governing

output voltage is the power supply voltage, V_DD

.

To achieve a differential output, the ADN8830 has two separate

output stages. OUT A is a switched output or pulse-width

modulated (PWM) amplifier, and OUT B is a high gain linear

amplifier. Although they achieve the same result, to provide

constant voltage and high current, their operation is different.

The exact equations for the two outputs are

V

_{TEC, MAX}is given in Equation 17 and the graph of this equation

is shown in Figure 12.

OUT A = 4 × COMPOUT – 1.5 + OUT B

(19)

(20)

(

)

V_{TEC, MAX}= 1.5V –VLIM × 4

(17)

(

)

OUT B = –14 × COMPOUT – 1.5 + 1.5

(

)

5

4

3

2

1

0

where COMPOUT is the voltage at Pin 13. The voltage at

COMPOUT is determined by the compensation network that is

fed by the input amplifier, which receives its input voltage from

TEMPSET and THERMIN. Equation 20 is valid only in the

linear region of the linear amplifier. OUT B has a lower limit of

0 V and an upper limit of the power supply.

Because the COMPOUT voltage is not readily known, Equa-

tion 20 can be rewritten in terms of the TEC voltage, VTEC,

which is defined as OUT B – OUT A.

OUT B = 4 ×VTEC +1.5

(21)

In Figure 1, Pins 10 and 11 provide the gate drive for Q3 and Q4,

which complete the linear output amplifier. This output voltage

is fed back to Pin 9 (OUT B) to close its loop. The gate-to-drain

capacitance of Q3 and Q4 provide the compensation for the

linear amplifier. If using the recommended FDW2520C transistors,

it will be necessary to add an additional 2.2 nF of capacitance

from the gate to the drain of the PMOS transistor to maintain

stability. A 3.3 nF capacitor should also be connected from the

drain to ground to prevent small oscillations when there is very

little or no current through the TEC.

0

0.5

1.0

VLIM (V)

1.5

2.0

Figure 12. VLIM Voltage vs. Maximum TEC Voltage

If the supply voltage is lower than V_{TEC, MAX}, the maximum TEC

voltage will obviously be equal to the supply voltage. The voltage

to VLIM should not exceed 1.5 V since this causes improper

operation of the output voltage limiting circuitry. Setting VLIM to

1.5 V can be used to deactivate the TEC current without

shutting down the ADN8830 in the event of a system failure. If a

maximum TEC voltage is not required, VLIM should be con-

nected to ground. It is not advisable to leave VLIM floating as

this would cause unpredictable output behavior.

These extra capacitors are specified only when using FDW2520C

transistors in the linear amplifier. If other transistors are used,

these values may need to be adjusted. To ensure the linear

amplifier is stable, the total gate-to-source capacitance for both

Q3 and Q4 should be at least 2.5 nF. Refer to the transistor’s

data sheet for its typical gate-to-drain capacitance values.

This feature should be used to limit the maximum output current

to the TEC as specified in the TEC data sheet. For example, if

the maximum TEC voltage is specified at 2 V, VLIM should be

set to 1 V. The maximum output voltage is then set to 2 V.

The output of the linear amplifier is proportional to the voltage

at Pin 13 (COMPOUT). Because the linear amplifier operates

with a gain of 14, its output will typically be at either ground or

V_DDif there is more than about 100 mA of current flowing

through the TEC. This ensures Q3 and Q4 will not be a domi-

nant source of power dissipation at high output currents.

Output Driver Amplifiers

The output voltage across the TEC as measured from Pin 19 to

Pin 9 can be monitored at Pin 16. This is labeled as VTEC in

the typical application schematic in Figure 1. The voltage at

VTEC can vary from 0 V to 3 V independent of the power

supply voltage. Its equation is given as

VTEC = 0.25 × V

–V_{OUT B}+ 1.5

(18)

(

)

OUT A

D

REV.

–13–

ADN8830

Inductor Selection

I_{L, MAX}= I_{TEC, MAX}+ 0.5 × ΔI_L

where ꢁI_Lcan be found from Equation 23 with the appropriate

(24)

In addition to the external transistors, the PWM amplifier requires

an inductor and a capacitor at its output to filter the switched

output waveform. Proper inductor selection is important to

achieve the best efficiency. The duty cycle of the PWM sets the

OUT A output voltage and is

duty cycle calculated from Equation 22 with OUT A = V_{TEC, MAX}

.

Design Example 3

A TEC is specified with a maximum current of 1.5 A and maxi-

mum voltage of 2.5 V. The ADN8830 will be operating from a

3.3 V supply voltage with a 200 kHz clock and a 4.7 μH inductor.

The duty cycle of the PWM amplifier at 2.5 V is calculated to be

75.8%. Using Equation 23, the inductor ripple current is found

to be 664 mA. From Equation 24, the maximum inductor current

will be 1.82 A and should be considered when selecting the

inductor. Notice that increasing the clock frequency to 1 MHz would

reduce I_{L, MAX}to 1.56 A.

OUT A

V_DD

D =

(22)

The average current through the inductor is equal to the TEC

current. The ripple current through the inductor, ꢁI_L, varies

with the duty cycle and is equal to

V_DD× D × 1– D

(

)

ΔI_L

=

(23)

L × f_CLK

Design Example 4

where f_CLKis the clock frequency as set by the resistor R_FREQat

Pin 26 or an external clock frequency. Refer to the Setting the

Switching Frequency section for more information. Selecting a

faster switching frequency or a larger value inductor will reduce

the ripple current through the inductor. The waveform of the

inductor current is shown in Figure 13.

Using the same TEC as above, the ADN8830 will be powered

from 5.0 V instead. Here, the duty cycle is 50%, which happens

to be the worst-case duty cycle for inductor current ripple. Now

DIL equals 1.33 A with a 200 kHz clock, and I_{L, MAX}is 2.83 A.

Reducing the inductor ripple current is another compelling

reason to operate the ADN8830 from a 3.3 V supply instead.

Table II lists some inductor manufacturers and part numbers

along with some key specifications. The column I_MAXrefers to the

maximum current at which the inductor is rated to remain linear.

Although higher currents can be pushed through the inductor,

efficiency and ripple voltage will be dramatically degraded.

I

TEC

ΔI

L

This is by no means a complete list of manufacturers or inductors

that can be used in the application. More information on these

inductors is available at their websites. Note the trade-offs

between inductor height, maximum current, and series resistance.

Smaller inductors cannot handle as muèH current and therefore

require higher clock speeds to reduce their ripple current. They

also have higher series resistance, which can lower the overall

efficiency of the ADN8830.

1

f_CLK

T =

TIME

PWM Output Filter Requirements

The switching of Q1 and Q2 creates a pulse width modulated

(PWM) square wave from 0 V to V_DD. This square wave must

be filtered sufficiently to create a steady voltage that will drive

the TEC. The ripple voltage across the TEC is a function of the

inductor ripple current, the L-C filter cutoff frequency, and the

equivalent series resistance (ESR) of the filter capacitor. The

equivalent circuit for the PWM side is given in Figure 14.

Figure 13. Current Waveform Through Inductor

It is important to select an inductor that can tolerate the maxi-

mum possible current that could pass through it. Most TECs

are specified with a maximum voltage and current for proper

and reliable operation. The maximum instantaneous inductor

current can be found as

Table II. Partial List of Inductors and Key Specifications

Inductance (␮H)

I_MAX(A)

R_{S, TYP}(m⍀)

Height (mm) Part Number

Manufacturer Website

4.7

4.7*

10

1.1

1.59

3.9

1.5

1.32

7.5

5.4

2.7

8

200

55

48

90

56

12

18

80

32

86

1

2

2.8

3

4.5

5.2

2.8

8

LPO1704-472M

A918CY-4R7M

UP2.8B-4R7

DO1608C-472

CDRH4D28 4R7

892NAS-4R7M

DO3316P-472

UP2.8B-100

Coilcraft

Toko

Cooper

Coilcraft

Sumida

Toko

www.coilcraft.com

www.toko.com

www.cooperet.com

www.coilcraft.com

www.sumida.com

www.toko.com

www.coilcraft.com

www.cooperet.com

www.coilcraft.com

Coilcraft

Cooper

15

47

DO5022P-153HC Coilcraft

DO5022P-473 Coilcraft

4.5

7.1

*Recommend inductor in typical application circuit Figure 1.

D

REV.

–14–

ADN8830

PVDD

Q1

Calculating PWM Output Ripple Voltage

OUT A

OUT B

Although it may seem that f_Ccan be arbitrarily lowered to reduce

output ripple, the ripple voltage is also dependent on the ESR of

C1, shown as R1 in Figure 14. This resistance creates a zero

that turns the second-order filter into a first-order filter at high

frequencies. The location of this zero is

P1

N1

R2

L1

R

L

V

X

R1

C1

Q2

DENOTES

PGND

1

Z1 =

(28)

2πR1C1

Figure 14. Equivalent Circuit for PWM Amplifier and Filter

With a clock frequency greater than Z1, and presumably greater

than f_C, the output voltage ripple is

In this circuit, R_Lis the TEC resistance, R2 is the parasitic

resistance of the inductor combined with the equivalent r_{DS, ON}

of Q1 and Q2, and R1 is the ESR of C1. The voltage, V_X, is the

pulse-width modulated waveform that switches between PVDD

and ground. This is a second-order low-pass filter with an exact

cutoff frequency of

(29)

ΔOUT A = ΔI_L× R1

V_DDD 1– D R1

(

)

ΔOUT A =

for f

> Z1

(

)

(30)

CLK

L1f_CLK

The worst-case voltage ripple occurs when the duty cycle of the

PWM output is exactly 50%, or when OUT A = 0.5 ꢅ V_DD. As

shown in Equation 31

1

2π

R2 + R_L

f_C

=

(25)

R1+ R C1L1

(

)

L

Practically speaking, R1 and R2 are several tens of milliohms and

are much smaller than the TEC resistance, which can be a few

ohms. The cutoff frequency can be roughly approximated as

V_DDR1

4 f_CLKL1

ꢁOUT A_MAX

≈

for f

> Z1

(

)

(31)

CLK

Here it can be directly seen that increasing the inductor value or

clock frequency will reduce the ripple. Choosing a low ESR

capacitor will ensure R1 remains low. Operating from a lower

supply voltage will also help reduce the output ripple voltage

from the L-C filter. With a clock frequency equal to Z1 but

presumably greater than f_C, the worst-case output voltage ripple is

1

f_C

=

(26)

2π C1L1

This cutoff frequency should be much lower than the clock

frequency to achieve adequate filtering of the switched output

waveform. Also of importance is the damping factor, ꢄ, of the

L-C filter. Too low a damping factor will result in a longer

settling time and could potentially cause stability problems for

the temperature control loop. Neglecting R1 and R2 again, the

damping factor is simply

2

16R1²C1²f_CLK+ 1

(

)

(32)

ΔOUT A_MAX=V_DD

for f

= Z1

(

)

CLK

32L1C1f_CLK

Which, if f_CLK< Z1, can be further simplified to

1

L1

V_DD

ζ =

ΔOUT A_MAX

=

for f

< Z1

(27)

(33)

(

)

CLK

2

2R_LC1

32L1C1f_CLK

Using the recommended values of L1 = 4.7 μH and C1 = 22 μF

results in a cutoff frequency of 15.7 kHz. With a TEC resistance

of 2 Ω, the damping factor is 0.12. The cutoff frequency can be

decreased to lower the output voltage ripple with slower clock

frequencies by increasing L1 or C1. Increasing C1 may appear

to be a simpler approach as it would not increase the physical

size of the inductor, but there is a potential stability danger in

lowering the damping factor too far. It is recommended that ζ

remain greater than 0.05 to provide a reasonable settling time

for the TEC. Increasing ζ also makes finding the proper PID

compensation easier as there is less ringing in the L-C output

filter. To allow adequate phase and gain margin for the PWM

amplifier, Table III should be used to find the lower limit of

cutoff frequency for a given damping factor.

A typical 100 μF surface-mount electrolytic capacitor can have

an ESR of over 100 mΩ, pulling this zero to below 16 kHz, and

resulting in an excess of ripple voltage across the TEC. Low ESR

capacitors, such as ceramic or polymer aluminum capacitors,

are recommended instead. Polymer aluminum capacitors can

provide more bulk capacitance per unit area over ceramic ones,

saving board space. Table IV shows a limited list of capacitors

with their equivalent series resistances.

This is by no means a complete list of all capacitor manufacturers

or capacitor types that can be used in the application. The 22 μF

capacitor recommended has a maximum ESR of 35 mΩ, which

puts Z1 at 207 kHz. Using a 3.3 V supply with the recommended

inductor and capacitor listed with a 1 MHz clock frequency will

yield a worst-case ripple voltage at OUT A of about 6 mV.

Table III. Minimum L-C Filter Cutoff

Frequency vs. Damping Factor

External FET Requirements

External FETs are required for both the PWM and linear amplifiers

that drive OUT A and OUT B from the ADN8830. Although it

is important to select FETs that can supply the maximum current

required to the TEC, they should also have a low enough resis-

tance (r_{DS, ON}) to prevent excessive power dissipation and improve

efficiency. Other key requirements from these FET pairs are

slightly different for the PWM and linear outputs.

␨

f_{C, MIN}(kHz)

0.05

0.1

0.2

8

4

2

0.3

0.5

> 0.707

1.9

1.6

1.5

D

REV.

–15–

ADN8830

The gate drive outputs for the PWM amplifier at P1 (Pin 21)

and N1 (Pin 22) have a typical nonoverlap delay of 65 ns.

This is done to ensure that one FET is completely off before

the other FET is turned on, preventing current from shooting

through both simultaneously.

Bear in mind that the addition of these capacitors is only

for local stabilization. The stability of the entire TEC appli-

cation may need adjustment, which should be done around the

compensation amplifier. This is covered in the Compensation

Loop section.

The input capacitance (C_ISS) of the FET should not exceed 5 nF.

The P1 and N1 outputs from the ADN8830 have a typical output

impedance of 6 Ω. This creates a time constant in combination

with C_ISSof the external FETs equal to 6 Ω ꢅ C_ISS. To ensure

shoot-through does not occur through these FETs, this time

constant should remain less than 30 ns.

There is one additional consideration for selecting both the

linear output FETs; they must have a minimum threshold

voltage (V_T) of 0.6 V. Lower threshold voltages could cause

shoot-through current in the linear output transistors.

Table V shows the recommended FETs that can be used for the

linear output in the ADN8830 application. Table V includes the

The linear output from the ADN8830 uses N2 (Pin 10) and

P2 (Pin 11) to drive the gates of the linear side FETs, shown as

Q3 and Q4 in Figure 1. Local compensation for the linear ampli-

fier is achieved through the gate-to-drain capacitances (C_GD) of

Q3 and Q4. The value of C_GD, which can be determined from

the data sheet, is usually referred to as C_RSS, the reverse transfer

capacitance. The exact C_RSSvalue should be determined from a

graph that shows capacitance versus drain-to-source voltage,

appropriate external gate-to-drain capacitance (external C_GD)

and snubber capacitor value (C_SNUB) connected from OUT B to

ground that should be added to ensure local stability. Table VI

shows the recommended PWM output FETs. Although other

transistors can be used, these combinations have been tested

and are proved stable and reliable for typical applications.

Data sheets for these devices can be found at their respective

websites:

using the power supply voltage as the appropriate V_DS

.

Fairchild – www.fairchildsemi.com

Vishay Siliconix – www.vishay.com

International Rectifier – www.irf.com

To ensure stability of the linear amplifier, the total C_GDof the

PMOS device, Q3, should be greater than 2.5 nF and the total

C_GDof the NMOS should be greater than 150 pF. External

capacitance can be added around the FET to increase the effective

C_GDof the transistor. This is the function of C6 in the typical

application schematic shown in Figure 1. If external capacitance

must be added, it will generally only be required around the

PMOS transistor.

Calculating Power Dissipation and Efficiency

The total efficiency of the ADN8830 application circuit is simply

the ratio of the output power to the TEC divided by the total

power delivered from the supply. The idea in minimizing power

dissipation is to avoid both drawing additional power and reduc-

ing heat generated from the circuit. The dominant sources

of power dissipation will include resistive losses, gate charge

loss, core loss from the inductor, and the current used by the

ADN8830 itself.

In the event of zero output current through the TEC, there will

be no current flowing through Q3 and Q4. In this condition,

these FETs will not provide any small signal gain and thus no

negative feedback for the linear amplifier. This leaves only a

feedforward signal path through C_GD, which could cause a

settling problem at OUT B. This is often seen as a small signal

oscillation at OUT B, but only when the TEC is at or very near

zero current.

The on-channel resistance of both the linear and PWM output

FETs will affect efficiency primarily at high output currents.

Because the linear amplifier operates in a high gain configuration,

it will be at either ground or V_DDwhen significant current is

flowing through the TEC. In this condition, the power dissipation

through the linear output FET will be

The remedy for this potential minor instability is to add

capacitance from OUT B to ground. This may need to be deter-

mined empirically, but a good starting point is 1.5 times the

total C_GD. This is the function of C12 in Figure 1. Note that

while adding more C_GDaround Q3 and Q4 will help to ensure

stability, it could potentially increase instability in the zero current

dead band region, requiring additional capacitance from

OUT B to ground.

2

(34)

P_FET,LIN= r_{DS ,ON}× I_TEC

using either the r_{DS, ON}for the NMOS or the PMOS depending

on the direction of the current flow. In the typical application

setup in Figure 2, if the TEC is cooling the target object, the

PMOS is sourcing the current. If the TEC is heating the

object, the NMOS will be sinking current.

Table IV. Partial List of Capacitors and Key Specifications

Value (␮F)

ESR (m⍀)

Voltage Rating (V)

Part Number

Manufacturer

Website

10

22*

22

47

68

100

60

35

25

18

95

6.3

8

6.3

8

NSP100M6.3D2TR

ESRD220M08B

NSP220M8D5TR

EEFFD0K220R

NSP470M6.3D2TR

ESRD680M08B

594D107X_010C2T

NIC Components

Cornell Dubilier

NIC Components

Panasonic

NIC Components

Cornell Dubilier

Vishay

www.niccomp.com

www.cornell-dubilier.com

www.niccomp.com

www.maco.panasonic.co.jp

www.niccomp.com

www.cornell-dubilier.com

www.vishay.com

10

*Recommend capacitor in typical application circuit Figure 1.

D

REV.

–16–

ADN8830

Although the FETs that drive OUT A alternate between Q1 and

Q2 being on, they have an equivalent series resistance that is

equal to a weighted average of their r_{DS, ON}values.

total current used by the ADN8830. The power dissipated from

the device itself is

(40)

P_ADN8830=V_DD×10 mA

R_EQIV= D × r_{DS, P1}+ 1– D × r

(35)

(

)

DS, N1

There are certainly other minor mechanisms for power dissipa-

tion in the circuit. However, a rough estimate of the total power

dissipated can be found by summing the preceding power dissi-

pation equations. Efficiency is then found by comparing the

power dissipated with the required output power to the load.

The resistive power loss from the PWM transistors is then

2

(36)

P_FET,PWM= R_EQIV× I_TEC

There is also a power loss from the continuing charging and

discharging of the gate capacitances on Q1 and Q2. The power

dissipated due to gate charge loss (P_GCL) is

P_LOAD

Efficiency =

(41)

P_LOAD+ P_{DISS, TOT}

1

2

where

P_GCL

=

C_ISSV_DDf_CLK

(37)

P_LOAD= I_LOAD×V_LOAD

using the appropriate input capacitance (C_ISS) for the NMOS

and PMOS. Both transistors are switching, so P_GCLshould be

calculated for each one and will be added to find the total power

dissipated from the circuit.

The measured efficiency of the system will likely be less than the

calculated efficiency. Measuring the efficiency of the application

circuit is fairly simple but must be done in an exact manner to

ensure the correct numbers are being measured. Using two high

current, low impedance ammeters and two voltmeters, the cir-

cuit should be set up as shown in Figure 15.

The series resistance of the inductor, R2 from Figure 14, will

also exhibit a power dissipation equal to

2

(38)

P_R2= R2 × I_TEC

POWER SUPPLY

Core loss from the inductor arises as a result of nonidealities of

the inductor. Although this is difficult to calculate explicitly, it

can be estimated as 80% of P_RLSat 1 MHz switching frequen-

cies and 50% of P_RLat 100 kHz. Judging conservatively

V

GND

DD

A

V

(39)

P_LOSS= 0.8 × P_RL

A

TEC

LOAD

Finally, the power dissipated by the ADN8830 is equal to the

current used by the device multiplied by the supply voltage.

Again, this exact equation is difficult to determine as we have

already taken into account some of the current while finding the

gate charge loss. A reasonable estimate is to use 40 mA as the

ADN8830

V

Figure 15. Measuring Efficiency of the ADN8830 Circuit

Table V. Recommended FETs for Linear Output Amplifier

Part Number

Type

C_GD(nF)

Ext. C_GD(nF) C_SNUB(nF)

r_{DS, ON}(m⍀) I_MAX(A)

Manufacturer

FDW2520C*

NMOS

PMOS

NMOS

PMOS

NMOS

PMOS

0.17

0.15

0.5

2.2

0.23

0.6

18

35

22

20

9.5

12

6.0

4.5

8.7

9.5

11.5

10

Fairchild

International Rectifier

Fairchild

2.2

1.0

3.3

IRF7401

IRF7233

FDR6674A

FDR840P

Fairchild

*Recommend transistors in typical application circuit Figure 1.

Table VI. Recommended FETs for PWM Output Amplifier

Part Number

Type

C_ISS(nF)

r_DS,ON(m⍀)

Continuous I_MAX(A)

Manufacturer

FDW2520C*

NMOS

PMOS

NMOS

PMOS

NMOS

PMOS

1.33

1.0

3.5

1.6

18

35

30

17

22

40

6.0

4.5

5.3

7.3

8.7

6.7

Fairchild

Vishay Siliconix

International Rectifier

Si7904DN

Si7401DN

IRF7401

IRF7404

1.5

*Recommend transistors in typical application circuit Figure 1.

D

REV.

–17–

ADN8830

The voltmeter to the TEC or output load should include the series

ammeter since the power delivered to the ammeter is considered part

of the total output power. However, the voltmeter measuring the

voltage delivered to the ADN8830 circuit should not include the

series ammeter from the power supply. This prevents a false supply

voltage power measurement since we are interested only in the

supply voltage power delivered to the ADN8830 circuit. Figures 16

and 17 show some efficiency measurements using the typical appli-

cation circuit shown in Figure 1.

POWER SUPPLY

GND

V

DD

AVDD

AGND

PGND

PVDD

NOISE

SENSITIVE

SECTION

TEC

OR

LOAD

OUTPUT

SECTION

100

Figure 18. Using Star Connections to Minimize

Noise Pickup from Switched Output

V

= 3V

SY

The low noise power and ground are referred to as AVDD and

AGND, with the output supply and ground paths labeled PVDD

and PGND. These pins are labeled on the ADN8830 and should

be connected appropriately. Both sets of external FETs should be

connected to PVDD and PGND. All output filtering and PVDD

supply bypass capacitors should be connected to PGND.

80

60

40

20

0

V

= 5V

SY

All remaining connections to ground and power supply should be

done through AVDD and AGND. A 4-layer board layout is rec-

ommended for best performance with split power and ground

planes between the top and bottom layers. This provides the

lowest impedance for both supply and ground points. Setting the

ADN8830 above the AGND plane will reduce the potential noise

injection into the device. Figure 19 shows the top layer of the

layout used for the ADN8830 evaluation boards, highlighting the

power and ground split planes.

0

500

1,000

(mA)

1,500

2,000

I

TEC

Figure 16. Efficiency with f_CLK= 1 MHz

100

80

60

40

20

0

V

= 3V

SY

V

= 5V

SY

0

500

1,000

(mA)

1,500

2,000

I

TEC

Figure 17. Efficiency with f_CLK= 200 kHz

Note that higher efficiency can be achieved using a lower supply

voltage or a slower clock frequency. This is due to the fact that the

dominant source of power dissipation at high clock frequencies is the

gate charge loss on the PWM transistors.

Figure 19. Top Layer Reference Layout for ADN8830

Layout Considerations

Proper supply voltage bypassing should also be taken into consid-

eration to minimize the ripple voltage on the power supply. A

minimum bypass capacitance of 10 μF should be placed in close

proximity to each component connected to the power supply. This

includes Pins 8 and 20 on the ADN8830 and both external PMOS

transistors. An additional 0.1 μF capacitor should be placed in

parallel to each 10 μF capacitor to provide bypass for high fre-

quency noise. Using a large bulk capacitor, 100 μF or greater, in

parallel with a low ESR capacitor where AVDD and PVDD con-

nect will further improve voltage supply ripple. This is covered in

more detail in the Power Supply Ripple section.

The two key considerations for laying out the board for the

ADN8830 are to minimize both the series resistance in the output

and the potential noise pickup in the precision input section. The

best way to accomplish both of these objectives is to divide the

layout into two sections, one for the output components and the

other for the remainder of the circuit. These sections should have

independent power supply and ground current paths that are each

connected together at a single point near the power supply. This is

used to minimize power supply and ground voltage bounce on the

more sensitive input stages to the ADN8830 caused by the switch-

ing of the PWM output. Such a layout technique is referred to as a

“star” ground and supply connection. Figure 18 shows a block dia-

gram of the concept.

D

REV.

–18–

ADN8830

Power Supply Ripple

A 10 mΩ resistor placed in series with the PVDD supply line creates a

voltage drop proportional to the absolute value of the output current.

The AD8601 is a CMOS amplifier that is configured as a com-

parator. As long as the voltage at its inverting input (V_S) exceeds

the voltage set by the resistor divider at the noninverting input (V_X),

the gate of Q1 will remain at ground. This leaves Q1 on, effectively

connecting D1 to the positive rail and leaving the voltage on C1 at

V_DD. Should enough current flow through R_Sto drop V_Sbelow V_X,

Q1 will turn off and C1 will discharge through R2 down to a logic

low to activate the ADN8830 shutdown. Once V_Sreturns to a

voltage greater than V_X, Q1 will turn back on and C1 will charge

back to V_DDthrough R1. The shutdown and reactivation time

constants are approximately

Minimizing ripple on the power supply voltage can be an impor-

tant consideration, particularly in signal source laser applications.

If the laser diode is operated from the same supply rail as the TEC

controller, ripple on the supply voltage could cause inadvertent

modulation of the laser frequency. As most laser diodes are driven

from a 5 V supply, it is recommended the ADN8830 be operated

from a separate 3.3 V regulated supply unless higher TEC voltages

are required. Operation from 3.3 V also improves efficiency, thus

minimizing power dissipation.

The power supply ripple is primarily a function of the supply by-

pass capacitance, also called bulk capacitance, and the inductor

ripple current. Similar to the L-C filter at the PWM amplifier

output, using more capacitance with low equivalent series resis-

tance (ESR) will lower the supply ripple. A larger inductor value

will reduce the inductor ripple current, but this may not be

practical in the application. A recommended approach is to use a

standard electrolytic capacitor in parallel with a low ESR capacitor.

A surface-mount 220 μF electrolytic in parallel with a 22 μF poly-

mer aluminum low ESR capacitor can occupy an approximate total

board area of only 0.94 square inches or 61 square millimeters.

Using these capacitors along with a 4.7 μH inductor can yield a

supply ripple of less than 5 mV.

ꢃ_SD= C1× R1

ꢃ_ON= C1× R1

(42)

The shutdown time constant should be a minimum of 10 clock

cycles to ensure high current switching transients do not trigger a

false activation. If powered from 5 V, the circuit shown will shut

down the ADN8830 should PVDD deliver over 5 A for more than

1 ms. After shutdown, the circuit will reactivate the ADN8830 in

about 1 second.

The voltage drop across R_Sis found as

I_OUT²R_LR_S

High frequency transient spikes may appear on the supply voltage

as well. This is due to the fast switching times on the PWM transis-

tors and the sharp edges of their gate voltages. Although these

transient spikes can reach several tens of millivolts at their peak,

they typically last for less than 20 ns and have a resonance greater

than 100 MHz. Additional bulk capacitance will not appreciably

affect the level of these spikes as such capacitance is not reactive at

these frequencies. Adding 0.01 μF ceramic capacitors on the sup-

ply line near the PWM PMOS transistor can reduce this switching

noise. Inserting an RF inductor with a High-Q around 100 MHz in

series with PVDD will also block this noise from traveling back to

the power supply.

V_R

=

(43)

S

ηV_DD

where R_Lis the load resistance or resistance of the TEC and ꢆ is

the efficiency of the system. An estimate of efficiency can be calculated

either from the Calculating Power Dissipation and Efficiency section

or from Figures 16 and 17. A reasonable approximation is ꢆ =

0.85. Although the exact resistance of a TEC varies with tempera-

ture, an estimation can be made by dividing the maximum voltage

rating of the TEC by its maximum current rating.

In addition to providing protection against a short at the output,

this circuit will also protect the FETs against shoot-through current.

Shoot-through will not occur when using the recommended

transistors and additional capacitance shown in Tables V and VI.

However, if different transistors are used where their shoot-

through potential is unknown, implementing the short-circuit

protection circuit will unconditionally protect these transistors.

Setting Maximum Output Current and Short-Circuit

Protection

Although the maximum output voltage can be programmed

through VLIM to protect the TEC from overvoltage damage,

the user may wish to protect the ADN8830 circuit from a possible

short circuit at the output. Such a short could quickly damage the

external FETs or even the power supply since they would attempt

to drive excessive current. Figure 20 shows a simple modification

that will protect the system from an output short circuit.

To set a maximum output current limit, use the circuit in Figure

21. This circuit can share the 10 mΩ power supply shunt resistor

as the short-circuit protection circuit to sense the output current.

In normal operation Q1 is on, pulling the ADN8830 VLIM pin

down to the voltage set by VLIMIT. This sets the maximum out-

put voltage limit as described in the Setting the Maximum TEC

Voltage and Current section.

V

S

PVDD

AVDD

R

S

TO

FETS

10m⍀

AND

DECOUPLING

CAPS

PVDD

R3

V

SY

PVDD

AVDD

R1

R

R1

1M⍀

TO

FETS

AND

Q1

S

FDV304P

1k⍀

10m⍀

OR EQUIVALENT

3.48k⍀

DECOUPLING

CAPS

AD8601

PVDD

R3

SD

TO

VLIM

R4

100k⍀

D1

Q1

R2

1k⍀

R2

V

C1

1␮F

MA116CT-ND

OR

C1

1nF

FDV301N

OR

X

1.47k⍀

178⍀

EQUIVALENT

AD8605

R4

100k⍀

V

X

DENOTES

AGND

DENOTES

PGND

VLIMIT

(0VTO 1.5V)

Figure 20. Implementing Output Short-Circuit Protection

DENOTES

AGND

DENOTES

PGND

Figure 21. Setting a Maximum Output Current Limit

D

REV.

–19–

ADN8830

5V

I

OUTA

ADT70

I

OUTB

+IN

OA

TOTHERM_IN

= 1V @ 25؇C

R3

82.5⍀

OUT

OA

25mV/؇C

+IN

IA

RGA

RGB

INST

AMP

4.99k⍀

R3

82.5⍀

–IN

IA

RTD

1k⍀

R3

1k⍀

GND

SENSE

AGND

OUT

–IN

OA

IA

1k⍀

NOTE: ADDITIONAL PINS OMITTED FOR CLARITY

5.11k⍀

Figure 22. Using an RTD for Temperature Feedback to the ADN8830

AVDD

R1

AVDD

R

If the voltage at V_SYdrops below V_X, Q1 is turned off and the

VLIM pin will be set to 1.5 V, effectively setting the maximum

voltage across the outputs to 0 V. The voltage divider for V_Xis

calculated from Equation 43.

S

10m⍀

TO

TEC

TO

200k⍀

OUT B

3.48k⍀

V

HI

TO

I

AVDD

L

VLIM

R2

1.47k⍀

1nF

300k⍀

Design Example 5

Q1,Q2

FDG6303N

OR

EQUIVA-

LENT

A maximum output current limit needs to be set at 1.5 A for a

TEC with a maximum voltage rating of 2.5 V. The ADN8830 is

powered from 5 V. The TEC resistance is estimated at 1.67 Ω and

efficiency at 85%. Using Equation 43, the voltage drop across

R_Swill be 8.8 mV when 1.5 A is delivered to the TEC. The trip

voltage V_Xis set to 4.991 V with R3 = 178 Ω and R4 = 100 kΩ

as shown in Figure 21. To set the output voltage limit to 2.5 V,

the voltage at VLIMIT should be set to 0.875 V according to

Equation 17.

8

V

X

AD8602

AD626

300k⍀

200k⍀

V

TO

VREF

LO

VLIMIT

(0VTO 1.5V)

Figure 23. High Accuracy Output Current Limit

The C1 capacitor is added to smooth the voltage transitions at

VLIM. Once an overcurrent condition is detected, the output

voltage will turn down to 0 V within 30 ms.

The upper and lower trip point voltages can be set independently,

allowing different maximum output current limits depending on

the direction of the current. The resistor divider for VHI and

VLO is tapped to VREF to maintain window accuracy with any

changes in VREF. Using the values from Figure 23 with a 5 V

supply, the output current will not exceed 1.5 A in either direction.

For a more exact measurement of the output current, place a

sense resistor in series with the output load, as shown in Figure 23.

The AD626 instrumentation amplifier is set for a gain of 100

with a reference voltage of 2.47 V from VREF. The output of

the AD626 is equal to 100 × R_S× I_Land is fed to the AD8602,

which is set up as a window comparator. With V_Xgreater than

VLO but less than VHI, VLIM will be pulled down to the volt-

age at VLIMIT. Should V_Xfall outside the voltage window,

VLIM will be pulled to 1.5 V as in Figure 21. The trip points

should be set according to

Adding the current sensing resistor will slightly reduce efficiency.

The power dissipated by this resistor is D × ITEC2 × R_Sif the

TEC is heating, or (1–D) × ITEC2 × R_Sif the TEC is cooling.

Include this when calculating efficiency as described in the

Calculating Power Dissipation and Efficiency section.

VHI =VREF +100 × R_SI_{LIMIT +}

VLO =VREF –100 × R_SI_{LIMIT –}

(44)

D

REV.

–20–

ADN8830

PVDD

Q1

OUT A

Using an RTD for Temperature Sensing

The ADN8830 can be used with a resistive temperature device

(RTD) as the temperature feedback sensor. The resistance of an

RTD is linear with respect to temperature, offering an advan-

tage over thermistors that have an exponential relationship to

temperature. A constant current applied through an RTD will

yield a voltage proportional to temperature. However, this volt-

age could be on the order of only 0.5 mV/°C, thus requiring the

use of additional amplification to achieve a usable signal level.

P1

N1

L1

R

L

OUT B

N2

Q2

Q3

C1

NO CONNECTIONTO P2 REQUIRED

The ADT70 from Analog Devices can be used to bias and amplify

the voltage across an RTD, which can then be fed directly to the

THERMIN pin on the ADN8830 to provide temperature

feedback for the TEC controller. The ADT70 uses a 0.9 mA

current source to drive the RTD and an instrumentation ampli-

fier with adjustable gain to boost the RTD voltage. Application

notes and typical schematics for this device can be found in the

ADT70 Data Sheet.

Figure 24. Using the ADN8830 to Drive a Heating Element

Current is delivered from the PWM amplifier through Q3 when

the voltage at THERMIN is lower than TEMPSET. If the object

temperature is greater than the target temperature, Q3 will turn

off and the current through the load goes to zero, allowing the

object to cool back toward the ambient temperature. As the

target temperature is approached, a steady output current should

be reached. Naturally, a proper compensation network must be

found to ensure stability and adequate temperature settling time.

The P2 output from the ADN8830 should be left unconnected.

Most RTDs have a positive temperature coefficient, also called

tempco, as opposed to thermistors, which have a negative tempco.

For the OUT A output to drive the TEC– input as shown in

Figure 1, the signal from an RTD must be conditioned to create

a negative tempco. This can be easily done using an inverting

amplifier. Alternately, OUT A can be connected to drive TEC+

with OUT B driving TEC– with a positive tempco at THERMIN.

This is highlighted in the Output Driver Amplifiers section.

Suggested Pad Layout for CP-32 Package

Figure 25 shows the dimensions for the PC board pad layout for

the ADN8830, which is a 5 ꢅ 5, 32-lead lead frame chipscale

package. This package has a metallic heat slug that should be

soldered to a copper pad on the PC board. Although the pack-

age slug is electrically connected to the substrate of the IC, the

copper pad should be left electrically floating. This prevents

potential noise injection into the substrate while maintaining

good thermal conduction to the PC board.

For the ADN8830, proper operation care should be taken

to ensure the voltage at THERMIN remains within 0.4 V

and 2.0 V. Using a 1 kΩ RTD with the ADT70 will yield a

THERMIN voltage of 0.9 V at 25°C. Using the application

circuit shown in Figure 22 will provide a nominal output

voltage of 1.0 V at 25°C and a total gain of 66.7 mV/Ω.

Using an RTD with a temperature coefficient of 0.375 Ω/°C

will give a THERMIN voltage swing from 1.5 V at 5°C to

0.5 V at 45°C, well within the input range of the ADN8830.

0.69

(0.0272)

0.10

(0.0039)

0.28

(0.0110)

Using a Resistive Load as a Heating Element

3.78

(0.1488)

5.36

(0.2110)

The ADN8830 can be used in applications that do not neces-

sarily drive a TEC but require only a high current output into a

load resistance. Such applications generally only require heating

above ambient temperature and simply use the power dissipated

by the load element to accomplish this. Because the power

dissipated by such an element is proportional to the square of

the output voltage, the ADN8830 application circuit must be

modified. Figure 24 shows the preferred method for driving a

heating element load.

0.50

(0.0197)

PACKAGE

OUTLINE

3.68

(0.1449)

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS

(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR

REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

THERMAL PAD SHOULD BE SOLDERED TO AN ELECTRICALLY FLOATING

PAD ON THE PC BOARD

Figure 25. Suggested PC Board Layout for CP-32

Pad Landing

D

REV.

–21–

ADN8830

OUTLINE DIMENSIONS

5.10

5.00 SQ

4.90

0.30

0.25

0.18

PIN 1

INDICATOR

PIN 1

INDICATOR

25

24

32

1

0.50

BSC

3.25

3.10 SQ

2.95

EXPOSED

PAD

17

16

8

9

0.50

0.40

0.30

0.25 MIN

TOP VIEW

BOTTOM VIEW

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

0.80

0.75

0.70

0.05 MAX

0.02 NOM

SECTION OF THIS DATA SHEET.

COPLANARITY

0.08

0.20 REF

SEATING

PLANE

COMPLIANT TO JEDEC STANDARDS MO-220-WHHD.

Figure 26. 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ]

5 mm × 5 mm Body, Very Very Thin Quad

(CP-32-7)

Dimensions shown in millimeters

ORDERING GUIDE

Model¹

Temperature Range

Package Description

Package Option

CP-32-7

ADN8830ACPZ

ADN8830ACPZ-REEL

ADN8830ACPZ-REEL7

−40°C to +85°C

32-Lead Lead Frame Chip Scale Package [LFCSP_WQ]

CP-32-7

¹Z = RoHS Compliant Part.

REVISION HISTORY

3/12—Rev. C to Rev. D

8/03—Rev. A to Rev. B

Added EPAD Notation .....................................................................3

Updated Outline Dimensions........................................................22

Changes to Ordering Guide...........................................................22

Updated Ordering Guide .................................................................3

Updated Thermal Setup Section.....................................................8

Updated Outline Dimensions........................................................23

11/03—Rev. B to Rev. C

2/03—Rev. 0 to Rev. A

Changes to Ordering Guide.............................................................3

Deleted Figure 24 ............................................................................21

Deleted Boosting the Output Voltage section .............................22

Deleted Figure 26 ............................................................................22

Deleted Equations 45, 46 and 47...................................................22

Updated Outline Dimensions........................................................23

Renumbered Figures.......................................................... Universal

Changes to Thermistor Setup Section............................................8

Changes to Figure 14 ......................................................................15

Changes to Figure 23 ......................................................................20

Changes to Figure 25 ......................................................................21

Updated Outline Dimensions........................................................23

registered trademarks are the property of their respective owners.

D02793-0-3/12(B)

–22–

REV. D


型号：	ADN8830ACP
厂家：	ADI
描述：	IC SPECIALTY ANALOG CIRCUIT, QCC32, 5 X 5 MM, MO-220-VHHD-2, LFCSP-32, Analog IC:Other
文件：	总22页 (文件大小：279K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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