ADN8831-EVALZ_技术文档

Thermoelectric Cooler (TEC) Controller

Data Sheet

ADN8831

FEATURES

GENERAL DESCRIPTION

Two integrated zero drift, rail-to-rail, chop amplifiers

TEC voltage and current operation monitoring

Programmable TEC maximum voltage and current

Programmable TEC current heating and cooling limits

Configurable PWM switching frequency up to 1 MHz

Power efficiency: > 90%

The ADN8831 is a monolithic TEC controller. It has two inte-

grated, zero drift, rail-to-rail comparators, and a PWM driver.

A unique PWM driver works with an analog driver to control

external selected MOSFETs in an H-bridge. By sensing the

thermal detector feedback from the TEC, the ADN8831 can

drive a TEC to settle the programmable temperature of a laser

diode or a passive component attached to the TEC module.

Temperature lock indication

Optional internal or external clock source

Clock phase adjustment for multiple drop operation

Supports negative temperature coefficient (NTC) thermistors

or positive temperature coefficient (PTC) resistance

thermal detectors (RTDs)

The ADN8831 supports NTC thermistors or positive tempera-

ture coefficient (PTC) RTDs. The target temperature is set as an

analog voltage input either from a DAC or from an external

resistor divider driven by a reference voltage source.

A proportional integral differential (PID) compensation

network helps to quickly and accurately stabilize the ADN8831

thermal control loop. An adjustable PID compensation network

example is described in the AN-695 Application Note, Using the

ADN8831 TEC Controller Evaluation Board. A typical reference

voltage of 2.5 V is available from the ADN8831 for thermistor

temperature sensing or for TEC voltage/current measuring and

limiting in both cooling and heating modes.

5 V typical and optional 3 V supplies

Standby and shutdown mode availability

Adjustable soft start feature

5 mm × 5 mm 32-lead LFCSP

APPLICATIONS

Thermoelectric cooler (TEC) temperature control

DWDM optical transceiver modules

Optical fiber amplifiers

Optical networking systems

Instruments requiring TEC temperature control

FUNCTIONAL BLOCK DIAGRAM

ILIMC ILIMH ITEC VLIM VTEC

CS

LIMITER/MONITOR

LFB

IN1P

IN1N

LINEAR

MOSFET

DRIVER

AMPLIFIER

Chop1

LPGATE

LNGATE

SFB

OUT1

SPGATE

SNGATE

COMPSW

SW

CONTROL

PWM

MOSFET

DRIVER

IN2P

IN2N

AMPLIFIER

Chop2

COMPOSC

SYNCO

SOFT START

SHUTDOWN

OSCILLATOR

REF

OUT2

TMPGD VREF

SS/SB

SYNCI/SD PHASE FREQ

Figure 1.

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rightsof third parties that may result fromits use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks andregisteredtrademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700 www.analog.com

ADN8831

Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Temperature Lock Indicator ..................................................... 13

Soft Start on Power-Up.............................................................. 13

Shutdown Mode ......................................................................... 13

Standby Mode ............................................................................. 13

TEC Voltage/Current Monitor ................................................. 13

Maximum TEC Voltage Limit .................................................. 13

Maximum TEC Current Limit ................................................. 14

Applications Information .............................................................. 15

Signal Flow .................................................................................. 15

Thermistor Setup........................................................................ 15

Thermistor Amplifier (Chop1) ................................................ 15

PID Compensation Amplifier (Chop2) .................................. 16

MOSFET Driver Amplifier ....................................................... 17

Outline Dimensions....................................................................... 18

Ordering Guide .......................................................................... 18

Applications....................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Detailed Block Diagram .................................................................. 3

Specifications..................................................................................... 4

Electrical Characteristics............................................................. 4

Absolute Maximum Ratings............................................................ 6

Thermal Characteristics .............................................................. 6

ESD Caution.................................................................................. 6

Pin Configuration and Function Descriptions............................. 7

Typical Performance Characteristics ............................................. 9

Theory of Operation ...................................................................... 11

Oscillator Clock Frequency....................................................... 12

Oscillator Clock Phase............................................................... 12

REVISION HISTORY

8/12—Rev. 0 to Rev. A

Changes to Features and General Description Sections.............. 1

Moved Figure 2 ................................................................................. 3

Changes to Figure 2.......................................................................... 3

Changes to Table 1............................................................................ 4

Changes to Table 2 and Table 3....................................................... 6

Changes to Figure 3 and Table 4..................................................... 7

Changes to Theory of Operation Section and Figure 12........... 11

Changes to Figure 14 and Figure 15............................................. 11

Changes to Oscillator Clock Frequency Section and Oscillator

Clock Phase Section ....................................................................... 12

Changes to Soft Start on Power-Up Section, Shutdown Mode

Section, Standby Mode Section, and TEC Voltage/Current

Monitor Section .............................................................................. 13

Changes to Figure 17...................................................................... 15

Changes to PID Compensation Amplifier (Chop2) Section .... 16

Changes to MOSFET Driver Amplifier Section and Figure 21 ..17

Updated Outline Dimensions....................................................... 18

Changes to Ordering Guide .......................................................... 18

9/05—Revision 0: Initial Version

Rev. A | Page 2 of 20

Data Sheet

ADN8831

DETAILED BLOCK DIAGRAM

ILIMH VLIM

VTEC

30

ITEC

29

CS

28

LFB LNGATE LPGATE

31

32

27

26

25

2kΩ

80kΩ

ADN8831

VC

25kΩ

5kΩ

1

ILIMC

5kΩ

20kΩ

25kΩ

VB

1.25V

20kΩ

LINEAR AMPLIFIER

1kΩ

24

23

COMPSW

SFB

VOLTAGE

LIMIT

2

3

IN1P

IN1N

VB

Chop1

Chop2

SFB

20kΩ

LFB

20kΩ

100kΩ

1.25V

22

PGND

g

1

20kΩ

VB

4

5

m

OUT1

IN2P

VC

20kΩ

10kΩ

100kΩ

21

20

19

SNGATE

SW

ILIMH

6

7

IN2N

LFB

g

2

m

OUT2

ILIMC

ITEC

SPGATE

VB

= 2.5V, V > 4.0V

g

3

m

VB

DD

18

17

PVDD

= 1.5V, V < 4.0V

DD

SOFT START

2.5V

COMPOSC

SD

250mV

8

REFERENCE

1.25V

VREF

OSCILLATOR

14

SB

TEMPERATURE

GOOD

DETECT

9

10

11

12

15

16

13

AVDD

PHASE

TMPGD

AGND

FREQ

SS/SB SYNCO

SYNCI/SD

Figure 2. Detailed Block Diagram

Rev. A | Page 3 of 20

ADN8831

Data Sheet

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS

V_DD= 3.0 V to 5.0 V, T_A= 25°C, unless otherwise noted.

Table 1.

Parameter¹

Symbol

Test Conditions/Comments

Min

Typ

Max

Unit

PWM OUTPUT DRIVER

Output Transition Time

Nonoverlapping Clock Delay

Output Resistance

Output Voltage Swing²

LINEAR OUTPUT AMPLIFIER

Output Resistance

t_R, t_F

C_L= 3300 pF

20

80

6

ns

Ω

40

0

R_{O (SNGATE, SPGATE)}

SFB

I_L= 10 mA, V_DD= 3.0 V

V_LIM= VREF

V_DD

V

R_{O, LNGATE}

R_{O, LPGATE}

LFB

I_OUT= 2 mA, V_DD= 3.0 V

200

100

Ω

V

Output Voltage Swing²

POWER SUPPLY

0

V_DD

Power Supply Voltage

Supply Current

V_DD

I_SY

3.0

5.5

12

15

V

PWM not switching

−40°C ≤ T_A≤ +85°C

SYNCI/SD = 0 V

8

mA

µA

V

Shutdown Current

I_SD

8

Soft Start Charging Current

Undervoltage Lockout³

Standby Current

I_SS

UVLO

I_SB

V_SS= 0 V

8

2.2

2

Low to high threshold

SYNCI/SD = V_DD, SS/SB = 0 V

SYNCI/SD = V_DD

2.6

mA

mV

Standby Threshold

V_SB

150

200

ERROR/COMPENSATION AMPLIFIERS

Input Offset Voltage

V_OS1

V_OS2

V_CM1, V_CM2

V_CM1= 1.5 V, V_IN1P− V_IN1M

V_CM2= 1.5 V, V_IN2P− V_IN2M

10

100

V_DD

μV

V

dB

V

mV

dB

mA

MHz

Input Voltage Range

Common-Mode Rejection Ratio

Output Voltage High

Output Voltage Low

Power Supply Rejection Ratio

Output Current

0

CMRR₁, CMRR₂V_CM1, V_CM2= 0.2 V to V_DD− 0.2 V

V_OH1, V_OH2

V_OL1, V_OL2

PSRR₁, PSRR₂

I_OUT1, I_OUT2

GBW₁, GBW₂

120

V_DD− 0.03

25

3.0 V ≤ V_DD≤ 5.0 V

Sourcing and sinking

V_OUT= 0.5 V to (V_DD− 1 V)

110

2

5

Gain Bandwidth Product

OSCILLATOR

Sync Range

f_CLK

SYNCI/SD connected to external

clock

COMPOSC = V_DD, R_FREQ= 118 kΩ,

SYNCI/SD = V_DD, V_DD= 5.0 V

300

800

200

1000

1250

1000

50

kHz

Oscillator Frequency

f_CLK

1000

Nominal Free-Run Oscillation

Frequency

Phase Adjustment Range²

f_CLK-NOMINAL

Φ_CLK

COMPOSC = V_DD, SYNCI/SD = V_DD

V_PHASE= 0.13 V, f_SYNCI/SD= 1 MHz

Degrees

V

_PHASE= 2.3 V, f_SYNCI/SD= 1 MHz

330

Phase Adjustment Default

REFERENCE VOLTAGE

Reference Voltage

Φ_CLK

V_REF

PHASE = open

180

I_REF= 2 mA

I_REF= 0 mA

2.35

2.47

V

2.37

2.57

Rev. A | Page 4 of 20

Data Sheet

ADN8831

Parameter¹

Symbol

Test Conditions/Comments

Min

Typ

Max

Unit

LOGIC Controls

Logic Low Output Voltage

Logic High Output Voltage

Logic Low Input Voltage

Logic High Input Voltage

Output High Impedance

Output Low Impedance

Output High Impedance

Output Low Impedance

TEC CURRENT MEASUREMENT

ITEC Gain

V_OL

V_OH

V_IL

TMPGD, SYNCO, I_OUT= 0 A

0.2

V

Ω

V_DD− 0.2

3

V_IH

V_DD= 5.0 V

V_DD= 3.0 V

35

20

50

25

A_{V, ITEC}

(V_ITEC– V_REF/2) / (V_LFB− V_CS)

No load

25

V/V

V

ITEC Output Range High

ITEC Output Range Low

ITEC Input Range²

V_{ITEC, HIGH}

V_{ITEC, LOW}

V_CS, V_LFB

V_{ITEC, B}

V_DD− 0.05

0.05

V_DD

1.30

0

1.10

ITEC Bias Voltage

V_LFB= V_CS= 0

1.20

1.5

Maximum ITEC Driving Current

TEC VOLTAGE MEASUREMENT

VTEC Gain

VTEC Output Range²

VTEC Bias Voltage²

I_{OUT, TEC}

mA

A_{V, VTEC}

V_VTEC

V_{VTEC, B}

R_VTEC

(V_VTEC– V_REF/2)/(V_LFB− V_SFB

V_DD= 5.0 V

)

0.23

0.05

1.20

0.25

0.28

2.5

1.35

V/V

V

V_LFB= V_SFB= 0 V

I_VTEC= 300 μA

1.25

35

VTEC Output Load Resistance

VOLTAGE LIMIT

Ω

VLIM Gain

VLIM Input Range²

A_{V, LIM}

V_VLIM

(V_LFB− V_SFB)/V_VLIM

5

V/V

V

0

V_DD

VLIM Input Current, Cooling

VLIM Input Current, Heating

VLIM Input Current Accuracy, Heating

CURRENT LIMIT

I_{VLIM, COOL}

I_{VLIM, HEAT}

V_OUT2< V_REF/2

V_OUT2> V_REF/2

I_VLIM/I_FREQ

100

nA

mA

A/A

I_FREQ

1.0

0.8

1.18

ILIMC Input Voltage Range

ILIMH Input Voltage Range

ILIMC Limit Threshold

ILIMH Limit Threshold

TEMPERATURE GOOD

High Threshold

V_ILIMC

V_ILIMH

V_{TH, ILIMC}

V_{TH, ILIMH}

V_REF/2

0.1

1.98

0.48

V_DD− 1

V_REF/2

2.02

V

V_ITEC= 2.0 V, R_S= 20 mΩ

V_ITEC= 0.5 V

2.0

0.5

0.52

V_{OUT1, TH1}

V_{OUT1, TH2}

IN2M tied to OUT2, V_IN2P= 1.5 V

1.55

1.45

1.60

V

Low Threshold

1.40

¹Logic inputs meet typical CMOS I/O conditions for source/sink current (~1 µA).

²Guaranteed by design or indirect test methods.

³The ADN8831 does not work when the supply voltage is less than UVLO.

Rev. A | Page 5 of 20

ADN8831

Data Sheet

ABSOLUTE MAXIMUM RATINGS

Absolute maximum ratings at 25°C, unless otherwise noted.

Stresses above those listed under Absolute Maximum Ratings may

cause permanent damage to the device. This is a stress rating

only; functional operation of the device at these or any other

conditions above those indicated in the operational section of this

specification is not implied. Exposure to absolute maximum

rating conditions for extended periods may affect device

reliability.

Table 2.

Parameter

Rating

Supply Voltage

Input Voltage

Storage Temperature Range

Junction Temperature

Lead Temperature (Soldering, 60 sec)

6 V

GND to V_S+ 0.3 V

−65°C to +150°C

125°C

THERMAL CHARACTERISTICS

300°C

θ_JAis specified for the worst-case conditions, that is, a device

soldered in a circuit board for surface-mount packages.

Table 3. Thermal Resistance

Package Type

θ_JA

θ_JC

Unit

32-lead LFCSP (ACPZ)

33.4

1.02

°C/W

ESD CAUTION

Rev. A | Page 6 of 20

Data Sheet

ADN8831

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

ILIMC

IN1P

IN1N

OUT1

IN2P

IN2N

OUT2

VREF

1

2

3

4

5

6

7

8

24 COMPSW

23 SFB

22 PGND

21 SNGATE

20 SW

19 SPGATE

18 PVDD

PIN 1

INDICATOR

ADN8831

TOP VIEW

(Not to Scale)

17 COMPOSC

NOTES

1. THE LFCSP PACKAGE HAS AN EXPOSED PADDLE

THAT SHOULD BE CONNECTED TO AGND (PIN 12)

AND THE ASSOCIATED PCB GROUND PLANE.

Figure 3. Pin Configuration

Table 4. Pin Function Descriptions

Pin No. Mnemonic Type

Description

1

2

3

4

5

6

7

8

ILIMC

IN1P

IN1N

OUT1

IN2P

IN2N

Analog Input

Analog Output

Analog Input

Analog Output

Power

Analog Input

Digital Output

Ground

Analog Input

Sets TEC Cooling Current Limit.

Noninverting Input to Error Amplifier.

Inverting Input to Error Amplifier.

Output of Error Amplifier.

Noninverting Input to Compensation Amplifier.

Inverting Input to Compensation Amplifier.

Output of Compensation Amplifier.

2.5 V Voltage Reference Output.

Power for Nondriver Sections. 3.0 V minimum; 5.5 V maximum.

Sets SYNCO Clock Phase Relative to SYNCI/SD Clock.

OUT2

VREF

9

AVDD

PHASE

TMPGD

AGND

FREQ

SS/SB

10

11

12

13

14

Logic Output. Active high. Indicates when the OUT1 voltage is within 100 mV of IN2P voltage.

Analog Ground. Connect to low noise ground.

Sets Switching Frequency with an External Resistor.

Sets Soft Start Time for Output Voltage. Pull low (VTEC = 0 V) to put the ADN8831 into standby

mode.

15

16

17

SYNCO

Digital Output

Digital Input

Phase Adjustment Clock Output. Phase set from PHASE pin. Used to drive SYNCI/SD of other

ADN8831 devices.

Optional Clock Input. If not connected, clock frequency is set by FREQ pin. Pull low to put

the ADN8831 into shutdown mode. Pull high to negate shutdown mode.

Compensation for Oscillator. Connect to PVDD when in free-run mode, connect to R-C

network when in external clock mode.

SYNCI/SD

COMPOSC

Analog Output

18

19

20

21

22

23

24

25

26

27

28

29

PVDD

SPGATE

SW

SNGATE

PGND

SFB

COMPSW

LPGATE

LNGATE

LFB

Power

Power for Output Driver Sections. 3.0 V minimum; 5.5 V maximum.

PWM Output Drives External PMOS Gate.

Connects to PWM FET Drains.

Analog Output

Analog Input

Analog Output

Ground

Analog Input

Analog Output

Analog Input

Analog Output

PWM Output Drives External NMOS Gate.

Power Ground. External NMOS devices connect to PGND. Connect to digital ground.

PWM Feedback. Connect to the TEC module negative (−) terminal.

Compensation Pin for Switching Amplifier.

Linear Output Drives External PMOS Gate.

Linear Output Drives External NMOS Gate.

Linear Feedback. Connect to H-Bridge transistor output and current sense resistor.

Linear Feedback. Connect to the TEC module positive (+) terminal.

Indicates TEC Current.

CS

ITEC

Rev. A | Page 7 of 20

ADN8831

Data Sheet

Pin No. Mnemonic Type

Description

30

31

32

33

VTEC

VLIM

ILIMH

EP

Analog Output

Analog Input

Indicates TEC Voltage.

Sets Maximum Voltage Across TEC Module.

Sets TEC Heating Current Limit.

Metal paddle at the Exposed Pad. The LFCSP package has an exposed pad that should be connected to AGND

back of package (Pin 12) and the associated PCB ground plate.

Rev. A | Page 8 of 20

Data Sheet

ADN8831

TYPICAL PERFORMANCE CHARACTERISTICS

360

300

240

180

120

60

SYNCI/SD = 1MHz

= 25°C

T

A

V

= 3V

DD

SPGATE

SNGATE

T

= 25°C

A

V

= 5V

DD

0

10ns/DIV

0

0.4

0.8

1.2

1.6

2.0

2.4

V

(V)

PHASE

Figure 4. SPGATE and SNGATE Rise Time Using Circuit Shown Figure 12

Figure 7. Clock Phase Shift vs. Phase Voltage

2.485

2.480

2.475

2.470

2.465

V

= 5V

DD

SNGATE

SPGATE

T

= 25°C

A

V

= 5V

DD

10ns/DIV

–40

–15

10

35

60

85

TEMPERATURE (°C)

Figure 5. SNGATE and SPGATE Fall Time Using Circuit Shown in Figure 12

Figure 8. V_REFvs. Temperature

360

1000

800

600

400

200

0

SYNCI/SD = 1MHz

V

= 5V

DD

T

= 25°C

A

T

= 25°C

A

V

= 5V

DD

300

240

180

120

60

0

0.4

0.8

1.2

1.6

2.0

2.4

0

250

500

(kΩ)

750

1000

V

(V)

R

PHASE

FREQ

Figure 9. Switching Frequency vs. R_FREQ

Figure 6. Clock Phase Shift vs. Phase Voltage

Rev. A | Page 9 of 20

ADN8831

Data Sheet

740

15

12

9

V

= 5V

V

= 5V

DD

= 25°C

DD

T

A

720

700

680

660

6

3

640

–40

0

200

–15

10

35

60

85

400

600

800

1000

TEMPERATURE (°C)

SWITCHING FREQUENCY (kHz)

Figure 10. Switching Frequency vs. Temperature

Figure 11. Supply Current vs. Switching Frequency

Rev. A | Page 10 of 20

Data Sheet

ADN8831

THEORY OF OPERATION

The ADN8831 is a single chip TEC controller that sets and

stabilizes a TEC temperature. A voltage applied to the input

of the ADN8831 corresponds to a target TEC temperature

setpoint (TEMPSET). By controlling an external FET H-bridge,

the appropriate current is then applied to the TEC to pump

heat either to or away from an object attached to the TEC.

The objective temperature is measured with a thermal sensor

attached to the TEC and the sensed temperature (voltage) is

fed back to the ADN8831 to complete a closed thermal control

loop of the TEC. For best stability, the thermal sensor is to be

closed to the object. In most laser diode modules, a TEC and a

NTC thermistor are already mounted in the same package to

regulate the laser diode temperature.

Adjusting the PID network optimizes the step response of

the TEC control loop. A compromised settling time and the

maximum current ringing become available when this is done.

Details of how to adjust the compensation network are in the

PID Compensation Amplifier (CHOP2) section. The TEC is

differentially driven in an H-bridge configuration. The ADN8831

drives external MOSFET transistors to provide the TEC current.

To further improve the power efficiency of the system, one side

of the H-bridge uses a PWM driver. Only one inductor and one

capacitor are required to filter out the switching frequency. The

other side of the H-bridge uses linear output without requiring

any additional circuitry. This proprietary configuration allows

the ADN8831 to provide efficiency of >90%. For most applica-

tions, a 4.7 μH inductor, a 22 μF capacitor, and a switching

frequency of 1 MHz, maintain less than 0.5% worst-case output

voltage ripple across a TEC.

The ADN8831 integrates two self-correcting, auto-zero amplifiers

(Chop1 and Chop2). The Chop1 amplifier usually takes a thermal

sensor input and converts or regulates the input to a linear

voltage output. The OUT1 (Pin 4) voltage is proportional to the

object temperature. The OUT1 (Pin 4) voltage is fed into the

compensation amplifier (Chop2) and compared with a tempera-

ture setpoint voltage, creating an error voltage that is proportional

to the difference. When using the Chop2 amplifier, a PID

network is recommended, as shown in Figure 12.

The maximum voltage across the TEC and current flowing

through the TEC is to be set using the VLIM (Pin 31) and

ILIMC (Pin 1)/ILIMH (Pin 32). Additional details are in the

Maximum TEC Voltage Limit section and the Maximum TEC

Current Limit section.

5Ω

0.1µF

VDD

3.0V TO 5.5V

0.1µF

AVDD

PVDD

VREF

VLIM

ILIMC

LPGATE

LFB

R

0.1µF

10kΩ

SENSE

10kΩ

0.1µF

LNGATE

CS

8.2kΩ

ILIMH

IN1P

8.2kΩ

10kΩ

COMPSW

TEC

17.8kΩ

SFB

SYNCI/SD

COMPOSC

IN1N

10kΩ

1kΩ

VDD

17.8kΩ

10kΩ

7.68kΩ

OUT1

60µF

THERMISTOR

SPGATE

IN2N

30.1kΩ

SW

SNGATE

SYNCO

PHASE

SS/SB

27nF

3.3µH

10µF

40µF

OUT2

IN2P

TEMPERATURE SET INPUT

NC

TEC VOLTAGE OUTPUT

TEC CURRENT OUTPUT

VTEC

ITEC

0.1µF

118kΩ

FREQ

TEMP GOOD INDICATOR

NC = NO CONNECT

TMPGD

PGND

AGND

Figure 12. Typical Application Circuit 1

Rev. A | Page 11 of 20

ADN8831

Data Sheet

Connecting Multiple ADN8831 Devices

OSCILLATOR CLOCK FREQUENCY

SD

Connecting SYNCO (Pin 15) to the SYNCI/ pin of another

ADN8831 allows for multiple ADN8831 devices to work

together using a single clock. Multiple ADN8831 devices can be

driven from a single master ADN8831 device, by connecting the

The ADN8831 has an internal oscillator to generate the switching

frequency for the output stage. This oscillator can be set in either

free-run mode or synchronized to an external clock signal.

Free-Run Operation

SD

SYNCO pin of the master device to each slave SYNCI/ pin,

or by daisy-chaining by connecting the SYNCO pin of each

device to the SYNCI/ pin of the next device. When multiple

ADN8831 devices are clocked at the same frequency, the phase is

to be adjusted to reduce power supply ripple.

The switching frequency is set by a single resistor connected

from FREQ (Pin 13) to ground. Table 5 shows R_FREQfor some

common switching frequencies. For free-run operation, connect

SD

SYNCI/ (Pin 16) and COMPOSC (Pin 17) to PVDD (Pin 18).

Table 5. Switching Frequencies vs. R_FREQ

ADN8831

MASTER

V

f_SWITCH

R_FREQ

COMPOSC

DD

250 kHz

500 kHz

750 kHz

1 MHz

484 kΩ

249 kΩ

168 kΩ

118 kΩ

118kΩ

FREQ

V

SYNCI/SD

DD

PHASE

NC

SYNCO

Higher switching frequencies reduce the voltage ripple across the

TEC. However, high switching frequencies create more power

dissipation in the external transistors due to the more frequent

charging and discharging of the transistor gate capacitances.

10kΩ

V

DD

1nF

0.1µF

ADN8831

SLAVE

1kΩ

COMPOSC

ADN8831

1MΩ

V

COMPOSC

FREQ

DD

FREQ

R

FREQ

V

SYNCI/SD PHASE

PHASE

V

SYNCI/SD

DD

1nF

Figure 13. Free-Run Mode

ADN8831

SLAVE

0.1µF

1kΩ

External Clock Operation

The switching frequency of the ADN8831 can be synchronized

SD

COMPOSC

FREQ

1MΩ

with an external clock. Connect the clock signal to SYNCI/

(Pin 16) and connect COMPOSC (Pin 17) to an R-C network. This

network compensates a PLL to lock on to the external clock.

V

SYNCI/SD PHASE

PHASE

1nF

ADN8831

Figure 15. Multiple ADN8831 Devices Driven from a Master Clock

0.1µF

1kΩ

COMPOSC

OSCILLATOR CLOCK PHASE

1MΩ

Adjust the oscillator clock phase using a simple resistor divider

at PHASE (Pin 10). Phase adjustment allows two or more

ADN8831 devices to operate from the same clock frequency

and not have all outputs switched simultaneously. This avoids

the potential of an excessive power supply ripple.

FREQ

EXT. CLOCK

SYNCI/SD

SOURCE

Figure 14. Synchronize to an External Clock

To ensure the correct operation of the oscillator, V_PHASEis to

remain in the range of 100 mV to 2.4 V. PHASE (Pin 10) is

internally biased at 1.2 V. If PHASE (Pin 10) remains open, the

clock phase is set at 180° as the default.

Rev. A | Page 12 of 20

Data Sheet

ADN8831

Current Monitor

TEMPERATURE LOCK INDICATOR

ITEC (Pin 29) is an analog voltage output pin with a voltage

proportional to the actual current through the TEC. A center

ITEC voltage of 1.25 V corresponds to 0 A through the TEC.

The output voltage is calculated using the following equation:

The TMPGD (Pin 11) outputs a logic high when the OUT1 (Pin 4)

voltage reaches the IN2P (Pin 5) temperature setpoint (TEMPSET)

voltage. The TMPGD has a detection range of 25 mV and a

10 mV typical hysteresis. This allows direct interfacing either to

the microcontrollers or to the supervisory circuitry.

V_ITEC=1.25 V+ 25×(V_LFB−V_CS)

SOFT START ON POWER-UP

The equivalent TEC current is calculated using the following

equation:

The ADN8831 can be programmed to ramp up for a specified

SD

time after the power supply is turned on or after the

pin is

V

_ITEC−1.25 V

I_TEC

=

deasserted. This feature, called soft start, is useful for gradually

increasing the duty cycle of the PWM amplifier. The soft start

time is set with a single capacitor connected from SS (Pin 14) to

ground. The capacitor value is calculated by the following

equation:

25×R_SENSE

MAXIMUM TEC VOLTAGE LIMIT

The maximum TEC voltage is set by applying a voltage at

VLIM (Pin 31) to protect the TEC. This voltage can be set with

a resistor divider or a DAC. The voltage limiter operates in

bidirectional TEC voltage, and cooling and heating voltage.

τ_SS=150 ×C_SS

where:

Using a DAC

C_SSis the value of the capacitor in microfarads.

τ

_SSis the soft start time in milliseconds.

Both the cooling and heating voltage limits are set at the same

levels when a voltage source directly drives VLIM (Pin 31).

The maximum TEC voltage is calculated using the following

equation:

To set a soft start time of 15 ms, C_SSis to equal 0.1 μF.

SHUTDOWN MODE

The shutdown mode sets the ADN8831 into an ultralow current

state. The current draw in shutdown mode is typically 8 µA.

V_TEC(MAX)= 5×V_VLIM

where:

SD

The shutdown input,

(Pin 16), is active low. To shut down

to logic low. Once a logic high is applied,

V

_{TEC (MAX)}is the maximum TEC voltage.

_VLIMis the voltage applied at VLIM (Pin 31).

SD

the device, drive

the ADN8331 is reactivated after the time delay set by the soft

start circuitry. Refer to the Soft Start on Power-Up section for

more details.

Using a Resistor Divider

Separate voltage limits are set using a resistor divider. The

internal current sink circuitry connected to VLIM (Pin 31) draws

a current when the ADN8831 drives the TEC in a heating

direction, which lowers the voltage at VLIM (Pin 31). The

current sink is not active when the TEC is driven in a cooling

direction; therefore, the TEC heating voltage limit is always

lower than the cooling voltage limit.

STANDBY MODE

The ADN8831 has a standby mode that deactivates a MOSFET

driver stage. The current draw for the ADN8831 in standby

SB

mode is less than 2 mA. The standby input SS/ (Pin 14) is

active low. After applying a logic high, the ADN8331 reactivates

following the delay. In standby mode, only SYNCO (Pin 15) has

a clock output. All the other function blocks are powered off.

V

REF

ADN8831

R

A

VLIM

TEC VOLTAGE/CURRENT MONITOR

R

B

The TEC real time voltage and current are detectable at VTEC

(Pin 30) and ITEC (Pin 29), respectively.

I

SINK

Voltage Monitor

FREQ

R

VTEC (Pin 30) is an analog voltage output pin with a voltage

proportional to the actual voltage across the TEC. A center

VTEC voltage of 1.25 V corresponds to 0 V across a TEC. The

output voltage is calculated using the following equation:

FREQ

Figure 16. Using a Resistor Divider

V_VTEC=1.25 V+ 0.25×(V_LFB−V_SFB

)

Rev. A | Page 13 of 20

ADN8831

Data Sheet

The sink current is set by the resistor connected from FREQ

(Pin 13) to ground. The sink current is calculated using the

following equation:

MAXIMUM TEC CURRENT LIMIT

To protect the TEC, separate maximum TEC current limits in

cooling and heating directions are set by applying a voltage at

ILIMC (Pin 1) and ILIMH (Pin 32). Maximum TEC currents

are calculated using the following equations:

1.25 V

I_SINK

=

R_FREQ

V_ILIMC−1.25 V

25×R_SENSE

where:

_SINCis the sink current at VLIM (Pin 31).

_FREQis the resistor connected at FREQ (Pin 13).

I_TEC,MAX,COOL

=

I

R

1.25 V−V_ILIMH

25×R_SENSE

I_TEC,MAX,HEAT

=

The cooling and heating limits are calculated using the

following equations:

V

_REF×R_B

V_VLIM,COOL

=

R_A+ R_B

V_VLIM,HEAT= V_VLIM,COOL− I_SINK×R_AR_B

Rev. A | Page 14 of 20

Data Sheet

ADN8831

APPLICATIONS INFORMATION

THERMISTOR INPUT

AMPLIFIER

PID COMPENSATOR

AMPLIFIER

MOSFET DRIVER

= 5

A

V

SFB

A

= R /(R + R ) – R /R

A = Z /Z

V

FB

TH

X

FB

OUT1

4

V 2 1

SPGATE

SNGATE

LPF

PWM

+

IN1P

IN1N

IN2P

IN2N

TEC

OUT2

CONTROL

Chop2

–

Chop1

–

LPGATE

LINEAR

LNGATE

LFB

V

2

3

5

6

7

REF

V

/2

V

TEMPSET

17.68kΩ

R

REF

R

FB

Z

2

1

R

7.68kΩ

X

V

OUT2

OUT1

R

TH

(10kΩ @ 25°C)

Figure 17. Signal Flow Block Diagram

T

R

_LOWand T_HIGHare the endpoints of the temperature range and

_MIDis the average. In some cases, with only B constant available ,

_THis calculated using the following equation:

SIGNAL FLOW

The ADN8831 integrates two auto-zero amplifiers defined

as the Chop1 amplifier and the Chop2 amplifier. Both of the

amplifiers can be used as standalone amplifiers, therefore, the

implementation of temperature control can vary. Figure 17

shows the signal flow through the ADN8831, and a typical

implementation of the temperature control loop using the Chop1

amplifier and the Chop2 amplifier.



















1

T

1

T_R



R_TH= R exp B

−





R









where:

R

_THis a resistance at T[K].

R_Ris a resistance at T_R[K].

R_Xis calculated using the following equation:

In Figure 17, the Chop1 amplifier and the Chop2 amplifier are

configured as the thermistor input amplifier and the PID

compensation amplifier, respectively. The thermistor input

amplifier gains the thermistor voltage then outputs to the PID

compensation amplifier. The PID compensation amplifier then

compensates a loop response over the frequency domain.













R_LOWR_MID+ R_MIDR_HIGH− 2R_LOWR_HIGH

R_LOW+ R_HIGH− 2R_MID

R_X

=

THERMISTOR AMPLIFIER (Chop1)

The output from the compensation loop at OUT2 is fed to the

linear MOSFET gate driver. The voltage at LFB is fed with OUT2

into the PWM MOSFET gate driver. Including the external

transistors, the gain of the differential output section is fixed at 5.

For details on the output drivers, see the MOSFET Driver

Amplifier section.

The Chop1 amplifier can be used as a thermistor input amplifier.

In Figure 17, the output voltage is a function of the thermistor

temperature. The voltage at OUT1 is expressed as













R_FB

R_TH+ R_X

R_FB

R

V_REF

2



V_OUT1

=

−

+1 ×

THERMISTOR SETUP

where:

_THis a thermistor.

R_Xis a compensation resistor.

The thermistor has a nonlinear relationship to temperature; near

optimal linearity over a specified temperature range can be

achieved with the proper value of R_Xplaced in series with the

thermistor. First, the resistance of the thermistor must be

known, where

R

R is calculated using the following equation:

R = R_X+ R_{TH @25°C}

V

_OUT1is centered around V_REF/2 at 25°C. With the typical

R_LOW= R_TH@T_LOW

R_MID= R_TH@T_MID

R_HIGH= R_TH@T_HIGH

values shown in Figure 17, an average temperature-to-voltage

coefficient is −25 mV/°C at a range of +5°C to +45°C.

Rev. A | Page 15 of 20

ADN8831

Data Sheet

2.5

1

f_{0 dB}



80TECGAIN

2R3C1

2.0

1.5

1.0

0.5

To ensure stability, the unity-gain crossover frequency is to be

lower than the thermal time constant of the TEC and thermistor.

However, this thermal time constant is sometimes unspecified

making it difficult to characterize. There are many texts written

on loop stabilization, and it is beyond the scope of this data

sheet to discuss all methods and trade offs in optimizing

compensation networks.

ADN8831

+

0

–15

CHOP2

–

5

25

45

65

TEMPERATURE(°C)

Figure 18. V_OUT1vs. Temperature

OUT1

IN2P

IN2N

OUT2

7

4

5

6

PID COMPENSATION AMPLIFIER (Chop2)

V

TEMPS

ET

Use the Chop2 amplifier as the PID compensation amplifier.

The voltage at OUT1 feeds into the PID compensation amplifier.

The frequency response of the PID compensation amplifier is

dictated by the compensation network. Apply the temperature

set voltage at IN2P. In Figure 17, the voltage at OUT2 is calcu-

lated using the following equation:

R3

R1

C1

R2

C2

CF

Figure 19. Implementing a PID Compensation Loop

Z2

Z1

V_OUT2 V_TEMPSET



(V_OUT1V_TEMPSET)

The user sets the exact compensation network. This network

varies from a simple integrator to PI, PID, or any other type of

network. The user also determines the type of compensation

and component values because they are dependent on the thermal

response of the object and the TEC. One method for empirically

determining these values is to input a step function to IN2P,

therefore changing the target temperature, and adjusting the

compensation network to minimize the settling time of the TEC

temperature.

0dB

R1

R2 || R3

R1

R3

1

A typical compensation network for temperature control of

a laser module is a PID loop consisting of a very low frequency

pole and two separate zeros at higher frequencies. Figure 19

shows a simple network for implementing PID compensation.

To reduce the noise sensitivity of the control loop, an additional

pole is added at a higher frequency than the zeros. The bode

plot of the magnitude is shown in Figure 20. The unity-gain

crossover frequency of the feedforward amplifier is calculated

using the following equation:

2πR3C1

2πR1C1

2πC2 (R2 + R3) 2πR3C2

FREQUENCY (Hz Log Scale)

Figure 20. Bode Plot for PID Compensation

With an ADN8831-EVALZ board, AN-695, an application note

shows how to determine the PID network components for a

stable TEC subsystem performance.

Rev. A | Page 16 of 20

Data Sheet

ADN8831

MOSFET DRIVER AMPLIFIER

5.0

2.5

0

The ADN8831 has two separate MOSFET drivers: a switched

output or pulse-width modulated (PWM) amplifier, and a high

gain linear amplifier. Each amplifier has a pair of outputs that drive

the gates of external MOSFETs which, in turn, drive the TEC as

shown in Figure 17. A voltage across the TEC is monitored via

SFB (Pin 23) and LFB (Pin 27). Although both MOSFET drivers

achieve the same result, to provide constant voltage and high

current, their operation is different. The exact equations for the

two outputs are

5.0

2.5

0

V_LFB= V_B− 40(V_OUT2−1.25)

V_SFB= V_LFB+ 5(V_OUT2−1.25)

where:

5.0

2.5

V_OUT2is the voltage at OUT2 (Pin 7).

V_Bis determined by V_DDas

V_B=1.5 V[V_DD< 4.0 V]

0

V_B= 2.5 V[V_DD> 4.0 V]

The voltage at OUT2 (Pin 7) is determined by the compensation

network that receives temperature set voltage and thermistor

voltage fed by the input amplifier. V_LFBhas a low limit of 0 V

and an upper limit of V_DD. Figure 21 shows the graphs of these

equations.

–2.5

–5.0

0

0.25

0.75

1.25

1.75

2.25

2.75

OUT2 (V)

Figure 21. OUT2 Voltage vs. TEC Voltage

Rev. A | Page 17 of 20

ADN8831

Data Sheet

OUTLINE DIMENSIONS

5.10

5.00 SQ

4.90

0.30

0.25

0.18

PIN 1

INDICATOR

PIN 1

INDICATOR

25

24

32

1

0.50

BSC

3.25

3.10 SQ

2.95

EXPOSED

PAD

17

16

8

9

0.50

0.40

0.30

0.25 MIN

TOP VIEW

BOTTOM VIEW

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

0.80

0.75

0.70

0.05 MAX

0.02 NOM

SECTION OF THIS DATA SHEET.

COPLANARITY

0.08

0.20 REF

SEATING

PLANE

COMPLIANT TO JEDEC STANDARDS MO-220-WHHD.

Figure 22. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

5 mm× 5 mm Body, Very Thin Quad

(CP-32-7)

Dimensions Shown in Millimeters

ORDERING GUIDE

Model¹

Temperature Range

Package Description

Package Option

CP-32-7

ADN8831ACPZ-R2

ADN8831ACPZ-REEL7

ADN8831-EVALZ

32-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

Evaluation Board

−40C to +85C

CP-32-7

¹Z = RoHS Compliant Part.

Rev. A | Page 18 of 20

Data Sheet

NOTES

ADN8831

Rev. A | Page 19 of 20

ADN8831

NOTES

Data Sheet

registered trademarks are the property of their respective owners.

D04663-0-8/12(A)

Rev. A | Page 20 of 20


型号：	ADN8831-EVALZ
厂家：	ADI
描述：	Thermoelectric Cooler (TEC) Controller 热电冷却器（ TEC ）控制器控制器
文件：	总20页 (文件大小：408K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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