ADN8834ACPZ-R7_技术文档

Ultracompact, 1.5 A Thermoelectric Cooler

(TEC) Controller

Data Sheet

ADN8834

FEATURES

FUNCTIONAL BLOCK DIAGRAM

VLIM/

Patented high efficiency single inductor architecture

Integrated low R_DSONMOSFETs for the TEC controller

TEC voltage and current operation monitoring

No external sense resistor required

Independent TEC heating and cooling current limit settings

Programmable maximum TEC voltage

2.0 MHz PWM driver switching frequency

External synchronization

Two integrated, zero drift, rail-to-rail chopper amplifiers

Capable of NTC or RTD thermal sensors

2.50 V reference output with 1% accuracy

Temperature lock indicator

VDD

SD ILIM VTEC ITEC

PVIN

ERROR

AMP

TEC DRIVER

IN1P

IN1N

TEC CURRENT

AND VOLTAGE

SENSE AND LIMIT

LDR

LINEAR

POWER

STAGE

OUT1

COMP

AMP

IN2P

IN2N

CONTROLLER

SW

PWM

POWER

STAGE

SFB

OUT2

Available in a 25-ball, 2.5 mm × 2.5 mm WLCSP or in a

24-lead, 4 mm × 4 mm LFCSP

VOLTAGE

REFERENCE

OSCILLATOR

APPLICATIONS

TEC temperature control

AGND

VREF

EN/SY

PGNDx

Optical modules

Optical fiber amplifiers

Figure 1.

Optical networking systems

Instruments requiring TEC temperature control

GENERAL DESCRIPTION

The ADN8834 is a monolithic TEC controller with an integrated

TEC controller. It has a linear power stage, a pulse-width

modulation (PWM) power stage, and two zero-drift, rail-to-rail

operational amplifiers. The linear controller works with the PWM

driver to control the internal power MOSFETs in an H-bridge

configuration. By measuring the thermal sensor feedback

voltage and using the integrated operational amplifiers as a

proportional integral differential (PID) compensator to condition

the signal, the ADN8834 drives current through a TEC to settle

the temperature of a laser diode or a passive component attached

to the TEC module to the programmed target temperature.

The temperature control loop of the ADN8834 is stabilized by

PID compensation utilizing the built in, zero drift chopper

amplifiers. The internal 2.50 V reference voltage provides a 1%

accurate output that is used to bias a thermistor temperature

sensing bridge as well as a voltage divider network to program

the maximum TEC current and voltage limits for both the heating

and cooling modes. With the zero drift chopper amplifiers,

extremely good long-term temperature stability is maintained via

an autonomous analog temperature control loop.

Table 1. TEC Family Models

Device No. MOSFET

Thermal Loop

Package

The ADN8834 supports negative temperature coefficient (NTC)

thermistors as well as positive temperature coefficient (PTC)

resistive temperature detectors (RTD). The target temperature is

set as an analog voltage input either from a digital-to-analog

converter (DAC) or from an external resistor divider.

ADN8831

ADN8833

Discrete

Integrated Digital

Digital/analog

LFCSP (CP-32-7)

WLCSP (CB-25-7),

LFCSP (CP-24-15)

ADN8834

Integrated Digital/analog

WLCSP (CB-25-7),

LFCSP (CP-24-15)

Rev. A

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Last Content Update: 02/23/2017

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DOCUMENTATION

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• ADN8834: Ultracompact, 1.5 A Thermoelectric Cooler

(TEC) Controller

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Thermoelectric Cooler (TEC) Controller

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REFERENCE MATERIALS

Technical Articles

• Tec Controller Applications In Telecommunication

Systems

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ADN8834

Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

TEC Voltage/Current Monitor ................................................. 16

Maximum TEC Voltage Limit .................................................. 16

Maximum TEC Current Limit ................................................. 17

Applications Information.............................................................. 18

Signal Flow .................................................................................. 18

Thermistor Setup........................................................................ 18

Thermistor Amplifier (Chopper 1).......................................... 19

PID Compensation Amplifier (Chopper 2)............................ 19

MOSFET Driver Amplifiers...................................................... 20

PWM Output Filter Requirements .......................................... 20

Input Capacitor Selection.......................................................... 21

Power Dissipation....................................................................... 21

PCB Layout Guidelines.................................................................. 23

Block Diagrams and Signal Flow ............................................. 23

Guidelines for Reducing Noise and Minimizing Power Loss.....23

Example PCB Layout Using Two Layers................................. 24

Outline Dimensions....................................................................... 27

Ordering Guide .......................................................................... 27

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description......................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Absolute Maximum Ratings............................................................ 6

Thermal Resistance ...................................................................... 6

ESD Caution.................................................................................. 6

Pin Configurations and Function Descriptions ........................... 7

Typical Performance Characteristics ............................................. 8

Detailed Functional Block Diagram ............................................ 12

Theory of Operation ...................................................................... 13

Analog PID Control................................................................... 14

Digital PID Control.................................................................... 14

Powering the Controller ............................................................ 14

Enable and Shutdown ................................................................ 15

Oscillator Clock Frequency....................................................... 15

Temperature Lock Indicator (LFCSP Only) ........................... 15

Soft Start on Power-Up.............................................................. 15

REVISION HISTORY

8/15—Rev. 0 to Rev. A

Added 24-Lead LFCSP.......................................................Universal

Changes to Features Section and Table 1 ...................................... 1

Changes to Table 2............................................................................ 3

Changes to Table 3............................................................................ 6

Added Figure 3; Renumbered Sequentially .................................. 7

Changes to Figure 13........................................................................ 9

Changes to Figure 23 and Figure 24............................................. 11

Changes to Figure 25...................................................................... 12

Changes to Powering the Controller Section and Figure 27

Caption............................................................................................. 14

Change to Soft Start on Power-Up Section................................. 15

Change to Figure 33 ....................................................................... 18

Changes to Table 7.......................................................................... 21

Added Table 8; Renumbered Sequentially .................................. 21

Updated Outline Dimensions....................................................... 27

Changes to Ordering Guide .......................................................... 27

4/15—Revision 0: Initial Version

Rev. A | Page 2 of 27

Data Sheet

ADN8834

SPECIFICATIONS

V_IN= 2.7 V to 5.5 V, T _J= −40°C to +125°C for minimum/maximum specifications, and T_A= 25°C for typical specifications, unless

otherwise noted.

Table 2.

Parameter

Symbol

Test Conditions/Comments

Min

Typ

Max

Unit

POWER SUPPLY

Driver Supply Voltage

Controller Supply Voltage

Supply Current

Shutdown Current

Undervoltage Lockout (UVLO)

UVLO Hysteresis

REFERENCE VOLTAGE

LINEAR OUTPUT

Output Voltage

V_PVIN

V_VDD

I_VDD

2.7

5.5

5

700

2.65

100

2.525

V

PWM not switching

EN/SY = AGND or VLIM/SD = AGND

V_VDDrising

3.3

mA

µA

V

mV

V

I_SD

350

2.55

90

V_UVLO

UVLO_HYST

V_VREF

2.45

80

I_VREF= 0 mA to 10 mA

I_LDR= 0 A

2.475

2.50

V_LDR

Low

High

0

V_PVIN

V

A

Maximum Source Current

I_{LDR_SOURCE}

I_{LDR_SINK}

T_J= −40°C to +105°C

T_J= −40°C to +125°C

T_J= −40°C to +105°C

T_J= −40°C to +125°C

I_LDR= 0.6 A

WLCSP, V_PVIN= 5.0 V

WLCSP, V_PVIN= 3.3 V

LFCSP, V_PVIN= 5.0 V

LFCSP, V_PVIN= 3.3 V

WLCSP, V_PVIN= 5.0 V

WLCSP, V_PVIN= 3.3 V

LFCSP, V_PVIN= 5.0 V

LFCSP, V_PVIN= 3.3 V

1.5

1.2

Maximum Sink Current

1.5

1.2

On Resistance

P-MOSFET

R_{DS_PL(ON)}

35

44

50

55

31

40

45

50

60

65

75

50

55

70

80

mΩ

N-MOSFET

R_{DS_NL(ON)}

Leakage Current

P-MOSFET

N-MOSFET

Linear Amplifier Gain

LDR Short-Circuit Threshold

I_{LDR_P_LKG}

I_{LDR_N_LKG}

A_LDR

I_{LDR_SH_GNDL}

I_{LDR_SH_PVIN(L)}

T_HICCUP

0.1

40

2.2

−2.2

15

10

µA

V/V

A

ms

LDR short to PGNDL, enter hiccup

LDR short to PVIN, enter hiccup

Hiccup Cycle

PWM OUTPUT

Output Voltage

Low

V_SFB

I_SFB= 0 A

V

A

0.06 × V_PVIN

0.93 × V_PVIN

High

Maximum Source Current

I_{SW_SOURCE}

I_{SW_SINK}

T_J= −40°C to +105°C

T_J= −40°C to +125°C

T_J= −40°C to +105°C

T_J= −40°C to +125°C

I_SW= 0.6 A

WLCSP, V_PVIN= 5.0 V

WLCSP, V_PVIN= 3.3 V

LFCSP, V_PVIN= 5.0 V

LFCSP, V_PVIN= 3.3 V

1.5

1.2

Maximum Sink Current

1.5

1.2

On Resistance

P-MOSFET

R_{DS_PS(ON)}

47

60

70

65

80

95

mΩ

Rev. A | Page 3 of 27

ADN8834

Data Sheet

Parameter

Symbol

Test Conditions/Comments

WLCSP, V_PVIN= 5.0 V

WLCSP, V_PVIN= 3.3 V

LFCSP, V_PVIN= 5.0 V

Min

Typ

40

45

55

Max

60

65

75

85

Unit

mΩ

N-MOSFET

R_{DS_NS(ON)}

LFCSP, V_PVIN= 3.3 V

Leakage Current

P-MOSFET

N-MOSFET

SW Node Rise Time¹

PWM Duty Cycle²

SFB Input Bias Current

PWM OSCILLATOR

I_{SW_P_LKG}

I_{SW_N_LKG}

t_{SW_R}

D_SW

I_SFB

0.1

1

10

µA

ns

%

µA

C_SW= 1 nF

6

93

2

1

Internal Oscillator Frequency

EN/SY Input Voltage

Low

f_OSC

EN/SY high

1.85

2.0

2.15

0.8

MHz

V_{EN/SY_ILOW}

V_{EN/SY_IHIGH}

f_SYNC

V

MHz

%

ns

Cycles

µA

High

2.1

1.85

10

External Synchronization Frequency

Synchronization Pulse Duty Cycle

EN/SY Rising to PWM Rising Delay

EN/SY to PWM Lock Time

EN/SY Input Current

Pull-Down Current

3.25

90

D_SYNC

t_{SYNC_PWM}

t_{SY_LOCK}

I_EN/SY

50

Number of SYNC cycles

10

0.5

0.3

ERROR/COMPENSATION AMPLIFIERS

Input Offset Voltage

V_OS1

V_OS2

V_CM1, V_CM2

V_CM1= 1.5 V, V_OS1= V_IN1P− V_IN1N

V_CM2= 1.5 V, V_OS2= V_IN2P− V_IN2N

10

100

V_VDD

µV

V

Input Voltage Range

0

Common-Mode Rejection Ratio (CMRR) CMRR₁, CMRR₂V_CM1, V_CM2= 0.2 V to V_VDD− 0.2 V

Output Voltage

120

dB

High

V_OH1, V_OH2

V_VDD

0.04

−

V

Low

V_OL1, V_OL2

PSRR₁, PSRR₂

I_OUT1, I_OUT2

10

mV

dB

mA

MHz

Power Supply Rejection Ratio (PSRR)

Output Current

Gain Bandwidth Product¹

TEC CURRENT LIMIT

ILIM Input Voltage Range

Cooling

120

2

Sourcing and sinking

V_OUT1,V_OUT2= 0.5 V to V_VDD− 1 V

5

GBW₁, GBW₂

V_ILIMC

V_ILIMH

1.3

0.2

V_VREF

0.2

1.2

−

V

Heating

Current-Limit Threshold

Cooling

Heating

V_{ILIMC_TH}

V_{ILIMH_TH}

V_ITEC= 0.5 V

V_ITEC= 2 V

1.98

0.48

2.0

0.5

2.02

0.52

V

ILIM Input Current

Heating

Cooling

Cooling to Heating Current Detection

Threshold

I_ILIMH

I_ILIMC

I_{COOL_HEAT_TH}

−0.2

37.5

+0.2

42.5

µA

mA

Sourcing current

(V_DRL− V_SFB)/V_VLIM

40

TEC VOLTAGE LIMIT

Voltage Limit Gain

VLIM/SD Input Voltage Range¹

VLIM/SD Input Current

Cooling

A_VLIM

V_VLIM

2

V/V

V

0.2

V_VDD/2

I_ILIMC

I_ILIMH

V_OUT2< V_VREF/2

V_OUT2> V_VREF/2, sinking current

−0.2

8

+0.2

12.2

µA

Heating

10

Rev. A | Page 4 of 27

Data Sheet

ADN8834

Parameter

Symbol

R_CS

Test Conditions/Comments

Min

Typ

Max

Unit

TEC CURRENT MEASUREMENT (WLCSP)

Current Sense Gain

V_PVIN= 3.3 V

V_PVIN= 5 V

700 mA ≤ I_LDR≤ 1.5 A, V_PVIN= 3.3 V

800 mA ≤ I_LDR≤ 1.5 A, V_PVIN= 5 V

V_PVIN= 3.3 V, cooling, V_VREF/2 +

I_LDR× R_CS

0.525

0.535

V/A

%

V

Current Measurement Accuracy

ITEC Voltage Accuracy

I_{LDR_ERROR}

−10

1.597

+10

1.649

V_{ITEC_@_700_mA}

V_{ITEC_@_−700_mA}

1.618

0.883

V_PVIN= 3.3 V, heating, V_VREF/2 −

0.846

0.891

V

I

_LDR× R_CS

V_{ITEC_@_800_mA}

V_{ITEC_@_−800_mA}

V_PVIN= 5 V, cooling, V_VREF/2 + I_LDR× R_CS

V_PVIN= 5 V, heating, V_VREF/2 − I_LDR× R_CS0.783

1.657

1.678

0.822

1.718

0.836

V

TEC CURRENT MEASUREMENT (LFCSP)

Current Sense Gain

R_CS

V_PVIN= 3.3 V

V_PVIN= 5 V

700 mA ≤ I_LDR≤ 1 A, V_PVIN= 3.3 V

800 mA ≤ I_LDR≤ 1 A, V_PVIN= 5 V

V_PVIN= 3.3 V, cooling, V_VREF/2 + I_LDR

R_CS

V_PVIN= 3.3 V, heating, V_VREF/2 − I_LDR

R_CS

V_PVIN= 5 V, cooling, V_VREF/2 + I_LDR

R_CS

V_PVIN= 5 V, heating, V_VREF/2 − I_LDR

R_CS

0.525

V/A

%

V

Current Measurement Accuracy

ITEC Voltage Accuracy

I_{LDR_ERROR}

−15

1.374

+15

1.861

V_{ITEC_@_700_mA}

V_{ITEC_@_−700_mA}

V_{ITEC_@_800_mA}

V_{ITEC_@_−800_mA}

V_ITEC

×

1.618

0.883

1.678

0.830

×

0.750

1.419

0.705

0

1.015

1.921

0.955

V

×

ITEC Voltage Output Range

I_TEC= 0 A

V_VREF

0.05

−

ITEC Bias Voltage

V_ITEC

I_ITEC

I_LDR= 0 A

1.210

−2

1.250

1.285

+2

V

mA

Maximum ITEC Output Current

TEC VOLTAGE MEASUREMENT

Voltage Sense Gain

A_VTEC

V_{VTEC_@_1_V}

0.24

1.475

0.25

1.50

0.26

1.525

V/V

V

Voltage Measurement Accuracy

V_LDR– V_SFB= 1 V, V_VREF/2+ A_VTEC

×

(V_LDR– V_SFB

)

VTEC Output Voltage Range

VTEC Bias Voltage

V_VTEC

V_{VTEC_B}

R_VTEC

0.005

1.225

−2

2.625

1.285

+2

V

mA

V_LDR= V_SFB

1.250

Maximum VTEC Output Current

TEMPERATURE GOOD (LFCSP Only)

TMPGD Low Output Voltage

TMPGD High Output Voltage

TMPGD Output Low Impedance

TMPGD Output High Impedance

High Threshold

V_{TMPGD_LO}

V_{TMPGD_HO}

R_{TMPGD_LOW}

V_{OUT1_THH}

V_{OUT1_THL}

No load

0.4

V

Ω

V

2.0

25

50

1.54

1.46

IN2N tied to OUT2, V_IN2P= 1.5 V

1.56

Low Threshold

1.40

INTERNAL SOFT START

Soft Start Time

t_SS

150

ms

V

VLIM/SD SHUTDOWN

VLIM/SD Low Voltage Threshold

THERMAL SHUTDOWN

V_{VLIM/SD_THL}

0.07

Thermal Shutdown Threshold

Thermal Shutdown Hysteresis

T_{SHDN_TH}

T_{SHDN_HYS}

170

17

°C

¹This specification is guaranteed by design.

²This specification is guaranteed by characterization.

Rev. A | Page 5 of 27

ADN8834

Data Sheet

ABSOLUTE MAXIMUM RATINGS

Table 3.

Stresses at or above those listed under Absolute Maximum

Ratings may cause permanent damage to the product. This is a

stress rating only; functional operation of the product at these

or any other conditions above those indicated in the operational

section of this specification is not implied. Operation beyond

the maximum operating conditions for extended periods may

affect product reliability.

Parameter

Rating

PVIN to PGNDL (WLCSP)

PVIN to PGNDS (WLCSP)

PVINL to PGNDL (LFCSP)

PVINS to PGNDS (LFCSP)

LDR to PGNDL (WLCSP)

LDR to PGNDL (LFCSP)

SW to PGNDS

−0.3 V to +5.75 V

−0.3 V to V_PVIN

−0.3 V to V_PVINL

−0.3 V to +5.75 V

−0.3 V to V_VDD

THERMAL RESISTANCE

θ_JAis specified for the worst-case conditions, that is, a device

soldered in a circuit board for surface-mount packages, and is

based on a 4-layer standard JEDEC board.

SFB to AGND

AGND to PGNDL

AGND to PGNDS

VLIM/SD to AGND

ILIM to AGND

−0.3 V to +0.3 V

−0.3 V to V_VDD

Table 4.

Package Type

25-Ball WLCSP

24-Lead LFCSP

θ_JA

48

37

θ_JC

Unit

°C/W

−0.3 V to V_VDD

0.6

1.65

VREF to AGND

VDD to AGND

IN1P to AGND

−0.3 V to +3 V

−0.3 V to +5.75 V

−0.3 V to V_VDD

IN1N to AGND

OUT1 to AGND

IN2P to AGND

−0.3 V to V_VDD

−0.3 V to +5.75 V

−0.3 V to V_VDD

ESD CAUTION

IN2N to AGND

−0.3 V to V_VDD

OUT2 to AGND

EN/SY to AGND

−0.3 V to +5.75 V

−0.3 V to V_VDD

ITEC to AGND

VTEC to AGND

−0.3 V to +5.75 V

Maximum Current

VREF to AGND

20 mA

OUT1 to AGND

50 mA

OUT2 to AGND

50 mA

ITEC to AGND

50 mA

VTEC to AGND

50 mA

Junction Temperature

Storage Temperature Range

125°C

−65°C to +150°C

Lead Temperature (Soldering, 10 sec) 260°C

Rev. A | Page 6 of 27

Data Sheet

ADN8834

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

1

2

3

4

5

A

B

C

D

E

PGNDL

OUT1

PGNDL

IN1P

IN2P

1

18 PGNDL

LDR

IN2N

OUT2 2

17

ADN8834

16 PVINL

15 PVINS

14 SW

3

VLIM/SD

VLIM/

SD

LDR

IN1N

ITEC

VTEC

LDR

IN2N

TOP VIEW

ILIM 4

(Not to Scale)

5

VDD

VREF 6

PGNDS

13

PVIN

2.54mm

PVIN

OUT2

ILIM

NOTES

1. EXPOSED PAD. SOLDER TO THE ANALOG

GROUND PLANE ON THE BOARD.

SW

EN/SY

AGND

VDD

0.5mm

PITCH

PGNDS

SFB

PGNDS

VREF

2.54mm

ADN8834

TOP VIEW

(BALLS ON THE BOTTOM SIDE)

Figure 3. LFCSP Pin Configuration (Top View)

Figure 2. WLCSP Pin Configuration (Top View)

Table 5. Pin Function Descriptions

Pin No.

WLCSP LFCSP

Mnemonic Description

A1, A2

N/A¹

A3

A4

A5

B1, B2

B3

B4

18, 19

20

21

23

24

17

22

1

PGNDL

TMPGD

OUT1

IN1P

IN2P

LDR

Power Ground of the Linear TEC Controller.

Temperature Good Output.

Output of the Error Amplifier.

Noninverting Input of the Error Amplifier.

Noninverting Input of the Compensation Amplifier.

Output of the Linear TEC Controller.

IN1N

IN2N

Inverting Input of the Error Amplifier.

Inverting Input of the Compensation Amplifier.

B5

3

VLIM/SD

Voltage Limit/Shutdown. This pin sets the cooling and heating TEC voltage limits. When this pin

is pulled low, the device shuts down.

C1, C2

N/A¹

C3

C4

C5

D1, D2

D3

D4

N/A¹

16

15

11

2

4

14

9

PVIN

PVINL

PVINS

ITEC

OUT2

ILIM

SW

VTEC

EN/SY

Power Input for the TEC Controller.

Power Input for the Linear TEC Driver.

Power Input for the PWM TEC Driver.

TEC Current Output.

Output of the Compensation Amplifier.

Current Limit. This pin sets the TEC cooling and heating current limits.

Switch Node Output of the PWM TEC Controller.

TEC Voltage Output.

8

Enable/Synchronization. Set this pin high to enable the device. An external synchronization

clock input can be applied to this pin.

D5

5

VDD

Power for the Controller Circuits.

E1, E2

E3

E4

E5

N/A¹

12, 13

10

7

6

0

PGNDS

SFB

AGND

VREF

EPAD

Power Ground of the PWM TEC Controller.

Feedback of the PWM TEC Controller Output.

Signal Ground.

2.5 V Reference Output.

Exposed Pad. Solder to the analog ground plane on the board.

¹N/A means not applicable.

Rev. A | Page 7 of 27

ADN8834

Data Sheet

TYPICAL PERFORMANCE CHARACTERISTICS

T_A= 25°C, unless otherwise noted.

100

90

80

70

60

50

40

30

20

10

0

100

V

= 3.3V

= 5V

IN

90

80

70

60

50

40

30

20

10

0

LOAD = 2Ω

LOAD = 3Ω

LOAD = 4Ω

LOAD = 5Ω

0

0.5

1.0

1.5

0

1.5

0.5

1.0

TEC CURRENT (A)

Figure 4. Efficiency vs. TEC Current at V_IN= 3.3 V and 5 V in Cooling Mode

with 2 Ω Load

Figure 7. Efficiency vs. TEC Current at V_IN= 3.3 V with Different Loads in

Heating Mode

100

V

= 3.3V

= 5V

IN

1.4

1.2

1.0

0.8

0.6

90

80

70

60

50

40

30

20

10

0

0.4

LOAD = 2Ω

0.2

LOAD = 3Ω

LOAD = 4Ω

LOAD = 5Ω

0

2.7

3.0

3.5

4.0

4.5

5.0

5.5

0

0.5

1.0

1.5

INPUT VOLTAGE AT PVIN (V)

TEC CURRENT (A)

Figure 5. Efficiency vs. TEC Current at V_IN= 3.3 V and 5 V in Heating Mode

with 2 Ω Load

Figure 8. Maximum TEC Current vs. Input Voltage at PVIN (V_IN= 3.3 V),

Without Voltage and Current Limit in Cooling Mode

100

90

80

70

60

50

40

30

1.4

1.2

1.0

0.8

0.6

0.4

20

LOAD = 2Ω

0.2

LOAD = 3Ω

10

LOAD = 4Ω

LOAD = 5Ω

LOAD = 4Ω

LOAD = 5Ω

0

2.7

0

0.5

1.0

1.5

3.0

3.5

4.0

4.5

5.0

5.5

TEC CURRENT (A)

INPUT VOLTAGE AT PVIN (V)

Figure 9. Maximum TEC Current vs. Input Voltage at PVIN (V_IN= 3.3 V),

Without Voltage and Current Limit in Heating Mode

Figure 6. Efficiency vs. TEC Current at V_IN= 3.3 V with Different Loads in

Cooling Mode

Rev. A | Page 8 of 27

Data Sheet

ADN8834

0.10

0.20

0.15

0.10

0.05

0

V

= 3.3V, ITEC = 0A

T = 15°C

IN

T = 25°C

T = 35°C

T = 45°C

T = 55°C

0.08

0.06

0.04

0.02

0

= 3.3V, ITEC = 0.5A, COOLING

= 3.3V, ITEC = 0.5A, HEATING

= 5.0V, ITEC = 0A

= 5.0V, ITEC = 0.5A, COOLING

= 5.0V, ITEC = 0.5A, HEATING

–0.02

–0.04

–0.06

–0.08

–0.10

–0.05

–0.10

–0.15

–0.20

0

1

2

3

4

5

6

7

8

9

10

0

20

40

60

80

100 120 140 160 180 200

LOAD CURRENT AT V

(mA)

REF

TIME (Seconds)

Figure 10. Thermal Stability over Ambient Temperature at V_IN= 3.3 V,

V_TEMPSET= 1 V

Figure 13. V_REFLoad Regulation

0.10

20

15

T = 15°C

V

= 3.3V

= 5V

IN

T = 25°C

0.08

T = 35°C

T = 45°C

0.06

0.04

T = 55°C

10

5

0.02

0

–0.02

–0.04

–0.06

–0.08

–0.10

–5

–10

–15

–20

0

20

40

60

80

100 120 140 160 180 200

0

0.5

1.0

1.5

TIME (Seconds)

TEC CURRENT (A)

Figure 11. Thermal Stability over Ambient Temperature at V_IN= 3.3 V,

V_TEMPSET= 1.5 V

Figure 14. ITEC Current Reading Error vs. TEC Current in Cooling Mode

1.0

20

V

= 3.3V

= 5V

V

= 2.7V AT NO LOAD

= 3.3V AT NO LOAD

= 5.5V AT NO LOAD

= 2.7V AT 5mA LOAD

= 3.3V AT 5mA LOAD

= 5.5V AT 5mA LOAD

IN

0.8

0.6

15

10

5

0.4

0.2

0

–0.2

–0.4

–0.6

–0.8

–1.0

–5

–10

–15

–20

–

1.5

–1.0

–0.5

0

–50

0

50

100

150

AMBIENT TEMPERATURE (°C)

TEC CURRENT (A)

Figure 15. ITEC Current Reading Error vs. TEC Current in Heating Mode

Figure 12. V_REFError vs. Ambient Temperature

Rev. A | Page 9 of 27

ADN8834

Data Sheet

20

V

= 3.3V

= 5V

IN

15

10

5

TEC CURRENT

0

4

1

PWM (TEC–)

–5

–10

–15

–20

LDO (TEC+)

0.5

1.0

1.5

2.0

2.5

B

W

CH1 500mV

CH3 300mA Ω

CH2 500mV

M10ms

5.4ms

A CH4

–8mA

W

B

TEC VOLTAGE (V)

T

W

Figure 16. VTEC Voltage Reading Error vs. TEC Voltage in Cooling Mode

Figure 19. Zero Crossing TEC Current Zoom in from Heating to Cooling

20

V

= 3.3V

= 5V

IN

15

10

5

TEC CURRENT

0

4

PWM (TEC–)

–5

–10

–15

LDO (TEC+)

1

–20

–2.5

–2.0

–1.5

–1.0

–0.5

B

W

CH1 500mV

CH3 200mA Ω

CH2 500mV

M10ms

5.4ms

A CH4

12mA

W

B

TEC VOLTAGE (V)

T

W

Figure 17. VTEC Voltage Reading Error vs. TEC Voltage in Heating Mode

Figure 20. Zero Crossing TEC Current Zoom in from Cooling to Heating

LDO (TEC+)

EN

3

PWM (TEC–)

TEC CURRENT

4

LDO (TEC–)

PWM (TEC+)

1

B

W

CH1 500mV

CH4 200mA Ω

CH2 500mV

M200ms

A CH4

–108mA

W

B

W

CH1 1V ^BCH2 1V

CH3 2V

M20.0ms

A CH3

800mV

W

T

–28.000ms

W

B

CH4 500mA Ω

T

40ms

W

Figure 18. Cooling to Heating Transition

Figure 21. Typical Enable Waveforms in Cooling Mode,

V_IN= 3.3 V, Load = 2 Ω, TEC Current = 1 A

Rev. A | Page 10 of 27

Data Sheet

ADN8834

EN

SW

3

TEC CURRENT

4

LDO (TEC+)

1

2

PWM (TEC–)

LDO (TEC+)

2

B

M20.0ms

W

CH1 20mV

CH3 2.0V

CH2 20mV

M400ns

W

A CH3

2.50GS/s

1.00V

CH1 1V ^BCH2 1V

CH3 2V

A CH3

800mV

W

B

T

0.0s

W

CH4 500mA Ω

T

40ms

W

Figure 22. Typical Enable Waveforms in Heating Mode,

V_IN= 3.3 V, Load = 2 Ω, TEC Current = 1 A

Figure 24. Typical Switch and Voltage Ripple Waveforms in Heating Mode,

V_IN= 3.3 V, Load = 2 Ω, TEC Current = 1 A

SW

3

LDO (TEC+)

PWM (TEC–)

1

2

B

CH1 20mV

CH3 2.0V

CH2 20mV

M400ns

W

A CH3

2.50GS/s

1.00V

W

B

T

0.0s

W

Figure 23. Typical Switch and Voltage Ripple Waveforms in Cooling Mode

V_IN= 3.3 V, Load = 2 Ω, TEC Current = 1 A

Rev. A | Page 11 of 27

ADN8834

Data Sheet

DETAILED FUNCTIONAL BLOCK DIAGRAM

VTEC

ITEC

ADN8834

TEC DRIVER

LINEAR POWER

STAGE

VDD

COOLING

HEATING

VDD

5kΩ

PVIN

20kΩ

BAND GAP

2.5V

5kΩ

VOLTAGE

1.25V

VREF

1.25V

REFERENCE

TEC CURRENT SENSE

LDR

–

+

20kΩ

V

= 2.5V AT VDD > 4.0V

= 1.5V AT VDD < 4.0V

B

TEC

VOLTAGE

SENSE

V

B

SFB

2kΩ

80kΩ

LDR

V

C

AGND

IN1P

+

–

TEMPERATURE

ERROR

AMPLIFIER

V

B

LINEAR

AMPLIFIER

PGNDL

V

B

IN1N

80kΩ

OUT1

400kΩ

SFB

20kΩ

PWM POWER

STAGE

1.25V

PVIN

100kΩ

COMPENSATION

AMPLIFIER

V

C

IN2P

IN2N

20kΩ

PWM

MODULATOR

20kΩ

PWM

MOSFET

DRIVER

PWM

OUT2

VDD

SW

ERROR

AMPLIFIER

TEC VOLTAGE

LIMIT AND INTERNAL

SOFT START

40µA

CLK

V

B

OSCILLATOR

CLK

COOLING

HEATING

PGNDS

V

≥ 2.1V

≤ 0.8V

HIGH

LOW

SHUTDOWN

ITEC

10µA

DEGLITCH

TEC

CURRENT

LIMIT

SHUTDOWN

0.07V

ILIM

EN/SY

VLIM/SD

Figure 25. Detailed Functional Block Diagram of the ADN8834 for the WLCSP

Rev. A | Page 12 of 27

Data Sheet

ADN8834

THEORY OF OPERATION

The ADN8834 is a single chip TEC controller that sets and

stabilizes a TEC temperature. A voltage applied to the input of

the ADN8834 corresponds to the temperature setpoint of the target

object attached to the TEC. The ADN8834 controls an internal

FET H-bridge whereby the direction of the current fed through

the TEC can be either positive (for cooling mode), to pump

heat away from the object attached to the TEC, or negative (for

heating mode), to pump heat into the object attached to the TEC.

The ADN8834 drives its internal MOSFET transistors to provide

the TEC current. To provide good power efficiency and zero

crossing quality, only one side of the H-bridge uses a PWM

driver. Only one inductor and one capacitor are required to filter

out the switching frequency. The other side of the H-bridge uses a

linear output without requiring any additional circuitry. This pro-

prietary configuration allows the ADN8834 to provide efficiency of

>90%. For most applications, a 1 µH inductor, a 10 μF capacitor,

and a switching frequency of 2 MHz maintain less than 1% of the

worst-case output voltage ripple across a TEC.

Temperature is measured with a thermal sensor attached to the

target object and the sensed temperature (voltage) is fed back to

the ADN8834 to complete a closed thermal control loop of the

TEC. For the best overall stability, couple the thermal sensor

close to the TEC. In most laser diode modules, a TEC and a

NTC thermistor are already mounted in the same package to

regulate the laser diode temperature.

The maximum voltage across the TEC and the current flowing

through the TEC are set by using the VLIM/SD and ILIM pins.

The maximum cooling and heating currents can be set indepen-

dently to allow asymmetric heating and cooling limits. For

additional details, see the Maximum TEC Voltage Limit section

and the Maximum TEC Current Limit section.

The TEC is differentially driven in an H-bridge configuration.

TEC

CURRENT

ENABLE/

SYNC

TEC

VOLTAGE

SHUTDOWN

C

VDD

0.1µF

V

IN

R

BP

2.7V TO 5.5V

EN/SY

ITEC

VTEC

VDD

VLIM/SD

TEC

VOLTAGE

LIMIT

PVIN

C

10µF

R

IN

V2

V1

TEC

CURRENT

LIMITS

ILIM

R

C1

R

C2

LDR

PGNDL

SFB

C

0.1µF

TEC

+

L_OUT

ADN8834

VREF

C

0.1µF

VREF

–

R

A

AGND

TEMP

SET

L = 1µH

IN2P

IN1P

IN1N

SW

C

10µF

SW_OUT

OUT1

IN2N

OUT2 PGNDS

R

X

B

R

FB

C

I

R

P

I

NTC

R

TH

C

R

D

F

D

THERMISTER

Figure 26. Typical Application Circuit with Analog PID Compensation in a Temperature Control Loop

Rev. A | Page 13 of 27

ADN8834

Data Sheet

The Chopper 2 amplifier is used as a buffer for the external

ANALOG PID CONTROL

DAC, which controls the temperature setpoint. Connect the

DAC to IN2P and short the IN2N and OUT2 pins together. See

Figure 27 for an overview of how to configure the ADN8834

external circuitry for digital PID control.

The ADN8834 integrates two self-correcting, auto-zeroing

amplifiers (Chopper 1 and Chopper 2). The Chopper 1 amplifier

takes a thermal sensor input and converts or regulates the input

to a linear voltage output. The OUT1 voltage is proportional to

the object temperature. The OUT1 voltage is fed into the

POWERING THE CONTROLLER

compensation amplifier (Chopper 2) and is compared with a

temperature setpoint voltage, which creates an error voltage that is

proportional to the difference. For autonomous analog temperature

control, Chopper 2 can be used to implement a PID network as

shown in Figure 27 to set the overall stability and response of the

thermal loop. Adjusting the PID network optimizes the step

response of the TEC control loop. A compromised settling time

and the maximum current ringing become available when this

adjustment is done. To adjust the compensation network, see

the PID Compensation Amplifier (Chopper 2) section.

The ADN8834 operates at an input voltage range of 2.7 V to

5.5 V that is applied to the VDD pin and the PVIN pin for the

WLCSP (the PVINS pin and PVINL pin for the LFCSP. The

VDD pin is the input power for the driver and internal reference.

The PVIN input power pins are combined for both the linear

and the switching driver. Apply the same input voltage to all power

input pins: VDD and PVIN. In some circumstances, an RC low-

pass filter can be added optionally between the PVIN for the

WLCSP (PVINS and PVINL for the LFCSP) and VDD pins to

prevent high frequency noise from entering VDD, as shown in

Figure 27. The capacitor and resistor values are typically 10 Ω

and 100 nF, respectively.

DIGITAL PID CONTROL

The ADN8834 can also be configured for use in a software

controlled PID loop. In this scenario, the Chopper 1 amplifier

can either be left unused or configured as a thermistor input

amplifier connected to an external temperature measurement

analog-to-digital converter (ADC). For more information, see

the Thermistor Amplifier (Chopper 1) section. If Chopper 1 is

left unused, tie IN1N and IN1P to AGND.

When configuring power supply to the ADN8834, keep in mind

that at high current loads, the input voltage may drop substantially

due to a voltage drop on the wires between the front-end power

supply and the PVIN for the WLCSP (PVINS and PVINL for

the LFCSP) pin. Leave a proper voltage margin when designing

the front-end power supply to maintain the performance.

Minimize the trace length from the power supply to the PVIN

for the WLCSP (PVINS and PVINL for the LFCSP) pin to help

mitigate the voltage drop.

ENABLE

COOLING AND HEATING

TEC CURRENT LIMITS

2.5V VREF

R

C2

C1

R

C

0.1µF

V1

TEC

VOLTAGE

LIMIT

VDD

V

IN

R

2.7V TO 5.5V

BP

EN/SY

ILIM

VDD

2.5V VREF

VLIM/SD

PVIN

C

10µF

R

IN

V2

TEMPERATURE SET

DAC

IN2P

TEC CURRENT READBACK

ITEC

VTEC

VREF

LDR

C

0.1µF

TEC

+

L_OUT

TEC VOLTAGE READBACK

ADN8834

PGNDL

2.5V VREF

–

C

NTC

VREF

R

0.1uF

R

SFB

A

B

TH

AGND

L = 1µH

= 2MHz

IN1P

IN1N

SW

PGNDS

C

10µF

SW_OUT

THERMISTER

IN2N OUT2

OUT1

F

SW

R

X

2.5V VREF

R

FB

TEMPERATURE

READBACK

ADC

Figure 27. TEC Controller in a Digital Temperature Control Loop (WLCSP)

Rev. A | Page 14 of 27

Data Sheet

ADN8834

Connecting Multiple ADN8834 Devices

ENABLE AND SHUTDOWN

Multiple ADN8834 devices can be driven from a single master

clock signal by connecting the external clock source to the

EN/SY pin of each slave device. The input ripple can be greatly

reduced by operating the ADN8834 devices 180° out of phase

from each other by placing an inverter at one of the EN/SY pins,

as shown in Figure 29.

To enable the ADN8834, apply a logic high voltage to the

EN/SY pin while the voltage at the VLIM/SD pin is above the

maximum shutdown threshold of 0.07 V. If either the EN/SY

pin voltage is set to logic low or the VLIM/SD voltage is below

0.07 V, the controller goes into an ultralow current state. The

current drawn in shutdown mode is 350 μA typically. Most of

the current is consumed by the VREF circuit block, which is

always on even when the device is disabled or shut down. The

device can also be enabled when an external synchronization

clock signal is applied to the EN/SY pin, and the voltage at

VLIM/SD input is above 0.07 V. Table 6 shows the combinations

of the two input signals that are required to enable the ADN8834.

ADN8834

EXTERNAL CLOCK

EN/SY

SOURCE

AGND

Table 6. Enable Pin Combinations

EN/SY Input

VLIM/SD Input

Controller

Enabled

>2.1 V

>0.07 V

Switching between high >0.07 V

>2.1 V and low < 0.8 V

Enabled

ADN8834

<0.8 V

Floating

No effect¹

Shutdown

No effect¹

EN/SY

AGND

≤0.07 V

¹No effect means this signal has no effect in shutting down or in enabling the

device.

Figure 29. Multiple ADN8834 Devices Driven from a Master Clock

OSCILLATOR CLOCK FREQUENCY

TEMPERATURE LOCK INDICATOR (LFCSP ONLY)

The ADN8834 has an internal oscillator that generates a 2.0 MHz

switching frequency for the PWM output stage. This oscillator is

active when the enabled voltage at the EN/SY pin is set to a logic

level higher than 2.1 V and the VLIM/SD pin voltage is greater

than the shutdown threshold of 0.07 V.

The TMPGD outputs logic high when the temperature error

amplifier output voltage, V_OUT1, reaches the IN2P temperature

setpoint (TEMPSET) voltage. The TMPGD has a detection range

between 1.46 V and 1.54 V of V_OUT1and hysteresis. The TMPGD

function allows direct interfacing either to the microcontrollers

or to the supervisory circuitry.

External Clock Operation

The PWM switching frequency of the ADN8834 can be

synchronized to an external clock from 1.85 MHz to 3.25 MHz,

applied to the EN/SY input pin as shown on Figure 28.

SOFT START ON POWER-UP

The ADN8834 has an internal soft start circuit that generates

aramp with a typical 150 ms profile to minimize inrush current

during power-up. The settling time and the final voltage across

the TEC depends on the TEC voltage required by the control

voltage of voltage loop. The higher the TEC voltage is, the longer it

requires to be built up.

ADN8834

When the ADN8834 is first powered up, the linear side discharges

the output of any prebias voltage. As soon as the prebias is

eliminated, the soft start cycle begins. During the soft start

cycle, both the PWM and linear outputs track the internal soft

start ramp until they reach midscale, where the control voltage,

V_C, is equal to the bias voltage, V_B. From the midscale voltage,

the PWM and linear outputs are then controlled by V_Cand

diverge from each other until the required differential voltage is

developed across the TEC or the differential voltage reaches the

voltage limit. The voltage developed across the TEC depends on

the control point at that moment in time. Figure 30 shows an

example of the soft start in cooling mode. Note that, as both the

LDR and SFB voltages increase with the soft start ramp and

EXTERNAL CLOCK

EN/SY

SOURCE

AGND

Figure 28. Synchronize to an External Clock

Rev. A | Page 15 of 27

ADN8834

Data Sheet

approach V_B, the ramp slows down to avoid possible current

Using a Resistor Divider to Set the TEC Voltage Limit

overshoot at the point where the TEC voltage starts to build up.

Separate voltage limits are set using a resistor divider. The

internal current sink circuitry connected to VLIM/SD draws a

current when the ADN8834 drives the TEC in a heating direction,

which lowers the voltage at VLIM/SD. The current sink is not

active when the TEC is driven in a cooling direction; therefore,

the TEC heating voltage limit is always lower than the cooling

voltage limit.

LDR

REACH

VOLTAGE LIMIT

SFB

TEC VOLTAGE

BUILDS UP

V

B

DISCHARGE

PREBIAS

SOFT START

BEGINS

TIME

TEC VOLTAGE

Figure 30. Soft Start Profile in Cooling Mode

CLK

LIMIT AND

INTERNAL

SOFT START

TEC VOLTAGE/CURRENT MONITOR

HEATING

The TEC real-time voltage and current are detectable at VTEC

and ITEC, respectively.

V

REF

DISABLE

Voltage Monitor

R

V1

10µA

VLIMH

VTEC is an analog voltage output pin with a voltage proportional

to the actual voltage across the TEC. A center VTEC voltage of

1.25 V corresponds to 0 V across the TEC. Convert the voltage

at VTEC and the voltage across the TEC using the following

equation:

VLIM/SD

SW OPEN = V

SW CLOSED = V

VLIMC

V2

Figure 31. Using a Resistor Divider to Set the TEC Voltage Limit

V

_VTEC= 1.25 V + 0.25 × (V_LDR− V_SFB

)

Calculate the cooling and heating limits using the following

equations:

Current Monitor

ITEC is an analog voltage output pin with a voltage proportional

to the actual current through the TEC. A center ITEC voltage of

1.25 V corresponds to 0 A through the TEC. Convert the

voltage at ITEC and the current through the TEC using the

following equations:

V

_{VLIM_COOLING}= V_REF× R_V2/(R_V1+R_V2)

where V_REF= 2.5 V.

V

_{VLIM_HEATING}= V_{VLIM_COOLING}− I_{SINK_VLIM}× R_V1||R_V2

where I_{SINK_VLIM}= 10 μA.

V

_{ITEC_COOLING}= 1.25 V + I_LDR× R_CS

where the current sense gain (R_CS) is 0.525 V/A.

_{ITEC_HEATING}= 1.25 V − I_LDR× R_CS

V

_{TEC_MAX_COOLING}= V_{VLIM_COOLING}× A_VLIM

where A_VLIM= 2 V/V.

V

_{TEC_MAX_HEATING}= V_{VLIM_HEATING}× A_VLIM

MAXIMUM TEC VOLTAGE LIMIT

The maximum TEC voltage is set by applying a voltage divider

at the VLIM/SD pin to protect the TEC. The voltage limiter

operates bidirectionally and allows the cooling limit to be

different from the heating limit.

Rev. A | Page 16 of 27

Data Sheet

ADN8834

1.25 V V_{ILIM _ HEATING}

MAXIMUM TEC CURRENT LIMIT

I_{TEC _ MAX _ HEATING}



R_CS

To protect the TEC, separate maximum TEC current limits in

cooling and heating directions are set by applying a voltage

combination at the ILIM pin.

V_{ILIM_HEATING}must not exceed 1.2 V and V_{ILIM_COOLING}must be

more than 1.3 V to leave proper margins between the heating

and the cooling modes.

Using a Resistor Divider to Set the TEC Current Limit

The internal current sink circuitry connected to ILIM draws a

40 μA current when the ADN8834 drives the TEC in a cooling

direction, which allows a high cooling current. Use the following

equations to calculate the maximum TEC currents:

VDD

40µA

V

REF

COOLING

–

V

_{ILIM_HEATING}= V_REF× R_C2/(R_C1+R_C2)

R

C1

+

ITEC

where V_REF= 2.5 V.

ILIM

TEC

CURRENT

LIMIT

V

_{ILIM_COOLING}= V_{ILIM_HEATING}+ I_{SINK_ILIM}× R_C1||R_C2

C2

SW OPEN = V

SW CLOSED = V

ILIMH

where I_{SINK_ILIM}= 40 μA.

ILIMC

V

_{ILIM _COOLING}1.25 V

I_{TEC _ MAX _COOLING}



Figure 32. Using a Resistor Divider to Set the TEC Current Limit

R_CS

where R_CS= 0.525 V/A.

Rev. A | Page 17 of 27

ADN8834

Data Sheet

APPLICATIONS INFORMATION

TEC DRIVER

LINEAR POWER

STAGE

V

IN

PVIN

–

+

TEC CURRENT SENSE

LDR

+

–

TEMPERATURE ERROR

AMPLIFIER

PID COMPENSATION

AMPLIFIER

LINEAR

AMPLIFIER

PGNDL

TEC

+

A

= R /(R + R ) – R /R

FB TH FB

A = Z2/Z1

V

X

CHOPPER 1

CHOPPER 2

IN2P

–

IN1P

SFB

OUT2

OUT1

CONTROL

IN1N

IN2N

V

IN

PWM POWER

STAGE

PVIN

PWM

MODULATOR

PWM

MOSFET

DRIVER

SW

OSCILLATOR

PGNDS

V

R

REF

V

/2

TEMPSET

REF

Z

1

Z

2

R

FB

R

X

V

OUT2

OUT1

R

TH

Figure 33. Signal Flow Block Diagram

SIGNAL FLOW

THERMISTOR SETUP

The ADN8834 integrates two auto-zero amplifiers, defined as

the Chopper 1 amplifier and the Chopper 2 amplifier. Both of the

amplifiers can be used as standalone amplifiers; therefore, the

implementation of temperature control can vary. Figure 33

shows the signal flow through the ADN8834, and a typical

implementation of the temperature control loop using the

Chopper 1 amplifier and the Chopper 2 amplifier.

The thermistor has a nonlinear relationship to temperature; near

optimal linearity over a specified temperature range can be achieved

with the proper value of R_Xplaced in series with the thermistor.

First, the resistance of the thermistor must be known, where

•

R_LOW= R_THat T_LOW

R_MID= R_THat T_MID

R_HIGH= R_THat T_HIGH

In Figure 33, the Chopper 1 and Chopper 2 amplifiers are config-

ured as the thermistor input amplifier and the PID compensation

amplifier, respectively. The thermistor input amplifier gains the

thermistor voltage, then outputs to the PID compensation amplifier.

The PID compensation amplifier then compensates a loop

response over the frequency domain.

T_LOWand T_HIGHare the endpoints of the temperature range and

_MIDis the average. In some cases, with only the β constant

available, calculate R_THusing the following equation:

T





















1

T

1

T_R



R_TH= R exp β

−





R





The output from the compensation loop at OUT2 is fed to the linear

MOSFET gate driver. The voltage at LDR is fed with OUT2 into

the PWM MOSFET gate driver. Including the internal transistors,

the gain of the differential output section is fixed at 5. For details

on the output drivers, see the MOSFET Driver Amplifier section.

where:

_THis a resistance at T (K).

R_Ris a resistance at T_R(K).

R

Rev. A | Page 18 of 27

Data Sheet

ADN8834

Calculate R_Xusing the following equation:

values is to input a step function to IN2P; thus changing the target

temperature, and adjust the compensation network to minimize

the settling time of the TEC temperature.













R_LOWR_MID R_MIDR_HIGH 2R_LOWR_HIGH

R_LOW R_HIGH 2R_MID

R_X



A typical compensation network for temperature control of a laser

module is a PID loop consisting of a very low frequency pole and

two separate zeros at higher frequencies. Figure 35 shows a simple

network for implementing PID compensation. To reduce the noise

sensitivity of the control loop, an additional pole is added at a higher

frequency than that of the zeros. The bode plot of the magnitude is

shown in Figure 36. Use the following equation to calculate the

unity-gain crossover frequency of the feed-forward amplifier:

THERMISTOR AMPLIFIER (CHOPPER 1)

The Chopper 1 amplifier can be used as a thermistor input

amplifier. In Figure 33, the output voltage is a function of the

thermistor temperature. The voltage at OUT1 is expressed as:













R_FB

R_TH R_X

R_FB

R

V_REF

2



V_OUT1





 1 

where:

_THis a thermistor.

R_Xis a compensation resistor.









^FB



R_FB

_THR_X

R

1

f

_0dB





TECGAIN

R

2πR_IC_I

R



To ensure stability, the unity-gain crossover frequency must be

lower than the thermal time constant of the TEC and thermistor.

However, this thermal time constant is sometimes unspecified,

making it difficult to characterize. There are many texts written

on loop stabilization, and it is beyond the scope of this data sheet to

discuss all methods and trade-offs for optimizing compensation

networks.

Calculate R using the following equation:

R = R_X+ R_{TH_@_25°C}

V_OUT1is centered around V_REF/2 at 25°C. An average temperature-

to-voltage coefficient is −25 mV/°C at a range of 5°C to 45°C.

2.5

V

_OUT1is a convenient measure to gauge the thermal instability of

2.0

1.5

1.0

0.5

0

the system, which is also known as TEMPOUT. If the thermal loop

is in steady state, the TEMPOUT voltage equals the TEMPSET

voltage, meaning that the temperature of the controlled object

equals the target temperature.

ADN8834

CHOPPER 2

–15

5

25

45

65

TEMPERATURE (°C)

IN2P

OUT1

IN2N

OUT2

Figure 34. V_OUT1vs. Temperature

C

I

R

P

I

PID COMPENSATION AMPLIFIER (CHOPPER 2)

V

TEMPSET

C

R

D

F

D

Use the Chopper 2 amplifier as the PID compensation amplifier.

The voltage at OUT1 feeds into the PID compensation amplifier.

The frequency response of the PID compensation amplifier is

dictated by the compensation network. Apply the temperature

set voltage at IN2P. In Figure 39, the voltage at OUT2 is

calculated using the following equation:

PID COMPENSATOR

Figure 35. Implementing a PID Compensation Loop

Z2

Z1

0dB

V_OUT2 V_TEMPSET



(V_OUT1 V_TEMPSET)

where:

_TEMPSETis the control voltage input to the IN2P pin.

R

P

R

|| R

V

D

I

Z1 is the combination of R_I, R_D, and C_D(see Figure 35).

Z2 is the combination of R_P, C_I, and C_F(see Figure 35).

R

P

R

I

The user sets the exact compensation network. This network

varies from a simple integrator to proportional-integral (PI), PID

(proportional-integral-derivative), or any other type of network.

The user also determines the type of compensation and component

values because they are dependent on the thermal response of the

object and the TEC. One method to empirically determine these

1

2π × R C

2π × R

C

2π × C (R + R ) 2π × R C

I

P

I

D D I I D

FREQUENCY (Hz Log Scale)

Figure 36. Bode Plot for PID Compensation

Rev. A | Page 19 of 27

ADN8834

Data Sheet

5.0

2.5

MOSFET DRIVER AMPLIFIERS

V

= 5.0V

= 3.3V

SYS

The ADN8834 has two separate MOSFET drivers: a switched

output or pulse-width modulated (PWM) amplifier, and a high

gain linear amplifier. Each amplifier has a pair of outputs that drive

the gates of the internal MOSFETs, which, in turn, drive the TEC as

shown in Figure 33. A voltage across the TEC is monitored via

the SFB and LDR pins. Although both MOSFET drivers achieve

the same result, to provide constant voltage and high current,

their operation is different. The exact equations for the two

outputs are

0

–2.5

–5.0

V

_LDR= V_B− 40(V_OUT2− 1.25 V)

_SFB= V_LDR+ 5(V_OUT2− 1.25 V)

0

0.25

0.75

1.25

1.75

2.25

2.75

V

OUT2 (V)

where:

Figure 39. TEC Voltage vs. OUT2 Voltage

V

_OUT2is the voltage at OUT2.

PWM OUTPUT FILTER REQUIREMENTS

V_Bis determined by V_VDDas

V_B= 1.5 V for V_VDD< 4.0 V

V_B= 2.5 V for V_VDD> 4.0 V

A type three compensator internally compensates the PWM

amplifier. As the poles and zeros of the compensator are designed

and fixed by assuming the resonance frequency of the output

LC tank being 50 kHz, the selection of the inductor and the

capacitor must follow this guideline to ensure system stability.

The compensation network that receives the temperature set voltage

and the thermistor voltage fed by the input amplifier determines

the voltage at OUT2. V_LDRand V_SFBhave a low limit of 0 V and

an upper limit of V_VDD. Figure 37, Figure 38, and Figure 39 show

the graphs of these equations.

Inductor Selection

The inductor selection determines the inductor current ripple and

loop dynamic response. Larger inductance results in smaller

current ripple and slower transient response as smaller inductance

results in the opposite performance. To optimize the performance,

the trade-off must be made between transient response speed,

efficiency, and component size. Calculate the inductor value

with the following equation:

7.5

V

= 5.0V

= 3.3V

SYS

5.0

2.5

0

V_{SW _OUT}

×

(

V_IN–V_{SW _OUT}

)

L =

V_IN× f_SW× ∆I_L

where:

_{SW_OUT}is the PWM amplifier output.

_SWis the switching frequency (2 MHz by default).

V

f

–2.5

∆I_Lis the inductor current ripple.

0

0.25

0.75

1.25

1.75

2.25

2.75

OUT2 (V)

A 1 µH inductor is typically recommended to allow reasonable

output capacitor selection while maintaining a low inductor current

ripple. If lower inductance is required, a minimum inductor value

of 0.68 µH is suggested to ensure that the current ripple is set to

a value between 30% and 40% of the maximum load current,

which is 1.5 A.

Figure 37. LDR Voltage vs. OUT2 Voltage

7.5

5.0

2.5

0

V

= 5.0V

= 3.3V

SYS

Except for the inductor value, the equivalent dc resistance (DCR)

inherent in the metal conductor is also a critical factor for

inductor selection. The DCR accounts for most of the power loss

on the inductor by DCR × I_OUT². Using an inductor with high

DCR degrades the overall efficiency significantly. In addition,

there is a conduct voltage drop across the inductor because of

the DCR. When the PWM amplifier is sinking current in cooling

mode, this voltage drives the minimum voltage of the amplifier

higher than 0.06 × V_INby at least tenth of millivolts. Similarly, the

maximum PWM amplifier output voltage is lower than 0.93 × V_IN.

–2.5

0

0.25

0.75

1.25

1.75

2.25

2.75

OUT2 (V)

Figure 38. SFB Voltage vs. OUT2 Voltage

Rev. A | Page 20 of 27

Data Sheet

ADN8834

This voltage drop is proportional to the value of the DCR and it

reduces the output voltage range at the TEC.

POWER DISSIPATION

This section provides guidelines to calculate the power

dissipation of the ADN8834. Approximate the total power

dissipation in the device by

When selecting an inductor, ensure that the saturation current

rating is higher than the maximum current peak to prevent sat-

uration. In general, ceramic multilayer inductors are suitable for low

current applications due to small size and low DCR. When the

noise level is critical, use a shielded ferrite inductor to reduce the

electromagnetic interference (EMI).

P

_LOSS= P_PWM+ P_LINEAR

where:

P

_LOSSis the total power dissipation in the ADN8834.

_LINEARis the power dissipation in the linear regulator.

Table 7. Recommended Inductors

PWM Regulator Power Dissipation

Vendor Value

Device No.

Footprint

The PWM power stage is configured as a buck regulator and

its dominant power dissipation (P_PWM) includes power switch

conduction losses (P_COND), switching losses (P_SW), and transition

losses (P_TRAN). Other sources of power dissipation are usually

less significant at the high output currents of the application

thermal limit and can be neglected in approximation.

Toko

1.0 µH 20%,

2.6 A (typical)

1.0 µH 20%,

2.2 A (typical)

1.0 µH 20%,

2.3 A (typical)

DFE201612R-H-1R0M

2.0 × 1.6

Taiyo

Yuden

Murata

MAKK2016T1R0M

LQM2MPN1R0MGH

2.0 × 1.6

Use the following equation to estimate the power dissipation of

the buck regulator:

Capacitor Selection

The output capacitor selection determines the output voltage

ripple, transient response, as well as the loop dynamic response

of the PWM amplifier output. Use the following equation to

select the capacitor:

P

_LOSS= P_COND+ P_SW+ P_TRAN

Conduction Loss (P_COND

)

The conduction loss consists of two parts: inductor conduction

loss (P_{COND_L}) and power switch conduction loss (P_{COND_S}).

V_{SW _ OUT}

×

(

V_IN–V_{SW _ OUT}

)

C =

V

_IN×8× L ×( f_SW)²× ∆V_OUT

P_COND= P_{COND_L}+ P_{COND_S}

Note that the voltage caused by the product of current ripple,

ΔI_L, and the capacitor equivalent series resistance (ESR) also

add up to the total output voltage ripple. Selecting a capacitor

with low ESR can increase overall regulation and efficiency

performance.

Inductor conduction loss is proportional to the DCR of the output

inductor, L. Using an inductor with low DCR enhances the overall

efficiency performance. Estimate inductor conduction loss by

2

P

_{COND_L}= DCR × I_OUT

Power switch conduction losses are caused by the flow of the

output current through both the high-side and low-side power

switches, each of which has its own internal on resistance (R_DSON).

Table 8. Recommended Capacitors

Footprint

(mm)

Vendor Value

Device No.

Use the following equation to estimate the amount of power

switch conduction loss:

Murata 10 µF

ZRB18AD71A106KE01L

1.6 × 0.8

10%, 10 V

Murata 10 µF

20%, 10 V

10 µF

20%, 10 V

2

P

_{COND_S}= (R_{DSON_HS}× D + R_{DSON_LS}× (1 − D)) × I_OUT

where:

_{DSON_HS}is the on resistance of the high-side MOSFET.

D is the duty cycle (D = V_OUT/V_IN).

_{DSON_LS}is the on resistance of the low-side MOSFET.

GRM188D71A106MA73 1.6 × 0.8

LMK107BC6106MA-T 1.6 × 0.8

Taiyo

Yuden

R

INPUT CAPACITOR SELECTION

On the PVIN pin, the amplifiers require an input capacitor

to decouple the noise and to provide the transient current to

maintain a stable input and output voltage. A 10 µF ceramic

capacitor rated at 10 V is the minimum recommended value.

Increasing the capacitance reduces the switching ripple that

couples into the power supply but increases the capacitor size.

Because the current at the input terminal of the PWM amplifier

is discontinuous, a capacitor with low effective series inductance

(ESL) is preferred to reduce voltage spikes.

In most applications, a decoupling capacitor is used in parallel

with the input capacitor. The decoupling capacitor is usually a

100 nF ceramic capacitor with very low ESR and ESL, which

provides better noise rejection at high frequency bands.

Rev. A | Page 21 of 27

ADN8834

Data Sheet

Use the following equation to estimate the transition loss:

_TRAN= 0.5 × V_IN× I_OUT× (t_R+ t_F) × f_SW

Switching Loss (P_SW)

P

Switching losses are associated with the current drawn by the

controller to turn the power devices on and off at the switching

frequency. Each time a power device gate is turned on or off,

the controller transfers a charge from the input supply to the

gate, and then from the gate to ground. Use the following

equation to estimate the switching loss:

where:

t_Ris the rise time of the switch node.

t_Fis the fall time of the switch node.

For the ADN8834, t_Rand t_Fare both approximately 1 ns.

Linear Regulator Power Dissipation

P

_SW= (C_{GATE_HS}+ C_{GATE_LS}) × V_IN²× f_SW

The power dissipation of the linear regulator is given by the

following equation:

where:

C

_{GATE_HS}is the gate capacitance of the high-side MOSFET.

_{GATE_LS}is the gate capacitance of the low-side MOSFET.

P

_LINEAR= [(V_IN− V_OUT) × I_OUT] + (V_IN× I_GND

where:

_INand V_OUTare the input and output voltages of the linear

regulator.

)

f

_SWis the switching frequency.

V

For the ADN8834, the total of (C_{GATE_HS}+ C_{GATE_LS}) is

approximately 1 nF.

I_OUTis the load current of the linear regulator.

Transition Loss (P_TRAN

)

I_GNDis the ground current of the linear regulator.

Transition losses occur because the high-side MOSFET cannot

turn on or off instantaneously. During a switch node transition,

the MOSFET provides all the inductor current. The source-to-

drain voltage of the MOSFET is half the input voltage, resulting

in power loss. Transition losses increase with both load and input

voltage and occur twice for each switching cycle.

Power dissipation due to the ground current is generally small

and can be ignored for the purposes of this calculation.

Rev. A | Page 22 of 27

Data Sheet

ADN8834

PCB LAYOUT GUIDELINES

SOURCE OF

ELECTRICAL

POWER

TEC

VOLTAGE

LIMITING

TEC

VOLTAGE

SENSING

OBJECT

TEMPERATURE

ERROR

COMPENSATION

THERMOELECTRIC

COOLER

TARGET

TEMPERATURE

TEC

DRIVER

TEMPERATURE

SENSOR

(TEC)

TEC

CURRENT

LIMITING

TEC

CURRENT

SENSING

TEMPERATURE

SIGNAL

CONDITIONING

Figure 40. System Block Diagram

To prevent noise signal from circulating through ground plates,

reference all of the sensitive analog signals to AGND and connect

AGND to PGNDS using only a single point connection. This

ensures that the switching currents of the power stage do not

flow into the sensitive AGND node.

BLOCK DIAGRAMS AND SIGNAL FLOW

The ADN8834 integrates analog signal conditioning blocks, a

load protection block, and a TEC controller power stage all in a

single IC. To achieve the best possible circuit performance,

attention must be paid to keep noise of the power stage from

contaminating the sensitive analog conditioning and protection

circuits. In addition, the layout of the power stage must be

performed such that the IR losses are minimized to obtain the

best possible electrical efficiency.

PWM Power Stage Layout Guidelines

The PWM power stage consists of a MOSFET pair that forms a

switch mode output that switches current from PVIN to the load

via an LC filter. The ripple voltage on the PVIN pin is caused by

the discontinuous current switched by the PWM side MOSFETs.

This rapid switching causes voltage ripple to form at the PVIN

input, which must be filtered using a bypass capacitor. Place a 10 μF

capacitor as close as possible to the PVIN pin to connect PVIN to

PGNDS. Because the 10 μF capacitor is sometimes bulky and has

higher ESR and ESL, a 100 nF decoupling capacitor is usually

used in parallel with it, placed between PVIN and PGNDS.

The system block diagram of the ADN8834 is shown in Figure 40.

GUIDELINES FOR REDUCING NOISE AND

MINIMIZING POWER LOSS

Each printed circuit board (PCB) layout is unique because of

the physical constraints defined by the mechanical aspects of a

given design. In addition, several other circuits work in conjunction

with the TEC controller; these circuits have their own layout

requirements, so there are always compromises that must be

made for a given system. However, to minimize noise and keep

power losses to a minimum during the PCB layout process,

observe the following guidelines.

Because the decoupling is part of the pulsating current loop,

which carries high di/dt signals, the traces must be short and

wide to minimize the parasitic inductance. As a result, this

capacitor is usually placed on the same side of the board as the

ADN8834 to ensure short connections. If the layout requires

that a 10 μF capacitor be on the opposite side of the PCB, use

multiple vias to reduce via impedance.

General PCB Layout Guidelines

Switching noise can interfere with other signals in the system;

therefore, the switching signal traces must be placed away from

the power stage to minimize the effect. If possible, place the

ground plate between the small signal layer and power stage

layer as a shield.

The layout around the SW node is also critical because it switches

between PVIN and ground rapidly, which makes this node a

strong EMI source. Keep the copper area that connects the SW

node to the inductor small to minimize parasitic capacitance

between the SW node and other signal traces. This helps minimize

noise on the SW node due to excessive charge injection. However,

in high current applications, the copper area may be increased

reasonably to provide heat sink and to sustain high current flow.

Supply voltage drop on traces is also an important consideration

because it determines the voltage headroom of the TEC controller

at high currents. For example, if the supply voltage from the front-

end system is 3.3 V, and the voltage drop on the traces is 0.5 V,

PVIN sees only 2.8 V, which limits the maximum voltage of the

linear regulator as well as the maximum voltage across the TEC. To

mitigate the voltage waste on traces and impedance interconnec-

tion, place the ADN8834 and the input decoupling components

close to the supply voltage terminal. This placement not only

improves the system efficiency but also provides better regulation

performance at the output.

Connect the ground side of the capacitor in the LC filter as close as

possible to PGNDS to minimize the ESL in the return path.

Rev. A | Page 23 of 27

ADN8834

Data Sheet

Linear Power Stage Layout Guidelines

Place the thermistor conditioning and PID circuit components

close to each other near the inputs of Chopper 1 and Chopper 2.

Avoid crossing paths between the amplifier circuits and the

power stages to prevent noise pickup on the sensitive nodes.

Always reference the thermistor to AGND to have the cleanest

connection to the amplifier input and to avoid any noise or

offset build up.

The linear power stage consists of a MOSFET pair that forms a

linear amplifier, which operates in linear mode for very low output

currents, and changes to fully enhanced mode for greater

output currents.

Because the linear power stage does not switch currents rapidly

like the PWM power stage, it does not generate noise currents.

However, the linear power stage still requires a minimum

amount of bypass capacitance to decouple its input.

EXAMPLE PCB LAYOUT USING TWO LAYERS

Figure 41, Figure 42, and Figure 43 show an example ADN8834

PCB layout that uses two layers. This layout example achieves a

small solution size of approximately 20 mm²with all of the

conditioning circuitry and PID included. Using more layers and

blinds via allows the solution size to be reduced even further

because more of the discrete components can relocate to the

bottom side of the PCB.

Place a 100 nF capacitor that connects from PVIN to PGNDL as

close as possible to the PVIN pin.

Placing the Thermistor Amplifier and PID Components

The thermistor conditioning and PID compensation amplifiers

work with very small signals and have gain; therefore, attention

must be paid when placing the external components with these

circuits.

0

R_X

C_D

C_F

NTC

0201

C_I

AGND

0.5

1.0

1.5

0402

R_I

0201

R_P

0201

R

0201

PGND

TEMPSET

ITEC

CONNECT TO GROUND PLANE

R_A

0201

PGNDL

OUT 1

IN1N

ITEC

VTEC

SFB

IN1P

IN2N

IN2P

R_B

0201

VLIM /

SD

TEC+

LDR

R_V1

0201

TEC–

C_{IN_L}

2.0

2.5

3.0

3.5

4.0

PVIN

OUT 2

EN/SY

AGND

ILIM

R_V2

0201

VIN

R_C1

0201

SW

VDD

VTEC

C_{IN_S}

R_C2

0201

C_VDD

PGNDS

VREF

CONNECT AGND

R_BP

TO PGNDS ONLY AT A

SINGLE POINT AS A

STAR CONNECTION

C_VREF

0201

C_{SW_OUT}

0402

CONNECT TO GROUND PLANE

Figure 41. Example PCB Layout Using Two Layers (Top and Bottom Layers)

Rev. A | Page 24 of 27

Data Sheet

ADN8834

Figure 42. Example PCB Layout Using Two Layers (Top Layer Only)

Rev. A | Page 25 of 27

ADN8834

Data Sheet

0

NTC

AGND

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

PGND

TEMPSET

ITEC

CONNECT TO GROUND PLANE

TEC+

C_{IN_L}

TEC–

VIN

VTEC

C_{IN_S}

C_VDD

R_BP

CONNECT TO GROUND PLANE

Figure 43. Example PCB Layout Using Two Layers (Bottom Layer Only)

Rev. A | Page 26 of 27

Data Sheet

ADN8834

OUTLINE DIMENSIONS

2.58

2.54 SQ

2.50

BOTTOM VIEW

(BALL SIDE UP)

5

4

3

2

1

A

B

C

D

E

BALL A1

IDENTIFIER

2.00

REF

0.50

BSC

TOP VIEW

(BALL SIDE DOWN)

0.390

0.360

0.330

0.660

0.600

0.540

END VIEW

COPLANARITY

0.05

0.270

0.240

0.210

SEATING

PLANE

0.360

0.320

0.280

Figure 44. 25-Ball Wafer Level Chip Scale Package [WLCSP]

(CB-25-7)

Dimensions shown in millimeters

4.10

0.30

4.00 SQ

0.25

3.90

PIN 1

INDICATOR

0.18

PIN 1

INDICATOR

24

19

1

18

0.50

BSC

2.70

2.60 SQ

2.50

EXPOSED

PAD

13

6

12

7

0.50

0.40

0.30

0.20 MIN

TOP VIEW

BOTTOM VIEW

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

0.80

0.75

0.70

0.05 MAX

0.02 NOM

SECTION OF THIS DATA SHEET.

COPLANARITY

0.08

0.20 REF

SEATING

PLANE

COMPLIANT TO JEDEC STANDARDS MO-220-WGGD-8.

Figure 45. 24-Lead Lead-frame Chip Scale Package [LFCSP_WQ]

(CP-24-15)

Dimensions shown in millimeters

ORDERING GUIDE

Package

Option

Model¹

Temperature Range²Package Description

ADN8834ACBZ-R7

ADN8834CB-EVALZ

ADN8834ACPZ-R2

ADN8834ACPZ-R7

ADN8834CP-EVALZ

ADN8834MB-EVALZ

−40°C to +125°C

25-Ball Wafer Level Chip Scale Package [WLCSP]

25-Ball WLCSP Evaluation Board: 1.5 A TEC Current Limit, 3 V TEC Voltage Limit

24-Lead Lead Frame Chip Scale Package [LFCSP_WQ]

24-Lead LFCSP Evaluation Board: 1.5 A TEC Current Limit, 3 V TEC Voltage Limit

Mother Evaluation Board of the ADN8834 for PID tuning

CB-25-7

−40°C to +125°C

CP-24-15

¹Z = RoHS Compliant Part.

²Operating junction temperature range. The ambient operating temperature range is −40°C to +85°C.

registered trademarks are the property of their respective owners.

D12954-0-8/15(A)

Rev. A | Page 27 of 27


型号：	ADN8834ACPZ-R7
厂家：	ADI
描述：	Ultra compact 1.5 A Thermoelectric Cooler (TEC) Controller
文件：	总28页 (文件大小：1258K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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