ADN8835CP-EVALZ [ADI]
Ultracompact, 3 A Thermoelectric Cooler (TEC) Controller;
| 型号： | ADN8835CP-EVALZ |
| 厂家： | 
ADI |
| 描述： | Ultracompact, 3 A Thermoelectric Cooler (TEC) Controller |
| 文件： | 总30页 (文件大小：1513K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LT8722
Ultracompact 4A, 15V,
Full Bridge Driver with SPI
FEATURES
DESCRIPTION
n
25-Bit Digital Output Voltage Control
The LT®8722 is a high performance, high efficiency,
monolithic full bridge DC/DC converter. One side of the
full bridge is driven by a pulse width modulation (PWM)
buck power stage, while the other side of the full bridge
is driven by a linear power stage. The LT8722 can deliver
up to 54W1 of power to its load while only requiring
a single inductor. An integrated 25-bit digital-to-analog
converter (DAC) is used to control the LT8722 output
voltage. Two additional 9-bit DACs control the positive and
negative output current limits. An analog output telemetry
pin can be used to monitor SPI selectable parameters
n
Wide Input Voltage Range: 3.1V to 15V
n
4A Output Current
1
n
High Output Power: Up to 54W
High Efficiency at High Frequency
n
n
92.6% Efficiency at 4A, 15V , f = 3MHz
IN SW
n
SPI Interface Allows User to:
n
Set Output Regulation Voltage
n
Set Output Current Limits
n
Check Device Status
n
Enable/Disable Output
n
Integrated 4A Power Switches
such as V , V , I
or the LT8722 junction tempera-
IN OUT OUT
Silent Switcher® Architecture
ture. The serial peripheral interface (SPI) can be used to
configure and control the LT8722 allowing for flexibility
to set the desired output voltage, output current limits,
voltage limits, switching frequency and control ON/OFF
behavior. The SPI operates at up to 10MHz allowing for
fast readback and control. The LT8722 operates from a
single 3.1V to 15V supply. Silent Switcher techniques are
used to minimize EMI/EMC emissions while delivering
high efficiency at high switching frequencies. The LT8722
is available in a 3mm × 3mm LQFN package.
n
n
Analog Output for Diagnostics/Telemetry
n
Adjustable and Synchronizable: 500kHz to 3MHz
n
Small 3mm × 3mm 18-Lead LQFN
APPLICATIONS
n
Driving a Thermo Electric Cooler (TEC) with Fine Control
n
Transmit Optical Sub-Assembly (TOSA) Cooling
n
Erbium Doped Fiber Amplifier (EDFA) Temperature
Regulation
Photonic Integrated Circuit (PIC) Cooling
LiDAR Mirror Control
Motor Control
n
1
V
TEC
= 13.5V/ 4A with V = 15V, f = 1MHz
IN SW
n
All registered trademarks and trademarks are the property of their respective owners.
n
TYPICAL APPLICATION
Electrical Efficiency in
Cooling Configuration
13.5V/ 4A TEC Driver
95
V
IN
LDR
V
IN
3.1V TO 15V
+
4.7μF
0.1μF
150nF
80
65
50
35
20
5
V
TEC LOAD
0.1μF
OUT
V
BST
IN
4.7μF
0.1μF
–
1μH
SCK
MOSI
MISO
CS
SW
FROM SPI
MASTER
LT8722
SFB
1μF
V
DDIO
V
EN
SWEN
SYNC
A
OUT
TO ADC
DDIO
2.7V TO 6V
0.1μF
f
= 3MHz
SW
IN
V
CC
V
= 15V
1μF
R
= 2.5Ω
LOAD
GND
8722 TA01a
0
1
2
3
4
LOAD CURRENT (A)
8722 TA01b
Rev. 0
1
Document Feedback
For more information www.analog.com
LT8722
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Note 1)
TOP VIEW
V , SFB, LDR, EN, SW .............................. –0.3V to 15V
IN
SWEN, SYNC ............................................... –0.3V to 6V
V ............................................................ –0.3V to 3.8V
18
17
16
15
CC
SYNC
1
2
3
4
5
14
V
DDIO
V
A
, SCK, MOSI, CS.................................. –0.3V to 6V
DDIO
20 A
19 EN
............................................................. –0.3V to 6V
OUT
OUT
V
13 SWEN
CC
MISO............................................................ –0.3V to 6V
BST–SW....................................................... –0.3V to 6V
Operating Junction Temperature Range (Note 2)
BST
SFB
12
11
10
21
GND
22
GND
V
IN
V
IN
LT8722A ............................................ –40°C to 125°C
GND
GND
ABSMAX T .......................................... –40°C to +150°C
J
6
7
8
9
Storage Temperature Range .................. –65°C to 150°C
Maximum Reflow (Package Body) Temperature ...260°C
LQFN PACKAGE
18-LEAD (3mm × 3mm × 0.95mm)
J
= 42°C/W, /J = 14°C/W
B
A
J
= 9°C/W, θJ
= 62°C/W, Ψ = 1.25°C/W
CTOP JT
CBOTTOM
AND Ψ VALUES DETERMINED PER JESD51-12
EXPOSED PADS (PINS 19-22) MUST BE SOLDERED TO PCB
ORDER INFORMATION
PART MARKING*
PAD
FINISH
PACKAGE
TYPE
MSL
TEMPERATURE RANGE
LEAD FREE FINISH
DEVICE
FINISH CODE
RATING (SEE NOTE 2)
18 Lead (3mm × 3mm)
LT8722AV#PBF
Au (RoHS)
LHMC
e4
3
–40°C to 125°C
LQFN (Laminate Package with QFN Footprint)
Contact the factory for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix.
Rev. 0
2
For more information www.analog.com
LT8722
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C, VIN = 15V, VDDIO = 3.3V and GND = SYNC = 0V, EN = SWEN = high
unless otherwise specified. VCC has a 1μF capacitor to GND and is driven by the VCC regulator unless otherwise stated.
PARAMETER
CONDITIONS
MIN
TYP
MAX UNITS
Voltage Supplies
l
l
V
V
Supply Voltage
3.1
15
V
μA
IN
IN
Quiescent Current
EN = 0V
15
2.8
mA
V
V
Supply Voltage
Linear Power Stage ON with LDR Floating
2.7
0.1
0.1
1.1
1.7
5.5
0.35
0.45
3.2
DDIO
VDDIO
VDDIO
I
I
Supply Shutdown Current EN = 0V, V
Supply Shutdown Current EN = 0V, V
= 2.7V, MOSI/CS/SCK = 0V
= 5.5V, MOSI/CS/SCK = 0V
0.21
0.27
2
mA
mA
mA
mA
DDIO
DDIO
l
l
IV
IV
Supply Current
Supply Current
EN = 15V, Linear Power Driver ON with V = 0, V
= 2.7V
= 5.5V
DDIO
DDIO
TEC
DDIO
EN = 15V, Linear Power Driver ON with V = 0, V
2.8
4.2
TEC
DDIO
Internal Regulator (V Pin)
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
Regulator Output Voltage 1 SPIS_COMMAND[9] = 1
3.473
3.149
V
V
Regulator Output Voltage 2 SPIS_COMMAND[9] = 0
l
l
When Overdriven
If V Driven from External Supply Set SPIS_COMMAND[9] = 0
3.4
2.7
3.8
3.1
V
CC
Supply Current at 3.4V
Supply Current at 3.8V
Regulator Output Voltage 3
Current Limit
If V Driven from External Supply Set SPIS_COMMAND[9] = 0
3.1
3.3
2.9
66
mA
mA
V
CC
If V Driven from External Supply Set SPIS_COMMAND[9] = 0
CC
V
IN
V
IN
= 3.1V, External V Load = 20mA
CC
= 5V
mA
Enable Control
l
l
l
EN Pin Threshold
EN Rising
0.475
–1
0.66
52
0
0.82
1
V
mV
µA
EN Pin Hysteresis
EN Pin Leakage Current
Switching Enable Control
SWEN Pin Threshold
SWEN Pin Hysteresis
SWEN Pin Pull-Down Current
SWEN Pin Leakage Current
Undervoltage Lockout (UVLO)
EN = 15V
SWEN Rising
1.14
1.2
21
1.26
V
mV
µA
SWEN = 0.25V
406
28
l
l
l
SWEN = 5.5V, SPIS_STATUS = 0
10
1.9
55
2.65
2.7
µA
V
UVLO Rising Threshold
Hysteresis
2.36
90
V
mV
V
CC
V
DDIO
UVLO Rising Threshold
2.25
2.425
110
Hysteresis
mV
Rev. 0
3
For more information www.analog.com
LT8722
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C, VIN = 15V, VDDIO = 3.3V and GND = SYNC = 0V, EN = SWEN = high
unless otherwise specified. VCC has a 1μF capacitor to GND and is driven by the VCC regulator unless otherwise stated.
PARAMETER
CONDITIONS
MIN
TYP
MAX UNITS
Linear Output Stage
On-Resistance
Top MOSFET (M1)
V
IN
V
IN
= 15V, I
= 1.5A
= 1.5A
38
40
mΩ
mΩ
LDR
LDR
= 3.1V, I
Bot MOSFET (M2)
V
IN
V
IN
= 15V, I
= 1.5A
= 1.5A
38
40
mΩ
mΩ
LDR
LDR
= 3.1V, I
LDR Pin Leakage Current
LDR Current Sink Limit
LDR Current Source Limit
LDR Zero Voltage
V
= 15V, LDR = 0V
13.6
–4.8
5.6
µA
IN
l
l
–6.7
4
–4
A
A
V
7.5
SPIS_DAC = 0x0, SYS_DC[1:0] = 2b11, I = 0A, ENABLE_REQ = 1
7.5
TEC
Linear Power Loss Limit Regulation
Regulation Power for 2W Option M1 MOSFET, Sourcing Current
M2 MOSFET, Sinking Current
2.07
2.225
2.7
W
W
W
W
W
W
Regulation Power for 3W Option M1 MOSFET, Sourcing Current
M2 MOSFET, Sinking Current
3.0
Regulation Power for 3.5W Option M1 MOSFET, Sourcing Current
M2 MOSFET, Sinking Current
3.4
3.8
PWM Output Stage
On-Resistance
M3, I = 1.5A
M4, I = 1.5A
38
40
mΩ
mΩ
µA
µA
ns
ns
ns
A
SW Pin Leakage Current
V
SW
V
SW
= 15V
= 0V
–1
0
1
500
40
Min SW On-Time
Min SW Off-Time
Internal Clock, I = 4A
SW
Internal Clock, I = 1A
37
SW
External Clock, I = 1A
37
SW
M3 Source Current Limit
M3 Sink Current Limit
V , Max
C
7
10
12
V , Min
C
–8
–6
–4.5
–6.5
A
M4 Sink Current Limit
V , Min
C
–10.5
–8.2
A
PWM Oscillator Frequency
Internal Frequency Accuracy
l
l
f
f
f
f
f
f
= 500kHz
459
510
561
kHz
kHz
%
SW
SW
SW
SW
SW
SW
= 3000kHz
2643
2936
+14.8
+12.7
–15.4
–13.7
3420
Internal Frequency Increment
Internal Frequency Decrement
SYNC Pin Logic Threshold
SYNC Pin Leakage Current
= 500kHz, SW_FRQ_ADJ[1:0] = 2b01
= 3000kHz, SW_FRQ_ADJ[1:0] = 2b01
= 500kHz, SW_FRQ_ADJ[1:0] = 2b10
= 3000kHz, SW_FRQ_ADJ[1:0] = 2b10
%
%
%
Logic High
Logic Low
1.6
V
0.45
0.2
30
V
l
l
V
V
= 0V
–0.2
0
0
µA
µA
SYNC
SYNC
= V
10
CC
Rev. 0
4
For more information www.analog.com
LT8722
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C, VIN = 15V, VDDIO = 3.3V and GND = SYNC = 0V, EN = SWEN = high
unless otherwise specified. VCC has a 1μF capacitor to GND and is driven by the VCC regulator unless otherwise stated.
PARAMETER
CONDITIONS
MIN
TYP
MAX UNITS
PWM Duty Control
20%~80% Duty Option
l
l
Max V /V Ratio
80
20
82.5
89
%
%
SFB IN
Min V /V Ratio
17.5
13.5
8
SFB IN
15%~85% Duty Option
l
l
Max V /V Ratio
85
%
%
SFB IN
Min V /V Ratio
15.6
SFB IN
10%~90% Duty Option
l
l
Max VSFB/V Ratio
89.6
10.9
93
%
%
IN
Min VSFB/V Ratio
IN
Positive Current Limit DAC (Note 4)
Resolution
9
Bits
mA
Code
Code
A
LSB
13.3
0
Minimum Code
Maximum Code
462
2.157
4.157
Positive Current Limit Accuracy 1 SPIS_DAC_ILIMP = 0x96, I
=150 • 13.3mA
LIMP
Positive Current Limit Accuracy 2 SPIS_DAC_ILIMP = 0x12C, I
= 300 • 13.3mA
A
LIMP
Negative Current Limit DAC (Note 4)
Resolution
9
Bits
mA
Code
Code
A
LSB
13.3
48
Minimum Code
Maximum Code
511
Negative Current Limit Accuracy SPIS_DAC_ILIMN = 0x169, I
= (361–511) • 13.3mA
–2.116
–4.077
LIMN
Negative Current Limit Accuracy SPIS_DAC_ILIMN = 0xD3, I
= (211–511) • 13.3mA
A
LIMN
Output Voltage Setpoint DAC
Resolution (No Missing Codes)
VDAC INL
(Note 5)
25
Bits
µV
–900
105
900
V
OUT
V
OUT
V
OUT
V
OUT
V
OUT
Gain Adjust, Ga
V
V
= V –V
LDR SFB
0.969
V/V
OUT
Regulation Accuracy
= V –V , V = 15V, I
= 0A
LDR
OUT
LDR SFB IN
24
< 0
= 0
> 0
SPIS_DAC = 0xFFB20000, V
SPIS_DAC = 0x00000000, V
SPIS_DAC = 0x00E00000, V
= –11927552/2 • 1.25 • 16 • Ga
–13.818
0
V
V
V
OUT
OUT
OUT
24
= 0/2 • 1.25 • 16 • Ga
24
= 11927552/2 • 1.25 • 16 • Ga
13.819
Rev. 0
5
For more information www.analog.com
LT8722
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C, VIN = 15V, VDDIO = 3.3V and GND = SYNC = 0V, EN = SWEN = high
unless otherwise specified. VCC has a 1μF capacitor to GND and is driven by the VCC regulator unless otherwise stated.
PARAMETER
CONDITIONS
MIN
TYP
MAX UNITS
A
OUT
Analog Monitor
V
SPIS_DAC_ILIMP = 0x200, I
= (512–512) • 13.3mA = 0A.
1.665
1.913
2.135
1.663
1.429
1.221
1.51
V
V
V
V
V
V
V
V
V
V
ILIMP_ZERO
LIMP
V
= V
+ I
/8, SPIS_AMUX = 0x40
ILIMP
1P65
LIMP
V
V
V
V
V
A
A
A
A
SPIS_DAC_ILIMP = 0x294, I
= (660–512) • 13.3mA = 1.9684A.
ILIMP_MID
LIMP
V
= V
+ I
/8, SPIS_AMUX = 0x40
LIMP
ILIMP
1P65
SPIS_DAC_ILIMP = 0x318, I
= (792–512) • 13.3mA = 3.724A.
ILIMP_HIGH
ILIMN_ZERO
ILIMN_MID
LIMP
V
= V
+ I
/8, SPIS_AMUX = 0x40
ILIMP
1P65
LIMP
SPIS_DAC_ILIMN = 0x1FF, I
= (511–511) • 13.3mA = 0A.
LIMP
V
= V
+ I
/8, SPIS_AMUX = 0x41
ILIMP
1P65
LIMP
SPIS_DAC_ILIMN = 0x174, I
= (372–511) • 13.3mA = –1.8487A.
LIMP
V
= V
+ I
LIMP
/8, SPIS_AMUX = 0x41
ILIMP
1P65
SPIS_DAC_ILIMN = 0xF8, I
= (248–511) • 13.3mA = –3.4979A.
ILIMN_HIGH
OUT_DAC_NEG
OUT_DAC_ZERO
OUT_DAC_POS
VOUT_NEG
LIMP
V
= V
+ I
/8, SPIS_AMUX = 0x41
ILIMP
1P65
LIMP
SPIS_DAC = 0x00E00000, A
SPIS_AMUX=0x42
=1.8 • V
- 0.8 • V
,
OUT_DAC_NEG
1P25
DAC
SPIS_DAC = 0x00000000, A
SPIS_AMUX=0x42
=1.8 • V
- 0.8 • V
,
1.263
0.991
2.125
OUT_DAC_ZERO
1P25
DAC
SPIS_DAC = 0xFF100000, A
SPIS_AMUX=0x42
=1.8 • V
- 0.8 • V
,
OUT_DAC_POS
1P25
DAC
SPIS_DAC = 0xFFB20000, V
OUT
= –11927552/224 • 1.25 • 16 • Ga = –13.792V
OUT
A
= V
–V /16, SPIS_AMUX = 0x43
1P25 OUT
A
A
SPIS_DAC = 0x00000000, V
= 0V, SPIS_AMUX = 0x43
1.259
0.394
V
V
VOUT_ZERO
OUT
SPIS_DAC = 0x00E00000, V
= +11927552/224 • 1.25 • 16 • Ga = 13.792V
OUT_DAC_POS
OUT
A
= V
–V /16, SPIS_AMUX = 0x43
1P25 TEC
OUT
LDR
LDR
LDR
Output Current, V
I
I
I
= –1A. A
= V
+ I /10, SPIS_AMUX = 0x44
1.538
1.666
1.799
1.5138
1.26
V
V
V
V
V
V
V
V
V
V
V
IMON
OUT
1P65
LDR
= 0A. A
= V
+ I /10, SPIS_AMUX = 0x44
1P65 LDR
OUT
= 1A. A
= V
+ I /10, SPIS_AMUX = 0x44
1P65 LDR
OUT
A
A
A
A
A
A
= 0.6 • V , SPIS_AMUX = 0x45
2P5
OUT_2P5V
OUT_1P25V
OUT_1P65V
OUT
OUT
OUT
= V
= V
, SPIS_AMUX = 0x46
, SPIS_AMUX = 0x47
1P25
1P65
1.665
1.543
0.3933
1.36
Temp Sense Voltage at 25°C
Die Temp = (A
–1.4207)/0.0047148, SPIS_AMUX = 0x48
OUT
A
A
A
A
V
V
V
V
= 15V, A
0.9 • V –V /8, SPIS_AMUX = 0x49
OUT_VIN
IN
OUT = 2P5 IN
= 3.4V, A
= 0.4 • V , SPIS_AMUX = 0x4A
CC
OUT_VCC
OUT_VDDIO
OUT_VSFB
CC
OUT_VCC
= 3.3V, SPIS_AMUX = 0x4B, A
= 0.4 • V
DDIO
1.32
DDIO
OUT
= 15V, SPIS_AMUX = 0x4C, A
= (16/17) • V
+ V
SFB/17
2.072
SFB
OUT
1P25
Rev. 0
6
For more information www.analog.com
LT8722
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C, VIN = 15V, VDDIO = 3.3V and GND = SYNC = 0V, EN = SWEN = high
unless otherwise specified. VCC has a 1μF capacitor to GND and is driven by the VCC regulator unless otherwise stated.
PARAMETER
CONDITIONS
MIN
TYP
MAX UNITS
Serial Bus Interface and Timing Characteristics
l
l
CS, SCK, MOSI Input
0.7•V
V
DDIO
High Logic Level
CS, SCK, MOSI Input
Low Logic Level
0.3•V
V
DDIO
l
l
l
l
l
l
MISO Output Low Level
MISO Output High Level
SCK Clock Period
I
I
= 1mA, V
= 3.3V, 5V
0.4
V
V
SINK
DDIO
= 1mA, V
= 3.3V, 5V
V
–0.4
DDIO
SOURCE
DDIO
100
40
ns
ns
ns
ns
SCK Pulse High Time
SCK Pulse Low Time
40
CS Falling to SCK Rising
Delay Time
45
l
SCK Falling to CS Rising
Delay Time
45
ns
l
l
l
l
CS High Time
20
ns
ns
ns
ns
MOSI to SCK
12.5
12.5
MOSI to SCK
SCK to MISO, 80pF Load
27.5
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: LT8722A is specified over the –40°C to 125°C operating junction
temperature range. High Junction temperatures degrade operating
lifetimes. Note the maximum ambient temperature consistent with
these specifications is determined by specific operating conditions in
conjunction with board layout, the rated package thermal impedance and
other environmental factors.
Note 3: This IC includes overtemperature protection that is intended to
protect the device during overload conditions. Junction temperature will
exceed 150°C when overtemperature protection is active. Continuous
operation above the specified maximum operating junction temperature
will reduce lifetime.
Note 4: Current flow out of LDR and into SFB is regarded as
being positive.
Note 5 : Guaranteed by design, not subject to test.
Rev. 0
7
For more information www.analog.com
LT8722
TIMING DIAGRAM
t
t
DCS
CSD
CS
t
CSH
t
t
t
SCKH
SCK
SCKL
SCK
t
DS
t
DH
MOSI
t
DV
MISO
8722 F01
Figure 1. Timing Diagram for SPI
Rev. 0
8
For more information www.analog.com
LT8722
TA = 25°C, unless otherwise noted.
TYPICAL PERFORMANCE CHARACTERISTICS
Electrical Efficiency in Cooling
Configuration, VIN = 15V
Electrical Efficiency in Heating
Configuration, VIN = 15V
Electrical Efficiency in Cooling
Configuration, VIN = 5.5V
95
80
65
50
35
20
5
95
80
65
50
35
20
5
95
80
65
50
35
20
5
f
= 3MHz
f
= 3MHz
SW
IN
SW
IN
f
= 3MHz
SW
IN
V
= 15V
V
= 15V
V
= 5.5V
R
= 2.5Ω
R
=2.5Ω
LOAD
LOAD
R
=1Ω
LOAD
0
1
2
3
4
–4
–3
–2
–1
0
0
1
2
3
4
LOAD CURRENT (A)
LOAD CURRENT (A)
LOAD CURRENT (A)
8722 G01
8722 G02
8722 G03
Electrical Efficiency in Heating
Configuration, VIN = 5.5V
LDR Bottom NMOS, M2,
Power Limit
LDR Top NMOS, M1, Power Limit
5.0
4.0
3.0
2.0
1.0
0
5.0
4.0
3.0
2.0
1.0
0
95
80
65
50
35
20
5
f
= 2MHz
= 15V
f
= 2MHz
= 15V
SW
IN
SW
IN
V
V
2W POWER LIMIT
3W POWER LIMIT
3.5W POWER LIMIT
POWER LIMIT DISABLED
2W POWER LIMIT
2W POWER LIMIT
3.5W POWER LIMIT
POWER LIMIT DISABLED
f
= 3MHz
SW
IN
V
= 5.5V
R
= 1Ω
LOAD
0
0.5
1
1.5
2
2.5
–2.5
–2
–1.5
–1
–0.5
0
–4
–3
–2
–1
0
LOAD CURRENT (A)
LOAD CURRENT (A)
LOAD CURRENT (A)
8722 G05
8722 G06
8722 G04
Rev. 0
9
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LT8722
PIN FUNCTIONS
VIN (Pins 4 and 11): Input Supply Pins. The VIN pins
supply current to the LT8722 internal circuitry, the linear
power stage as well as the buck power stage. Bypass
these pins to ground with two 4.7μF capacitors and two
0.1μF capacitors as shown in Figure 15.
is not used. This option may allow a more substantial PCB
ground connection under the LT8722, thereby keeping the
LT8722 junction temperature cooler. Do not float this pin.
SWEN (Pin 13): The SWEN pin is an input/output pin.
The LT8722 switching behavior can be enabled when this
pin is high and is disabled when this pin is low. This pin
is pulled low internally by the LT8722 when the LT8722
detects a fault. This pin can also be pulled low by an
external circuit. See the Driving the SWEN Pin section for
further information.
GND (Pins 5, 10, 21 and 22): Ground Pins. Tie directly
to local ground plane.
SW (Pins 6 and 7): Switch Pins. The SW pins are the
outputs of the buck stage’s internal power switches. Tie
these pins together and connect them to the inductor and
boost capacitor. This node should be kept small on the
PCB for good performance and low EMI.
CS (Pin 15): Chip Select Input Pin. The serial data I/O bus
is enabled when CS is low and disabled when CS is high.
LDR (Pins 8 and 9): Linear Drive Pins. The LDR pins are
the outputs of the linear stage’s internal power switches.
Tie these pins together.
MISO (Pin 18): Serial Data Output Pin. Output data format-
ting is described in the Applications Information section.
MOSI (Pin 17): Serial Data Input Pin. Drive this pin with
the desired configuration as described in the Applications
Information section.
V
(Pin 2): Internal 3.4V Regulator Bypass Pin. The inter-
CC
nal power drivers and control circuits are powered from
this voltage. Do not load the VCC pin with external circuitry.
SCK (Pin 16): Serial Clock Input Pin. Drive SCK with the
serial I/O clock. SCK rising edges latch serial data in on
the MOSI. Capture output data from the MISO on rising
edges of SCK.
SYNC (Pin 1): Synchronization Pin. Clocking Modes: 1)
Drive this pin with a clock source to synchronize to an
external frequency. 2) Tie this pin to GND to use the inter-
nal oscillator.
BST (Pin 3): Boost Pin. This pin is used to provide a drive
voltage, higher than the input voltage, to the buck stage’s
topside power switch (M3). Place a 0.1µF boost capacitor
from this pin to the SW pin as close to the IC as possible.
V
(Pin 14): Serial Interface Supply Pin. The range of
DDIO
DDIO
V
is 2.7V to 5.5V. Use a minimum 0.1µF local bypass
capacitor to GND on this pin.
EN (Pin 19): The LT8722 is in shutdown when both EN pin
and ENABLE_REQ SPI bit are low. The LT8722 is active
when either the EN pin is high or the ENABLE_REQ is
SFB (Pin 12): Switcher Feedback Pin. This pin pro-
vides feedback to the buck stage for regulating the
output voltage.
high. The V regulator is on when the LT8722 is active.
CC
AOUT (Pin 20): Analog Output Pin. Internal analog signals
can be buffered out to this pin by sending commands
through the digital serial interface. See the Applications
Information section for more information.
The hysteretic threshold voltage is 0.66V going up and
0.61V going down. An external resistor divider from V
IN
can be used to program a V threshold below which the
IN
EN pin will be considered low. Tie EN to GND if the EN pin
Rev. 0
10
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LT8722
BLOCK DIAGRAM
V
IN
V
DDIO
V
DDIO
A
V
IN
OUT
V
V
V
V
V
V
V
V
V
V
V
V
V
MOSI
ILIMP
ILIMN
DAC
1P65
TEMP
IN
MISO
SCK
CS
OUT
CC
LOGIC
AND
REGISTERS
CHARGE PUMP
SPI
MASTER
IMON
2P5
DDIO
SFB
1P25
1
:
2000
+
–
V
= 1.65V
1P65
M1
V
IMON
SWEN
+
–
5k
FAULT
SWEN_INT
SPIS_DAC
SWEN_REG
L •R
G
R
V
HIGH RES
DAC
DAC
SWEN_REQ
LDR
(TEC+)
EN
V
+
–
IN
–
R
EN_INT
V
= 1.25V
R
ENABLE_REQ
1P25
+
L •R
G
R
+
ENABLE_REQ
V
TEC
LOAD
V
IN
M2
LDR
16R
1
:
2000
–
R
R
V
DAC
+
–
(TEC–)
SFB
V
IN
EA1
V
1P25
V
CC
V
3.4V
REG
CC
16R
EN_INT
V
SFB
V
9-BIT
ILIMP
SPIS_DAC_
ILIMP
+
–
SWEN_INT
VC_INT
DAC
BST
SW
EA2
EA3
M3
BUCK
SWITCH
LOGIC
V
ILIMN
9-BIT
DAC
SPIS_DAC_
ILIMN
+
–
M4
V
IMON
GND
SYNC
8722 BD
Rev. 0
11
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LT8722
OPERATION
The LT8722 is a monolithic, fixed-frequency, current-mode,
full bridge DC/DC converter. Utilizing a hybrid drive system,
where one side of the load employs a linear drive (LDR)
while the other side of the load employs a traditional PWM
switching drive (SFB). Due to this unique architecture,
only a single inductor and output capacitor are required
to achieve traditional full bridge drive capability.
V
, I
, die temp, etc. These outputs and their scal-
LOAD LOAD
ing equations are included in the Applications Information
section of this document.
ENABLE AND STARTUP SEQUENCE
The LT8722 is in shutdown mode with ultralow quiescent
current when both the EN pin is low and the ENABLE_REQ
register bit is low. The V LDO regulator can be activated
by either pulling the EN pin high or by setting the ENABLE_
REQ bit high through the SPI. The rising threshold of the
EN pin comparator is 0.74V with 30mV of hysteresis.
The LT8722 comes equipped with a serial peripheral inter-
face (SPI). Using the SPI, a 25-bit digital control word can
be applied to the LT8722 to achieve a desired voltage at
the converter output. Additional digital control informa-
tion can be sent and received through the SPI to achieve
the desired current limits, power limits as well as read
back device status information. Setting the switching fre-
quency of the LT8722 is also accomplished with sending
of SPI commands. Alternatively, an external clock can be
applied to the SYNC pin forcing the switching regulator
drive to operate at the externally applied clock frequency.
CC
To enable the linear driver, the SPIS_STATUS register
must be cleared. This is done by writing all SPIS_STATUS
registers to a value of 0. The output current monitoring
circuitry and integrated charge pump, which powers the
linear power stage’s top MOSFET, are enabled when the
ENABLE_REQ bit is high. Clearing the latched CP_UVLO
bit is required to enable the linear power driver.
If the EN pin is low and the ENABLE_REQ control bit is
low, the LT8722 is shut down and draws ~15μA from the
input. When the EN pin is above 0.74V or the ENABLE_
REQ control bit is set high, the LT8722 will become pow-
ered on waiting for additional SPI commands to operate
begin switching. When driving the SWEN pin above 1.25V
and setting the SWEN_REQ control bit high, the LT8722
will begin a switching start-up sequence further detailed
in the Applications Information section of this document.
Finally, the PWM driver is enabled by applying a logic high
voltage to the SWEN pin (through a series 20k, or greater,
resistor) and writing the SWEN_REQ register to a 1.
During LT8722 start-up, large inrush currents can occur.
Using proper SPI commands and wait times, a software
controlled soft-start function can be synthesized that
keeps inrush current to a minimum. The following state-
ments encompass the recommended start-up sequence:
Electrical efficiency for the LT8722 is given by Equation 1.
• First, apply proper VIN and VDDIO voltages to the LT8722.
Electrical Efficiency = 100% •
• Second, enable the V LDO and other LT8722 circuitry
CC
(1)
Electrical Power Delivered to LT8722 VOUT Load
LT8722 Electrical Input Power
by raising the EN pin above the 0.74V threshold and
writing the ENABLE_REQ bit to a 1.
• Third, configure the output voltage control DAC (SPIS_
DAC) to 0xFF000000. This code will force the LDR pin
to GND when the linear power stage is later enabled.
To improve efficiency across all loads, supply current to
the internal circuitry can be sourced through the V pin
CC
by reducing the V voltage output to 3.1V via SPI control
CC
and overdriving V with 3.3V to 5.5V. Otherwise, the
• Fourth, write all SPIS_STATUS registers to 0. This
clears all faults and allows the linear power stage to
be enabled. Due to the actions in the prior step, when
the linear power stage turns on in this step, the output
load will be discharged to GND. Pause between this
step and the next for ~1ms to allow any prebiased out-
put condition to dissipate.
CC
V
voltage should be programmed to 3.4V and internal
circuity will draw current directly from V .
CC
IN
The use of the analog output telemetry (AOUT) pin on the
LT8722 is optional. This output pin can be used in con-
junction with an external ADC to obtain information about
various aspects of the LT8722 operation including V ,
IN
Rev. 0
12
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LT8722
OPERATION
V
• Fifth, ramp the output voltage control DAC (SPIS_DAC)
from code 0xFF000000 to code 0x00000000 in a con-
trolled manner so that the linear driver output (LDR)
LDR
V
SFB
V
BUILDS UP
OUT
1/2 V
IN
ramps from GND to V /2. During this ramping period,
IN
V
FOLLOWS V
LDR
SFB
both the PWM driver output (SFB) and linear driver
output (LDR) move together to V /2. The ramp time
IN
8722 F03
for this controlled movement to VIN/2 should be a mini
-
Figure 3. Soft-Start Profile in Cooling Mode
mum of 5ms.
• Sixth, enable the PWM switching behavior by raising
the SWEN pin above the 1.25V threshold and writing
the SWEN_REQ bit to a 1. With both output terminals
at VIN/2, the inrush current through the output load
is greatly minimized. After the PWM driver switching
activity is enabled, keep the output voltage control DAC
(SPIS_DAC) code unchanged for a minimum of 160μs.
POWERING THE DRIVERS
The LT8722 operates at an input voltage range of 3.1V to
15V that is applied to the V pin and an input range of
IN
2.7V to 6V that is applied to the V
pin.
DDIO
The V pin is the power supply for the PWM driver and
IN
the linear power driver. When configuring the power sup-
ply to the V pin keep in mind that, at high current loads,
IN
• Finally, the output voltage control DAC (SPIS_DAC)
code can be stepped in a controlled manner to the
desired code. The LDR and SFB outputs will begin to
diverge from one another until the desired differential
voltage is developed across the output load, the differ-
ential output voltage reaches the preset voltage limit,
or the output current reaches the preset current limit.
the input voltage may drop substantially due to a voltage
drop in the wires between the front end power supply and
the V pin. Leave a proper voltage margin when design-
IN
ing the front-end power supply to maintain good perfor-
mance. Minimize the trace length from the power supply
to the V pin to help mitigate the voltage drop.
IN
Figure 2 shows the flow chart of the enable sequence and
Figure 3 shows an example of the soft-start profile where
the instruction about soft-start guidance is followed.
SETTING THE SWITCHING FREQUENCY
The LT8722 uses a constant frequency PWM architec-
ture that can be programmed to switch from 500kHz to
3MHz through the SW_FRQ_SET register bits and further
be adjusted by 15% through the SW_FRQ_ADJ regis-
ter bits. Table 1 and Table 2 show the frequency setup
summary.
V
AND V
UP
DDIO
IN
LINEAR OUTPUT
STARTS CONTROLLED
YES
EN PIN > 0.74V?
NO
BY V
DAC
Table 1. Switching Frequency Configuration
NO
NO
1?
_REQ =
ENABLE
SW_FRQ_SET BITS
SWITCHING FREQUENCY
125V
EN > 1.
AND SW
AND SW
V
CC
REGULATOR ON
ENABLE_REQ = 1?
YES
= 1?
EN_REQ
000
001
500kHz
1MHz
YES
010
1.5MHz
2MHz
BOOTSTRAP CAP
VOLTAGE REFRESH
SUCCESSFULLY CLEAR
SPIS_STATUS
011
FAULT REGISTERS
100
2.5MHz
3.0MHz
101, 110, 11
V
AND V
LDR
SFB
DIVERGE CONTROLLED
BY V
LINEAR OUTPUT
ENABLED
DAC
8722 F02
Figure 2. Flow Chart of Start-Up Sequence
Rev. 0
13
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LT8722
OPERATION
Table 2. Switching Frequency Adjustment
inrush load current is minimized. Figure 4 shows the typical
waveforms during the bootstrap cap voltage refresh period.
SW_FRQ_ADJ BITS
CHANGE FROM NOMINAL
00
01
10
11
0%
+15%
–15%
0%
TOP MOSFET
ON
80ns
BOT MOSFET
ON
160ns
INDUCTOR
CURRENT
The operating frequency of the LT8722 PWM buck
driver can also be synchronized to an external source
automatically.
5μs
32 CYCLES IN TOTAL
8722 F04
Figure 4. Bootstrap Capacitor Voltage Refresh Cycles
To synchronize to the external source, simply provide a digi-
tal clock signal into the SYNC pin and the LT8722 will oper-
ate at the SYNC clock frequency. The duty cycle of the SYNC
clock must be between 20% and 80% for proper operation.
And the SYNC frequency can always be higher than the free-
running oscillator frequency but should not be less than 30%
of the configured free-running oscillator frequency.
V
LDO REGULATOR
CC
An internal low dropout (LDO) regulator produces a 3.4V
supply to the V pin from V when the VCC_VREG reg-
CC
ister bit is 1. This LDO canINsupply enough current for
the LT8722’s circuitry and must be bypassed to ground
with a minimum 1µF ceramic capacitor. This bypassing is
necessary to supply the high transient currents required
by the PWM power MOSFET drivers.
Selection of the operating frequency is a trade-off between
efficiency, component size and PWM duty cycle range.
The advantage of high frequency operation is that lower
value and smaller size inductors and capacitors can be
used. The disadvantages are lower efficiency and nar-
rower duty cycle range as required by the min-on time
and min-off time of the PWM driver.
To improve overall efficiency, an external supply between
3.4V to 3.8V can be applied to the VCC pin. When an exter-
nal supply is used, the VCC_VREG register bit needs to be
configured to 0. With this setting, the V LDO’s regula-
CC
tion voltage will be reduced to 3.1V. The V pin can then
CC
be overdriven with an external supply between 3.4V and
BOOTSTRAP CIRCUITRY AND REFRESH PERIOD
3.8V. Because the V target output voltage is 3.1V and
CC
The LT8722 integrates the bootstrap regulator to pro-
vide gate drive voltage for the top MOSFET of the PWM
driver (M3). The regulator generates a bootstrap voltage
between the BST pin and the SW pin, which is equal to
because the V LDO can only source current, only the
CC
external supply will control the V pin in this situation.
CC
SETTING INITIAL PEAK INDUCTOR CURRENT
the V voltage.
CC
When the PWM driver is enabled, the initial peak inductor
current can cause some transient behavior to the output
voltage and current for a short period of time. The optimal
It is recommended that an X7R or an X5R, 0.1µF ceramic
capacitor is placed between the BST pin and the SW pin.
Immediately after enabling the PWM driver, the bootstrap
capacitor voltage may not be high enough to drive the
M3 gate. A total of 32 refresh cycles, with 5μs period, are
required to charge the bootstrap capacitor before the PWM
driver starts to work properly. During each refresh cycle,
the M3 MOSFET is designed to be turned on first for 80ns
(typ), and then the M4 MOSFET is turned on for 160ns
(typ). After that, both the top and bottom MOSFETs are
turned off for the rest of the refresh cycle. By doing this, the
initial peak inductor current is different for different V ,
IN
switching frequency and inductor values. The SW_VC_INT
register bits can be used to set this initial peak current.
Table 3 shows the configuration summary. When the rec-
ommended startup sequence is followed, the optimal initial
peak inductor current can be calculated with Equation 2.
V
IN
IPEAK_INIT
=
(2)
4 •L • fSW
Rev. 0
14
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LT8722
OPERATION
Configure the SW_VC_INT bits so the initial peak inductor
current is closest to the calculated optimal value.
high current, their operation is different. The two outputs
can be calculated with Equation 3 and Equation 4.
Table 3. Initial Peak Inductor Current Control
(3)
V
= 1/ 2 • V +L • V − V1P25
IN
G DAC
(
)
(
)
LDR
SW_VC_INT BITS
DESCRIPTION, IPEAK_INIT
000
001
010
011
100
101
110
111
0.251A
0.594A
0.936A
1.278A
1.62A
(4)
VSFB = V +16 • V − V1P25
(
)
LDR
DAC
Where LG is the linear amplifier gain as shown in Equation 5.
8
LG =
(5)
Duty _Cycle_Max
1.962A
2.304A
2.646A
Where Duty_Cycle_Max is listed in Table 6.
R
16R
R
R
V
V
DAC
1P25
L XR
G
V
/2
IN
+
–
+
–
LDR DRIVER INTERNAL POWER MITIGATION
V
R
V
LOAD SFB
LDR
R
V
In some conditions, the power dissipation of the LDR
driver can be quite high. The LT8722 integrates power
dissipation feedback loops to limit the maximum power
dissipation of the LDR driver’s top (M1) and bottom (M2)
power devices. This maximum power can be configured
through the PWR_LIM_BOT and PWR_LIM_TOP regis-
ters. Table 4 shows the power limit setup summary.
DAC
L XR
G
16R
V
1P25
8722 F05
Figure 5. Switched (PWM) Amplifier and Linear Amplifier
Figure 6 shows how the output voltage changes as the
V
voltage setting is adjusted.
DAC
Table 4. LDR Driver Power Limit Control for M2 MOSFET
16
APPROX. M1/M2
V
IS NOT LIMITED
OUT
PWR_LIM_BITS
0000
POWER DISSIPATION LIMIT
ON POSITIVE SIDE
BECAUSE PULSE-
SKIPPING OCCURS
12
8
2W
No Limit
3W
0101
V
= 12V
= 15V
IN
4
V
1010
IN
0
1111
3.5W
–4
–8
–12
–16
SETTING THE OUTPUT VOLTAGE
V
IS LIMITED ON NEGATIVE
OUT
SIDE DUE TO SW MIN-OFF TIME
The LT8722 has two separate amplifiers to control the
MOSFET (M1–M4) drivers: a switched output (or PWM)
amplifier and a high gain linear amplifier. Each amplifier
has a pair of outputs that drive the gates of the inter-
nal MOSFETs, which in turn drive the load as shown
in Figure 5. A voltage across the load is monitored via
the SFB and LDR pins. Although both MOSFET drivers
achieve the same result of providing constant voltage and
–15
–10
–5 10 15
SPIS_DAC CODE (MILLIONS)
0
5
8722 F06
Figure 6. Output Voltage VOUT = VLDR – VSFB
vs SPIS_DAC Code
VSFB and VLDR are individually driven as shown in Figure 7
and Figure 8 depending on the V setting and the SYS_
DC register bits. The differential V
DAC
OUT
voltage (V –V
)
LDR SFB
Rev. 0
15
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LT8722
OPERATION
vs transfer function (Figure 6) is unaffected by SYS_DC.
However, the SYS_DC register setting effects the LDR
slope and the min/max duty cycle of the PWM driver as
shown in Figure 7 and Figure 8.
SPIS_DAC[31:26] are sign-extended and are decided by
the SPIS_DAC[25] bit. Table 5 shows how to set VDAC
through the SPIS_DAC register. Note that V
is equal to
DAC
V
when SPIS_DAC is 0x00000000. The output voltage
1P25
can be calculated by Equation 6 and Equation 7.
15
3V = 0.2•15V
(6)
(7)
VOUT = VLDR − V = −16 • V − V1P25
(
)
SFB
DAC
12
9
VDAC = V1P25 − SPIS_DAC • V2P5 • 2−25
The integrated 25-bit DAC is used to set the output dif-
ferential voltage, V , as per Equation 8. V can be
6
OUT
OUT
changed by setting the SPIS_DAC register through the
SPI. SPIS_DAC is stored in 2’s complement format. The
7MSB bits, SPIS_DAC[31:26] are sign-extended and are
decided by the SPIS_DAC[25] bit. Table 5 shows how to
set VDAC through the SPIS_DAC register. Note that VOUT is
equal to zero when SPIS_DAC is 0x00000000. The output
3V = 0.2•15V
3
V
V
LDR
SFB
0
–13.0 –8.7 –4.3
0.0
4.3
8.7
13.0
SPIS_DAC CODE (MILLIONS)
8722 F07
Figure 7. VLDR and VSFB vs SPIS_DAC Code
when VIN = 15V, SYS_DC[1:0] = 2b00,
fSW = 2MHz
voltage V
be calculated by Equation 8.
OUT
VOUT = 16 •SPIS_DAC • V2P5 • 2−25
(8)
15
1.5V = 0.1•15V
–25
Where 2 is approximately 29.802nV.
12
9
Table 5. VDAC vs SPIS_DAC
SW_DAC_VTEC BITS
DESCRIPTION, V
DAC
–25
0xFF000000
V
1P25
+ 16777216 • V • 2 V = 2.5V
2P5
–25
0xFF000001
V
1P25
+ 16777215 • V • 2 V = 2.49999997V
2P5
6
• • •
• • •
–25
0xFF999998
0xFF999999
V
+ 6710888 • V • 2 V = 2.00000003V
1P25
2P5
3
–25
V
+ 6710887 • V • 2 V = 2.0V
V
1P25
2P5
LDR
SFB
1.5V = 0.1•15V
4.3 8.7
SPIS_DAC CODE (MILLIONS)
V
–25
0xFF99999A
V
1P25
+ 6710886 • V • 2 V = 1.99999997V
0
2P5
–13.0 –8.7 –4.3
0.0
13.0
• • •
• • •
8722 F08
–25
0xFFFFFFFF
0x00000000
V
V
+ 1 • V • 2 V = 1.25000003V
1P25
2P5
–25
V
1P25
+ 0 • V • 2 V = 1.25V
Figure 8. VLDR and VSFB vs SPIS_DAC Code
when VIN =15V, SYS_DC[1:0] = 2b10,
fSW = 2MHz
2P5
–25
0x00000001
– 1 • V • 2 V = 1.24999997V
1P25
2P5
• • •
• • •
–25
0x00666666
0x00666667
V
V
– 6710886 • V • 2 V = 0.75000003V
The integrated high resolution DAC is used to set LDR,
SFB and the corresponding output voltage. In a regulation
feedback loop, a software controlled PID loop measures
a desired parameter, then adjusts the output voltage by
configuring the SPIS_DAC register through SPI. SPIS_
DAC is stored in 2’s complement format. The 7MSB bits,
1P25
2P5
–25
V
– 6710887 • V • 2 V = 0.75V
1P25
2P5
–25
0x00666668
– 6710888 • V • 2 V = 0.74999997V
1P25
2P5
• • •
• • •
–25
0x00FFFFFE
0x00FFFFFF
V
V
– 16777214 • V • 2 V = 0.00000006V
1P25
2P5
–25
– 16777215 • V • 2 V = 0.00000003V
1P25
2P5
Rev. 0
16
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LT8722
OPERATION
PWM DUTY CYCLE CONFIGURATION
MAXIMUM TEC VOLTAGE LIMITS
The minimum and maximum output voltage can be
achieved at operating points A and D as shown in Figure 7.
At the operating point labeled A, the PWM driver is oper-
ating with a minimum on-time (tON,MIN) of 50ns (typ).
If the PWM driver is commanded by the output voltage
control DAC to output a voltage at the SFB pin that violates
the minimum on-time, the PWM driver may begin pulse-
skipping to achieve the desired output voltage. It’s recom-
mended to avoid these extreme operating points as the
output voltage regulation may begin to degrade. Similarly,
at the operating point labeled D, the PWM driver is oper-
The maximum positive and negative TEC voltages are set
in the SPIS_OV_CLAMP and SPIS_UV_CLAMP registers
respectively. These two registers set the maximum and
minimum SPIS_DAC register values and, in turn, set the
maximum positive and negative TEC voltages. Table 7 and
Table 8 show how the SPIS_DAC register value is limited
by SPIS_OV_CLAMP register and the SPIS_UV_CLAMP
register, respectively.
Table 7. Max SPIS_DAC vs SPIS_OV_CLAMP
SPIS_OV_CLAMP BITS
MAX SPIS_DAC VALUE
4b0000
0x000FFFFF
ating with a minimum off-time (t
) of 50ns (typ).
OFF,MIN
4b0001
0x001FFFFF
If the PWM driver is commanded by the output voltage
control DAC to output a voltage that violates the minimum
off-time, the PWM driver may begin pulse-skipping to
achieve the desired output voltage. It’s recommended to
avoid these extreme operating points as the output volt-
age regulation may begin to degrade.
• • •
• • •
4b1110
4b1111
0x00EFFFFF
0x00FFFFFF
Table 8. Min SPIS_DAC vs SPIS_UV_CLAMP
SPIS_OV_CLAMP BITS
MIN SPIS_DAC VALUE
4b0000
0xFF000000
For a given switching frequency, operating points labeled
4b0001
• • •
0xFF100000
B and C need to be considered carefully to avoid t
ON,MIN
• • •
and t
violations. As an example, using a switching
frequOeFnF,cMyINof 3MHz, the typical tON,MIN and tOFF,MIN are
both 50ns. From this information, it can be calculated
that the minimum and maximum operating duty cycle that
can be tolerated by the PWM driver are 15% and 85%,
respectively. Thus, the selected duty cycle range configu-
ration, set by the SYS_DC register, should be within this
range. According to Table 6, the SYS_DC register should
be configured as [0,0].
4b1110
4b1111
0xFFE00000
0xFFF00000
OUTPUT CURRENT LIMITS
To protect the load, the LT8722 integrates two 9-bit DACs
to limit the maximum output currents in both directions
independently. Positive current refers to current flow-
ing from LDR to SFB. The current limits can be set in
the SPIS_DAC_ILIMP and SPIS_DAC_ILIMN registers.
The current limits can be calculated with Equation 9
and Equation 10.
Table 6. Duty Cycle Configuration
SYS_DC BITS
DUTY CYCLE RANGE
20~80%
DUTY_CYCLE_MAX
00
01
0.2
0.15
0.1
15~85%
(9)
I
LIMP = 6.8A − (SPIS_DAC_ILIMP • 13.28mA)
where SPIS_DAC_ILIMP is 0 to 462.
LIMN = SPIS_DAC_ILIMN • −13.28mA
where SPIS_DAC_ILIMN is 48 to 511.
The two 9-bit DACs provide wide output current limit
10, 11
10~90%
For a given VIN voltage and a switching frequency, the
maximum achievable output voltage is decided by the
minimum and maximum duty cycles. As an example,
I
(10)
assuming V = 8V and a switching frequency of 3MHz,
IN
the output voltage range is approximately –6.8V to +6.8V
when excluding the small voltage drops across the mono-
lithic power MOSFETs.
settings. When the output voltage is limited by I or
LIMP
I
, and the PWM driver reaches the min-on or min-off
LIMN
Rev. 0
17
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LT8722
OPERATION
time limitation, the PWM driver will pulse-skip cycles to
maintain the desired output voltage. The purpose of this
pulse-skipping is to protect the load from over current.
ANALOG MONITORING
Several analog signals can be monitored through the
A
OUT
pin. The signal selection is made in the SPIS_AMUX
register and is summarized in Table 10. When AOUT_EN =
0, the A pin is tri-stated. The AMUX_TEST bits can be
RESET
OUT
used to confirm the A
signal integrity by changing the
OUT
A reset can be triggered by system fault conditions like a
A
pin voltage by a pre-defined amount for the selected
OUT
V
UVLO fault or a thermal shutdown fault. The SPI_
RDSDTIObit can be asserted to initiate a reset, via the SPI
interface, if for example an external microcontroller needs
to re-initiate the system. The reset brings all registers to
their default values except for the SPIS_STATUS register.
signal. To ensure the most accurate A
calculation from
Table 10, be sure to use the most recOeUnTtly measured val-
ues for V
and V
.
1P25
1P65
Table 10. Analog Monitoring
AMUX[3:0] FOR MONITORING
0000
0001
0010
0011
0100
0101
0110
0111
9-bit DAC Voltage, V
for Positive Output Current Limit
for Negative Output Current Limit
ILIMP
STATUS MONITORING
9-bit DAC Voltage, V
ILIMN
LT8722 status is stored in the SPIS_STATUS register
summarized in Table 9. There are six fault bits: OVER_
CURRENT, TSD, VCC_UVLO, VDDIO_UVLO, CP_UVLO
and V2P5_UVLO. To enable the PWM driver and/or the
linear driver, all fault bits must be cleared by writing each
register value to 0.
25-bit DAC Voltage, V
DAC
V
Voltage Difference, V
OUT
OUT
OUT
I
Current Information
Internal Voltage Reference, V
Internal Voltage Reference, V
Internal Voltage Reference, V
2P5
1P25
. A
1P65 OUT
is Equal to V
1P65
Table 9. SPIS_STATUS Register
when Output Current is 0 when this Channel is Selected
1000
1001
1010
1011
Chip Temperature Monitor, V
BIT NAME
SWEN
DESCRIPTION
TEMP
V
V
V
V
Voltage
Voltage
1 Indicates That the PWM is Switching
1 Indicates That the Output Current Limit is Active
IN
SRVO_ILIM
SRVO_PLIM
CC
Voltage
1 Indicates That the Linear Regulator Power
Dissipation Limiting Is Active
DDIO
1100–1101,
1110–1111
Voltage
SFB
MIN_OT
1 Indicates That the PWM Switching Is Limited
By Min-On Or Min-Off Time
POR_OCC
OVER_CURRENT
TSD
1 is a Latched Indicator That the Reset Has
Happened Since Last Cleared
The A
pin output range is 0.2V to V
–0.2V. The
OUT
DDIO
analog MUX signal range can be beyond the AOUT pin volt-
age range, so some voltage conversions are made. Output
1 is a Latched Indicator That the Linear Driver
Overcurrent Fault Has Happened Last Cleared
current is transformed to the voltage V
ally equal to V
which is ide-
IMON
1 is a Latched Indicator That the Overtemperature
Fault Has Happened Since Last Cleared
when the output current is 0. When
1P65
temperature monitoring is selected, the AOUT pin will
output a voltage proportional to the die temperature with
1.498V (typ) at 25°C and a typical slope of 4.977mV/°C.
VCC_UVLO
VDDIO_UVLO
CP_UVLO
1 is a Latched Indicator That the V Regulator
CC
UVLO Fault Has Happened Since Last Cleared
1 is a Latched Indicator That the V
Voltage
DDIO
UVLO Fault Has Happened Since Last Cleared
Table 11 shows the A
pin voltage for various analog
OUT
1 is a Latched Indicator That the Charge Pump
UVLO Fault Has Happened Since Last Cleared
mux signals. The AMUX_TEST bits can change the A
OUT
pin output voltage for the same analog mux signal (see
V2P5_UVLO
1 is a latched indicator That the 2.5V Reference
UVLO Fault Has Happened Since Last Cleared
details in Table 12).
Rev. 0
18
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LT8722
OPERATION
Table 11. AOUT Voltage vs AMUX[3:0] when AMUX_TEST = 0
DRIVING THE SWEN PIN
AMUX[3:0]
0000
VOLTAGE
The SWEN pin is an input/output pin. When SWEN and
SWEN_REQ are high, SWEN_INT is asserted, and the SW
pin begins to switch. SWEN is pulled low internally by the
LT8722 when the LT8722 detects a fault. This pin can
also be pulled low by an external circuit to disable switch-
ing and put SW into a high impedance mode. The SWEN
pin can be driven in an open-drain fashion as shown in
Figure 9. The SWEN pin can be driven in a CMOS fashion
as shown in Figure 10. Figure 11 shows the SWEN pin
coupled to 3.3V through a 20k pull-up resistor. In this case
SWEN will go high when the SPIS_STATUS[10:4] bits are
cleared and FAULT goes low.
V
ILIMP
V
ILIMN
0001
0010
V – 0.8 • V
1P25 DAC
0011
V
– (V – V )/16
LDR SFB
1P25
0100
V – I /10
1P65 OUT
0101
0.6 • V
2P5
0110
V
1P25
0111
V
V
1P65
1000
TEMP
1001
0.9 • V – V /8
2P5 IN
1010
0.4 • V
CC
1011
0.4 • V
DDIO
EXTERNAL
CIRCUITRY
1100–1111
(16/17) • V
+ V /17
1P25 SFB
LT8722
3.3V
PULL-UP
RESISTOR
Table 12. AOUT Voltage vs AMUX[3:0] when AMUX_TEST = 1
20k
SWEN
+
–
AMUX[3:0]
VOLTAGE
SWEN_INT
OPEN-DRAIN
NMOS DEVICE
FAULT 1.25V
200k
0000–0100, 1001,
1100–1111
See Table 12
SWEN_REQ
8722 F09
0101
0110
0111
1000
1010
1011
(6/13) • V
2P5
Figure 9. Open-Drain Drive of the SWEN Pin
0.8 • V
+ 0.2 • V
CC
1P25
(2/3) • V
0.855 • V
1P65
EXTERNAL
CIRCUITRY
LT8722
TEMP
(3/7) • V
(4/7) • V
CC
3.3V
SWEN
DDIO
20k
+
–
SWEN_INT
FAULT 1.25V
200k
OPTIONAL LOGIC
TO SENSE SWEN
PIN STATUS
SWEN_REQ
8722 F10
Figure 10. CMOS Drive of the SWEN Pin
EXTERNAL
CIRCUITRY
LT8722
3.3V
PULL-UP
RESISTOR
20k
SWEN
+
–
SWEN_INT
200k
FAULT 1.25V
SWEN_REQ
8722 F11
Figure 11. Simple Resistor Pull-Up on the SWEN Pin
Rev. 0
19
For more information www.analog.com
LT8722
SPI ARCHITECTURE
SERIAL PERIPHERAL INTERFACE
CS
The LT8722 utilizes an SPI slave to communicate with
an external microcontroller. Through SPI, the master can
configure the LT8722 functions and set parameters. The
master can also read back the status of the LT8722.
C[7:0]
A[7:0]
CRC[7:0]
0xXX
0xXX
0xXX
0xXX
0xXX
MOSI
MISO
00000 STATUS[10:0] D[31:24] D[23:16] D[15:18]
D[7:0]
CRC[7:0] ACK[7:0]
8722 F14
Figure 14. Data Read Packet
The LT8722 SPI is a full duplex protocol on 4-signal lines.
A clock named SCK is sent from the master to synchronize
MOSI and MISO data. A chip-select enable bar signal (active
low) named CS is sent from the master to enable LT8722
SPI communication. A unidirectional data line named MOSI
is sent from the master to the LT8722 and a unidirectional
data line named MISO is driven from the LT8722 to the
master. Bits are always sent or driven MSB first. SPI Mode
0 is supported in the LT8722. In Mode 0, the SCK is low
when the clock is inactive, and bits are always sampled at
the rising edge of SCK and driven at the falling edge of SCK.
SPI: Command
C[7:0] is an 8-bit field indicating the action that the master
wants to perform as shown in Table 13.
Table 13. Command Byte Description
NAME
SQ
C[7:0]
0x00
0x02
0x04
DESCRIPTION
Status Acquisition Command
Data Write Command
Data Read Command
DW
DR
SPI: Packet Format
SPI: ADDRESS
A packet is a fundamental data element composed of indi-
vidual bits encoding the command, address and/or data
accompanied by a CRC/ACK. Different packet types con-
tain different numbers of bits. There are 3 types of packets
for the LT8722 SPI: Status Acquisition, Data Write, and
Data Read.
A[7:0] is an 8-bit field indicating the register address
that the master wants to access. Table 14 is the register
address summary and the address field duration is 8-SCK
cycles. A[0] is always zero.
Table 14. Address Description, A[0] Is Always Zero
ADDRESS, A[7:1]
0x00
REGISTER NAME
SPIS_COMMAND
SPIS_STATUS
Each packet accomplishes one complete transaction over
the interface, whether a Status Acquisition, Data Write,
or Data Read. Packets are always initiated by pulling CS
down and always end by pulling CS up.
0x01
0x02
SPIS_DAC_ILIMN
SPIS_DAC_ILIMP
SPIS_DAC
0x03
CS
0x04
0x05
SPIS_OV_CLAMP
SPIS_UV_CLAMP
SPIS_AMUX
C[7:0]
A[7:0]
CRC[7:0]
0xXX
MOSI
0x06
00000 STATUS[10:0] CRC[7:0] ACK[7:0]
0x07
MISO
8722 F12
Figure 12. Status Acquisition Packet
SPI: DATA
CS
D[31:0] is a 4-byte field containing the data to transfer.
The data field duration is 32-SCK cycles.
C[7:0]
A[7:0]
D[31:24] D[23:16] D[15:8]
D[7:0] CRC[7:0]
0xXX
MOSI
MISO
00000 STATUS[10:0] CRC[7:0]
0xXX
0xXX
0xXX
0xXX
ACK[7:0]
8722 F13
Figure 13. Data Write Packet
Rev. 0
20
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LT8722
SPI ARCHITECTURE
SPI: CRC
SPI: Acknowledge
The LT8722 uses a cyclic redundancy check (CRC) to
detect data communication errors in each SPI MOSI and
MISO packet. The CRC in the SPI frame is an 8-bit field
containing the computed CRC value spanning the com-
mand, address and data. The CRC is also sent MSB first.
ACK[7:0] is an 8-bit field of 8-SCK cycles. Table 15 shows
the acknowledge content.
Table 15. Acknowledge Content
ACK[7:0]
0xA5
DESCRIPTION
Acknowledge
0xC3
Non-Acknowledge
The default polynomial equation used for calculating the
CRC is CRC-8-CCITT: X + X + X + 1. The default initial
seed value for calculating the CRC is 0xF F.
8
2
0x0F
Reject Due to Unsupported Register Address
0x00
Stuck at 0
Stuck at 1
Corruption
0xFF
SPI: Status
Others
LT8722 SPI packets always contain Status Flags (11 bits)
which are identical to the bits in the SPIS_STATUS register.
SPI REGISTER MAP
SUMMARY TABLE
REGISTER
DESCRIPTION
READ/WRITE
SIZE
ADDRESS
DEFAULT VALUE
MAIN
SPIS_COMMAND
SPIS_STATUS
DAC CONTROL
SPIS_DAC_ILIMN
SPIS_DAC_ILIMP
SPIS_DAC
Device Control
R/W
R/W
22
11
0x0
0x1
0x08A214
Device Operation Summary
DAC Positive Current Limit Control Register
DAC Negative Current Limit Control Register
DAC Output Voltage Control Register
R/W
R/W
R/W
9
9
0x2
0x3
0x4
0x1FF
0x000
32
0xFF000000
OV/UV CLAMP
SPIS_OV_CLAMP
SPIS_UV_CLAMP
DAC Output Positive Voltage Limit Control Register
R/W
R/W
4
4
0x5
0x6
0xF
0x0
DAC Output Negative Voltage Limit Control
Register
AMUX
SPIS_AMUX
Analog MUX Control Register
R/W
7
0x7
0x00
Rev. 0
21
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LT8722
SPI REGISTER DESCRIPTIONS
SPIS_COMMAND Register
This register is used to enable and disable the device,
set the switching frequency, control the PWM output
duty cycle, set the VCC voltage, set initial peak inductor
current, execute the software reset and set the linear
driver’s power loss regulation threshold.
BITS
SYMBOL
OPERATION
B[0]
ENABLE_REQ
V
V
LDO enable bit and linear power stage enable request bit. Default: 0x0
CC
CC
LDO is enabled when ENABLE_REQ = 1 OR the EN pin is high.
Linear power stage is enabled when ENABLE_REQ = 1 and the SPIS_STATUS fault bits are cleared.
B[1]
SWEN_REQ
PWM switch enable request bit. Default: 0x0
1b1: Request PWM switching enable. PWM switching is enabled when SWEN_REQ = 1 and the SWEN pin is high
and the V LDO is enabled.
CC
1b0: PWM switching is disabled.
B[4:2]
SW_FRQ_SET[2:0] PWM switch frequency control bits. Default: 0x5
3b000: 0.5MHz
3b001: 1MHz
3b010: 1.5MHz
3b011: 2MHz
3b100: 2.5MHz
3b101, 3b110, 3b111: 3MHz
B[6:5]
B[8:7]
SW_FRQ_ADJ[1:0] PWM switch frequency adjustment bits. Default: 0x0
2b00: 0%
2b01: +15%
2b10: –15%
2b11: 0%
SYS_DC[1:0]
PWM duty cycle control bits. Default: 0x0
2b00: 20%–80% duty cycle
2b01: 15%–85% duty cycle
2b10, 2b11: 10%–90% duty cycle
Rev. 0
22
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LT8722
SPI REGISTER DESCRIPTIONS
BITS
SYMBOL
OPERATION
V LDO regulation control bit. Default: 0x1
CC
B[9]
VCC_VREG
1b1: V LDO regulation voltage = 3.4V
CC
1b0: V LDO regulation voltage = 3.1V
CC
B[10]
Unused
Must always be set to 0x0
B[13:11]
SW_VC_INT[2:0]
Typical peak inductor current after BST–SW refresh period control bits. Default: 0x2
3b000: 0.252A
3b001: 0.594A
3b010: 0.936A
3b011: 1.278A
3b100: 1.620A
3b101: 1.962A
3b110: 2.304A
3b111: 2.646A
B[14]
SPI_RST
Software reset request bit. Default: 0x0 (Active High)
This register bit (write “1” to this register bit) is used to manually reset all registers (except SPIS_STATUS register)
to default values
B[18:15]
PWR_LIM[3:0]
Linear power stage MOSFET power limit control bits. Default: 0x5
4b0000: 2W
4b0101: No Limit
4b1010: 3W
4b1111: 3.5W
Other bit combinations not allowed.
B[31:19]
–
Ignored
SPIS_STATUS REGISTER
failure status, V UVLO failure status, V
UVLO fail-
This register is used to store PWM out switching status,
output current limit loop status, linear power loss regula-
tion status, PWM output duty status, software reset event
status, output over current failure status, overtemperature
CC
DDIO
ure status, internal charge pump UVLO failure status and
internal 2.5V voltage reference UVLO failure status.
BITS
SYMBOL
OPERATION
B[0]
SWEN
Real-time PWM switching status indicator bit. Default: 0x0
1b1: PWM switching enabled
1b0: PWM switching disabled
B[1]
B[2]
B[3]
B[4]
SRVO_ILIM
SRVO_PLIM
MIN_OT
Real-time current limit loop status indicator bit. Default: 0x0
1b1: Operating in current limit loop
1b0: Not operating in current limit loop
Real-time linear power stage bottom MOSFET and top MOSFET power limit loop status indicator bit. Default: 0x0
1b1: Operating in power limit loop
1b0: Not operating in power limit loop
Real-time PWM duty cycle status indicator bit. Default: 0x0
1b1: Operating in min or max duty cycle,
1b0: Not operating in min or max duty cycle.
POR_OCC
Latched soft reset event status indicator bit. Default: 0x0
1b1: Soft reset event by SPI_RST bit or hard reset by faults happened since last cleared
1b0: Soft reset event by SPI_RST bit has not happened since last cleared
Rev. 0
23
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LT8722
SPI REGISTER DESCRIPTIONS
BITS
SYMBOL
OPERATION
B[5]
OVER_CURRENT
Latched Output over current event status indicator bit. Default: 0x0
1b1: Output overcurrent event happened since last cleared
1b0: Output overcurrent event has not happened since last cleared
B[6]
B[7]
TSD
VCC_UVLO
VDDIO_UVLO
CP_UVLO
V2P5_UVLO
–
Latched overtemperature event status indicator bit. Default: 0x0
1b1: Overtemperature event happened since last cleared
1b0: Overtemperature event has not happened since last cleared
Latched V LDO under voltage failure event status indicator bit. Default: 0x0
CC
1b1: V LDO under voltage failure event happened since last cleared
CC
1b0: V LDO under voltage failure event has not happened since last cleared
CC
B[8]
Latched V
voltage under voltage failure event status indicator bit. Default: 0x0
DDIO
1b1: V
1b0: V
voltage under voltage failure event happened since last cleared
DDIO
DDIO
voltage under voltage failure event has not happened since last cleared
B[9]
Latched charge pump power good failure event status indicator bit. Default: 0x0
1b1: Charge pump power good status failure event happened since last cleared
1b0: Charge pump power good status failure event has not happened since last cleared
B[10]
B[31:11]
Latched V good failure event status indicator bit. Default: 0x0
2P5
1b1: V good status failure event happened since last cleared
2P5
1b0: V good status failure event has not happened since last cleared
2P5
Ignored
SPIS_DAC_ILIMN REGISTER
This register is used to set negative output current limit regulation level. LT8722 current is specified down to –4A.
BITS
SYMBOL
OPERATION
B[8:0]
SPIS_DAC_ILIMN[8:0] 9-bit DAC control register for negative output current limit. Default: 0x03FF
Format: Unsigned Integer
9b000110000 = -637.44 mA [Minimum Code]
9b000110001 = -637.44 mA – 13.28 mA
9b…..
9b111111111 = -6.786 A [Maximum Code]
B[31:9]
–
Ignored
SPIS_DAC_ILIMP Register
This register is used to set positive output current limit regulation level. LT8722 current is specified up to 4A.
BITS
SYMBOL
OPERATION
B[8:0]
SPIS_DAC_ILIMP[8:0] 9-bit DAC control register for positive output current limit. Default: 0x0000
Format: Unsigned Integer
9b000000000 = 6.8 A [Minimum Code]
9b000000001 = 6.8 A – 13.28 mA
9b…..
9b111001110 = 637.44 mA [Maximum Code]
B[31:9]
–
Ignored
Rev. 0
24
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LT8722
SPI REGISTER DESCRIPTIONS
SPIS_DAC Register
This register is used to set output voltage.
BITS
SYMBOL
OPERATION
B[31:0]
SPIS_DAC[31:0] 25-bit DAC control register for TEC voltage difference. Default: 0xFF000000
Format: 2’s Complement. SPIS_DAC[31:25] are sign-extended bits determined by SPIS_DAC[24] and SPIS_
DAC[24] is sign bit.
-25
–9
Note: 2 = 29.8023x10
–25
0xFF000000 = 1.25V + 16777216 • 2.5 • 2 V = 2.5V
–25
0xFF000001 = 1.25V + 16777215 • 2.5 • 2 V = 2.49999997V
0x……
–25
–25
–25
0xFF999998 = 1.25V + 6710888 • 2.5 • 2 V = 2.00000003V
0xFF999999 = 1.25V + 6710887 • 2.5 • 2 V = 2.0V
0xFF99999A = 1.25V + 6710886 • 2.5 • 2 V = 1.99999997
……
–25
–25
–25
0xFFFFFFFF = 1.25V + 1 • 2.5 • 2 V = 1.25000003V
0x00000000 = 1.25V + 0 • 2.5 • 2 V = 1.25V
0x00000001 = 1.25V – 1 • 2.5 • 2 V = 1.24999997V
……
–25
–25
–25
0x00666666 = 1.25V – 6710886 • 2.5 • 2 V = 0.75000003V
0x00666667 = 1.25V – 6710887 • 2.5 • 2 V = 0.75V
0x00666668 = 1.25V – 6710888 • 2.5 • 2 V = 0.74999997V
……
–25
–25
0x00FFFFFE = 1.25V – 16777214 • 2.5 • 2 V = 0.00000006V
0x00FFFFFF = 1.25V – 16777215 • 2.5 • 2 V = 0.00000003V
SPIS_OV_CLAMP REGISTER
This register is used to set maximum positive output voltage (V –V ).
LDR SFB
BITS
SYMBOL
OPERATION
B[3:0]
SPIS_OV_
CLAMP[3:0]
Positive Output voltage limit register. Default: 0xF
4b0000 = Max SPIS_DAC code value is 0x000FFFFF
4b0001 = Max SPIS_DAC code value is 0x001FFFFF
4b……
4b1110 = Max SPIS_DAC code value is 0x00EFFFFF
4b1111 = Max SPIS_DAC code value is 0x00FFFFFF
[31:5]
–
Reserved
SPIS_UV_CLAMP Register
This register is used to set maximum negative output voltage (V –V ).
LDR SFB
BITS
SYMBOL
OPERATION
B[3:0]
SPIS_UV_
CLAMP[3:0]
Negative Output voltage limit register Default: 0x0
4b0000 = Min SPIS_DAC code value is 0xFF000000
4b0001 = Min SPIS_DAC code value is 0xFF100000
4b……
4b1110 = Min SPIS_DAC code value is 0xFFE00000
4b1111 = Min SPIS_DAC code value is 0xFFF00000
B[31:4]
–
Ignored
Rev. 0
25
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LT8722
SPI REGISTER DESCRIPTIONS
SPIS_AMUX Register
This register is used to enable and disable analog monitor for internal signal monitoring.
BITS
SYMBOL
VALUE
4b0000
4b0001
4b0010
4b0011
4b0100
SIGNAL
DESCRIPTION
B[3:0]
AMUX[3:0]
V
V
V
V
V
The 9-bit internal DAC Voltage that controls the positive Output current limit
The 9-bit internal DAC Voltage that controls the negative Output current limit
ILIMP
ILIMN
1P25
– 0.8 • V
Translation of the internal 25-bit DAC voltage that controls V
OUT
DAC
– V /16
Translation of the V
Voltage. V
can be measured on channel 4b0110
can be measured on channel 4b0111
1P25
1P65
OUT
OUT
OUT
1P25
1P65
– I /10
Translation of the I
Current. V
OUT
4b0101 0.6 • V
Translation of the V Voltage when AMUX_TEST = 2b00 or 2b10
2P5
2P5
(6/13) • V2P5
4b0110 V1P25
0.8 • V
Translation of the V Voltage when AMUX_TEST = 2b01 or 2b11
2P5
Translation of the V
Translation of the V
Translation of the V
Translation of the V
Translation of the V
Translation of the V
Voltage when AMUX_TEST = 2b00 or 2b10
Voltage when AMUX_TEST = 2b01 or 2b11
Voltage when AMUX_TEST = 2b00 or 2b10
Voltage when AMUX_TEST = 2b01 or 2b11
Voltage when AMUX_TEST = 2b00 or 2b10
Voltage when AMUX_TEST = 2b01 or 2b11
1P25
1P25
1P65
1P65
TEMP
TEMP
+ 0.2 • V
1P25
CC
4b0111
V
1P65
(2/3) • V
1P65
4b1000
V
TEMP
0.855 • V
TEMP
4b1001 0.9 • V – V /8
Translation of the V Input Voltage. V Can Be Measured by Using
IN 2P5
Channel 4b0110
2P5
IN
4b1010 0.4 • V
Translation of the V LDO Voltage when AMUX_TEST = 2b00 or 2b10
CC
CC
(3/7) • V
Translation of the V LDO Voltage when AMUX_TEST = 2b01 or 2b11
CC
CC
4b1011 0.4 • V
Translation of the V
Translation of the V
input Voltage when AMUX_TEST = 2b00 or 2b10
input Voltage when AMUX_TEST = 2b01 or 2b11
DDIO
DDIO
DDIO
(4/7) • V
DDIO
4b1100
4b1101
4b1110
4b1111
Translation of the V voltage. V
Can Be Measured by Using Channel
SFB
1P25
(16/17) • V
+ V /17
SFB
1P25
4b0110
B[5:4]
AMUX_TEST[1:0] 2b00
Affects Gain of AMUX[3:0] Channels 4b0101, 0110, 0111, 1000, 1010, 1011
Affects Gain of AMUX[3:0] Channels 4b0101, 0110, 0111, 1000, 1010, 1011
2b10
2b01
2b11
B[6]
AOUT_EN
–
1b0
1b1
–
Analog Output Buffer Disabled
Analog Output Buffer Enabled
Ignored
B[31:7]
Rev. 0
26
For more information www.analog.com
LT8722
APPLICATIONS INFORMATION
INDUCTOR SELECTION
of the PWM driver output. Use Equation 12 to select
the capacitor.
The inductor selection determines the inductor current
ripple and loop dynamic responses. Larger inductance
results in smaller current ripple and slower transient
response as smaller inductance results in the opposite
performance. To optimize the performance, trade-offs
must be made between transient response speed, effi-
ciency and component size. Normally the inductor cur-
rent ripple is set to a value between 30% and 40% of the
maximum load current (Equation 11).
ΔIL
CSFB
=
(12)
(8 • fSW • ΔfSFB
)
where ΔVSFB is the desired maximum SFB pin
voltage ripple.
Note that the voltage caused by the product of inductor
current ripple, and the capacitor equivalent series resis-
tance (ESR) also adds to the total output voltage ripple.
Selecting a capacitor with low ESR can increase overall
regulation and efficiency performance.
VSFB • V − V
(
)
IN
SFB
(11)
L =
(V • f • ΔIL)
IN
SW
Place the SFB capacitor as close to the LT8722 as possible.
where ΔI is the desired inductor current ripple in Amps.
L
The equivalent DC resistance (DCR) inherent in the metal
conductor of the inductor is also a critical factor for induc-
tor selection. The DCR can account for much of the power
LDR CAPACITOR SELECTION
To further improve systematic noise at the output of the
LT8722, additional ceramic capacitors can be added at
the LDR pin. Each additional capacitor should range from
10nF – 47nF, depending on application, and have very
low ESR and ESL characteristics. Capacitor positions are
as follows 1) between LDR – GND close to the LT8722,
2) between LDR – SFB close to the load and 3) between
LDR – GND close to the load. A lower cost, lower perfor-
mance alternative would be to place a 150nF capacitor
between LDR – SFB close to the primary SFB capacitor.
loss in the inductor according to PLOSS = DCR • ISFB2
.
Using an inductor with high DCR degrades the overall
efficiency significantly. In addition, there is a conducted
voltage drop through the inductor because of the DCR.
When the PWM amplifier is sinking current in cooling
mode, this DCR voltage drop sets the minimum voltage
of the amplifier a little higher by at least tens of millivolts.
Similarly, the maximum PWM amplifier output voltage is a
little lower by at least tens of millivolts. This voltage drop
is proportional to the value of the DCR, and reduces the
output voltage range across the TEC.
HIGH TEMPERATURE CONSIDERATIONS
The LT8722 has two over temperature monitors. If the
junction temperature exceeds ~170°C, mainly due to high
VCC regulator load current, the LT8722 will enter one ther-
When selecting an inductor, ensure the saturation cur-
rent rating is higher than the maximum current peak to
prevent saturation. In general, ceramic multilayer induc-
tors are suitable for low current applications due to small
size and low DCR. When the noise level is critical, use a
shielded ferrite inductor to reduce the electromagnetic
interference (EMI).
mal shutdown mode, and the V regulator, linear driver
CC
and PWM driver are all disabled. Otherwise, an overtem-
perature event causes the SPI register values to reset to
their default values and both drivers are disabled. Either
overtemperature event is latched in the thermal shutdown
(TSD) register bit. The TSD threshold has 15°C hysteresis
so that the LT8722 does not recover from thermal shut-
down until the on-chip temperature is below 155°C. Upon
recovery, the LT8722 will enter a new start-up sequence.
SFB CAPACITOR SELECTION
The SFB capacitor determines the output voltage ripple,
transient response, as well as the loop dynamic response
Rev. 0
27
For more information www.analog.com
LT8722
APPLICATIONS INFORMATION
To ensure that the LT8722 operates below the maximum
Step-down regulators draw current from the input sup-
ply in pulses with very fast rise and fall times. The input
capacitor is required to reduce the resulting voltage rip-
ple at the LT8722 and to force this very high frequency
switching current into a tight local loop, minimizing EMI.
Capacitors with small case size such as 0402 and 0603
are optimal due to their low parasitic inductance. It is best
to use ceramic capacitors of type X7R or X5R. Y5V types
have poor performance over temperature and applied
voltage and should not be used. The input capacitors
should be placed on the same side of the circuit board,
and their connections should be made on that layer. The
SW and BOOST nodes should be as small as possible.
To keep thermal resistance low, extend the ground plane
from GND as much as possible, and add thermal vias to
additional ground planes within the circuit board and on
the bottom side.
junction temperature, even at high load, careful atten-
tion must be paid to provide a lower θ value for the
JA
device. Typical techniques for enhancing heat dissipation
include using larger copper layers and more vias on the
printed circuit board (PCB) and possibly adding a heat
sink when needed.
The LT8722 LQFN package has a large exposed pad
(EPAD) at the bottom that must be soldered to the ana-
log ground plane on the board. Most of the device’s heat
dissipates through the EPAD. Therefore, the copper layer
connected to the EPAD as well as the vias on it must
be optimized to conduct the heat effectively. It is recom-
mended to use a large via array and distribute them evenly
on the EPAD. Generally, it is more effective to increase the
number of vias than to increase the diameter of the via
within a limited area.
V
IN
LOW EMI PCB LAYOUT AND INPUT CAPACITOR
SELECTION
18
15
The LT8722 is specifically designed to minimize EMI
emissions and maximize efficiency when switching at
high frequencies. For optimal performance the LT8722
1
5
14
10
requires the use of multiple V bypass capacitors. Two
IN
small ceramic 0.1µF capacitors should be placed as close
as possible to the LT8722: One of these capacitors should
6
9
be tied to V /GND (pins 4 and 5 respectively); a sec-
IN
ond capacitor should be tied to V /GND (pins 11 and 10
IN
respectively). Two ceramic 4.7μF capacitors should also
be used as bypass capacitors—one of these capacitors
should be placed close to pins 4 and 5 and one of these
capacitors should be placed close to pins 11 and 10. See
Figure 15 for a recommended PCB layout. For more detail
and PCB design files refer to the demo board guide for
the LT8722. Note that large, switched currents flow in the
GND
GND
LDR
TEC
+
–
TEC
SFB
LT8722 V and GND pins and the input bypass capaci-
IN
tors. The loops formed by the input capacitors should be
as small as possible by placing the capacitors adjacent
to the VIN and GND pins on either side of the LT8722.
8722 F15
AREA OF THE HOT LOOPS (SHOWN IN RED) SHOULD BE MINIMIZED
BY PLACING THE CAPACITORS AS CLOSE TO V /GND PINS AS POSSIBLE.
IN
Figure 15. Recommended PCB Layout
Rev. 0
28
For more information www.analog.com
LT8722
PACKAGE DESCRIPTION
Y
X
Z
M c c c
d d d
Z
Z
× 1 8
Z
/ / b b b
Z
0 . 7 5 0 0
0 . 2 5 0 0
0 . 0 0 0 0
0 . 2 5 0 0
0 . 7 5 0 0
a a a
Z
× 2
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
29
subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
LT8722
TYPICAL APPLICATION
12V Input Voltage, 4A, –11V to 12V Output, 1.5MHz TEC Driver
V
V
LDR
IN
IN
0603
0402
+
–
12V
150nF
4.7μF
0.1μF
V
TEC LOAD
OUT
V
BST
IN
0402
4.7μF
0603
0.1μF
0.1μF
1μH
SW
SCK
LT8722
MOSI
MISO
CS
SPI CONTROL
FROM μC
V
DDIO
SFB
1μF
20k
SWEN
A
OUT
OPEN-DRAIN SWEN
CONTROL FROM μC
TO ADC
V
DDIO
V
DDIO
3.3V
0.1μF
V
EN
SYNC
CC
1μF
GND
8722 TA02
f
= 1.5MHz
SW
L: XGL4020-102MEC
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
ADN8830
Thermoelectric Cooler Controller
Thermoelectric Cooler Controller
3.0V – 5.5V Input, External MOSFETs for High Current
3.0V – 5.5V Input, External MOSFETs for High Current
ADN8831
ADN8833
Ultracompact, 1A Thermoelectric Cooler (TEC) Driver for Digital
Control Systems
2.7V – 5.5V Input, Integrated MOSFETs, 2.5mm × 2.5mm WLCSP
or 24-Lead 4mm × 4mm LFCSP
ADN8834
ADN8835
LTM4663
LTC1923
Ultracompact, 1.5A Thermoelectric Cooler (TEC) Controller
Ultracompact, 3A Thermoelectric Cooler (TEC) Controller
Ultrathin 1.5A µModule Thermoelectric Cooler (TEC) Regulator
High Efficiency Thermoelectric Cooler Controller
2.7V – 5.5V Input, Integrated MOSFETs, 2.5mm × 2.5mm WLCSP
or 24-Lead 4mm × 4mm LFCSP
2.7V – 5.5V Input, Integrated MOSFETs, 36-Lead 6mm × 6mm
LFCSP
2.7V – 5.5V Input, 3.5mm × 4mm × 1.3mm LGA Package, Very
Few External Components Required
2.7V – 5.5V Input, External MOSFETs for High Current, 5mm ×
5mm QFN or 28-Lead SSOP
Rev. 0
10/21
www.analog.com
30
ANALOG DEVICES, INC. 2021
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