ADP1032ACPZ-2-R7_技术文档

Two-Channel, Isolated Micropower Management

Unit with Seven Digital Isolators

Data Sheet

ADP1032

FEATURES

TYPICAL APPLICATION CIRCUIT

V

INP

OUT1

6V TO 28V

D1

Wide input supply voltage range: 4.5 V to 60 V

Integrated flyback power switch

Generates two isolated, well regulated independent outputs

4.5V TO 60V

R

FT1

Z

C

CLAMP

FLY BK

D

CLAMP

Tx1

FB1

V_OUT1: 24 V or 6 V to 28 V

V

_OUT2: 3.3 V, 5.0 V, or 5.15 V

SWP

FB1

SGND2

VINP

EN

R3

R2

Uses a 1:1 ratio transformer for simplified transformer design

Peak current limiting and OVP for flyback and buck regulators

Precision enable input and power-good output

Adjustable switching frequency via SYNC input

Internal compensation and soft start control per regulator

High speed, low propagation delay, SPI signal isolation

channels

Three 100 kbps general-purpose isolated data channels

41-lead, 9 mm × 7 mm LFCSP form factor enables small

overall solution size

VOUT1

SYNC

C

IN

PGND

V

OUT2

PGNDP

GNDP

3.3V, 5.0V, 5.15V

VOUT2

SW2

SLEW

C

L1

BUCK

ADP1032

ISOLATED GPIO

CHANNELS AND SPI

INTERFACE

ISOLATED GPIO

CHANNELS AND SPI

INTERFACE

V

SVDD

1.8V TO 5.5V

PWRGD

MVDD

SVDD2

−40°C to +125°C operating junction temperature range

Safety and regulatory approvals (pending)

CISPR11 Class B radiated emission

C3

V

R1

C1

MVDD

2.3V TO 5.5V

SGND2

SVDD1

C4

UL recognition: 2500 V rms for 1 minute duration per UL 1577

CSA Component Acceptance Notice 5A

MGND

SGND1

300 V rms basic insulation between slave, master, and

field power domains (IEC 61010-1, pending)

VDE certificate of conformity

Figure 1.

The two regulators are phase shifted relative to each other to

reduce electromagnetic interference (EMI). The ADP1032 can

be driven by an external oscillator in the range of 350 kHz to

750 kHz to ease noise filtering in sensitive applications.

DIN V VDE 0884-10 (VDE 0884-10):2006-12

V

_IORM= 565 V_PEAK

APPLICATIONS

The digital isolators integrated in the ADP1032 use Analog

Devices, Inc., iCoupler® chip scale transformer technology,

optimized for low power and low radiated emissions.

Industrial automation and process control

Instrumentation and data acquisition systems

Data and power isolation

The ADP1032 is available in a 9 mm × 7 mm, 41-lead LFCSP and

is rated for a −40°C to +125°C operating junction temperature

range.

GENERAL DESCRIPTION

The ADP1032 is a high performance, isolated micropower

management unit (PMU) that combines an isolated flyback and a

dc-to-dc regulator providing two isolated power rails. Additionally,

the ADP1032 contains four high speed serial peripheral interface

(SPI) isolation channels and three general-purpose isolators for

channel to channel applications where low power dissipation

and small solution size is required. Operating over an input

voltage range of 4.5 V to 60 V, the ADP1032 generates isolated

output voltages of 6 V to 28 V (adjustable version) or 24 V

(fixed version) for V_OUT1, and factory programmable voltages

Table 1. Family Models

Flyback Switch

(mA)

Buck Switch

(mA)

Inverter Switch

(mA)

Model

ADP1031 300

ADP1032 440

300

Not applicable

COMPANION PRODUCTS

Analog Output DAC: AD5758

Universal Analog input: AD4110-1

Software Defined Input/Output: AD74412R

Precision Data Acquisition Subsystem: AD7768-1

Additional companion products on the ADP1032 product page

of 5.15 V, 5.0 V, or 3.3 V for V_OUT2

.

By default, the ADP1032 flyback regulator operates at a 250 kHz

switching frequency, and the buck regulator operates at 125 kHz.

Rev. 0

Document Feedback

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registeredtrademarks arethe property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Technical Support

www.analog.com

ADP1032

Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Flyback Regulator....................................................................... 24

Buck Regulator ........................................................................... 25

Power Good ................................................................................ 25

Power-Up Sequence ................................................................... 26

Oscillator and Synchronization................................................ 26

Thermal Shutdown .................................................................... 26

Data Isolation.............................................................................. 26

Applications Information.............................................................. 29

Component Selection ................................................................ 29

Flyback Regulator Components Selection.............................. 29

Buck Regulator Components Selection................................... 32

Insulation Lifetime..................................................................... 33

Thermal Analysis ....................................................................... 34

Typical Application Circuit....................................................... 35

PCB Layout Considerations.......................................................... 36

Outline Dimensions....................................................................... 37

Ordering Guide .......................................................................... 37

Applications....................................................................................... 1

General Description......................................................................... 1

Typical Application Circuit ............................................................. 1

Companion Products....................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Regulatory Information............................................................... 7

Electromagnectic Compatibility................................................. 7

Insulation and Safety Related Specifications ............................ 7

DIN V VDE 0884-10 (VDE V 0884-10) Insulation

Characteristics .............................................................................. 8

Absolute Maximum Ratings............................................................ 9

Thermal Resistance ...................................................................... 9

ESD Caution.................................................................................. 9

Pin Configuration and Function Descriptions........................... 10

Typical Performance Characteristics ........................................... 12

Theory of Operation ...................................................................... 23

REVISION HISTORY

1/2020—Revision 0: Initial Version

Rev. 0 | Page 2 of 37

Data Sheet

ADP1032

SPECIFICATIONS

VINP voltage (V_INP) = 2 4 V, MVDD voltage (V_MVDD) = 3.3 V, SVDDx voltage (V_SVDDx) = 3.3 V, VOUT1 voltage (V_OUT1) = 24 V, VOUT2 voltage

(V_OUT2) = 3.3 V, and ambient temperature (T_A) = 25°C for typical specifications. Minimum and maximum specifications apply over the entire

operating range of 4.5 V ≤ V_INP≤ 60 V, 2 . 3 V ≤ V_MVDD≤ 5.5 V, 1.8 V ≤ V_SVDDx≤ 5.5 V, and −40°C ≤ T_J≤ +125°C, unless otherwise noted.

Table 2.

Parameter

Symbol

Min

Typ

Max

Unit

Test Conditions/Comments

INPUT SUPPLY VOLTAGE RANGE

VINP

MVDD

SVDDx

V_INP

V_MVDD

V_SVDDx

4.5

2.3

1.8

60

5.5

V

Applies to SVDD1 and SVDD2

Transformer = Coilcraft ZA9644-AE

VOUT1 current (I_OUT1) = 100 mA

VOUT2 current (I_OUT2) = 30 mA

I_OUT1= 25 mA, I_OUT2= 7 mA

OUTPUT POWER AND EFFICIENCY

Total Output Power

2.5

W

623

86.5

mW

%

Efficiency

I_OUT1= 100 mA, I_OUT2= 30 mA

84.5

390

114

%

mW

I_OUT1= 25 mA, I_OUT2= 7 mA

I_OUT1= 100 mA, I_OUT2= 30 mA

I_OUT1= 25 mA, I_OUT2= 7 mA

Power Dissipation

QUIESCENT CURRENT

VINP

Operating Current

I_{Q_VINP}

1.9

mA

µA

Normal operation, VOUT1,

VOUT2 = no load

EN voltage (V_EN) = 0 V

Shutdown Current

MVDD

I_{SHDN_VINP}

125

175

1

SPI Active Mode

I_{Q_MVDD (SPI_ACTIVE)}

4.1

9.2

1.6

6.5

14

mA

MSS

V_Ix= logic low,

= logic low

= logic high

1

V_Ix= logic high,

1

SPI Low Power Mode

I_{Q_MVDD (SPI_LOWPWR)}

2.5

MSS

V_Ix= logic low,

1

MSS

V_Ix= logic high,

= logic high

SVDD1

SPI Active Mode

1

I_{Q_SVDD1 (SPI_ACTIVE)}

I_{Q_SVDD1 (SPI_LOWPWR)}

I_{Q_SVDD2}

1.8

5.7

1.8

15.5

2

2.7

8.6

2.7

22

mA

µA

SSS

V_Ix= logic low,

= logic low

= logic high

1

V_Ix= logic high,

1

SPI Low Power Mode

SVDD2

SSS

V_Ix= logic low,

1

SSS

V_Ix= logic high,

= logic high

V_Ix¹= logic low

V_Ix¹= logic high

2.5

mA

Undervoltage Lockout (UVLO)

VINP

Relative to PGNDP

Relative to MGND

Rising Threshold

Falling Threshold

Hysteresis

V_{UVLO_VINP (RISE)}

V_{UVLO_VINP (FALL)}

4.44

4.34

100

4.49

2.28

V

mV

4.29

1.9

MVDD

Rising Threshold

Falling Threshold

Hysteresis

V_{UVLO_MVDD (RISE)}

V_{UVLO_MVDD (FALL)}

2.14

2

140

V

mV

THERMAL SHUTDOWN

Threshold

Hysteresis

T_SHDN

T_HYS

150

15

°C

PRECISION ENABLE

Rising Input Threshold

Input Hysteresis

Leakage Current

V_{EN_RISING}

V_{EN_HYST}

1.10

1.135

100

0.03

1.20

0.5

V

mV

µA

V_EN= V_INP

Rev. 0 | Page 3 of 37

ADP1032

Data Sheet

Parameter

Symbol

Min

Typ

Max

Unit

Test Conditions/Comments

POWER GOOD

Power-Good Threshold

Flyback Regulator

Lower Limit

V_{PG_FLYBACK_LL}

V_{PG_FYLBACK_UL}

87.5

107.5

90

110

92.5

112.5

%

Fixed and adjustable output versions

Upper Limit

Buck Regulator

Lower Limit

Upper Limit

Glitch Rejection

Output Voltage

Logic High

V_{PG_BUCK_LL}

V_{PG_BUCK_UL}

87.5

107.5

90

110

1.36

92.5

112.5

%

µs

Glitch of 15% of the typical output

V_{PWRGD_OH}

V_{PWRGD_OL}

V_MVDD− 0.4

V

PWRGD current (I_PWRGD) = −1 mA

I_PWRGD= 1 mA

Logic Low

0.4

0.8

SLEW

Voltage Level Threshold

Slow Slew Rate

Normal Slew Rate

Input Current

V

2

Slow Slew Rate

Normal Slew Rate

Fast Slew Rate

CLOCK SYNCHRONIZATION

SYNC Input

−10

−1

µA

Slew voltage (V_SLEW) = 0 V to 0.8 V

V_SLEW= 2 V to V_INP

SLEW pin not connected

10

+1

Input Clock

Range

f_SYNC

350

100

150

1.3

750

kHz

ns

V

Minimum On Pulse Width

Minimum Off Pulse Width

High Logic

t_{SYNC_MIN_ON}

t_{SYNC_MIN_OFF}

V_{H (SYNC)}

Low Logic

V_{L (SYNC)}

0.4

+1

V

µA

Leakage Current

FLYBACK REGULATOR

Output Voltage Range

−1

6

+0.005

SYNC voltage (V_SYNC) = V_SVDDx

V_{OUT1 (ADJ)}

28

V

ADP1032ACPZ-1, ADP1032ACPZ-2,

and ADP1032ACPZ-3

ADP1032ACPZ-4 and

ADP1032ACPZ-5

V_{OUT1 (FIXED)}

24

Output Voltage Accuracy

Feedback Voltage

Feedback Voltage Accuracy

Feedback Bias Current

Load Regulation

−1.5

1.5

%

V

%

µA

%/mA

Fixed output options

V_FB1

I_FB1

(ΔV_FB1/V_FB1)/

ΔI_OUT1

(ΔV_OUT1/V_OUT1)/

ΔV_INP

R_{ON (FLYBACK)}

0.8

+1.5

0.05

Adjustable output options

−0.0005

0.0002

3

I_OUT1= 4 mA to 100 mA, I_OUT2= 30 mA

Line Regulation

%/V

Ω

V_INP= 18 V to 32 V, I_OUT1= 80 mA,

I_OUT2= 10 mA

SWP current (I_SWP) = 100 mA

Power Field Effect Transistor

(FET) On Resistance

Current-Limit Threshold

SWP Leakage Current

SWP Capacitance

I_{LIM (FLYBACK)}

400

235

440

0.03

50

250

f_SYNC/2

425

220

8

480

0.5

mA

µA

pF

kHz

ns

ms

V

SWP voltage (V_SWP) = 60 V

C_SWP

f_{SW (FLYBACK)}

Switching Frequency

265

SYNC = low or high

SYNC = external clock

Minimum On Time

Minimum Off Time

Soft Start Timer

t_{SS (FLYBACK)}

SOVP_FLYBACK

Severe Overvoltage Threshold

29.4

30

30.6

Flyback regulator stops switching until

the overvoltage is removed

Severe Overvoltage Hysteresis

SOVP_{FLYBACK_HYST}

500

mV

Rev. 0 | Page 4 of 37

Data Sheet

ADP1032

Parameter

Symbol

Min

Typ

Max

+1.5

320

Unit

Test Conditions/Comments

BUCK REGULATOR

Output Voltage

V_OUT2

5.15

5.0

V

ADP1032ACPZ-1

ADP1032ACPZ-2 and

ADP1032ACPZ-4

ADP1032ACPZ-3 and

ADP1032ACPZ-5

I_OUT2= 10 mA, applies to all models

I_OUT2= 2 mA to 50 mA

3.3

V

Output Voltage Accuracy

Load Regulation

−1.5

%

%/mA

(ΔV_OUT2/V_OUT2)/

ΔI_OUT2

(ΔV_OUT2/V_OUT2)/

ΔV_OUT1

R_{ON_NFET (BUCK)}

R_{ON_PFET (BUCK)}

I_{LIM (BUCK)}

−0.0005

0.0004

Line Regulation

%/V

V_OUT1= 6 V to 28 V, I_OUT2= 7 mA

Power FET On Resistance

1

2.5

300

Ω

mA

SW2 current (I_SW2) = 100 mA

I_SW2= 100 mA

Current-Limit Threshold

SW2 Leakage Current

280

P Type Metal-Oxide

Semiconductor (PMOS)

N Type Metal-Oxide

0.03

0.5

µA

V_SW2= 0 V

0.5

V_SW2= 28 V

Semiconductor (NMOS)

Switching Frequency

f_{SW (BUCK)}

117.5

125

f_SYNC/4

200

8

132.5

kHz

ns

ms

kΩ

SYNC = low or high

SYNC = external clock

Minimum On Time

Soft Start Timer

Active Pull-Down Resistor

ISOLATORS, DC SPECIFICATIONS

t_{SS (BUCK)}

R_{PD (BUCK)}

1.7

1.23 V < V_OUT1< 4.5 V

MSS

, MO, SO, MGPI1,

MCK,

MGPI2, SGPI3

Input Threshold

Logic High

Logic Low

Input Current

2

V_IH

V_IL

I_I

0.7 × V_xVDD

−1

V

µA

2

0.3 × V_xVDD

+1

2

0 V ≤ V_INPUT≤ V_xVDD

SSS

, SI, MI

SCK,

Output Voltage

Logic High

4

V_OH

V_OL

V_xVDD²− 0.1

V_xVDD²− 0.4

V

I_Ox³= −20 µA, V_Ix= V_IXH

4

I_Ox³= −2 mA, V_Ix= V_IXH

5

Logic Low

0.1

0.4

I_Ox³= 20 µA, V_Ix= V_IXL

5

0.15

I_Ox³= 2 mA, V_Ix= V_IXL

SGPO1, SGPO2, MGPO3

Output Voltage

Logic High

4

V_OH

V_OL

V_xVDD²− 0.1

V_xVDD²− 0.4

V

I_Ox³= −20 µA, V_Ix= V_IXH

I_Ox³= −500 µA, V_Ix= V_IXH

4

5

Logic Low

0.1

0.4

I_Ox³= 20 µA, V_Ix= V_IXL

I_Ox³= 500 µA, V_Ix= V_IXL

5

SCK, SI, MI

Tristate Leakage

−1

+0.01

+1

µA

MSS

= logic high

V_OX⁶= V_xVDD

2

ISOLATORS, SWITCHING

SPECIFICATION

MSS

, MO, SO

MCK,

SPI Clock Rate

MSS

SPI_MCK

16.6

125

MHz

ns

100

MSS

going low to the

Latency (

)

Delay from

first data out is valid

Input Pulse Width

Input Pulse Width Distortion

t_PW

t_PWD

17

ns

Within PWD limit

|t_PLH− t_PHL|

0.25

6.5

Rev. 0 | Page 5 of 37

ADP1032

Data Sheet

Parameter

Symbol

Min

Typ

Max

Unit

Test Conditions/Comments

Channel Matching

Codirectional

Opposing Direction

Propagation Delay

t_PSKCD

t_PSKOD

t_PHL, t_PLH

0.5

5.5

4

ns

50% input to 50% output

V_MVDD= 5 V, V_SVDD1= 5 V

V_MVDD= 3.3 V, V_SVDD1= 5 V

V_MVDD= 3.3 V, V_SVDD1= 3.3 V

V_MVDD= 2.3 V, V_SVDD1= 1.8 V

V_MVDD= 5 V, V_SVDD1= 5 V

V_MVDD= 3.3 V, V_SVDD1= 5 V

V_MVDD= 3.3 V, V_SVDD1= 3.3 V

V_MVDD= 2.3 V, V_SVDD1= 1.8 V

7

11

12

15

12

ns

ps p-p

ps rms

ps p-p

ps rms

ps p-p

ps rms

ps p-p

ps rms

8.5

620

100

440

80

290

60

410

110

Jitter

MGPI1, MGPI2, SGPI3

Data Rate

Input Pulse Width

Propagation Delay

Jitter

100

kbps

μs

t_PW

t_PHL, t_PLH

10

Within PWD limit

50% input to 50% output

14

19.5

μs

ISOLATORS AC SPECIFICATIONS

General-Purpose Input/Output

(GPIO)

Output Rise Time/Fall Time

SPI

Output Rise Time/Fall Time

t_R/t_F

2.5

ns

10% to 90%

t_R/t_F

2

ns

Common-Mode Transient

Immunity⁷

|CM|

100

kV/μs

¹V_Ixis the Channel x logic input, where Channel x can be MCK, MO, SO, MGPI1, MGPI2, or SGPI3.

²V_xVDD= V_MVDDor V_SVDDx. In these places, either V_MVDDor V_SVDDxcan be used.

³I_Oxis the output current of the pin.

⁴V_IXHis the input side, logic high.

⁵V_IXLis the input side, logic low.

⁶V_OXis the voltage where the output is pulled.

⁷|CM| is the maximum common-mode voltage slew rate that can be sustained while maintaining VOUT > 0.8 MVDD and/or SVDDx. The common-mode voltage slew

rates apply to both rising and falling common-mode voltage edges.

Rev. 0 | Page 6 of 37

Data Sheet

ADP1032

REGULATORY INFORMATION

See Table 9 and the Insulation Lifetime section for the recommended maximum working voltages for specific cross isolation waveforms

and insulation levels.

Table 3. Safety Certifications

UL (Pending)

CSA (Pending)

VDE (Pending)

Recognized Under UL 1577

Component Recognition Program

Approved under CSA Component Acceptance Notice 5A

Certified according to DIN V VDE V

0884-10 (VDE V 0884-10):2006-12

2500 V rms Single Protection

CSA 60950-1-07+A1+A2 and IEC 60950-1, second edition,

Basic insulation, 565 V_PEAK

+A1+A2: basic insulation at 300 V rms (424 V_PEAK

)

CSA 61010-1-12 and IEC 61010-1 third edition: basic

insulation at 300 V rms mains, 300 V rms (424 V_PEAK) secondary

ELECTROMAGNECTIC COMPATIBILITY

Table 4.

Regulatory Body

Standard

Comment

SGS-CCSR

CISPR11 Class B

Pending

INSULATION AND SAFETY RELATED SPECIFICATIONS

Table 5.

Parameter

Symbol

Test Conditions/Comments

Value Unit

Rated Dielectric Insulation Voltage

Minimum External Air Gap (Clearance)

Field Power Domain to Master Domain

1 minute duration

2500

V rms

Measured from field power pins and pads to master

pins and pads, shortest distance through air

Measured from field power pins and pads to slave pins

and pads, shortest distance through air

Measured from master pins and pads to slave pins and

pads, shortest distance through air

2.15

mm min

Field Power Domain to Slave Domain

Master Domain to Slave Domain

Minimum External Tracking (Creepage)

Field Power Domain to Master Domain

Measured from field power pins and pads to master

pins and pads, shortest distance path along body

Measured from field power pins and pads to slave pins

and pads, shortest distance path along body

Measured from master pins and pads to slave pins and

pads, shortest distance path along body

2.15

mm min

Field Power Domain to Slave Domain

Master Domain to Slave Domain

Minimum Internal Gap (Internal Clearance)

Tracking Resistance (Comparative Tracking Index)

Material Group

Insulation distance through insulation

DIN IEC 112/VDE 0303, Part 1

Material group (DIN VDE 0110, 1/89, Table 1)

18

>400

II

µm min

V

CTI

Rev. 0 | Page 7 of 37

ADP1032

Data Sheet

DIN V VDE 0884-10 (VDE V 0884-10) INSULATION CHARACTERISTICS

Table 6.

Description

Test Conditions/Comments

Symbol Characteristic Unit

Installation Classification per DIN VDE 0110

For Rated Mains Voltage ≤ 150 V rms

For Rated Mains Voltage ≤ 300 V rms

For Rated Mains Voltage ≤ 400 V rms

Climatic Classification

Pollution Degree per DIN VDE 0110, Table 1

Maximum Working Insulation Voltage

Input to Output Test Voltage, Method B1

I to III

I to II

I to I

40/105/21

2

V_IORM

V_{PD (M)}

565

1060

V_PEAK

V_IORM× 1.875 = V_{PD (M)}, 100% production test, t_INI= t_M= 1 sec,

partial discharge < 5 pC

Input to Output Test Voltage, Method A

After Environmental Tests Subgroup 1

V_IORM× 1.5 = V_{PD (M)}, t_INI= 60 sec, t_M= 10 sec, partial

discharge < 5 pC

V_{PD (M)}

847

678

V_PEAK

After Input and/or Safety Test Subgroup 2 V_IORM× 1.2 = V_{PD (M)}, t_INI= 60 sec, t_M= 10 sec, partial

and Subgroup 3

discharge < 5 pC

Highest Allowable Overvoltage

Surge Isolation Voltage

Safety Limiting Values

V_IOTM

V_IOSM

3537

4000

V_PEAK

V_PEAK= 12.8 kV, 1.2 µs rise time, 50 µs, 50% fall time

Maximum value allowed in the event of a failure (see

Figure 2)

Maximum Junction Temperature

Total Power Dissipation at 25°C

Insulation Resistance at T_S

T_S

P_S

R_S

150

2.48

>10⁹

°C

W

Ω

V_IO= 500 V

3.0

2.5

2.0

1.5

1.0

0.5

0

50

100

150

200

AMBIENT TEMPERATURE (°C)

Figure 2. Thermal Derating Curve, Dependence of Safety Limiting Values with Ambient Temperature per DIN V VDE V 0884-10

Rev. 0 | Page 8 of 37

Data Sheet

ADP1032

ABSOLUTE MAXIMUM RATINGS

THERMAL RESISTANCE

Table 7.

Thermal performance is directly linked to printed circuit board

(PCB) design and operating environment. Close attention to

PCB thermal design is required.

Parameter

Rating

VINP to PGNDP

SWP to VINP

61 V

V_INP+ 70 V or 110 V,

whichever is lower

−0.3 V to V_INP+ 0.3 V

−0.3 V to +61 V

35 V

−0.3 V to V_OUT1+ 0.3 V

6 V

θ_JAis the natural convection, junction to ambient thermal

resistance measured in a one cubic foot sealed enclosure. θ_JCis

measured at the top of the package and is independent of the

PCB. The Ψ_JTvalue is appropriate for calculating junction to

case temperature in the application.

SLEW to GNDP

EN to GNDP

VOUT1 to SGND2

FB1 to SGND2

SW2 to SGND2

VOUT2 to SGND2

SVDD1 to SGND1

Table 8. Thermal Resistance

Package Type^{1, 2, 3, 4}

θ_JA

θ_JC

Ψ_JT

Unit

6.0 V

SVDD2 to SGND2

6.0 V

CP-41-1

50.4

33.1

25

°C/W

SSS, SCK, SI, SO to SGND1

SGPO1, SGPO2, SGPI3 to SGND2

SYNC to SGND2

−0.3 V to SVDD1 + 0.3 V

−0.3 V to SVDD2 + 0.3 V

−0.3 V to +6 V

6.0 V

¹9 mm × 7 mm LFCSP with omitted pins for isolation purposes.

²Thermal impedance simulated values are based on a JEDEC 2S2P thermal

test board with 19 thermal vias. See JEDEC JESD-51.

³Case temperature was measured at the center of the package.

⁴Board temperature was measured near Pin 1.

MVDD to MGND

MSS, MCK, MO, MI to MGND

MGPI1, MGPI2, MGPO3 to MGND

PWRGD to MGND

−0.3 V to MVDD + 0.3 V

100 kV/µs

ESD CAUTION

Common-Mode Transients

Operating Junction Temperature

Range¹

−40°C to +125°C

Storage Temperature Range

Soldering Conditions

−65°C to +150°C

JEDEC J-STD-020

¹Power dissipated on chip must be derated to keep the junction temperature

below 125°C.

Stresses at or above those listed under Absolute Maximum

Ratings may cause permanent damage to the product. This is a

stress rating only; functional operation of the product at these

or any other conditions above those indicated in the operational

section of this specification is not implied. Operation beyond

the maximum operating conditions for extended periods may

affect product reliability.

Table 9. Maximum Continuous Working Voltage¹

Parameter

Value

Constraint

60 Hz AC Voltage

DC Voltage

300 V rms

424 V_PEAK

20-year lifetime at 0.1% failure rate, zero average voltage

Limited by the creepage of the package, Pollution Degree 2, Material Group II^{2, 3}

¹See the Insulation Lifetime section for more details.

²Other pollution degrees and material group requirements yield a different limit.

³Some system level standards allow components to use the printed wiring board (PWB) creepage values. The supported dc voltage may be higher for those standards.

Rev. 0 | Page 9 of 37

ADP1032

Data Sheet

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

MI 1

MSS 2

MGND 3

30 VIN

P

M

FP

SWP

29

EPGNDM

EPGNDP

PGND

P

28

ADP1032

TOP VIEW

SGND2 4

SGND1 5

SSS 6

27 SGND2

26 DNC

25 DNC

(Not to Scale)

EPGND2

S

SO 7

DNC

24

NOTES

1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN.

2. EPGNDP IS INTERNALLY CONNECTED TO PGNDP,

EPGNDM IS INTERNALLY CONNECTED TO MGND,

AND EPGND2 IS INTERNALLY CONNECTED TO SGND.

Figure 3. Pin Configuration

Table 10. Pin Function Descriptions

Isolation

Mnemonic Domain

Pin No.

Direction

Description

1

MI

Master

Output

SPI Data Output from the Slave MI and SO Line. This pin is paired with SO. On the

slave domain, SO drives this pin.

2

MSS

Master

Input

SPI Slave Select Input from the Master Controller. This pin is paired with SSS. On the

slave domain, this pin drives SSS. This signal uses an active low logic.

3

4

5

6

MGND

SGND2

SGND1

SSS

Master

Slave

Ground

Output

Master Domain Signal Ground Connection.

Slave Domain Ground Connection. This pin can be left unconnected.

Slave Domain SPI Isolator Ground.

SPI Slave Select Output. This pin is paired with MSS. On the master domain, MSS

drives this pin.

7

SO

Slave

Input

SPI Data Input Going to the Master MI and SO Line. This pin is paired with MI. On

the master domain, this pin drives MI.

SPI Data Output from the Master MO and SI Line. This pin is paired with MO. On

the master domain, MO drives this pin.

SPI Clock Output from the Master. This pin is paired with MCK. On the master

domain, MCK drives this pin.

SPI Isolator Power Supply. Connect a 100 nF decoupling capacitor from SVDD1 to

SGND1.

8

SI

Output

Power

9

SCK

SVDD1

10

11 to 14, 24 DNC

to 26

14

Not applicable Do Not Connect. Do not connect to this pin.

SYNC

Input

SYNC Pin. To synchronize the switching frequency, connect the SYNC pin to an

external clock at twice the required switching frequency. Do not leave this pin

floating. Connect a 100 kΩ pull-down resistor to SGND2.

15

16

17

18

19

20

VOUT2

SGND2

SW2

VOUT1

FB1

Slave

Power

Ground

Buck Regulator Output Feedback.

Slave Power Ground. Ground return for buck regulator output capacitors.

Not applicable Buck Regulator Switch Node.

Power

Flyback Regulator Output and Overvoltage Sense. Input to buck regulator.

Feedback Node for the Flyback Regulator.

GPIO Isolators Power Supply. Connect a 100 nF decoupling capacitor from SVDD2

to SGND2.

SVDD2

Power

21

22

23

SGPI3

SGPO2

SGPO1

Slave

Input

Output

General-Purpose Input 3. This pin is paired with MGPO3.

General-Purpose Output 2. This pin is paired with MGPI2.

General-Purpose Output 1. This pin is paired with MGPI1.

Rev. 0 | Page 10 of 37

Data Sheet

ADP1032

Isolation

Mnemonic Domain

Pin No.

27

28

Direction

Ground

Description

SGND2

PGNDP

Slave

Field

Slave Domain Ground Connection. This pin can be left unconnected.

Ground Return for Flyback Regulator Power Supply.

power

29

30

31

32

SWP

VINP

EN

Field

power

Field

power

Field

power

Field

power

Not applicable Flyback Regulator Switching Node. Primary side transformer connection.

Power

Input

Flyback Regulator Supply Voltage. Connect a minimum of 3.3 µF capacitor from

VINP to PGNDP.

Precision Enable. Compare the EN pin to an internal precision reference to enable

the flyback regulator output.

Flyback Regulator Slew Rate Control. The SLEW pin sets the slew rate for the SWP

driver. For the fastest slew rate (best efficiency), leave the SLEW pin open. For the

normal slew rate, connect the SLEW pin to VINP. For the slowest slew rate (best

EMI performance), connect the SLEW pin to GNDP.

SLEW

33

GNDP

Field

Ground

Field Power Signal Ground Connection.

power

34

35

MGND

PWRGD

Master

Ground

Master Domain Power Ground Connection.

Power Good. This pin indicates when the secondary side supplies are within their

programmed range.

36

37

38

39

MGPI1

MGPI2

MGPO3

MVDD

Master

Input

Output

Power

General-Purpose Input 1. This pin is paired with SGPO1.

General-Purpose Input 2. This pin is paired with SGPO2.

General-Purpose Output 3. This pin is paired with SGPI3.

Master Domain Power. Connect a 100 nF decoupling capacitor from MVDD to

MGND.

40

41

MCK

Master

Input

SPI Clock Input from the Master Controller. Paired with SCK. On the slave domain,

this pin drives SCK.

SPI Data Input Going to Slave MO and SI Line. Paired with SI. On the slave domain,

this pin drives SI.

MO

Input

EPGNDP

Field

Ground

PGNDP Exposed Pad. This pad is internally connected to PGNDP.

power

EPGNDM

EPGND2

Master

Slave

Ground

MGND Exposed Pad. This pad is internally connected to MGND.

SGND Exposed Pad. This pad is internally connected to SGND.

Rev. 0 | Page 11 of 37

ADP1032

Data Sheet

TYPICAL PERFORMANCE CHARACTERISTICS

90

1.0

0.8

0.6

0.4

0.2

0

V

= 5V

INP

= 18V

= 24V

= 32V

= 60V

85

80

75

70

65

60

V

= 5V

INP

= 18V

= 24V

= 32V

= 60V

55

50

0

100

200

300

0

100

200

300

I

(mA)

I

(mA)

OUT1

Figure 4. Overall Efficiency at Various Input Voltages, T_A= 25°C,

V_OUT1= 24 V, V_OUT2= 3.3 V, I_OUT2= 30 mA, Using a Coilcraft ZA9644-AE

Transformer and a Zener Clamp Circuit

Figure 7. Power Dissipation at Various Input Voltages, T_A= 25°C,

V_OUT1= 24 V, V_OUT2= 3.3 V, I_OUT2= 30 mA, Using a Coilcraft ZA9644-AE

Transformer and a Zener Clamp Circuit

1.0

88

86

84

82

80

78

76

D-Z CLAMP

NO CLAMP

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

RCD CLAMP

74

D-Z CLAMP

72

70

NO CLAMP

RCD CLAMP

0

50

100

(mA)

150

200

0

50

100

(mA)

150

200

I

OUT1

Figure 5. Overall Efficiency at Various Input Voltages, T_A= 25°C,

V_OUT1= 24 V, V_OUT2= 3.3 V, I_OUT2= 30 mA, Using a Coilcraft ZA9644-AE

Transformer over Different Clamp Circuits

Figure 8. Power Dissipation at Various Input Voltages, T_A= 25°C,

V_OUT1= 24 V, V_OUT2= 3.3 V, I_OUT2= 30 mA, Using a Coilcraft ZA9644-AE

Transformer over Different Clamp Circuits

90

85

80

75

70

65

60

1.2

–40°C

+25°C

+105°C

1.0

0.8

0.6

0.4

0.2

0

–40°C

+25°C

+105°C

55

50

0

50

100

(mA)

150

200

0

50

100

(mA)

150

200

I

OUT1

I

OUT1

Figure 6. Overall Efficiency Across Temperature, V_INP= 24 V, V_OUT1= 24 V,

V_OUT2= 3.3 V, I_OUT2= 30 mA, Using a Coilcraft ZA9644-AE Transformer and a

Zener Clamp Circuit

Figure 9. Power Dissipation Across Temperature, V_INP= 24 V, V_OUT1= 24 V,

V_OUT2= 3.3 V, I_OUT2= 30 mA, Using a Coilcraft ZA9644-AE Transformer and a

Zener Clamp Circuit

Rev. 0 | Page 12 of 37

Data Sheet

ADP1032

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

90

88

86

84

82

80

78

76

74

72

ZA9644-AE

750317986

750318257

750318377

ZA9384-AL

ZA9644-AE

750317986

750318257

750318377

ZA9384-AL

70

0

50

100

(mA)

150

200

0

50

100

(mA)

150

200

I

OUT1

Figure 13. Power Dissipation Using Various Transformers, T_A= 25°C,

V_INP= 24 V, V_OUT1= 19.4 V, V_OUT2= 3.3 V, I_OUT2= 13 mA

Figure 10. Overall Efficiency Using Various Transformers, T_A=25°C,

V_INP= 24 V, V_OUT1= 19.4 V, V_OUT2= 3.3 V, I_OUT2= 13 mA

1.4

90

ZA9644-AE

750317986

ZA9644-AE

750317986

88

750318257

750318377

ZA9384-AL

1.2

750318377

ZA9384-AL

86

1.0

0.8

0.6

0.4

0.2

0

84

82

80

78

76

74

72

70

0

50

100

(mA)

150

200

0

50

100

(mA)

150

200

I

OUT1

Figure 14. Power Dissipation Using Various Transformers, T_A= 105°C,

V_INP= 24 V, V_OUT1= 19.4 V, V_OUT2= 3.3 V, I_OUT2= 13 mA

Figure 11. Overall Efficiency Using Various Transformers, T_A= 105°C,

V

_INP= 24 V, V_OUT1= 19.4 V, V_OUT2= 3.3 V, I_OUT2= 13 mA

1.0

90

88

86

84

82

80

78

76

74

72

70

ZA9644-AE

750317986

750318257

750318377

ZA9384-AL

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

ZA9644-AE

750317986

750318257

750318377

ZA9384-AL

0

50

100

(mA)

150

200

0

50

100

(mA)

150

200

I

OUT1

Figure 12. Overall Efficiency Using Various Transformers, T_A= 25°C,

V_INP= 24 V, V_OUT1= 24 V, V_OUT2= 3.3 V, I_OUT2= 30 mA

Figure 15. Power Dissipation Using Various Transformers, T_A= 25°C,

V_INP= 24 V, V_OUT1= 24 V, V_OUT2= 3.3 V, I_OUT2= 30 mA

Rev. 0 | Page 13 of 37

ADP1032

Data Sheet

90

88

86

84

82

80

78

76

74

72

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0

ZA9644-AE

750317986

750318257

750318377

ZA9384-AL

ZA9644-AE

750317986

750318257

750318377

ZA9384-AL

70

0

50

100

(mA)

150

200

0

50

100

(mA)

150

200

I

OUT1

Figure 19. Power Dissipation Using Various Transformers, T_A= 105°C,

V_INP= 24 V, V_OUT1= 24 V, V_OUT2= 3.3 V, I_OUT2= 30 mA

Figure 16. Overall Efficiency Using Various Transformers, T_A= 105°C,

V_INP= 24 V, V_OUT1= 24 V, V_OUT2= 3.3 V, I_OUT2= 30 mA

1.5

–40°C

+25°C

+125°C

1.0

0.5

1.0

0.5

0

–0.5

–1.0

–1.5

–0.5

–1.0

–1.5

0

50

100

150

0

50

100

150

I

(mA)

I

(mA)

OUT1

Figure 17. Flyback Regulator Load Regulation Across Temperature,

Figure 20. Flyback Regulator Load Regulation Across Temperature,

V_INP= 24 V, V_OUT1= 24 V (Adjustable Output Version),

Nominal = V_OUT1at 20 mA Load

V

_INP= 24 V, V_OUT1= 24 V (Fixed Output Version),

Nominal = V_OUT1at 20 mA Load

1.5

1.0

1.5

V

= 5V

–40°C

+25°C

+125°C

INP

V

= 18V

= 24V

= 32V

= 60V

INP

1.0

0.5

0

–0.5

–1.0

–1.5

–0.5

–1.0

–1.5

0

50

100

150

0

10

20

30

40

50

I

(mA)

OUT1

V

(V)

INP

Figure 18. Flyback Regulator Load Regulation at Various Input Voltages,

T_A= 25°C, V_OUT1= 24 V, Nominal = V_OUT1at 20 mA Load

Figure 21. Flyback Regulator Line Regulation Across Temperature,

_OUT1= 24 V, I_OUT1= 20 mA, Nominal = V_OUT1with V_INP= 24 V

V

Rev. 0 | Page 14 of 37

Data Sheet

ADP1032

250

180

160

140

120

100

80

–40°C

+25°C

+105°C

200

150

100

50

60

40

V

= 6V

OUT1

= 15V

= 24V

= 28V

20

0

10

20

30

40

50

60

0

10

20

30

40

50

60

V

(V)

INP

V

(V)

INP

Figure 22. Flyback Regulator Maximum Output Current at Various Output

Voltages, T_A= 25°C, Using a Coilcraft ZA9644-AE Transformer and a Zener

Clamp Circuit, Based on Target of 70% I_{LIM (FLYBACK)}

Figure 25. Flyback Regulator Maximum Output Current Across Temperature,

V_OUT1= 24 V, Using a Coilcraft ZA9644-AE Transformer and a Zener Clamp

Circuit, Based on Target of 70% I_{LIM (FLYBACK)}

180

ZA9644-AE

750317986

ZA9644-AE

750317986

160

750318257

750318377

ZA9384-AL

140

120

100

80

ZA9384-AL

140

120

100

80

60

40

20

0

10

20

30

40

50

60

0

10

20

30

40

50

60

V

(V)

INP

V

(V)

INP

Figure 23. Flyback Regulator Maximum Output Current Over Various

Transformers, T_A= 25°C, V_OUT1= 24 V, Over Various Input Voltages and a

Zener Clamp Circuit, Based on Target of 70% I_{LIM (FLYBACK)}

Figure 26. Flyback Regulator Maximum Output Current Over Various

Transformers, T_A= 105°C, V_OUT1= 24 V, Over Various Input Voltages and a

Zener Clamp Circuit, Based on Target of 70% I_{LIM (FLYBACK)}

EN

1

V

OUT1

EN

1

V

OUT2

2

V

OUT1

OUT2

2

3

4

PWRGD

3

4

PWRGD

B

M4.00ms

12.1000ms

CH1 5.00V

CH3 2.00V

CH2 10.0V

CH4 5.00V

A CH1

2.40V

W

CH1 5.00V ^BCH2 10.0V

M4.00ms

A CH1

3.00V

B

W

B

T

W

CH3 2.00V ^BCH4 5.00V

T

7.96000ms

W

Figure 27. Power-Down Sequence at EN Falling, T_A= +25°C, V_INP= 24 V,

V_OUT1= 24 V, I_OUT1= 50 mA, V_OUT2= 3.3 V, I_OUT2= 15 mA

Figure 24. Power-Up Sequence at EN Rising, T_A= 25°C, V_INP= 24 V,

V_OUT1= 24 V, I_OUT1= 50 mA, V_OUT2= 3.3 V, I_OUT2= 15 mA

Rev. 0 | Page 15 of 37

ADP1032

Data Sheet

V

OUT1

V

OUT1

2

I

SWP

I

SWP

3

V

SWP

V

SWP

4

CH2 50.0mV Ω ^BCH3 100mA ^B

M1.00µs

W

T

CH2 10.0mV Ω ^BCH3 50.0mA ^B

A CH1

0.00000s

38.0V

W

_WM1.00µs

0.00000s

A CH4

38.0V

W

B

CH4 20.0V

W

B

CH4 20.0V

W

T

Figure 28. Flyback Regulator Continuous Conduction Mode Operation

Showing I_SWP, Switch Node Voltage, and Output Ripple, T_A= 25°C,

Figure 31. Flyback Regulator Discontinuous Conduction Mode Operation

Showing I_SWP, Switch Node Voltage, and Output Ripple, T_A= 25°C,

V

_INP= 24 V, V_OUT1= 24 V, I_OUT1= 80 mA

V_INP= 24 V, V_OUT1= 24 V, I_OUT1= 20 mA

V

OUT1

2

EN

1

2

V

OUT1

I

SWP

3

I

SWP

4

3

V

SWP

V

SWP

4

CH2 5.00mV Ω ^BCH3 100mA ^B

M4.00µs

T

A CH4

0.00000s

38.0V

W

CH1 5.00V ^BCH2 10.0V

A CH1

3.00V

W

B

CH4 50.0V

W

CH3 50.0V ^B

B

CH4 500mA

T

19.90%

W

Figure 32. Flyback Regulator Short-Circuit Current Limit During Startup,

V_INP= 24 V, V_OUT1= SGND2, T_A= 25°C

Figure 29. Flyback Regulator Pulse Skipping Operation Showing Inductor

Current (I_SWP), Switch Node Voltage, and Output Ripple, T_A= 25°C,

V_INP= 48 V, V_OUT1= 24 V, I_OUT1= 4 mA

I

OUT1

4

V

OUT1

2

V

SWP

V

SWP

3

CH2 1.00V Ω ^BCH3 20.0V

B

M4.00ms

CH2 1.00V Ω^BCH3 20.0V

M4.00ms

12.7800ms

A CH2

–120mV

A CH4

–14.0mA

W

CH4 –20.0mA ^B

T

22.50%

W

CH4 100mA ^B

T

W

Figure 33. Flyback Regulator Load Transient Response, V_INP= 24 V,

V_OUT1= 24 V, I_OUT1= 1 mA to 20 mA Step, T_A= 25°C

Figure 30. Flyback Regulator Load Transient Response, V_INP= 24 V,

V_OUT1= 24 V, I_OUT1= 1 mA to 80 mA Step, T_A= 25°C

Rev. 0 | Page 16 of 37

Data Sheet

ADP1032

400µs STEP

15µs STEP

V

OUT1

INP

1

2

1

2

V

I

OUT1

SWP

V

SWP

3

B

CH1 10.0V ^BCH2 1.00V

A CH1

20.6V

B

CH1 10.0V ^BCH2 1.00V

M4.00ms

20.20%

A CH1

20.6V

W

CH3 50.0V ^B

T

20.20%

T

W

Figure 34. Flyback Regulator Line Transient Response,

Figure 37. Flyback Regulator Line Transient Response,

V_INP= 18 V to 32 V at 400 µs Step Time, V_OUT1= 24 V,

V

_INP= 18 V to 32 V at 15 µs Step Time, V_OUT1= 24 V,

I_OUT1= 80 mA, T_A= 25°C

I

_OUT1= 80 mA, T_A= 25°C

1.5

1.0

1.5

1.0

–40°C

+25°C

+125°C

–40°C

+25°C

+125°C

0.5

0

–0.5

–1.0

–1.5

–0.5

–1.0

–1.5

0

10

20

30

(mA)

40

50

0

50

100

150

I

(mA)

OUT2

OUT1

Figure 35. Cross Regulation, Flyback Regulator Regulation vs. Buck Regulator

Load Current Across Temperature, V_INP= 24 V, V_OUT1= 24 V, I_OUT1= 80 mA,

V_OUT2= 3.3 V

Figure 38. Cross Regulation, Buck Regulator Regulation vs. Flyback Regulator

Load Current Across Temperature, V_INP= 24 V, V_OUT1= 24 V,

V

_OUT2= 3.3 V, I_OUT2= 13 mA

100

95

90

85

80

75

70

65

60

55

50

V

= 6V

OUT1

= 15V

= 24V

= 28V

90

80

70

60

50

V

= 6V

OUT1

= 15V

= 24V

= 28V

0

20

40

60

80

100

120

140

160

0

20

40

60

80

100

120

140

160

I (mA)

OUT2

I

(mA)

OUT2

Figure 36. Buck Regulator Efficiency vs. Load Current over Various V_OUT1

V_OUT2= 5.15 V, T_A= 25°C

,

Figure 39. Buck Regulator Efficiency vs. Load Current over Various V_OUT1

_OUT2= 5.0 V, T_A= 25°C

,

V

Rev. 0 | Page 17 of 37

ADP1032

Data Sheet

90

85

80

75

70

65

60

55

50

90

85

80

75

70

65

60

55

50

V

= 6V

OUT1

= 15V

= 24V

= 28V

–40°C

+25°C

+125°C

0

20

40

60

80

100

120

140

160

0

20

40

60

80

100

120

140

160

I

(mA)

I

(mA)

OUT2

Figure 43. Buck Regulator Efficiency vs. Load Current Across Temperature,

V_OUT1= 24 V, V_OUT2= 5 V

Figure 40. Buck Regulator Efficiency vs. Load Current over Various V_OUT1

V_OUT2= 3.3 V, T_A= 25°C

,

1.5

–40°C

+25°C

+125°C

+25°C

+125°C

1.0

0.5

1.0

0.5

0

–0.5

–1.0

–1.5

–0.5

–1.0

–1.5

5

10

15

20

25

30

0

20

40

60

(mA)

80

100

V

(V)

I

OUT1

OUT2

Figure 44. Buck Regulator Line Regulation Across Temperature,

V_OUT2= 5.15 V, I_OUT2= 7 mA, Nominal Conditions = V_OUT2at 24 V V_OUT1

Figure 41. Buck Regulator Load Regulation Across Temperature,

V_OUT2= 3.3 V, V_OUT1= 24 V, Nominal Conditions = V_OUT2at 25 mA I_OUT2

180

160

V

= 3.3V

= 5V

= 5.15V

OUT2

V

= 3.3V

= 5V

= 5.15V

OUT2

160

140

120

100

80

140

120

100

80

60

40

20

0

5

10

15

20

25

30

0

10

20

30

V

(V)

V

(V)

OUT1

Figure 45. Buck Regulator Maximum Output Current Over Various Buck

Regulator Output Voltages, T_A= 25°C, V_INP= 24 V, V_OUT1= 24 mA,

Based on Target of 70% I_{LIM (FLYBACK)}or I_{LIM (BUCK)}, Whichever Comes First

Figure 42. Buck Regulator Maximum Output Current Over Various Buck

Regulator Output Voltages, T_A= 25°C, V_INP= 24 V, I_OUT1= 0 mA,

Based on Target of 70% I_{LIM (FLYBACK)}or I_{LIM (BUCK)}, Whichever Comes First

Rev. 0 | Page 18 of 37

Data Sheet

ADP1032

V

OUT2

V

OUT2

1

I

SW2

I

SW2

2

3

2

3

V

SW2

V

SW2

CH1 10.0mV Ω ^BCH2 20.0mA ^B

M10.0µs A CH3

700.000ns

20.4V

W

B

CH1 50.0mV Ω ^BCH2 100mA

M2.00µs A CH3

–40.000ns

3.80V

W

B

CH3 10.0V

T

W

B

CH3 10.0V

T

W

Figure 46. Buck Regulator Pulse Skipping Operation Showing Inductor

Current 2 (I_SW2), Switch Node Voltage, and Output Ripple, T_A= 25°C,

V_OUT1= 24 V, V_OUT2= 5.15 V, I_OUT2= 0.3 mA

Figure 49. Buck Regulator Discontinuous Conduction Mode Operation

Showing I_SW2, Switch Node Voltage, and Output Ripple, T_A= 25°C,

V_OUT1= 21 V, V_OUT2= 5.15 V, I_OUT2= 50 mA

V

OUT2

V

1

OUT2

1

I

SW2

2

3

V

SW2

V

SW2

3

B

CH1 1.00V Ω ^B

CH2 200mA

M200µs A CH2

595.000µs

164mA

CH1 20.0mV Ω ^BCH2 50.0mA ^B

M2.00µs A CH3

40.0000ns

16.0V

W

B

CH3 10.0V

T

W

CH3 10.0V

T

W

Figure 50. Buck Regulator Short-Circuit Current Limit During Startup,

V_OUT1= 24 V, V_OUT2= SGND2, T_A= 25°C

Figure 47. Buck Regulator Discontinuous Conduction Mode Operation

Showing I_SW2, Switch Node Voltage, and Output Ripple, T_A= 25°C,

V

_OUT1= 21 V, V_OUT2= 5.15 V, I_OUT2= 7 mA

I

OUT2

I

OUT2

1

2

1

2

V

OUT2

V

OUT2

V

SW2

V

SW2

3

B

CH1 5.00mA

CH3 10.0V

CH2 500mV

M2.00ms A CH1

4.30mA

B

W

CH1 5.00mA

CH3 10.0V

CH2 500mV

M2.00ms A CH1

4.30mA

W

B

T

5.92000ms

W

T

5.92000ms

W

Figure 51. Buck Regulator Load Transient Response, V_OUT1= 21 V,

_OUT2= 5.15 V, I_OUT2= 0.3 mA to 7 mA Step, T_A= 25°C

Figure 48. Buck Regulator Load Transient Response, V_OUT1= 24 V,

_OUT2= 5.15 V, I_OUT2= 0.3 mA to 7 mA Step, T_A= 25°C

V

Rev. 0 | Page 19 of 37

ADP1032

Data Sheet

10

V

10

8

V

= 2.5V, V

= 3.3V, V

= 5.0V, V

= 1.8V

= 3.3V

= 5.0V

= 2.5V, V

= 3.3V, V

= 5.0V, V

= 1.8V

= 3.3V

= 5.0V

MVDD

SVDD1

MVDD

SVDD1

V

MVDD

8

6

4

2

0

6

4

2

0

10

20

30

40

50

60

70

80

90

100

0

10

20

30

40

50

60

70

80

90

100

DATA RATE (Mbps)

Figure 55.SVDD1 Supply Current (I_SVDD1) per SPI Input vs. Data Rate at Various

Figure 52.MVDD Supply Current (I_MVDD) per SPI Input vs. Data Rate at Various

SSS

Supply Voltages,

Low, Clock Signal Applied on Single SPI Channel,

Other Input Channels Tied Low

MSS

Supply Voltages,

Low, Clock Signal Applied on Single SPI Channel, Other

Input Channels Tied Low

16

V

MVDD

= 2.5V, V

= 3.3V, V

= 5.0V, V

= 1.8V

= 3.3V

= 5.0V

= 2.5V, V

= 3.3V, V

= 5.0V, V

= 1.8V

= 3.3V

= 5.0V

MVDD

SVDD1

MVDD

SVDD1

V

14

12

10

8

14

12

10

8

6

4

2

0

10

20

30

40

50

60

70

80

90

100

0

10

20

30

40

50

60

70

80

90

100

DATA RATE (Mbps)

SSS

Figure 56. I_SVDD1vs. Data Rate at Various Supply Voltages,

Low, Clock

MSS

Figure 53. I_MVDDper SPI Output vs. Data Rate at Various Supply Voltages,

Low,

Signal Applied on Single SPI Channel, Other Input Channels Tied Low

Clock Signal Applied on Single SPI Channel, Other Input Channels Tied Low

10

V

= 2.5V, V

= 3.3V, V

= 5.0V, V

= 1.8V

= 3.3V

= 5.0V

V

= 2.5V, V

= 3.3V, V

= 5.0V, V

= 1.8V

= 3.3V

= 5.0V

MVDD

SVDD1

MVDD

SVDD1

8

6

4

2

0

8

6

4

2

0

–50

–25

0

25

50

75

100

125

–50

–25

0

25

50

75

100

125

TEMPERATURE (°C)

SSS

Figure 57. I_SVDD1vs. Temperature at Various Supply Voltages,

Rate = 10 Mbps on All SPI Channels

Low, Data

MSS

Figure 54. I_MVDDvs. Temperature at Various Supply Voltages,

Rate = 10 Mbps on All SPI Channels

Low, Data

Rev. 0 | Page 20 of 37

Data Sheet

ADP1032

14

12

10

8

V

= 2.5V, V

= 3.3V, V

= 5.0V, V

= 1.8V

= 3.3V

= 5.0V

V

= 2.5V, V

= 3.3V, V

= 5.0V, V

= 1.8V

= 3.3V

= 5.0V

MVDD

SVDD1

MVDD

SVDD1

12

10

8

6

4

2

0

–50

0

–25

0

25

50

75

100

125

–50

–25

0

25

50

75

100

125

TEMPERATURE (°C)

Figure 61. SPI Channels t_PHLvs. Temperature at Various Supply Voltages

Figure 58. SPI Channels t_PLHvs. Temperature at Various Supply Voltages

45

4.0

V

= 2.5V, V

= 3.3V, V

= 5.0V, V

= 1.8V

= 3.3V

= 5.0V

MVDD

SVDD2

V

= 2.5V, V

= 3.3V, V

= 5.0V, V

= 1.8V

= 3.3V

= 5.0V

MVDD

SVDD2

40

35

30

25

20

15

10

5

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

20

40

60

80

100

0

20

40

60

80

100

DATA RATE (kbps)

Figure 62. SVDD2 Supply Current (I_SVDD2) vs. Data Rate on All GPIO Channels

MSS

Figure 59. I_MVDDvs. Data Rate on All GPIO Channels at Various Supply

MSS

at Various Supply Voltages,

High

Voltages,

High

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

45

40

35

30

25

20

15

10

5

V

= 2.5V, V

= 1.8V

V

= 2.5V, V

= 3.3V, V

= 5.0V, V

= 1.8V

= 3.3V

= 5.0V

MVDD

SVDD2

MVDD

SVDD2

= 3.3V, V

= 5.0V, V

= 3.3V

= 5.0V

0

–50

–25

0

25

50

75

100

125

–50

–25

0

25

50

75

100

125

TEMPERATURE (°C)

SSS

Figure 63. I_SVDD2vs. Temperature at Various Supply Voltages,

Rate = 40 kbps on All GPIO Channels

Low, Data

Figure 60. I_MVDDSupply Current vs. Temperature at Various Supply Voltages,

MSS

Low, Data Rate = 40 kbps on All GPIO Channels

Rev. 0 | Page 21 of 37

ADP1032

Data Sheet

10

9

8

7

6

5

4

3

2

1

0

V

MVDD

= 2.5V, V

= 3.3V, V

= 5.0V, V

= 1.8V

= 3.3V

= 5.0V

V

= 2.5V, V

= 3.3V, V

= 5.0V, V

= 1.8V

= 3.3V

= 5.0V

MVDD

SVDD2

MVDD

SVDD2

V

9

8

7

6

5

4

3

2

1

0

–50

–25

0

25

50

75

100

125

–50

–25

0

25

50

75

100

125

TEMPERATURE (°C)

Figure 65. GPIO Channels t_PHLvs. Temperature at Various Supply Voltages

Figure 64. GPIO Channels t_PLHvs. Temperature at Various Supply Voltages

Rev. 0 | Page 22 of 37

Data Sheet

ADP1032

THEORY OF OPERATION

The ADP1032 is a high performance, isolated micro PMU that

combines an isolated flyback regulator and a buck regulator,

providing two isolated power rails. Additionally, the ADP1032

includes seven low power digital isolators in a 41-lead LFCSP

package for channel to channel isolated applications where

power dissipation and board space are at a premium.

D1

V

OUT1

R

FT1

FB1

Tx1

1:1

C

FLYBK

SWP

FB1

VOUT1

SYNC

FEEDBACK

AND

FLYBACK

CONTROLLER

OVER VOLTAGE

CONTROL

V

INP

C

VINP

EN

PLL

PG1

÷2

R5

R6

IN

V

OUT2

÷2

VOUT2

SW2

GNDP

PGNDP

C

BUCK

HIGH

EFFICIENCY

BUCK

L1

SLEW

PG2

MVDD

C1

MVDD

MGND

PWRGD

SVDD2

SGND2

C3

PWRGD

MGPO3

MGPI2

SGPI3

CONTROL

BLOCK

CONTROL

BLOCK

SGPO2

SGPO1

SVDD1

MGPI1

SVDD1

C4

ENCODE

DECODE

ENCODE

MSS

MCK

SSS

SCK

SI

MO

SO

MI

SGND1

MGND

NOTES

1. C

2. C

IS THE FLYBACK REGULATOR OUTPUT CAPACITOR VALUE.

IS THE BUCK REGULATOR OUTPUT CAPACITOR VALUE.

FLYBK

BUCK

Figure 66. Simplified Block Diagram

Rev. 0 | Page 23 of 37

ADP1032

Data Sheet

Flyback Undervoltage Lockout (UVLO)

FLYBACK REGULATOR

The UVLO circuitry monitors the VINP pin voltage level. If the

input voltage drops below the V_{UVLO_VINP (FALL)}threshold, the

flyback regulator turns off. After the VINP pin voltage rises

above the V_{UVLO_VINP (RISE)}threshold, the soft start period

initiates, and the flyback regulator enables.

Flyback Regulator Operation

The flyback regulator in the ADP1032 generates an isolated output

supply rail that can be programmed from 6 V to 28 V for the

adjustable output version or 24 V for the factory programmable

fixed output versions. The flyback regulator adopts current mode

control, resulting in a fast, inner current controlled loop that

regulates the peak inductor current and a slower outer loop via

an isolated iCoupler channel that adjusts the current controlled

loop to define a regulated output voltage. When the high voltage

switch is on, the diode on the secondary side of the transformer

is reverse biased, which causes an increase in the current in the

primary inductance of the transformer and is stored as energy.

When the switch turns off, the diode becomes forward biased,

and energy stored in the transformer is transferred to the load.

Flyback Regulator Precision Enable Control

The flyback regulator in the ADP1032 features a precision

enable circuit with an accurate reference voltage. If the voltage

at the EN pin rises above the V_{EN_RISING}threshold, the flyback

regulator soft start period initiates, and the regulator enables. If

the EN pin voltage falls below the V_{EN_RISING}− V_{EN_HYST}threshold,

the flyback regulator turns off.

Flyback Regulator Soft Start

The flyback regulator includes a soft start function that limits

the inrush current from the supply and ramps up the output

voltage in a controlled manner. The flyback regulator soft start

period initiates when the voltage at the EN pin rises above the

Traditionally, in an isolated flyback regulator, a discrete opto-

coupler is used in the feedback path to transmit the signal from

the secondary side to the primary side. However, the current

transfer ratio (CTR) of the optocouplers degrades over time and

over temperature. Therefore, the optocoupler must be replaced

every 5 years to 10 years. The ADP1032 eliminates the use of an

optocoupler and the associated problems by integrating Analog

Devices, Inc., iCoupler technology for feedback, which reduces

system cost, PCB area, and complexity, while improving system

reliability without the issue of CTR degradation.

V_{EN_RISING}threshold.

Flyback Slew Rate Control

The flyback regulator employs programmable output driver slew

rate control circuitry. This circuitry adjusts the slew rate of the

switching node as shown in Figure 67, where lower EMI and

reduced ringing can be achieved at slightly lower efficiency

operation and vice versa. To program the slew rate, connect the

SLEW pin to the VINP pin for normal mode, to the GNDP pin

for slow mode, or leave it open for fast mode.

The flyback regulator uses a transformer with a single primary

and secondary winding. This configuration is possible because

iCoupler technology is used to send an isolated control signal to

the primary side controller so that a primary sense winding is

not required. In addition, because the secondary rail is generated

using a high efficiency switching regulator, extra secondary

windings are not required. This approach offers a number of

advantages over an alternative multiwinding solution, such as

the following:

Slew rate control causes a trade-off between efficiency and

low EMI.

FASTEST



A smaller transformer solution size due to a lower number

of turns required on the core and a fewer number of pins.

Each output can be independently set. The multitap

approach requires a custom multitap transformer for

different output voltage combinations.

SLOWEST



Outputs are more accurate because the outputs do not rely

on the discrete ratios between the transformer windings.

Output accuracy is unaffected by load changes on each rail.

Figure 67. Switching Node at Various Slew Rate Settings

Power Saving Mode (PSM)

Table 11. Slew Rate Settings

During light load operation, the regulators can skip pulses to

maintain output voltage regulation. Therefore, no minimum

load is required. Skipping pulses increases the device efficiency

but results in larger output ripple.

SLEW Pin

Connection

Slew Rate

Slow

Normal

Fast

Comment

GNDP

VINP

Unconnected

Lowest EMI

Optimized efficiency and EMI

Highest efficiency

Rev. 0 | Page 24 of 37

Data Sheet

ADP1032

Flyback Regulator Overcurrent Protection

Buck Regulator UVLO

The flyback regulator features a current-limit function that senses

the forward current in the switching metal-oxide semiconductor

field effect transistor (MOSFET) on a cycle by cycle basis. If the

current exceeds the I_{LIM (FLYBACK)}threshold, the switch turns off.

The step-down regulator of theADP1032 features an internal

UVLO circuit that monitors the input voltage to the regulator or

VOUT1. If the voltage at VOUT1 drops below the internal

threshold level of 4.5 V, the regulator turns off. If the output at

VOUT1 rises above the internal threshold, the regulator soft

start period initiates, and the regulator enables.

Flyback Regulator Overvoltage Protection

The flyback regulator of the ADP1032 implements a number of

OVP methods to detect and prevent an overvoltage condition

on the flyback regulator output, such as the following:

Buck Regulator Soft Start

The step-down regulator in the ADP1032 includes soft start

circuitry that ramps the output voltage in a controlled manner

during start-up, limiting the inrush current.

•

If the voltage on the FB1 pin exceeds V_FB1by 10% for the

adjustable output version, or the VOUT1 pin exceeds the

factory programmed V_OUT1by 10% for the fixed output

version, an OVP fault is detected, which prevents the

flyback regulator switch from turning on. The flyback

regulator primary switch stays off until the OVP condition

is no longer present.

Buck Regulator Current-Limit Protection

The step-down regulator in the ADP1032 includes a current-

limit protection circuit to limit the amount of forward current

through the high-side MOSFET switch. The inductor peak current

is monitored cycle by cycle to detect an overload condition. When

the overload condition occurs, the current-limit protection

limits the peak inductor current to I_{LIM (BUCK)}, resulting in a drop

in the output voltage.

•

If communication across the isolation barrier from the

secondary controller to the primary controller fails, the

flyback regulator shuts down, and a new soft start power-up

cycle initiates.

If the voltage on the output of the flyback regulator exceeds

the severe overvoltage threshold (SOVP_FLYBACK), the primary

controller does not turn on the primary side switch. The

flyback regulator primary switch stays off until the voltage on

the VOUT1 pin falls below the SOVP_FLYBACK− SOVP_{FLYBACK_HYST}

threshold.

Buck Regulator Active Pull-Down Resistor

The buck regulator has an active pull-down resistor that discharges

the output capacitor when the output of the VOUT1 pin is

between 1.23 V and 4.5 V. The pull-down resistor connects

between VOUT2 and SGND2.

Buck Regulator OVP

The step-down regulator of the ADP1032 features an OVP

circuit that monitors the output voltage. If the voltage on the

VOUT2 pin exceeds the nominal output voltage by 10%, the

step-down, dc-to-dc regulator stops switching until the voltage

falls below the threshold again.

BUCK REGULATOR

Buck Regulator Operation

The step-down, dc-to-dc (or buck) regulator in the ADP1032

uses a current mode controlled scheme, operating at a fixed

frequency set by an internal oscillator. Current mode uses a fast

inner current-controlled loop to regulate peak inductor current

and a slower outer loop to adjust the current loop to regulate

the output voltage. At the start of each oscillator cycle, the high-

side MOSFET switch turns on, applying the input voltage to one

end of the inductor, which normally causes the buck regulator

inductor current (I_{L_BUCK}) to increase until the current sense

signal crosses the peak inductor current threshold that turns

off the MOSFET switch. The error amplifier output sets this

threshold. During the high-side MOSFET off time, the inductor

current declines through the low-side MOSFET switch until

either the next oscillator clock pulse starts a new cycle that results

in continuous conduction mode (CCM) operation, or the inductor

current reaches zero. The low-side MOSFET switch is turned

off, and the control system waits for the next oscillator clock

pulse to start a new cycle, resulting in discontinuous mode

(DCM) operation. Under light load conditions, the regulator

can skip pulses to maintain regulation and increase power

conversion efficiency.

POWER GOOD

The ADP1032 provides a push pull, power-good output to

indicate when the two isolated output voltage rails are valid.

The PWRGD pin pulls high when the voltages on the two

supplies are within the respective power-good threshold limits.

Rev. 0 | Page 25 of 37

ADP1032

Data Sheet

POWER-UP SEQUENCE

DATA ISOLATION

High Speed SPI Channels

The power-up sequence is as follows (see Figure 68):

The ADP1032 has four high speed channels. The first three,

CLK, MI/SO, and MO/SI (the slash indicates the connection of

the input and output forming a datapath across the isolator that

corresponds to an SPI bus signal), are optimized for low

propagation delay. With a maximum propagation delay of 15 ns,

the ADP1032 supports read and write clock rates up to 16.6 MHz

in the standard 4-wire SPI. However, in practice, the maximum

clock rate of 16.6 MHz is reduced as a result of the delays added

across the total ground trip of the signal.

1. The flyback regulator powers up first (see Label 1 in

Figure 68).

2. When V_OUT1rises above the lower power-good threshold

(V_{PG_FLYBACK_LL}), the buck regulator turns on (see Label 2 in

Figure 68).

3. When the buck regulator output (V_OUT2) rises above the

lower power-good threshold (V_{PG_BUCK_LL}), the PWRGD is

driven high (see 3 in Figure 68).

4. If any of the two analog supplies move outside the

power-good threshold ranges, PWRGD drives low after a

short deglitch delay (see 4 in Figure 68).

The relationship between the SPI signal paths, the ADP1032 pin

mnemonics, and the data directions are detailed in Table 13.

V

OUT1

PG_FLYBACK_UL

Table 13. Correspondence of the Pin Mnemonics to the SPI

Signal Path Names

V

PG_FLYBACK_LL

SPI Signal Path Master Side

Data Direction Slave Side

2

V

INP

CLK

MCK

MO

MI

SCK

SI

→

←

→

MO/SI

MI/SO

SS

4

V

OUT2

SO

SSS

V

PG_BUCK_LL

MSS

1

3

The datapaths are SPI mode agnostic. The CLK and MO/SI SPI

datapaths are optimized for propagation delay and channel to

channel matching. The MI/SO SPI datapath is optimized for

propagation delay. The device does not synchronize to the clock

channels. Therefore, there are no constraints on the clock

polarity or timing with respect to the data lines.

0V

PWRGD

HIGH

LOW

Figure 68. Power Sequencing and PWRGD

OSCILLATOR AND SYNCHRONIZATION

SS

Slave select ( ) is an active low signal. To save power in a

A phase-locked loop (PLL)-based oscillator generates the internal

clock for the flyback and buck regulators and offers an internally

generated frequency or external clock synchronization. Connect

the SYNC pin as described in Table 12 to configure the switching

frequency. For external synchronization, connect the SYNC pin to

a suitable clock source. The PLL locks to an input clock within

SS

multichannel system, puts the other SPI isolator channels in

SS

a low power state when the channels are not in use ( = high),

and these channels are only active when required, which is when

SS

is low. The clock and data channels are gated to the as shown

in Figure 69. However, this power saving mode adds 100 ns of

latency. This latency is the time required for the internal circuitry

to wake up from the low power state and to start transmitting

data to the isolation barrier. Conversely, the latency is the delay

the range specified by f_SYNC

.

Table 12. Sync Pin Functionality

MSS

from the falling edge of

to the first clock edge or data edge

Switching Frequency (f_SW

Flyback Buck

)

that appears on the slave side, as shown in Figure 70.

SYNC Pin State

Low or High

350 kHz to 750 kHz

250 kHz

f_SYNC/2

125 kHz

f_SYNC/4

ENCODE

DECODE

ENCODE

SSS

SCK

SI

MSS

MCK

MO

THERMAL SHUTDOWN

If the ADP1032 junction temperature rises above T_SHDN, the

thermal shutdown circuit turns the flyback regulator off.

SO

MI

Extreme junction temperatures can be the result of prolonged

high current operation, poor circuit board design, and/or high

ambient temperatures. When thermal shutdown occurs, hysteresis

is included so that the ADP1032 does not return to operation until

the on-chip temperature drops below T_SHDN− T_HYS. When resuming

from thermal shutdown, the ADP1032 performs a soft start.

Figure 69. High Speed Data Isolation Channel Gating

Rev. 0 | Page 26 of 37

Data Sheet

ADP1032

SPI

ACTIVATION

(LATENCY)

SPI TRANSMIT

MSS

SSS

t_PW

t_P2

t_P1

MCK, MO, SO

SCK, SI, MI

t_P3

HIGH IMPEDANCE

ADD A PULL HIGH OR PULL LOW RESISTOR

TO HAVE A KNOWN STATE WHEN MSS IS HIGH.

LATENCY = MSS FALLING EDGE TO SCK, SI, MI STARTS SENDING DATA (EXIT TO HIGH IMPEDANCE MODE).

t

= MCK, MO, SO PULSE WIDTH.

= MSS TO SSS PROPAGATION DELAY.

= MCK TO SCK, MO TO SI, SO TO MI PROPAGATION DELAY.

= MSS RISING EDGE TO SCK, SI, MI RETURN TO HIGH IMPEDANCE STATE. SAME AS t

PW

P1

P2

P3

.

P1

Figure 70. SPI Isolators Timing Diagram

MSS

The MI, SCK, and SI outputs are also tristated when

is high

MSS

MCK

MO

SSS

SCK

SI

(see Table 14) to allow a more flexible design and to avoid the

requirement for external multiplexing of MI in a multichannel

system. Figure 71 shows how the SPI busses from multiple

ADP1032 devices can be connected together.

MSS

1

MCK

MO

MI

CHANNEL 1

MI

SO

MSS

Table 14. SPI

Parameter

Gating

MSS High

MSS Low

MSS

MCK

MO

SSS

SCK

SI

MSS

2

SSS

SCK

SI

High

Low

MCK

MO

SO

Tristate

CHANNEL 2

CHANNEL 3

CHANNEL 4

SO

MI

Connect a pull-up or pull-down resistor to MI, SCK, and SI to

MSS

SSS

SCK

SI

pull these pins to the desired logic state when

is high.

MSS

MCK

MO

MSS

3

SO

MI

SSS

SCK

SI

MSS

MCK

MO

MSS

4

SO

MI

TO CHANNEL 5

THROUGH

CHANNEL 8

Figure 71. Multichannel SPI Muxing Scheme

Rev. 0 | Page 27 of 37

ADP1032

Data Sheet

GPIO Data Channels

sending these inputs back for similar processing. Because of the

sampled nature of this process, the general-purpose data channels

exhibit a sampling uncertainty that resembles 19.5 µs peak jitter.

The general-purpose data channels are provided as space saving

isolated datapaths where timing is not critical. The dc value of

all low speed general-purpose inputs, on a given side of the device,

are sampled simultaneously, packetized, and shifted across a single

isolation coil. The process is then reversed by reading the inputs

on the opposite side of the device, packetizing the inputs and

For proper operation of the GPIO channels, refer to Table 15.

Power both the MVDD pin and SVDD2 pin within the specified

input voltage range for these pins.

Table 15. Truth Table for GPIO Channels

MVDD State

Unpowered

Powered

SVDD2 State

xGPIx

MGPOx

Low

High

Low

SGPOx

Low

High

Low

Test Conditions/Comments

During startup

Normal operation

Powered

Unpowered

Powered

Don’t care

High

Powered

Low

Powered

Powered to Unpowered

Powered

Don’t care

Hold¹

Low

Hold¹

¹Hold means that the current state of the outputs are preserved.

Rev. 0 | Page 28 of 37

Data Sheet

ADP1032

APPLICATIONS INFORMATION

COMPONENT SELECTION

Feedback Resistors

Capacitor Selection

Higher output capacitor values reduce the output voltage ripple

and improve the load transient response. When choosing this

value, it is also important to account for the loss of capacitance

due to the output voltage dc bias.

The ADP1032 provides an adjustable output voltage for the

flyback regulator. An external resistor divider sets the output

voltage, for which the divider output must equal the appropriate

feedback reference voltage, V_FB1. To limit the output voltage

accuracy degradation due to the feedback bias current, ensure

that the current through the divider is at least 10 times I_FB1. The

recommended first feedback resistor (R_FB1) values are in the

range of 50 kΩ to 250 kΩ to minimize the output voltage error

due to the bias current and to lessen the power dissipation

across the feedback resistors. The external feedback resistors are

not required for the fixed output versions because the feedback

resistors are already inside the chip.

Ceramic capacitors are manufactured with a variety of dielectrics,

each with a different behavior over temperature and applied

voltage. Capacitors must have a dielectric adequate to ensure the

minimum capacitance over the necessary temperature range and

dc bias conditions. X5R or X7R dielectrics with voltage ratings of

25 V to 50 V (depending on output) are recommended for best

performance. Y5V and Z5U dielectrics are not recommended for

use with any dc-to-dc converter because of their poor temperature

and dc bias characteristics.

V_OUT1

6V TO 28V

D1

Calculate the worst case capacitance accounting for capacitor

variation over temperature, component tolerance, and voltage

using the following equation:

1:1

V_INP

R_FT1

R_FB1

C_FLYBK

10µF

Tx1

C

_EFFECTIVE= C_NOMINAL× (1 − TEMPCO) × (1 − DCBIASCO) ×

(1 − Tolerance)

where:

SWP

VINP

FB1

SGND2

VOUT1

FLYBACK

Figure 72. Flyback Regulator Output Voltage Setting

C_EFFECTIVEis the effective capacitance at the operating voltage.

_NOMINALis the nominal capacitance shown in this data sheet.

C

TEMPCO is the worst case capacitor temperature coefficient.

DCBIASCO is the dc bias derating at the output voltage.

Tolerance is the worst case component tolerance.

Set the positive output for the flyback regulator by using the

following equation:

V

_OUT1= V_FB1× (1 + (R_FT1/R_FB1))

To guarantee the performance of the device, it is imperative to

evaluate the effects of dc bias, temperature, and tolerances on

the behavior of the capacitors for each application.

where:

V

_OUT1is the flyback output voltage.

V

_FB1is the flyback feedback voltage.

Capacitors with lower effective series resistance (ESR) and effective

series inductance (ESL) are preferred to minimize voltage ripple.

R

_FT1is the feedback resistor from VOUT1 to FB1.

_FB1is the feedback resistor from FB1 to SGND2.

FLYBACK REGULATOR COMPONENTS SELECTION

Input Capacitor

Conversely, calculate the value of the top resistor for the target

_OUT1by:

V

An input capacitor must be placed between the VINP pin and

ground. Ceramic capacitors greater than or equal to 3.3 μF over

temperature and voltage are recommended. The input capacitor

reduces the input voltage ripple caused by the switching current.

Place the input capacitor as close as possible to the VINP pin

and PGNDP pin to reduce input voltage spikes. The voltage

rating of the input capacitor must be greater than the maximum

input voltage.

R

_FT1= R_FB1× ((V_OUT1/V_FB1) − 1)

Table 16. Recommended Feedback Resistor Values

Flyback Regulator

Desired Output

Voltage (V)

Calculated Output

R_FT1(MΩ) R_FB1(kΩ) Voltage (V)

6

0.715

1.24

1.54

2.15

3.48

3.4

110

121

110

121

120

100

6.000

9

8.998

12

15

24

28

12.000

15.015

24.000

28.000

Output Capacitor

Higher output capacitor values reduce the output voltage ripple

and improve load transient response. When choosing this value,

it is also important to account for the loss of capacitance due to

the output voltage dc bias. A 10 μF capacitor is recommended as a

balance between performance and size.

Rev. 0 | Page 29 of 37

ADP1032

Data Sheet

Ripple Current vs. Capacitor Value

Series Winding Resistance

The output capacitor value must be chosen to minimize the

output voltage ripple while considering the increase in size and

cost of a larger capacitor. Use the following equation to calculate

the output capacitance:

In power loss sensitive applications, keep the series resistance of

the primary and secondary windings as low as possible to

improve overall efficiency.

Leakage Inductance and Clamping Circuits

C

_OUT= (L_PRI× I_SWP²)/(2 × V_OUT1× ΔV_OUT1

)

When choosing a transformer to operate with the ADP1032,

minimize transformer leakage inductance. Leakage inductance

causes a voltage spike to appear on the SWP node when the

flyback regulator switch is off due to energy storage in the

leakage inductance that is not transferred to the output. The

voltage spike is more prominent at higher load currents and

increases with higher leakage inductance. It is important to

keep the voltage spikes lower than the voltage rating of the

flyback switch that drives the SWP pin. Margin must be built

into any design to avoid exceeding this limit if no clamp or

snubber circuit is used to protect the flyback switch.

where:

C

L

I

_OUTis the capacitance of the flyback output capacitor.

_PRIis the primary inductance of the transformer.

_SWPis the peak switch current.

ΔV_OUT1is the allowable flyback regulator output ripple.

Schottky Diode

A Schottky diode with low junction capacitance is recommended

for the rectification diode D1. At higher output voltages and

especially at higher switching frequencies, the junction capacitance

is a significant contributor to efficiency. Choose an output diode

with a forward current rating (I_F) that is greater than the maximum

load requirement and with a reverse voltage rating (V_R) that is

greater than the summation of the maximum supply voltage

(V_{INP (MAX)}) and the maximum output voltage (V_{OUT1 (MAX)}).

To estimate the leading voltage spike at the SWP pin when the

switch turns off, use the following equation:

V

_PEAK= I_PEAK× (L_LEAK/(C_P+ C_SWP))^1/2+ V_INP+ V_OUT1+ V_D

where:

Transformer

V

_PEAKis the voltage spike amplitude.

_PEAKis the peak current on the flyback switch.

_LEAKis the leakage inductance of the transformer.

C_Pis the parasitic capacitance of the transformer.

_SWPis the capacitance on the flyback switch.

_INPis the input supply voltage.

I

L

The transformer used with the ADP1032 is an important

component within the system, in terms of efficiency and

maximum output power capability. The transformer designs are

listed in Table 17. A number of factors must be taken into account

when designing a transformer for use with the ADP1032.

C

V

V_Dis the forward voltage drop across the rectifier diode.

Turn Ratio

A snubber or clamp circuit can protect the flyback switch for

cases where the leakage inductance is too high for application

conditions. Two common types of clamping circuits are the

resistor, capacitor, diode clamp shown in Figure 73 and the diode

Zener diode clamp shown in Figure 74. The resistor, capacitor,

diode clamp quickly dampens the voltage spike and provides

improved EMI performance, and the diode Zener diode clamp

can be used when the clamping level must be consistent and well

defined. The diode Zener diode clamp has slightly higher power

efficiency over the resistor, capacitor, diode clamp. However, the

cost of the diode Zener diode clamp solution is typically higher

than the resistor, capacitor, diode solution.

The ADP1032 requires the use of a transformer with a primary

to secondary turn ratio of 1:1 to start up properly.

Primary Inductance

The ADP1032 operates with a transformer with an inductance

in the 80 μH to 560 μH range. However, it is recommended to

choose an inductance value that results in the flyback regulator

output voltage (V_OUT1) divided by the transformer primary

inductance being less than or equal to 140,000 to maintain

control loop stability.

V

_OUT1/L_PRI≤ 140,000

Using a transformer at the lower end of the inductance range can

result in a smaller transformer but also reduces the output power

capabilities due to larger ac ripple current through the transformer.

Conversely, operating at higher inductance can result in higher

output power at the expense of a potentially larger transformer.

Tx1

1:1

D1

V

OUT1

INP

R

C

CLAMP

L

PRI

Flyback Transformer Saturation Current

L

LEAK

D

CLAMP

Do not exceed the saturation current of the transformer in

operation, or this may lead to much higher losses and overall

lower system efficiency. Choose a transformer with a saturation

current rating that is greater than the expected peak switch

current (I_SWP) across line and load conditions.

SWP

Figure 73. Resistor, Capacitor, Diode Clamp

Rev. 0 | Page 30 of 37

Data Sheet

ADP1032

Tx1

1:1

D1

V

OUT1

Clamping Capacitor

INP

The clamping capacitor (C_CLAMP) is used to minimize the voltage

ripple level (V_RIPPLE) superimposed in V_CLAMP. Calculate the

clamping capacitor by using the following equation for the

Z

CLAMP

L

PRI

desired V_RIPPLElevel and the calculated R_CLAMP

:

D

L

LEAK

C_CLAMP= V_CLAMP/(V_RIPPLE× f_SW× R_CLAMP)

where:

SWP

C_CLAMPis the value of the clamping capacitor.

V

_RIPPLEis the voltage ripple superimposed in V_CLAMP. A V_RIPPLEof

about 5% to 10% of V_CLAMPis reasonable.

Clamping Diode

Figure 74. Diode, Zener Diode Clamp

Schottky diodes are typically the best choice for clamping diodes.

However, fast recovery diodes can also be used. The diode reverse

voltage rating must be higher than the maximum SWP pin voltage

rating.

Clamping Resistor

To calculate the clamping resistor (R_CLAMP) value, the clamping

voltage (V_CLAMP) must be determined. The clamping voltage is

the voltage on which any voltage spike that occurs on the flyback

switch is clamped. Choose a V_CLAMPthat provides sufficient margin

between the SWP maximum voltage rating (SWP_VMAX) specified

in the Absolute Maximum Ratings section and that also is greater

than the summation of the maximum input supply (V_{INP (MAX)}

and the maximum flyback output voltage (V_{OUT1 (MAX)}) of the

application as given by

Diode, Zener Diode Clamp

A Zener diode can replace the resistor, capacitor (RC) network

on the resistor, capacitor, diode clamp when the clamping level

must be consistent and well defined. Choose the Zener diode

breakdown voltage to balance power loss and switch voltage

protection. Calculate the Zener voltage by using the following

equation:

)

SWP_VMAX> V_{INP (MAX)}+ V_CLAMP> V_{INP (MAX)}+ V_{OUT1 (MAX)}

SWP

V

_{ZENER (MAX)}≤ SWP_VMAX− V_{INP (MAX)}

VMAX

where V_{ZENER (MAX)}is the maximum Zener diode breakdown

voltage or the Zener voltage, which can be the same as the

V

+ V

INP (MAX)

OUT1 (MAX)

V

CLAMP

V

V_CLAMP

.

INP (MAX)

The power loss in the clamp determines the power requirement

for the Zener diode. Use the following equation to calculate the

Zener diode power dissipation:

Figure 75. Clamping Waveform

P

_ZENER= (V_ZENER× L_LEAK× I_PEAK²× f_SW)/(2 × (V_ZENER− V_OUT1))

where:

_ZENERis the Zener diode power dissipation. Choose a Zener

diode with power rating higher than the calculated value.

_ZENERis the Zener diode breakdown voltage or the Zener voltage.

Use the following equation to calculate the value of the clamping

resistor for a given V_CLAMPvalue:

P

R

_CLAMP= (2 × V_CLAMP× (V_CLAMP− V_OUT1))/(L_LEAK× I_PEAK²× f_SW)

where f_SWis the switching frequency of the flyback regulator.

V

To calculate the power dissipation across the snubber resistor,

use the following equation:

Ripple Current (I_AC) vs. Inductance

Calculate the ripple current by first determining the duty cycle

in continuous conduction mode.

P

_RCLAMP= (V_CLAMP)²/(R_CLAMP

where P_RCLAMPis the power dissipation across R_CLAMP. Choose

_CLAMPwith a power rating of about twice this value to have a

margin.

)

D

_CCM= (V_OUT1+ V_D)/(V_OUT1+ V_D+ V_INP)

R

where D_CCMis the duty cycle of the flyback switch.

Then, from the duty cycle, calculate the I_ACin the flyback switch

and transformer primary.

I_AC= (V_INP× D_CCM)/(f_SW× L_PRI)

where I_ACis the ripple current through the primary side of the

transformer and flyback switch.

Rev. 0 | Page 31 of 37

ADP1032

Data Sheet

Maximum Output Current Calculation

load using the worst case transformer inductance, efficiency,

diode forward voltage drop, and flyback switching frequency.

The maximum output power and current that can be achieved

from the flyback output depends on a number of variables within

the regulator. These variables include the transformer choice,

the operating frequency, and the rectifier diode choice. The

flyback regulator output is the supply to the buck regulator that

drives V_OUT2. Determine the maximum output power capability by

Calculate the maximum load current on V_OUT1by

I_{VOUT1 (MAX)}= P_{VOUT1 (MAX)}/V_OUT1

where I_{VOUT1 (MAX)}is the maximum output current from V_OUT1

.

BUCK REGULATOR COMPONENTS SELECTION

Inductor

P

_{VOUT1 (MAX)}= 0.5 × (I_PEAK²− (I_PEAK− I_AC/2)²) × L_PRI× f_SW× η

where:

_{VOUT1 (MAX)}is the maximum output power from V_OUT1

η is the expected efficiency of the flyback regulator.

The lower limit of the flyback current-limit threshold, I_{LIM (FLYBACK)}

The value of the inductor for the ADP1032 buck regulator

affects the efficiency and the output voltage ripple. Larger value

inductors typically improve efficiency. However, for a given

package size, as load increases, the dc resistance (DCR) and core

losses eventually have an increasing negative impact on efficiency.

Using a smaller value inductor reduces output voltage ripple but

can decrease the overall efficiency due to increased switching

losses.

P

.

,

limits the maximum I_PEAK. However, it is not recommended to

operate at this level to avoid unwanted current-limit events due to

variation in transformer inductance, efficiency, flyback switching

frequency, and rectifier diode forward voltage drop. If the load on

the flyback causes the current limit to trip, the output voltage may

not regulate as expected. It is recommended to choose a peak

operating current with a built-in margin for the variations

mentioned or to calculate the maximum output power or output

Output Capacitor

The output capacitor selection affects the output ripple voltage,

load step transient, and the loop stability of the regulator. A 4.7 µF

capacitor is recommended as a balance between performance and

size, but a larger capacitor reduces output ripple.

Table 17. Transformer Selection

Primary

Saturation

Current²

(mA)

Leakage

Inductance

(µH)

Isolation

Voltage³

(V rms)

Turns

Ratio¹

Inductance

(µH)

Resistance

(Ω)

Size, Length × Width

× Height, (mm)

Part Number

ZA9644-AE

Manufacturer

Coilcraft

1:1

470

1.8

490

480

3.8 maximum

2000

1500

10.92 × 9.25 × 10

750317986R6A

Würth Elektronik

1.27

3.5 typical,

10.8 × 13.35 × 9.76

7 maximum

750318257R6A

Würth Elektronik

1:1

470

1.56

550

1.0 typical,

2.0 maximum

1500

16 × 16.8 × 7.62

ZA9384-AL

Coilcraft

1:1

470

1.1

800

470

4.0

2000

1500

15.3 × 16.5 × 6.7

750318377R6A

Würth Elektronik

1.42

0.8 typical,

17.78 × 22.35 × 8.89

1.6 maximum

751318463R6A

Würth Elektronik

1:1

470

1.22

450

0.5 typical,

1.0 maximum

Functional

isolation

10.8 × 13.35 × 9.76

¹Turns ratio between the primary and secondary coils.

²20% drop from initial.

³1 minute duration. Basic insulation.

Table 18. Buck Regulator Recommended Inductors

Size, Length ×

Part Number

Manufacturer

Inductance (µH)

DC Resistance (Ω)

Saturation Current¹(mA)

Width × Height, (mm)

4.8 × 4.8 × 2.8

3.2 × 3.2 × 1.3

3 × 3 × 1.4

3 × 3 × 1.5

2.8 × 2.8 × 1.65

2 × 2 × 0.6

744043101

Würth Elektronik 100

0.55

2.63

1.59

2.92

4.9

290

280

260

270

150

115

XFL3012-104MEB

LQH3NPN101MMEL

SRN3015-101M

SRU2016-101Y

XFL2006-104MEB

Coilcraft

Murata

Bourns

Coilcraft

100

11.1

¹30% drop in inductance.

Rev. 0 | Page 32 of 37

Data Sheet

ADP1032

2

V_RMS= V_{AC RMS}²+V_DC

INSULATION LIFETIME

(1)

All insulation structures eventually break down when subjected to

voltage stress over a sufficiently long period. The rate of insulation

degradation is dependent on the characteristics of the voltage

waveform applied across the insulation as well as on the materials

and material interfaces.

or

2

V_{AC RMS}= V_RMS²−V_DC

(2)

where:

V

_{AC RMS}is the time varying portion of the working voltage.

_RMSis the total rms working voltage.

_DCis the dc offset of the working voltage.

The two types of insulation degradation of primary interest are

breakdown along surfaces exposed to the air, and insulation wear

out. Surface breakdown is the phenomenon of surface tracking

and the primary determinant of surface creepage requirements

in system-level standards. Insulation wear out is the phenomenon

where charge injection or displacement currents inside the

insulation material cause long-term insulation degradation.

Calculation and Use of Parameters Example

The following example frequently arises in power conversion

applications. Assume that the line voltage on one side of the

isolation is 240 V ac rms and a 400 V dc bus voltage is present

on the other side of the isolation barrier. The isolator material is

polyimide. To establish the critical voltages in determining the

creepage, clearance and lifetime of a device, see Figure 76 and

the following equations.

Surface Tracking

Surface tracking is addressed in electrical safety standards by

setting a minimum surface creepage based on the working voltage,

the environmental conditions, and the properties of the insulation

material. Safety agencies perform characterization testing on the

surface insulation of components that allows the components to be

categorized in different material groups. Lower material group

ratings are more resistant to surface tracking and, therefore, can

provide adequate lifetime with smaller creepage. The minimum

creepage for a given working voltage and material group is in

each system level standard and is based on the total rms voltage

across the isolation, pollution degree, and material group. The

material group and creepage for the ADP1032 isolators are

shown in Table 5.

V

AC RMS

V

DC

PEAK

RMS

TIME

Insulation Wear Out

Figure 76. Critical Voltage Example

The lifetime of insulation caused by wear out is determined by

its thickness, material properties, and the voltage stress applied.

It is important to verify that the product lifetime is adequate at

the application working voltage. The working voltage supported

by an isolator for wear out may not be the same as the working

voltage supported for tracking. The working voltage applicable

to tracking is specified in most standards.

The working voltage across the barrier from Equation 1 is

2

V_RMS= V_{AC RMS}²+V_DC

V_RMS= 240²+ 400²

V

_RMS= 466 V

Testing and modeling have shown that the primary driver of

long-term degradation is displacement current in the polyimide

insulation causing incremental damage. The stress on the insul-

ation can be broken down into broad categories, such as dc stress,

which causes very little wear out because there is no displacement

current, and an ac component time varying voltage stress, which

causes wear out.

This V_RMSvalue is the working voltage used together with the

material group and pollution degree when looking up the creepage

required by a system standard.

To determine if the lifetime is adequate, obtain the time varying

portion of the working voltage. To obtain the ac rms voltage,

use Equation 2.

2

V_{AC RMS}= V_RMS²−V_DC

The ratings in certification documents are usually based on

60 Hz sinusoidal stress because this reflects isolation from line

voltage. However, many practical applications have combinations

of 60 Hz ac and dc across the barrier as shown in Equation 1.

Because only the ac portion of the stress causes wear out, the

equation can be rearranged to solve for the ac rms voltage, as is

shown in Equation 2. For insulation wear out with the polyimide

materials used in these products, the ac rms voltage determines

the product lifetime.

V_{AC RMS}

_{AC RMS}= 240 V rms

=

466²− 400²

V

Rev. 0 | Page 33 of 37

ADP1032

Data Sheet

In this case, the ac rms voltage is simply the line voltage of

240 V rms. This calculation is more relevant when the waveform is

not sinusoidal. The value is compared to the limits for working

voltage in Table 9 for the expected lifetime, which is less than a

60 Hz sine wave, and it is well within the limit for a 20-year

service life.

reflected in the θ_JAvalues from Table 8. The value of θ_JAis based

on measurements taken with the devices mounted on a JEDEC

standard, 4-layer board with fine width traces and still air. Under

normal operating conditions, the ADP1032 operates at a full

load across the full temperature range without derating the output

current. However, following the recommendations in the PCB

Layout Considerations section decreases thermal resistance to

the PCB, allowing increased thermal margins in high ambient

temperatures. Each switching regulator in the ADP1032 has a

thermal shutdown circuit that turns off the dc-to-dc converter

and the outputs when a die temperature of approximately 150°C is

reached. When the die cools below approximately 135°C, the

ADP1032 dc-to-dc converter outputs turn on again.

The dc working voltage limit is set by the creepage of the

package as specified in IEC 60664-1. This value can differ for

specific system level standards.

THERMAL ANALYSIS

For the purpose of thermal analysis, the ADP1032 die are

treated as a thermal unit, with the highest junction temperature

Rev. 0 | Page 34 of 37

Data Sheet

ADP1032

TYPICAL APPLICATION CIRCUIT

Figure 77 shows the typical application circuit.

7 0 9 3 - 0 2 3 6

SENSOR

4 0 M 5 C 0 u D A

Figure 77. Typical Application Circuit

Rev. 0 | Page 35 of 37

ADP1032

Data Sheet

PCB LAYOUT CONSIDERATIONS

To achieve optimum efficiency, proper regulation, strong

stability, and low noise, a well-designed PCB layout is required.

Follow these guidelines when designing PCBs:



Place the SVDD1 decoupling capacitor (C3) as close

to the SVDD1 pin (Pin 10) and the SGND1 pin

(Pin 5) as possible.

Place the SVDD2 decoupling capacitor (C7) as close to

the SVDD2 pin (Pin 20) and the SGND2 pin (Pin 16) as

possible.



Keep the input bypass capacitor (C_IN) close to the VINP pin

and the PGNDP pin.



Keep the high current switching paths as short as possible.

These paths include the connections between the following:

Figure 78 shows a suggested top layer layout for the ADP1032



C_IN, the VINP pin, the primary winding of the

transformer, and the PGNDP pin

The VOUT1 pin, C_FLYBK, Diode 1 (D1), the secondary

winding of the transformer, and the SGND2 pin

The VOUT2 pin, the SW2 pin, Inductance 1 (L1),

to minimize EMI.

22mm

C6 OR D3

R7

SGND

T1

C_BUCK, and the SGND2 pin

D2

D1

V_OUT1

C_{FLY BK}



Keep high current traces as short and wide as possible to

minimize parasitic series inductance, which causes spiking

and EMI.

Avoid routing high impedance traces near any node

connected to the SWP pin and SW2 pin or near the L1

inductor or the T1 transformer to prevent radiated

switching noise injection.

V

INP

R10

R9

PGNDP

C7

C_IN

U1

L1

V_OUT2

SGND

MVDD

MGND

C1

C_BUCK

C3

Figure 78. Suggested Top Layer Layout



Place the feedback resistors as close to the FB1 pin as

possible to prevent high frequency switching noise injection.

To minimize EMI, perform the following actions:



Place the MVDD decoupling capacitor (C1) as close to

the MVDD pin (Pin 39) and the MGND pin (Pin 3) as

possible.

Rev. 0 | Page 36 of 37

Data Sheet

ADP1032

OUTLINE DIMENSIONS

9.10

9.00

8.90

2.15

MIN

1.72

1.62

1.52

3.88

3.78

3.68

0.35

0.30

0.25

PIN 1

INDICATOR

AREA

31

41

1

0.50

BSC

30

1.46

1.36

1.26

*

EXPOSED

PA D

EXPOSED

PA D

7.10

7.00

6.90

2.15

MIN

2.14

2.04

1.94

2.75

BSC

*

EXPOSED

PA D

24

7

23

8

0.45

0.40

TOP VIEW

SIDE VIEW

BOTTOM VIEW

0.435

0.385

3.75

BSC

7.70

7.60

7.50

0.35

(Pins 8-41)

1.00

0.95

0.90

0.335

(Pins 1-7)

0.05 MAX

0.02 NOM

*

COPLANARITY

0.08

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

0.30

0.25

0.20

SEATING

PLANE

0.203 REF

SECTION OF THIS DATA SHEET.

Figure 79. 41-Lead Lead Frame Chip Scale Package [LFCSP]

9 mm × 7 mm Body and 0.95 mm Package Height

(CP-41-1)

Dimensions shown in millimeters

ORDERING GUIDE

Model¹

V_OUT1

V_OUT2

Temperature Range Package Description

Package Option

2

ADP1032ACPZ-1-R7

ADP1032ACPZ-2-R7

ADP1032ACPZ-3-R7

ADP1032ACPZ-4-R7

ADP1032ACPZ-5-R7

ADP1032CP-1-EVALZ Adjustable 5.15 V

ADP1032CP-2-EVALZ Adjustable 5 V

ADP1032CP-3-EVALZ Adjustable 3.3 V

Adjustable 5.15 V

Adjustable 5 V

Adjustable 3.3 V

−40°C to +125°C

41-Lead Lead Frame Chip Scale Package [LFCSP] CP-41-1

Evaluation Board for the ADP1032ACPZ-1

24 V

5 V

3.3 V

Evaluation Board for the ADP1032ACPZ-2

Evaluation Board for the ADP1032ACPZ-3

ADP1032CP-4-EVALZ 24 V

ADP1032CP-5-EVALZ 24 V

5 V

3.3 V

Evaluation Board for the ADP1032ACPZ-4

Evaluation Board for the ADP1032ACPZ-5

¹Z = RoHS Compliant Part.

²For other V_OUT1voltage options, contact an Analog Devices local sales representatives for additional information.

registered trademarks are the property of their respective owners.

D20363-0-1/20(0)

Rev. 0 | Page 37 of 37


型号：	ADP1032ACPZ-2-R7
厂家：	ADI
描述：	Two-Channel, Isolated Micropower Management Unit with Seven Digital Isolators
文件：	总37页 (文件大小：1345K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADP1032ACPZ-2-R7 [ADI]

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