ADP160AUJZ-2.5-R7_技术文档

Ultralow Quiescent Current,

150 mA, CMOS Linear Regulator

ADP160/ADP161

FEATURES

TYPICAL APPLICATION CIRCUITS

ADP160

Ultralow quiescent current

V

= 2.3V

1µF

V

= 1.8V

IN

OUT

I

_Q= 560 nA with 0 μA load

_Q= 860 nA with 1 μA load

5

1

2

3

VIN

GND

EN

VOUT

1µF

Stable with 1 μF ceramic input and output capacitors

Maximum output current: 150 mA

Input voltage range: 2.2 V to 5.5 V

Low shutdown current: <50 nA typical

Low dropout voltage: 195 mV @ 150 mA load

Initial accuracy: 1ꢀ

Accuracy over line, load, and temperature: 3.5ꢀ

15 fixed output voltage options: 1.2 V to 4.2 V

Adjustable output available

ON

4

NC

OFF

NC = NO CONNECT

Figure 1. 5-Lead TSOT ADP160 with Fixed Output Voltage, 1.8 V

ADP161

V

= 4.2V

1µF

V

= 3.2V

1µF

IN

OUT

5

4

1

2

3

VIN

GND

EN

VOUT

R1

R2

ON

ADJ

PSRR performance of 72 dB @ 100 Hz

Current limit and thermal overload protection

Logic-control enable

OFF

Figure 2. 5-Lead TSOT ADP161 with Adjustable Output Voltage, 3.2 V

Integrated output discharge resistor

5-lead TSOT package

ADP160

1

2

V

= 2.8V

4-ball, 0.5 mm pitch WLCSP

V

= 3.3V

1µF

OUT

IN

VIN

VOUT

A

B

1µF

TOP VIEW

(Not to Scale)

APPLICATIONS

ON

EN

GND

OFF

Mobile phones

Digital cameras and audio devices

Portable and battery-powered equipment

Post dc-to-dc regulation

Figure 3. 4-Ball WLCSP ADP160 with Fixed Output Voltage, 2.8 V

Portable medical devices

GENERAL DESCRIPTION

The ADP160/ADP161 are ultralow quiescent current, low

dropout, linear regulators that operate from 2.2 V to 5.5 V and

provide up to 150 mA of output current. The low 195 mV dropout

voltage at 150 mA load improves efficiency and allows operation

over a wide input voltage range.

The ADP160 is available in 15 fixed output voltage options,

ranging from 1.2 V to 4.2 V. The ADP160/ADP161 also include

a switched resistor to discharge the output automatically when

the LDO is disabled.

The ADP161 is available as an adjustable output voltage regulator.

It is only available in a 5-lead TSOT package.

The ADP160/ADP161 are specifically designed for stable operation

with tiny 1 μF ꢀ0ꢁ ceramic input and output capacitors to

meet the requirements of high performance, space-constrained

applications.

Short-circuit and thermal overload protection circuits prevent

damage in adverse conditions. The ADP160 is available in a tiny

5-lead TSOT and a 4-ball, 0.5 mm pitch WLCSP package for the

smallest footprint solution to meet a variety of portable power

applications.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registeredtrademarks arethe property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113

www.analog.com

ADP160/ADP161

TABLE OF CONTENTS

Features .............................................................................................. 1

Typical Performance Characteristics ..............................................8

Theory of Operation ...................................................................... 12

Applications Information.............................................................. 1ꢀ

Capacitor Selection .................................................................... 1ꢀ

Enable Feature ............................................................................ 14

Current Limit and Thermal Overload Protection ................. 14

Thermal Considerations............................................................ 15

PCB Layout Considerations...................................................... 17

Outline Dimensions....................................................................... 19

Ordering Guide .......................................................................... 20

Applications....................................................................................... 1

Typical Application Circuits............................................................ 1

General Description......................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... ꢀ

Input and Output Capacitor, Recommended Specifications.. 4

Absolute Maximum Ratings............................................................ 5

Thermal Data................................................................................ 5

Thermal Resistance ...................................................................... 5

ESD Caution.................................................................................. 5

Pin Configurations and Function Descriptions ........................... 6

REVISION HISTORY

6/10—Revision 0: Initial Version

Rev. 0 | Page 2 of 20

ADP160/ADP161

SPECIFICATIONS

V_IN= (V_OUT+ 0.5 V) or 2.2 V, whichever is greater; EN = V_IN, I_OUT= 10 mA, C_IN= C_OUT= 1 μF, T_A= 25°C, unless otherwise noted.

Table 1.

Parameter

Symbol

V_IN

Conditions

Min Typ

2.2

Max

Unit

INPUT VOLTAGE RANGE

OPERATING SUPPLY CURRENT

T_J= −40°C to +125°C

I_OUT= 0 μA

I_OUT= 0 μA, T_J= −40°C to +125°C

I_OUT= 1 μA

I_OUT= 1 μA, T_J= −40°C to +125°C

I_OUT= 100 μA

I_OUT= 100 μA, T_J= −40°C to +125°C

I_OUT= 10 mA

I_OUT= 10 mA, T_J= −40°C to +125°C

I_OUT= 150 mA

I_OUT= 150 mA, T_J= −40°C to +125°C

EN = GND

5.5

V

I_GND

560

1250 nA

2.3 μA

1800 nA

2.8

4.5

5.8

860

2.6

11

μA

nA

μA

19

65

1

42

SHUTDOWN CURRENT

I_GND-SD

50

EN = GND, T_J= −40°C to +125°C

OUTPUT VOLTAGE ACCURACY

V_OUT

I_OUT= 10 mA

0 μA < I_OUT< 150 mA, V_IN= (V_OUT+ 0.5 V) to 5.5 V

0 μA < I_OUT< 150 mA, V_IN= (V_OUT+ 0.5 V) to 5.5 V,

T_J= −40°C to +125°C

−1

−2

−3.5

+1

+2

+3.5

%

ADJUSTABLE-OUTPUT VOLTAGE

ACCURACY (ADP161)¹

V_ADJ

I_OUT= 10 mA

0.99 1.0

1.01

V

0 μA < I_OUT< 150 mA, V_IN= (V_OUT+ 0.5 V) to 5.5 V

0 μA < I_OUT< 150 mA, V_IN= (V_OUT+ 0.5 V) to 5.5 V,

T_J= −40°C to +125°C

0.98

0.97

1.02

1.03

V

REGULATION

Line Regulation

Load Regulation²

∆V_OUT/∆V_IN

V_IN= (V_OUT+ 0.5 V) to 5.5 V, T_J= −40°C to +125°C

−0.1

+0.1

0.01

%/V

%/mA

∆V_OUT/∆I_OUTI_OUT= 100 ꢀA to 150 mA

I_OUT= 100 ꢀA to 150 mA, T_J= −40°C to +125°C

0.004

DROPOUT VOLTAGE³

4-Ball WLCSP

V_OUT= 3.3 V

I_OUT= 10 mA

I_OUT= 10 mA, T_J= −40°C to +125°C

I_OUT= 150 mA

I_OUT= 150 mA, T_J= −40°C to +125°C

I_OUT= 10 mA

I_OUT= 10 mA, T_J= −40°C to +125°C

I_OUT= 150 mA

I_OUT= 150 mA, T_J= −40°C to +125°C

2.2 V ≤ V_IN≤ 5.5 V, ADJ connected to VOUT

V_OUT= 2.8 V, R_LOAD= ∞, ADP160 only

V_OUT= 3.3 V

V_DROPOUT

7

mV

nA

13

105

8

195

15

5-Lead TSOT

120

225

600

500

ADJ INPUT BIAS CURRENT (ADP161)

ACTIVE PULL-DOWN RESISTANCE

START-UP TIME⁴

ADJ_I-BIAS

T_SHUTDOWN

T_START-UP

I_LIMIT

10

300

1100

320

Ω

μs

CURRENT LIMIT THRESHOLD⁵

220

1.2

mA

THERMAL SHUTDOWN

Thermal Shutdown Threshold

Thermal Shutdown Hysteresis

TS_SD

T_Jrising

150

15

°C

TS_SD-HYS

EN INPUT

En Input Logic High

EN Input Logic Low

EN Input Leakage Current

V_IH

V_IL

V_I-LEAKAGE

2.2 V ≤ V_IN≤ 5.5 V

EN = V_INor GND

EN = V_INor GND, T_J= −40°C to +125°C

V

μA

0.4

1

0.1

Rev. 0 | Page 3 of 20

ADP160/ADP161

Parameter

Symbol

UVLO

UVLO_RISE

UVLO_FALL

UVLO_HYS

OUT_NOISE

Conditions

Min Typ

Max

Unit

UNDERVOLTAGE LOCKOUT

Input Voltage Rising

Input Voltage Falling

Hysteresis

2.19

V

1.60

100

105

100

80

mV

μV rms

dB

OUTPUT NOISE

10 Hz to 100 kHz, V_IN= 5 V, V_OUT= 3.3 V

10 Hz to 100 kHz, V_IN= 5 V, V_OUT= 2.5 V

10 Hz to 100 kHz, V_IN= 5 V, V_OUT= 1.2 V

100 Hz, V_IN= 5 V, V_OUT= 3.3 V

POWER SUPPLY REJECTION RATIO

PSRR

60

100 Hz, V_IN= 5 V, V_OUT= 2.5 V

65

dB

100 Hz, V_IN= 5 V, V_OUT= 1.2 V

72

dB

1 kHz, V_IN= 5 V, V_OUT= 3.3 V

50

dB

1 kHz, V_IN= 5 V, V_OUT= 2.5 V

50

dB

1 kHz, V_IN= 5 V, V_OUT= 1.2 V

62

dB

¹Accuracy when VOUT is connected directly to ADJ. When the VOUT voltage is set by external feedback resistors, the absolute accuracy in adjust mode depends on the

tolerances of resistors used.

²Based on an end-point calculation using 0 ꢀA and 150 mA loads.

³Dropout voltage is defined as the input-to-output voltage differential when the input voltage is set to the nominal output voltage. This applies only for output

voltages above 2.2 V.

⁴Start-up time is defined as the time between the rising edge of EN to V_OUTbeing at 90% of its nominal value.

⁵Current limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 3.0 V

output voltage is defined as the current that causes the output voltage to drop to 90% of 3.0 V or 2.7 V.

INPUT AND OUTPUT CAPACITOR, RECOMMENDED SPECIFICATIONS

Table 2.

Parameter

Symbol

C_MIN

Conditions

Min

0.7

Typ

Max

Unit

μF

MINIMUM INPUT AND OUTPUT CAPACITANCE¹

T_A= −40°C to +125°C

CAPACITOR ESR

R_ESR

0.001

0.2

Ω

¹The minimum input and output capacitance should be greater than 0.7 μF over the full range of operating conditions. The full range of operating conditions in the

application must be considered during device selection to ensure that the minimum capacitance specification is met. X7R and X5R type capacitors are recommended;

however, Y5V and Z5U capacitors are not recommended for use with any LDO.

Rev. 0 | Page 4 of 20

ADP160/ADP161

ABSOLUTE MAXIMUM RATINGS

Table 3.

Junction-to-ambient thermal resistance (θ_JA) of the package is

based on modeling and calculation using a 4-layer board. The

junction-to-ambient thermal resistance is highly dependent on the

application and board layout. In applications where high maximum

power dissipation exists, close attention to thermal board design

is required. The value of θ_JAmay vary, depending on PCB material,

layout, and environmental conditions. The specified values of

θ_JAare based on a 4-layer, 4 inches × ꢀ inches, circuit board. Refer

to JESD 51-7 and JESD 51-9 for detailed information on the

board construction. For additional information, see Application

Note AN-617, MicroCSP™ Wafer Level Chip Scale Package.

Parameter

Rating

VIN to GND

VOUT to GND

−0.3 V to +6.5 V

−0.3 V to VIN

EN to GND

−0.3 V to VIN

Storage Temperature Range

Operating Junction Temperature Range

Operating Ambient Temperature Range

Soldering Conditions

−65°C to +150°C

−40°C to +125°C

JEDEC J-STD-020

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

Ψ

_JBis the junction to board thermal characterization parameter

with units of °C/W. Ψ_JBof the package is based on modeling and

calculation using a 4-layer board. The JESD51-12, Guidelines for

Reporting and Using Electronic Package Thermal Information,

states that thermal characterization parameters are not the same

as thermal resistances. Ψ_JBmeasures the component power flowing

through multiple thermal paths rather than a single path as in

thermal resistance, θ_JB. Therefore, Ψ_JBthermal paths include

convection from the top of the package as well as radiation from

the package, factors that make Ψ_JBmore useful in real-world

applications. Maximum junction temperature (T_J) is calculated

from the board temperature (T_B) and power dissipation (P_D)

using the formula

THERMAL DATA

Absolute maximum ratings only apply individually; they do not

apply in combination. The ADP160/ADP161 can be damaged

when the junction temperature limits are exceeded. Monitoring

ambient temperature does not guarantee that T_Jis within the

specified temperature limits. In applications with high power

dissipation and poor thermal resistance, the maximum ambient

temperature may have to be derated.

T_J= T_B+ (P_D× Ψ_JB)

Refer to JESD51-8 and JESD51-12 for more detailed information

about Ψ_JB.

In applications with moderate power dissipation and low PCB

thermal resistance, the maximum ambient temperature can

exceed the maximum limit as long as the junction temperature

is within specification limits. The junction temperature (T_J) of

the device is dependent on the ambient temperature (T_A), the

power dissipation of the device (P_D), and the junction to ambient

thermal resistance of the package (θ_JA).

THERMAL RESISTANCE

θ_JAand Ψ_JBare specified for the worst-case conditions, that is, a

device soldered in a circuit board for surface-mount packages.

Table 4. Thermal Resistance

Package Type

θ_JA

Ψ_JB

43

58

Unit

°C/W

Maximum junction temperature (T_J) is calculated from the ambient

temperature (T_A) and power dissipation (P_D) using the formula

5-Lead TSOT

4-Ball, 0.4 mm Pitch WLCSP

170

260

T_J= T_A+ (P_D× θ_JA)

ESD CAUTION

Rev. 0 | Page 5 of 20

ADP160/ADP161

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

5

VIN

GND

EN

1

2

3

VOUT

ADP160

TOP VIEW

(Not to Scale)

4

NC

NC = NO CONNECT

Figure 4. 5-Lead TSOT, Fixed Output Pin Configuration, ADP160

Table 5. 5-Lead TSOT Pin Function Descriptions, ADP160

Pin No.

Mnemonic

Description

1

2

3

VIN

GND

EN

Regulator Input Supply. Bypass VIN to GND with a 1 μF or greater capacitor.

Ground.

Enable Input. Drive EN high to turn on the regulator; drive EN low to turn off the regulator. For automatic startup,

connect EN to VIN.

4

5

NC

VOUT

No Connect. This pin is not connected internally.

Regulated Output Voltage. Bypass VOUT to GND with a 1 μF or greater capacitor.

5

VIN

GND

EN

1

2

3

VOUT

ADP161

TOP VIEW

(Not to Scale)

4

ADJ

Figure 5. 5-Lead TSOT, Adjustable Output Pin Configuration, ADP161

Table 6. 5-Lead TSOT Pin Function Descriptions, ADP161

Pin No.

Mnemonic

Description

1

2

3

VIN

GND

EN

Regulator Input Supply. Bypass VIN to GND with a 1 μF or greater capacitor.

Ground.

Enable Input. Drive EN high to turn on the regulator; drive EN low to turn off the regulator. For automatic startup,

connect EN to VIN.

4

5

ADJ

Output Voltage Adjust Pin. Connect the midpoint of the voltage divider between VOUT and GND to this pin to set

the output voltage.

Regulated Output Voltage. Bypass VOUT to GND with a 1 μF or greater capacitor.

VOUT

Rev. 0 | Page 6 of 20

ADP160/ADP161

1

2

A

B

VIN

VOUT

ADP160

EN

GND

TOP VIEW

(Not to Scale)

Figure 6. 4-Ball WLCSP Pin Configuration, ADP160

Table 7. 4-Ball WLCSP Pin Function Descriptions, ADP160

Pin No.

Mnemonic

Description

A1

B1

VIN

EN

Regulator Input Supply. Bypass VIN to GND with a 1 μF or greater capacitor.

Enable Input. Drive EN high to turn on the regulator; drive EN low to turn off the regulator. For automatic

startup, connect EN to VIN.

A2

B2

VOUT

GND

Regulated Output Voltage. Bypass VOUT to GND with a 1 μF or greater capacitor.

Ground.

Rev. 0 | Page 7 of 20

ADP160/ADP161

TYPICAL PERFORMANCE CHARACTERISTICS

V_IN= ꢀ.8 V, V_OUT= ꢀ.ꢀ V, I_OUT= 1 mA, C_IN= C_OUT= 1 μF, T_A= 25°C, unless otherwise noted.

3.35

3.34

3.33

3.32

3.31

3.30

3.29

3.28

3.27

3.26

3.25

100

10

1

LOAD = 1µA

LOAD = 100µA

LOAD = 1mA

LOAD = 10mA

LOAD = 100mA

LOAD = 150mA

LOAD = 10mA

LOAD = 100mA

LOAD = 150mA

NO LOAD

LOAD = 1µA

LOAD = 100µA

LOAD = 1mA

0.1

–40

–5

25

85

125

–40

–5

25

85

125

JUNCTION TEMPERATURE (°C)

Figure 7. Output Voltage (V_OUT) vs. Junction Temperature

Figure 10. Ground Current vs. Junction Temperature

100

10

1

3.35

3.34

3.33

3.32

3.31

3.30

3.29

3.28

3.27

3.26

3.25

0.1

0.001

0.01

0.1

1

10

100

1000

0.001

0.01

0.1

1

10

100

1000

I

(mA)

I

(mA)

LOAD

Figure 11. Ground Current vs. Load Current (I_LOAD

)

Figure 8. Output Voltage (V_OUT) vs. Load Current (I_LOAD

)

3.35

3.34

3.33

3.32

3.31

3.30

3.29

3.28

3.27

3.26

3.25

100

10

1

LOAD = 1µA

LOAD = 100µA

LOAD = 1mA

LOAD = 10mA

LOAD = 100mA

LOAD = 150mA

LOAD = 10mA

LOAD = 100mA

LOAD = 150mA

NO LOAD

LOAD = 1µA

LOAD = 100µA

LOAD = 1mA

0.1

3.7

3.9

4.1

4.3

4.5

V

4.7

(V)

4.9

5.1

5.3

5.5

3.9

4.1

4.3

4.5

V

4.7

(V)

4.9

5.1

5.3

5.5

IN

Figure 9. Output Voltage (V_OUT) vs. Input Voltage

Figure 12. Ground Current vs. Input Voltage (V_IN

)

Rev. 0 | Page 8 of 20

ADP160/ADP161

0.18

0.16

0.14

0.12

0.10

0.08

0.06

0.04

0.02

0

140

120

100

80

V

= 2.9V

= 3.2V

= 3.8V

= 4.1V

= 4.7V

= 5.5V

IN

60

40

I

= 1mA

= 5mA

= 10mA

= 50mA

= 100mA

= 150mA

GND

20

0

3.1

–40

–5

25

85

125

3.2

3.3

3.4

3.5

3.6

TEMPERATURE (°C)

V

(V)

IN

Figure 16. Ground Current vs. Input Voltage(V_IN) in Dropout

Figure 13. Shutdown Current vs. Temperature at Various Input Voltages

0

250

LOAD = 200mA

LOAD = 100mA

–10

V

= 2V

OUT

LOAD = 10mA

LOAD = 1mA

LOAD = 100µA

–20

–30

–40

–50

–60

–70

–80

–90

–100

200

150

100

50

V

= 3.3V

OUT

0

10

100

1k

10k

100k

1M

10M

1

10

100

1000

FREQUENCY (Hz)

LOAD CURRENT (mA)

Figure 17. Power Supply Rejection Ratio vs. Frequency, V_OUT= 1.2 V, V_IN= 2.2 V

Figure 14. Dropout Voltage vs. Load Current

0

3.35

3.30

3.25

3.20

3.15

3.10

3.05

3.00

LOAD = 200mA

LOAD = 100mA

LOAD = 10mA

LOAD = 1mA

–10

–20

LOAD = 100µA

–30

–40

–50

–60

–70

–80

–90

–100

V

= 1mA

= 5mA

= 10mA

= 50mA

= 100mA

= 250mA

DROP

10

100

1k

10k

100k

1M

10M

3.1

3.2

3.3

3.4

3.5

3.6

FREQUENCY (Hz)

V

(V)

IN

Figure 18. Power Supply Rejection Ratio vs. Frequency, V_OUT= 2.5 V, V_IN= 3.5 V

Figure 15. Output Voltage (V_OUT) vs. Input Voltage (in Dropout)

Rev. 0 | Page 9 of 20

ADP160/ADP161

0

1k

100

10

LOAD = 200mA

LOAD = 100mA

LOAD = 10mA

LOAD = 1mA

V

= 3.3V

= 2.5V

= 1.2V

OUT

–10

ADJ 3.3V

–20

LOAD = 100µA

–30

–40

–50

–60

–70

–80

–90

–100

1

10

100

1k

10k

100k

1M

10M

0.001

0.01

0.1

1

10

100

1000

FREQUENCY (Hz)

LOAD CURRENT (mA)

Figure 19. Power Supply Rejection Ratio vs. Frequency, V_OUT= 3.3 V, V_IN= 4.3 V

Figure 22. Output Noise vs. Load Current and Output Voltage,

V_IN= 5 V, C_OUT= 1 μF

0

10

LOAD = 3.3V/200mA

LOAD = 2.5V/200mA

LOAD = 1.2V/200mA

LOAD = 3.3V/1mA

V

= 1.2V

= 3.3V

= 2.5V

OUT

–10

–20

LOAD = 2.5V/1mA

LOAD = 1.2V/1mA

–30

–40

–50

–60

–70

–80

–90

–100

1

0.1

10

100

1k

10k

100k

1M

10M

100

1k

10k

100k

FREQUENCY (Hz)

Figure 20. Power Supply Rejection Ratio vs. Frequency

Figure 23. Output Noise Spectral Density, V_IN= 5 V, I_LOAD= 10 mA, C_OUT= 1 μF

Various Output Voltages and Load Currents, V_IN− V_OUT= 1 V

0

T

LOAD = 200mA

LOAD = 100mA

LOAD CURRENT

–10

LOAD = 10mA

LOAD = 1mA

LOAD = 100µA

–20

–30

–40

–50

–60

–70

–80

–90

–100

1

2

V

OUT

CH1 100mA Ω CH2 200mV

M200µs

A CH1

62mA

10

100

1k

10k

100k

1M

10M

T

10.40%

FREQUENCY (Hz)

Figure 24. Load Transient Response, C_IN, C_OUT= 1 μF, I_LOAD= 1 mA to 150 mA,

200 ns Rise Time, CH1 = Load Current, CH2 = V_OUT

Figure 21. Adjustable ADP161 Power Supply Rejection Ratio vs. Frequency,

V_OUT= 3.3 V, V_IN= 4.3 V

Rev. 0 | Page 10 of 20

ADP160/ADP161

T

LOAD CURRENT

V

IN

1

V

OUT

V

OUT

2

1

2

CH1 20mA Ω CH2 5mV

M200µs

A CH1

24mA

CH1 1V Ω

CH2 20mV

M200µs

A CH1

4.56V

T

10.40%

T 10.20%

Figure 25. Load Transient Response, C_IN, C_OUT= 1 ꢀF, I_LOAD= 1 mA to 50 mA,

200 ns Rise Time, CH1 = Load Current, CH2 = V_OUT

Figure 27. Line Transient Response, V_IN= 4 V to 5 V , C_IN, - 1ꢀF, C_OUT=10 ꢀF,

I_LOAD= 150 mA, CH1 = V_IN, CH2 = V_OUT

T

V

IN

V

OUT

2

1

CH1 1V Ω

CH2 20mV

M200µs

A CH1

4.34V

T

10.20%

Figure 26. Line Transient Response, V_IN= 4 V to 5 V, C_IN, C_OUT= 1 ꢀF,

I_LOAD= 150 mA, CH1 = V_IN, CH2 = V_OUT

Rev. 0 | Page 11 of 20

ADP160/ADP161

THEORY OF OPERATION

The ADP160/ADP161 are ultralow quiescent current, low dropout

linear regulators that operate from 2.2 V to 5.5 V and can provide

up to 150 mA of output current. Drawing only 560 nA (typical)

at no load and a low 42 μA of quiescent current (typical) at full

load makes the ADP160 ideal for battery-operated portable

equipment. Shutdown current consumption is typically 50 nA.

Internally, the ADP160 consists of a reference, an error amplifier,

a feedback voltage divider, and a PMOS pass transistor. Output

current is delivered via the PMOS pass device, which is controlled

by the error amplifier. The error amplifier compares the reference

voltage with the feedback voltage from the output and amplifies

the difference. If the feedback voltage is lower than the reference

voltage, the gate of the PMOS device is pulled lower, allowing

more current to pass and increasing the output voltage. If the

feedback voltage is higher than the reference voltage, the gate

of the PMOS device is pulled higher, allowing less current to pass

and decreasing the output voltage.

Using new innovative design techniques, the ADP160 provides

ultralow quiescent current and superior transient performance

for digital and RF applications. The ADP160 is also optimized

for use with small 1 μF ceramic capacitors.

VIN

VOUT

The adjustable ADP161 has an output voltage range of 1.0 V to

4.2 V. The output voltage is set by the ratio of two external resistors,

as shown in Figure 2. The device servos the output to maintain

the voltage at the ADJ pin at 1.0 V referenced to ground. The

current in R1 is then equal to 1.0 V/R2, and the current in R1 is

the current in R2 plus the ADJ pin bias current. The ADJ pin

bias current, 10 nA at 25°C, flows through R1 into the ADJ pin.

SHORT CIRCUIT,

UVLO, AND

THERMAL

GND

R1

R2

R3

PROTECT

EN

SHUTDOWN

REFERENCE

The output voltage can be calculated using the equation:

ADP160

Figure 28. Internal Block Diagram, Fixed Output with Output Discharge Function

V

_OUT= 1.0 V(1 + R1/R2) + (ADJ_I-BIAS)(R1)

The value of R1 should be less than 200 kΩ to minimize errors in

the output voltage caused by the ADJ pin bias current. For example,

when R1 and R2 each equal 200 kΩ, the output voltage is 2.0 V.

The output voltage error introduced by the ADJ pin bias current is

2 mV or 0.10ꢁ, assuming a typical ADJ pin bias current of

10 nA at 25°C.

VIN

VOUT

SHORT CIRCUIT,

UVLO, AND

THERMAL

GND

R1

PROTECT

Note that in shutdown, the output is turned off and the divider

current is zero.

ADJ

EN

SHUTDOWN

REFERENCE

The ADP160/ADP161 also include an output discharge resistor to

force the output voltage to zero when the LDO is disabled. This

ensures that the output of the LDO is always in a well-defined state,

whether it is enabled or not.

ADP161

Figure 29. Internal Block Diagram, Adjustable Output with

Output Discharge Function

The ADP160 is available in 15 output voltage options, ranging from

1.2 V to 4.2 V. The ADP160/ADP161 use the EN pin to enable

and disable the VOUT pin under normal operating conditions.

When EN is high, VOUT turns on, and when EN is low, VOUT

turns off. For automatic startup, EN can be tied to VIN.

Rev. 0 | Page 12 of 20

ADP160/ADP161

APPLICATIONS INFORMATION

CAPACITOR SELECTION

Input and Output Capacitor Properties

Any good quality ceramic capacitors can be used with the ADP160/

ADP161, as long as they meet the minimum capacitance and

maximum ESR requirements. Ceramic capacitors are manufactured

with a variety of dielectrics, each with different behavior over

temperature and applied voltage. Capacitors must have a dielectric

adequate to ensure the minimum capacitance over the necessary

temperature range and dc bias conditions. X5R or X7R dielectrics

with a voltage rating of 6.ꢀ V or 10 V are recommended. Y5V

and Z5U dielectrics are not recommended due to their poor

temperature and dc bias characteristics.

Output Capacitor

The ADP160/ADP161 are designed for operation with small,

space-saving ceramic capacitors, but functions with most

commonly used capacitors as long as care is with regard to the

effective series resistance (ESR) value. The ESR of the output

capacitor affects stability of the LDO control loop. A minimum

of 1 μF capacitance with an ESR of 1 ꢂ or less is recommended

to ensure stability of the ADP160/ADP161. Transient response

to changes in load current is also affected by output capacitance.

Using a larger value of output capacitance improves the transient

response of the ADP160/ADP161 to large changes in load current.

Figure ꢀ0 and Figure ꢀ1 show the transient responses for output

capacitance values of 1 μF and 10 μF, respectively.

Figure ꢀ2 depicts the capacitance vs. voltage bias characteristic

of a 0402, 1 μF, 10 V, X5R capacitor. The voltage stability of a

capacitor is strongly influenced by the capacitor size and voltage

rating. In general, a capacitor in a larger package or higher voltage

rating exhibits better stability. The temperature variation of the X5R

dielectric is about 15ꢁ over the −40°C to +85°C temperature

range and is not a function of package or voltage rating.

1.2

T

LOAD CURRENT

1

1.0

0.8

0.6

0.4

0.2

0

2

V

OUT

CH1 100mA Ω CH2 200mV

M200µs

T

A CH1

62mA

10.40%

Figure 30. Output Transient Response, C_OUT= 1 μF,

CH1 = Load Current, CH2 = V_OUT

T

0

2

4

6

8

10

LOAD CURRENT

VOLTAGE

Figure 32. Capacitance vs. Voltage Characteristic

1

Use Equation 1 to determine the worst-case capacitance accounting

for capacitor variation over temperature, component tolerance,

and voltage.

C_EFF= C_BIAS× (1 − TEMPCO) × (1 − TOL)

(1)

2

where:

V

OUT

C_BIASis the effective capacitance at the operating voltage.

TEMPCO is the worst-case capacitor temperature coefficient.

TOL is the worst-case component tolerance.

In this example, the worst-case temperature coefficient (TEMPCO)

over −40°C to +85°C is assumed to be 15ꢁ for an X5R dielectric.

The tolerance of the capacitor (TOL) is assumed to be 10ꢁ, and

CH1 100mA Ω CH2 200mV

M200µs

A CH1

74mA

T

10.00%

Figure 31. Output Transient Response, C_OUT= 10 μF,

CH1 = Load Current, CH2 = V_OUT

C

_BIASis 0.94 μF at 1.8 V, as shown in Figure ꢀ2.

Substituting these values in Equation 1 yields

_EFF= 0.94 ꢃF × (1 − 0.15) × (1 − 0.1) = 0.719 μF

Input Bypass Capacitor

Connecting a 1 μF capacitor from VIN to GND reduces the circuit

sensitivity to the printed circuit board (PCB) layout, especially

when long input traces or high source impedance are encountered.

If greater than 1 μF of output capacitance is required, the input

capacitor should be increased to match it.

C

Therefore, the capacitor chosen in this example meets

the minimum capacitance requirement of the LDO over

temperature and tolerance at the chosen output voltage.

Rev. 0 | Page 13 of 20

ADP160/ADP161

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

To guarantee the performance of the ADP160/ADP161, it is

imperative that the effects of dc bias, temperature, and tolerances

on the behavior of the capacitors are evaluated for each.

3.3V

2.5V

ENABLE FEATURE

The ADP160/ADP161 use the EN pin to enable and disable the

VOUT pin under normal operating conditions. As shown in

Figure ꢀꢀ, when a rising voltage on EN crosses the active threshold,

VOUT turns on. When a falling voltage on EN crosses the inactive

threshold, VOUT turns off.

EN

1.2V

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

500 1000 1500 2000 2500 3000 3500 4000 4500

TIME (µs)

Figure 35. Typical Start-Up Behavior

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

4.2V

EN

0.5

0.7

0.9

1.1

1.3

1.5

EN VOLTAGE (V)

Figure 33. Typical EN Pin Operation

1.2V

As shown in Figure ꢀꢀ, the EN pin has hysteresis built in. This

prevents on/off oscillations that can occur due to noise on the

EN pin as it passes through the threshold points.

0

200

400

600

TIME (µs)

800

1000

The EN pin active/inactive thresholds are derived from the VIN

voltage. Therefore, these thresholds vary with changing input

voltage. Figure ꢀ4 shows typical EN active/inactive thresholds

when the input voltage varies from 2.2 V to 5.5 V.

1.1

Figure 36. Typical Shutdown Behavior

CURRENT LIMIT AND THERMAL OVERLOAD

PROTECTION

The ADP160/ADP161 are protected against damage due to

excessive power dissipation by current and thermal overload

protection circuits. The ADP160/ADP161 are designed to

current limit when the output load reaches ꢀ20 mA (typical).

When the output load exceeds ꢀ20 mA, the output voltage is

reduced to maintain a constant current limit.

1.0

0.9

EN RISE

0.8

Thermal overload protection is included, which limits the junction

temperature to a maximum of 150°C (typical). Under extreme

conditions (that is, high ambient temperature and power dissipation),

when the junction temperature starts to rise above 150°C, the

output is turned off, reducing the output current to zero. When

the junction temperature drops below 1ꢀ5°C, the output is turned

on again and the output current is restored to its nominal value.

EN FALL

0.7

0.6

0.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

INPUT VOLTAGE (V)

Figure 34. Typical EN Pin Thresholds vs. Input Voltage

The start-up and shutdown behavior of the ADP160 is shown in

Figure ꢀ5 and Figure ꢀ6.

Rev. 0 | Page 14 of 20

ADP160/ADP161

Consider the case where a hard short from OUT to ground occurs.

At first, the ADP160/ADP161 current limits so that only ꢀ20 mA is

conducted into the short. If self-heating of the junction is great

enough to cause its temperature to rise above 150°C, thermal

shutdown activates, turning off the output and reducing the

output current to zero. As the junction temperature cools and

drops below 1ꢀ5°C, the output turns on and conducts ꢀ20 mA

into the short, again causing the junction temperature to rise

above 150°C. This thermal oscillation between 1ꢀ5°C and

150°C causes a current oscillation between ꢀ20 mA and 0 mA

that continues as long as the short remains at the output.

Table 9. Typical Ψ_JBValues

Ψ_JB(°C/W)

TSOT

WLCSP

42.8

58.4

The junction temperature of the ADP160/ADP161 can be

calculated from the following equation:

T_J= T_A+ (P_D× θ_JA)

(2)

(ꢀ)

where:

T_Ais the ambient temperature.

P_Dis the power dissipation in the die, given by

Current and thermal limit protections are intended to protect

the device against accidental overload conditions. For reliable

operation, device power dissipation must be externally limited

so junction temperatures do not exceed 125°C.

P_D= [(V_IN− V_OUT) × I_LOAD] + (V_IN× I_GND

)

where:

_LOADis the load current.

_GNDis the ground current.

I

V

THERMAL CONSIDERATIONS

_INand V_OUTare input and output voltages, respectively.

In most applications, the ADP160/ADP161 do not dissipate

much heat due to their high efficiency. However, in applications

with high ambient temperature and high supply voltage to output

voltage differential, the heat dissipated in the package is large

enough that it can cause the junction temperature of the die to

exceed the maximum junction temperature of 125°C.

Power dissipation due to ground current is quite small and can be

ignored. Therefore, the junction temperature equation simplifies to

the following:

T_J= T_A+ {[(V_IN− V_OUT) × I_LOAD] × θ_JA}

(4)

As shown in Equation 4, for a given ambient temperature, input-

to-output voltage differential, and continuous load current, there

exists a minimum copper size requirement for the PCB to ensure

the junction temperature does not rise above 125°C. Figure ꢀ7 to

Figure 44 show the junction temperature calculations for the

different ambient temperatures, load currents, V_IN-to-V_OUT

differentials, and areas of PCB copper.

When the junction temperature exceeds 150°C, the converter enters

thermal shutdown. It recovers only after the junction temperature

has decreased below 1ꢀ5°C to prevent any permanent damage.

Therefore, thermal analysis for the chosen application is very

important to guarantee reliable performance over all conditions.

The junction temperature of the die is the sum of the ambient

temperature of the environment and the temperature rise of the

package due to the power dissipation, as shown in Equation 2.

In the case where the board temperature is known, use the

thermal characterization parameter, Ψ_JB, to estimate the junction

temperature rise (see Figure 45 and Figure 46). Maximum junction

temperature (T_J) is calculated from the board temperature (T_B)

and power dissipation (P_D) using the following formula:

To guarantee reliable operation, the junction temperature of the

ADP160/ADP161 must not exceed 125°C. To ensure the junction

temperature stays below this maximum value, the user needs to

be aware of the parameters that contribute to junction temperature

changes. These parameters include ambient temperature, power

dissipation in the power device, and thermal resistances between

the junction and ambient air (θ_JA). The θ_JAnumber is dependent

on the package assembly compounds that are used and the amount

of copper used to solder the package GND pins to the PCB.

Table 8 shows the typical θ_JAvalues of the 5-lead TSOT and the

4-ball WLCSP for various PCB copper sizes. Table 9 shows the

typical Ψ_JBvalue of the 5-lead TSOT and 4-ball WLCSP.

T_J= T_B+ (P_D× Ψ_JB)

(5)

The typical value of Ψ_JBis 58°C/W for the 4-ball WLCSP package

and 4ꢀ°C/W for the 5-lead TSOT package.

140

MAXIMUM JUNCTION TEMPERATURE

120

100

80

Table 8. Typical θ_JAValues

60

θ_JA(°C/W)

Copper Size (mm²)

TSOT

170

152

146

134

131

WLCSP

260

159

157

153

40

0¹

20

I

= 1mA

= 10mA

= 50mA

I

= 100mA

= 150mA

= 200mA

LOAD

50

100

300

500

0

0.3

0.8

1.3

1.8

2.3

– V

2.8

(V)

3.3

3.8

4.3

4.8

V

IN

OUT

151

Figure 37. 500 mm²of PCB Copper, WLCSP, T_A= 25°C

¹Device soldered to minimum size pin traces.

Rev. 0 | Page 15 of 20

ADP160/ADP161

140

120

100

80

MAXIMUM JUNCTION TEMPERATURE

120

100

80

60

40

20

0

60

40

20

I

= 1mA

= 10mA

= 50mA

I

= 100mA

= 150mA

= 200mA

I

= 1mA

= 10mA

= 50mA

I

= 100mA

= 150mA

= 200mA

LOAD

0

0.3

0.8

1.3

1.8

2.3

– V

2.8

(V)

3.3

3.8

4.3

4.8

0.8

1.3

1.8

2.3

– V

2.8

(V)

3.3

3.8

4.3

4.8

V

IN

OUT

IN

OUT

Figure 38. 100 mm²of PCB Copper, WLCSP, T_A= 50°C

Figure 41. 500 mm²of PCB Copper, TSOT, T_A= 25°C

140

120

100

80

140

120

100

80

MAXIMUM JUNCTION TEMPERATURE

60

40

20

I

= 1mA

= 10mA

= 50mA

I

= 100mA

= 150mA

= 200mA

I

= 1mA

= 10mA

= 50mA

I

= 100mA

= 150mA

= 200mA

LOAD

0

0.3

0.8

1.3

1.8

2.3

– V

2.8

(V)

3.3

3.8

4.3

0.8

1.3

1.8

2.3

– V

2.8

(V)

3.3

3.8

4.3

V

IN

OUT

IN

OUT

Figure 39. 500 mm²of PCB Copper, WLCSP, T_A= 85°C

Figure 42. 100 mm²of PCB Copper, TSOT, T_A= 25°C

140

120

100

80

140

120

100

80

MAXIMUM JUNCTION TEMPERATURE

60

40

20

I

= 1mA

= 10mA

= 50mA

I

= 100mA

= 150mA

= 200mA

I

= 1mA

= 10mA

= 50mA

I

= 100mA

= 150mA

= 200mA

LOAD

0

0.3

0.8

1.3

1.8

2.3

– V

2.8

(V)

3.3

3.8

4.3

0.8

1.3

1.8

2.3

– V

2.8

(V)

3.3

3.8

4.3

V

IN

OUT

IN

OUT

Figure 40. 100 mm²of PCB Copper,WLCSP, T_A= 50°C

Figure 43. 500 mm²of PCB Copper, TSOT, T_A= 50°C

Rev. 0 | Page 16 of 20

ADP160/ADP161

140

120

100

80

140

120

100

80

MAXIMUM JUNCTION TEMPERATURE

60

40

20

I

= 1mA

= 10mA

= 50mA

I

= 100mA

= 150mA

= 200mA

I

= 1mA

= 10mA

= 50mA

I

= 100mA

= 150mA

= 200mA

LOAD

0

0.3

0

0.3

0.8

1.3

1.8

2.3

– V

2.8

(V)

3.3

3.8

4.3

4.8

0.8

1.3

1.8

2.3

– V

2.8

(V)

3.3

3.8

4.3

4.8

V

IN

OUT

IN

OUT

Figure 44. 100 mm²of PCB Copper, TSOT, T_A= 50°C

Figure 46. TSOT, T_A= 85°C

140

120

100

80

PCB LAYOUT CONSIDERATIONS

MAXIMUM JUNCTION TEMPERATURE

Heat dissipation from the package can be improved by increasing

the amount of copper attached to the pins of the ADP160/ADP161.

However, as listed in Table 8, a point of diminishing returns is

reached eventually, beyond which an increase in the copper size

does not yield significant heat dissipation benefits.

60

Place the input capacitor as close as possible to the VIN and

GND pins. Place the output capacitor as close as possible to the

VOUT and GND pins. Use of 0402 or 060ꢀ size capacitors and

resistors achieves the smallest possible footprint solution on

boards where area is limited.

40

20

I

= 1mA

= 10mA

= 50mA

I

= 100mA

= 150mA

= 200mA

LOAD

0

0.3

0.8

1.3

1.8

2.3

– V

2.8

(V)

3.3

3.8

4.3

4.8

V

IN

OUT

Figure 45. WLCSP, T_A= 85°C

Rev. 0 | Page 17 of 20

ADP160/ADP161

Figure 47. Example of 5-Lead TSOT PCB Layout

Figure 48. Example of 4-Ball WLCSP PCB Layout

Rev. 0 | Page 18 of 20

ADP160/ADP161

OUTLINE DIMENSIONS

2.90 BSC

5

1

4

3

2.80 BSC

1.60 BSC

2

0.95 BSC

1.90

BSC

*

0.90 MAX

0.70 MIN

*

1.00 MAX

0.20

0.08

8°

4°

0°

0.10 MAX

0.50

0.30

0.60

0.45

0.30

SEATING

PLANE

*

COMPLIANT TO JEDEC STANDARDS MO-193-AB WITH

THE EXCEPTION OF PACKAGE HEIGHT AND THICKNESS.

Figure 49. 5-Lead Thin Small Outline Transistor Package [TSOT]

(UJ-5)

Dimensions shown in millimeters

0.640

0.595

0.550

1.000

0.965 SQ

0.925

0.370

0.355

0.340

SEATING

PLANE

2

1

A

B

BALL A1

IDENTIFIER

0.340

0.320

0.300

0.50

BALL PITCH

TOP VIEW

(BALL SIDE DOWN)

BOTTOM VIEW

(BALL SIDE UP)

0.270

0.240

0.210

0.030 NOM

COPLANARITY

Figure 50.4-Ball Wafer Level Chip Scale Package [WLCSP]

(CB-4-1)

Dimensions shown in millimeters

Rev. 0 | Page 19 of 20

ADP160/ADP161

ORDERING GUIDE

Model¹

Temperature Range

−40°C to +125°C

Output Voltage (V)

Package Description

4-Ball WLCSP

5-Lead TSOT

Evaluation board kit

Package Option

CB-4-1

UJ-5

Branding

5K

5L

5N

5P

5Q

5R

5S

5T

ADP160ACBZ-1.2-R7

ADP160ACBZ-1.5-R7

ADP160ACBZ-1.8-R7

ADP160ACBZ-2.1-R7

ADP160ACBZ-2.5-R7

ADP160ACBZ-2.75-R7

ADP160ACBZ-2.8-R7

ADP160ACBZ-2.85-R7

ADP160ACBZ-3.0-R7

ADP160ACBZ-3.3-R7

ADP160ACBZ-4.2-R7

ADP160AUJZ-1.2-R7

ADP160AUJZ-1.5-R7

ADP160AUJZ-1.8-R7

ADP160AUJZ-2.5-R7

ADP160AUJZ-2.8-R7

ADP160AUJZ-3.0-R7

ADP160AUJZ-3.3-R7

ADP160AUJZ-4.2-R7

ADP161AUJZ-R7

1.2

1.5

1.8

2.1

2.5

2.75

2.8

2.85

3.0

3.3

4.2

1.2

1.5

1.8

2.5

2.8

3.0

3.3

5U

5V

6U

LDQ

LDR

LE0

LFZ

LG0

Y2U

LG1

LGY

LHW

4.2

Adjustable

ADP160UJZ-REDYKIT

¹Z = RoHS Compliant Part.

registered trademarks are the property of their respective owners.

D08628-0-6/10(0)

Rev. 0 | Page 20 of 20


型号：	ADP160AUJZ-2.5-R7
厂家：	ADI
描述：	Ultralow Quiescent Current, 150 mA, CMOS Linear Regulator 超低静态电流150毫安， CMOS线性稳压器稳压器
文件：	总20页 (文件大小：500K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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