ADP1753ACPZ [ADI]
IC,VOLT REGULATOR,ADJUSTABLE,+0.5 TO +3V,CMOS,LLCC,16PIN,PLASTIC;
| 型号： | ADP1753ACPZ |
| 厂家： | 
ADI |
| 描述： | IC,VOLT REGULATOR,ADJUSTABLE,+0.5 TO +3V,CMOS,LLCC,16PIN,PLASTIC |
| 文件： | 总20页 (文件大小：686K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
0.8 A, Low VIN, Low Dropout
Linear Regulator
ADP1752/ADP1753
FEATURES
TYPICAL APPLICATION CIRCUITS
V
IN
= 1.8V
V
= 1.5V
OUT
Maximum output current: 0.8 A
Input voltage range: 1.6 V to 3.6 V
Low shutdown current: <2 µA
Very low dropout voltage: 70 mV @ 0.8 A load
Initial accuracy: 1%
Accuracy over line, load, and temperature: 2%
7 fixed output voltage options with soft start
0.75 V to 2.5 V (ADP1752)
4.7µF
4.7µF
14
VIN VIN VOUT VOUT
13
16
15
1 VIN
2 VIN
3 VIN
4 EN
VOUT 12
ADP1752
TOP VIEW
(Not to Scale)
VOUT 11
VOUT 10
SENSE 9
100kΩ
PG
Adjustable output voltage option with soft start
0.75 V to 3.0 V (ADP1753)
High PSRR
PG GND SS NC
7
8
5
6
65 dB @ 1 kHz
10nF
65 dB @ 10 kHz
54 dB @ 100 kHz
Figure 1. ADP1752 with Fixed Output Voltage, 1.5 V
23 μV rms at 0.75 V output
V
IN
= 1.8V
V
= 0.5V(1 + R1/R2)
OUT
Stable with small 4.7 µF ceramic output capacitor
Excellent load and line transient response
Current-limit and thermal overload protection
Power-good indicator
Logic-controlled enable
Reverse current protection
4.7µF
4.7µF
14
VIN VIN VOUT VOUT
13
16
15
1 VIN
2 VIN
3 VIN
4 EN
VOUT 12
ADP1753
TOP VIEW
(Not to Scale)
VOUT 11
VOUT 10
100kΩ
R1
APPLICATIONS
PG
ADJ
PG GND SS NC
9
Server computers
Memory components
R2
7
8
5
6
Telecommunications equipment
Network equipment
10nF
DSP/FPGA/microprocessor supplies
Instrumentation equipment/data acquisition systems
Figure 2. ADP1753 with Adjustable Output Voltage, 0.75 V to 3.0 V
GENERAL DESCRIPTION
voltages that range from 0.75 V to 3.0 V via an external divider.
The ADP1752/ADP1753 allow an external soft start capacitor
to be connected to program the startup. A digital power-good
output allows power system monitors to check the health of the
output voltage.
The ADP1752/ADP1753 are low dropout (LDO) CMOS linear
regulators that operate from 1.6 V to 3.6 V and provide up to
800 mA of output current. These low VIN/VOUT LDOs are ideal
for regulation of nanometer FPGA geometries operating from
2.5 V down to 1.8 V I/O rails, and for powering core voltages
down to 0.75 V. Using an advanced proprietary architecture,
they provide high power supply rejection ratio (PSRR) and low
noise, and achieve excellent line and load transient response
with only a small 4.7 µF ceramic output capacitor.
The ADP1752/ADP1753 are available in a 16-lead, 4 mm × 4 mm
LFCSP, making them not only very compact solutions, but also
providing excellent thermal performance for applications that
require up to 800 mA of output current in a small, low profile
footprint.
The ADP1752 is available in seven fixed output voltage options.
The ADP1753 is the adjustable version, which allows output
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rightsof third parties that may result fromits use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks andregisteredtrademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2008 Analog Devices, Inc. All rights reserved.
ADP1752/ADP1753
TABLE OF CONTENTS
Soft Start Function (ADP1752/ADP1753) ............................. 11
Adjustable Output Voltage (ADP1753)................................... 12
Enable Feature ............................................................................ 12
Power-Good Feature.................................................................. 12
Reverse Current Protection Feature ........................................ 13
Applications Information .............................................................. 14
Capacitor Selection .................................................................... 14
Undervoltage Lockout ............................................................... 15
Current-Limit and Thermal Overload Protection................. 15
Thermal Considerations............................................................ 15
PCB Layout Considerations...................................................... 18
Outline Dimensions....................................................................... 19
Ordering Guide .......................................................................... 19
Features .............................................................................................. 1
Applications....................................................................................... 1
Typical Application Circuits............................................................ 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Input and Output Capacitor, Recommended Specifications.. 4
Absolute Maximum Ratings............................................................ 5
Thermal Data ................................................................................ 5
Thermal Resistance ...................................................................... 5
ESD Caution.................................................................................. 5
Pin Configurations and Function Descriptions ........................... 6
Typical Performance Characteristics ............................................. 7
Theory of Operation ...................................................................... 11
REVISION HISTORY
10/08—Revision 0: Initial Version
Rev. 0 | Page 2 of 20
ADP1752/ADP1753
SPECIFICATIONS
VIN = (VOUT + 0.4 V) or 1.6 V (whichever is greater), IOUT = 10 mA, CIN = COUT = 4.7 µF, TA = 25°C, unless otherwise noted.
Table 1.
Parameter
Symbol
VIN
Test Conditions/Comments
TJ = −40°C to +125°C
Min
Typ Max
Unit
V
INPUT VOLTAGE RANGE
OPERATING SUPPLY CURRENT1
1.6
3.6
90
400
IGND
IOUT = 500 μA
IOUT = 100 mA
IOUT = 100 mA, TJ = −40°C to +125°C
IOUT = 0.8 A
IOUT = 0.8 A, TJ = −40°C to +125°C
EN = GND, VIN = 1.6 V
µA
µA
µA
mA
mA
µA
µA
µA
800
0.9
1.2
SHUTDOWN CURRENT
IGND-SD
2
6
EN = GND, VIN = 1.6 V, TJ = −40°C to +85°C
EN = GND, VIN = 3.6 V, TJ = −40°C to +85°C
30
100
OUTPUT VOLTAGE ACCURACY
Fixed Output Voltage Accuracy
(ADP1752)
VOUT
IOUT = 10 mA
IOUT = 10 mA to 0.8 A
10 mA < IOUT < 0.8 A, TJ = −40°C to +125°C
IOUT = 10 mA
IOUT = 10 mA to 0.8 A
−1
−1.5
−2
0.45
0.492
0.490
−0.3
+1
+1.5
+2
0.55
0.508
0.510
+0.3
0.8
%
%
%
V
Adjustable Output Voltage Accuracy VADJ
(ADP1753)2
0.5
V
10 mA < IOUT < 0.8 A, TJ = −40°C to +125°C
V
LINE REGULATION
LOAD REGULATION3
DROPOUT VOLTAGE4
∆VOUT/∆VIN VIN = (VOUT + 0.4 V) to 3.6 V, TJ = −40°C to +125°C
∆VOUT/∆IOUT IOUT = 10 mA to 0.8 A, TJ = −40°C to +125°C
%/V
%/A
mV
mV
mV
mV
µs
VDROPOUT
IOUT = 100 mA, VOUT ≥ 1.8 V
IOUT = 100 mA, VOUT ≥ 1.8 V, TJ = −40°C to +125°C
IOUT = 0.8 A, VOUT ≥ 1.8 V
IOUT = 0.8 A, VOUT ≥ 1.8 V, TJ = −40°C to +125°C
CSS = 0 nF, IOUT = 10 mA
CSS = 10 nF, IOUT = 10 mA
10
70
16
140
START-UP TIME5
tSTART-UP
ILIMIT
200
5.2
1.4
ms
A
CURRENT-LIMIT THRESHOLD6
THERMAL SHUTDOWN
1
5
Thermal Shutdown Threshold
Thermal Shutdown Hysteresis
TSSD
TJ rising
150
15
°C
°C
TSSD-HYS
PG OUTPUT LOGIC LEVEL
PG Output Logic High
PG Output Logic Low
PG Output Delay from EN Transition
Low to High
PGHIGH
PGLOW
1.6 V ≤ VIN ≤ 3.6 V, IOH < 1 µA
1.6 V ≤ VIN ≤ 3.6 V, IOL < 2 mA
1.6 V ≤ VIN ≤ 3.6 V, CSS = 10 nF
1.0
V
V
ms
0.4
5.5
PG OUTPUT THRESHOLD
Output Voltage Falling
Output Voltage Rising
EN INPUT
PGFALL
PGRISE
1.6 V ≤ VIN ≤ 3.6 V
1.6 V ≤ VIN ≤ 3.6 V
−10
−6.5
%
%
EN Input Logic High
EN Input Logic Low
VIH
VIL
1.6 V ≤ VIN ≤ 3.6 V
1.6 V ≤ VIN ≤ 3.6 V
EN = VIN or GND
1.2
V
V
µA
0.4
1
EN Input Leakage Current
UNDERVOLTAGE LOCKOUT
Input Voltage Rising
Input Voltage Falling
Hysteresis
VI-LEAKAGE
UVLO
UVLORISE
UVLOFALL
UVLOHYS
ISS
0.1
TJ = −40°C to +125°C
TJ = −40°C to +125°C
TJ = 25°C
1.58
V
V
mV
µA
nA
µA
1.25
0.6
100
0.9
10
SOFT START CURRENT
ADJ INPUT BIAS CURRENT (ADP1753)
SENSE INPUT BIAS CURRENT
1.6 V ≤ VIN ≤ 3.6 V
1.2
ADJI-BIAS
SNSI-BIAS
1.6 V ≤ VIN ≤ 3.6 V, TJ = −40°C to +125°C
1.6 V ≤ VIN ≤ 3.6 V
150
10
Rev. 0 | Page 3 of 20
ADP1752/ADP1753
Parameter
Symbol
Test Conditions/Comments
10 Hz to 100 kHz, VOUT = 0.75 V
10 Hz to 100 kHz, VOUT = 2.5 V
VIN = VOUT + 1 V, IOUT = 10 mA
1 kHz, VOUT = 0.75 V
1 kHz, VOUT = 2.5 V
10 kHz, VOUT = 0.75 V
10 kHz, VOUT = 2.5 V
100 kHz, VOUT = 0.75 V
100 kHz, VOUT = 2.5 V
Min
Typ Max
Unit
OUTPUT NOISE
OUTNOISE
23
65
µV rms
µV rms
POWER SUPPLY REJECTION RATIO
PSRR
65
56
65
56
54
51
dB
dB
dB
dB
dB
dB
1 Minimum output load current is 500 μA.
2 Accuracy when VOUT is connected directly to ADJ. When VOUT voltage is set by external feedback resistors, absolute accuracy in adjust mode depends on the
tolerances of resistors used.
3 Based on an end-point calculation using 10 mA and 0.8 A loads. See Figure 6 for typical load regulation performance.
4 Dropout voltage is defined as the input to output voltage differential when the input voltage is set to the nominal output voltage. This applies only to output voltages
above 1.6 V.
5 Start-up time is defined as the time between the rising edge of EN to VOUT being at 95% of its nominal value.
6 Current-limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 1.0 V
output voltage is defined as the current that causes the output voltage to drop to 90% of 1.0 V, or 0.9 V.
INPUT AND OUTPUT CAPACITOR, RECOMMENDED SPECIFICATIONS
Table 2.
Parameter
Symbol
CMIN
Test Conditions/Comments
TA = −40°C to +125°C
Min
3.3
Typ
Max
Unit
µF
MINIMUM INPUT AND OUTPUT CAPACITANCE1
CAPACITOR ESR
RESR
TA = −40°C to +125°C
0.001
0.1
Ω
1 The minimum input and output capacitance should be greater than 3.3 µF over the full range of operating conditions. The full range of operating conditions in the
application must be considered during device selection to ensure that the minimum capacitance specification is met. X7R and X5R type capacitors are recommended;
Y5V and Z5U capacitors are not recommended for use with this LDO.
Rev. 0 | Page 4 of 20
ADP1752/ADP1753
ABSOLUTE MAXIMUM RATINGS
Junction-to-ambient thermal resistance (θJA) of the package is
based on modeling and calculation using a 4-layer board. The
junction-to-ambient thermal resistance is highly dependent on
the application and board layout. In applications where high
maximum power dissipation exists, close attention to thermal
board design is required. The value of θJA may vary, depending
on PCB material, layout, and environmental conditions. The
specified values of θJA are based on a 4-layer, 4 in × 3 in circuit
board. Refer to JEDEC JESD51-7 for detailed information about
board construction. For more information, see the AN-772
Application Note, A Design and Manufacturing Guide for the
Lead Frame Chip Scale Package (LFCSP) at www.analog.com.
Table 3.
Parameter
Rating
VIN to GND
VOUT to GND
−0.3 V to +3.6 V
−0.3 V to VIN
EN to GND
SS to GND
PG to GND
SENSE/ADJ to GND
Storage Temperature Range
Operating Junction Temperature Range
Soldering Conditions
−0.3 V to +3.6 V
−0.3 V to +3.6 V
−0.3 V to +3.6 V
−0.3 V to +3.6 V
−65°C to +150°C
−40°C to +125°C
JEDEC J-STD-020
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ΨJB is the junction-to-board thermal characterization parameter
with units of °C/W. ΨJB of the package is based on modeling and
calculation using a 4-layer board. The JESD51-12 document,
Guidelines for Reporting and Using Electronic Package Thermal
Information, states that thermal characterization parameters are
not the same as thermal resistances. ΨJB measures the component
power flowing through multiple thermal paths rather than
through a single path as in thermal resistance, θJB. Therefore,
ΨJB thermal paths include convection from the top of the package
as well as radiation from the package, factors that make ΨJB more
useful in real-world applications. Maximum junction temperature
(TJ) is calculated from the board temperature (TB) and the power
dissipation (PD) using the following formula:
THERMAL DATA
Absolute maximum ratings apply individually only, not in
combination. The ADP1752/ADP1753 may be damaged if the
junction temperature limits are exceeded. Monitoring ambient
temperature does not guarantee that TJ is within the specified
temperature limits. In applications with high power dissipation
and poor thermal resistance, the maximum ambient tempera-
ture may need to be derated. In applications with moderate
power dissipation and low PCB thermal resistance, the maximum
ambient temperature can exceed the maximum limit as long as
the junction temperature is within specification limits. The
junction temperature (TJ) of the device is dependent on the
ambient temperature (TA), the power dissipation of the device
(PD), and the junction-to-ambient thermal resistance of the
package (θJA). TJ is calculated using the following formula:
TJ = TB + (PD × ΨJB)
Refer to the JEDEC JESD51-8 and JESD51-12 documents for more
detailed information about ΨJB.
THERMAL RESISTANCE
θJA and ΨJB are specified for the worst-case conditions, that is, a
device soldered in a circuit board for surface-mount packages.
Table 4. Thermal Resistance
Package Type
θJA
ΨJB
Unit
TJ = TA + (PD × θJA).
16-Lead LFCSP with Exposed Pad (CP-16-4) 130 32.7 °C/W
ESD CAUTION
Rev. 0 | Page 5 of 20
ADP1752/ADP1753
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
PIN 1
PIN 1
INDICATOR
INDICATOR
12 VOUT
11 VOUT
10 VOUT
12 VOUT
11 VOUT
10 VOUT
VIN
VIN
VIN
EN
1
2
3
4
VIN
VIN
VIN
EN
1
2
3
4
ADP1752
TOP VIEW
(Not to Scale)
ADP1753
TOP VIEW
(Not to Scale)
9
SENSE
9 ADJ
NOTES
1. NC = NO CONNECT.
2. THE EXPOSED PAD ON THE BOTTOM OF THE LFCSP ENHANCES
THERMAL PERFORMANCE AND IS ELECTRICALLY CONNECTED TO GND
INSIDE THE PACKAGE. IT IS RECOMMENDED THAT THE EXPOSED PAD
BE CONNECTED TO THE GROUND PLANE ON THE BOARD.
NOTES
1. NC = NO CONNECT.
2. THE EXPOSED PAD ON THE BOTTOM OF THE LFCSP ENHANCES
THERMAL PERFORMANCE AND IS ELECTRICALLY CONNECTED TO GND
INSIDE THE PACKAGE. IT IS RECOMMENDED THAT THE EXPOSED PAD
BE CONNECTED TO THE GROUND PLANE ON THE BOARD.
Figure 3. ADP1752 Pin Configuration
Figure 4. ADP1753 Pin Configuration
Table 5. Pin Function Descriptions
ADP1752
Pin No.
ADP1753
Pin No.
Mnemonic
Description
1, 2, 3, 15, 16 1, 2, 3, 15, 16 VIN
Regulator Input Supply. Bypass VIN to GND with a 4.7 µF or greater capacitor. Note that all
five VIN pins must be connected to the source.
4
5
4
5
EN
PG
Enable Input. Drive EN high to turn on the regulator; drive it low to turn off the regulator. For
automatic startup, connect EN to VIN.
Power Good. This open-drain output requires an external pull-up resistor to VIN. If the part is
in shutdown mode, current-limit mode, thermal shutdown, or if it falls below 90% of the
nominal output voltage, PG immediately transitions low.
6
7
8
9
6
7
8
N/A
GND
SS
NC
Ground.
Soft Start. A capacitor connected to this pin determines the soft start time.
Not Connected. No internal connection.
Sense. This pin measures the actual output voltage at the load and feeds it to the error
amplifier. Connect SENSE as close as possible to the load to minimize the effect of IR drop
between the regulator output and the load.
SENSE
N/A
9
ADJ
Adjust. A resistor divider from VOUT to ADJ sets the output voltage.
10, 11, 12,
13, 14
10, 11, 12,
13, 14
VOUT
Regulated Output Voltage. Bypass VOUT to GND with a 4.7 µF or greater capacitor. Note that
all five VOUT pins must be connected to the load.
17 (EPAD)
17 (EPAD)
Exposed
paddle
(EPAD)
The exposed pad on the bottom of the LFCSP package enhances thermal performance and
is electrically connected to GND inside the package. It is recommended that the exposed
pad be connected to the ground plane on the board.
Rev. 0 | Page 6 of 20
ADP1752/ADP1753
TYPICAL PERFORMANCE CHARACTERISTICS
VIN = 1.9 V, VOUT = 1.5 V, IOUT = 10 mA, CIN = 4.7 µF, COUT = 4.7 µF, TA = 25°C, unless otherwise noted.
1.520
1.515
1.510
1.505
1.500
1.495
1.490
1.485
1.480
1000
900
800
700
600
500
400
300
200
100
0
LOAD = 800mA
LOAD = 400mA
LOAD = 10mA
LOAD = 100mA
LOAD = 100mA
LOAD = 10mA
LOAD = 400mA
LOAD = 800mA
–40
–5
25
85
125
–40
–5
25
85
125
JUNCTION TEMPERATURE (°C)
JUNCTION TEMPERATURE (°C)
Figure 5. Output Voltage vs. Junction Temperature
Figure 8. Ground Current vs. Junction Temperature
1.520
1.515
1.510
1.505
1.500
1.495
1.490
1.485
1.480
1000
900
800
700
600
500
400
300
200
100
0
10
100
1k
10
100
1k
LOAD CURRENT (mA)
LOAD CURRENT (mA)
Figure 6. Output Voltage vs. Load Current
Figure 9. Ground Current vs. Load Current
1.520
1.515
1.510
1.505
1.500
1.495
1.490
1.485
1.480
1000
900
800
700
600
500
400
300
200
100
0
LOAD = 800mA
LOAD = 400mA
LOAD = 10mA
LOAD = 100mA
LOAD = 400mA
LOAD = 800mA
LOAD = 100mA
LOAD = 10mA
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
Figure 7. Output Voltage vs. Input Voltage
Figure 10. Ground Current vs. Input Voltage
Rev. 0 | Page 7 of 20
ADP1752/ADP1753
100
90
80
70
60
50
40
30
20
10
0
4500
4000
3500
3000
2500
2000
1500
1000
500
LOAD = 10mA
LOAD = 100mA
LOAD = 400mA
LOAD = 800mA
1.9V
2.0V
2.4V
2.6V
3.0V
3.6V
0
–40
–15
10
35
60
85
2.3
2.4
2.5
2.6
2.7
2.8
TEMPERATURE (°C)
INPUT VOLTAGE (V)
Figure 11. Shutdown Current vs. Temperature at Various Input Voltages
Figure 14. Ground Current vs. Input Voltage (in Dropout), VOUT = 2.5 V
0.08
0.07
0.06
0.05
0.04
T
I
LOAD
1
2
1mA TO 800mA LOAD STEP, 2.5A/µs, 500mA/DIV
V
1.6V
OUT
0.03
50mV/DIV
0.02
2.5V
0.01
V
V
= 3.6V
= 1.5V
IN
OUT
0
B
B
W
CH1 500mA Ω
CH2 50mV
M10µs
A CH1
380mA
W
1
10
100
1k
T
10.20%
LOAD CURRENT (mA)
Figure 12. Dropout Voltage vs. Load Current, VOUT = 1.6 V, 2.5 V
Figure 15. Load Transient Response, CIN = 4.7 µF, COUT = 4.7 µF
2.60
2.55
2.50
2.45
2.40
2.35
T
I
LOAD
1
2
1mA TO 800mA LOAD STEP, 2.5A/µs, 500mA/DIV
V
OUT
20mV/DIV
2.30
LOAD = 10mA
LOAD = 100mA
2.25
V
V
= 3.6V
= 1.5V
IN
OUT
LOAD = 400mA
LOAD = 800mA
2.20
2.3
B
B
W
CH1 500mA Ω
CH2 20mV
M10µs
A CH1
530mA
W
2.4
2.5
2.6
2.7 2.8
T
10.20%
INPUT VOLTAGE (V)
Figure 13. Output Voltage vs. Input Voltage (in Dropout), VOUT = 2.5 V
Figure 16. Load Transient Response, CIN = 22 µF, COUT = 22 µF
Rev. 0 | Page 8 of 20
ADP1752/ADP1753
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
T
V
IN
3V TO 3.5V INPUT VOLTAGE STEP, 2V/µs
V
OUT
2
2mV/DIV
800mA
400mA
100mA
10mA
V
C
= 1.5V
OUT
= C = 4.7µF
IN
OUT
1
B
B
W
CH1 500mV
CH2 2.0mV
M10µs
A CH4
800mA
W
10
100
1k
10k
100k
1M
10M
T
9.40%
FREQUENCY (Hz)
Figure 20. Power Supply Rejection Ratio vs. Frequency,
OUT = 0.75 V, VIN = 1.75 V
Figure 17. Line Transient Response, Load Current = 800 mA
V
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
70
2.5V
60
50
40
1.5V
30
20
10
0.75V
LOAD = 800mA
LOAD = 400mA
LOAD = 100mA
LOAD = 10mA
0
10
100
1k
10k
100k
1M
10M
0.0001
0.001
0.01
LOAD CURRENT (A)
0.1
1
FREQUENCY (Hz)
Figure 21. Power Supply Rejection Ratio vs. Frequency,
OUT = 1.5 V, VIN = 2.5 V
Figure 18. Noise vs. Load Current and Output Voltage
V
10
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
1
1.5V
2.5V
0.1
LOAD = 800mA
LOAD = 400mA
LOAD = 100mA
LOAD = 10mA
0.75V
0.01
10
100
1k
10k
100k
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 22. Power Supply Rejection Ratio vs. Frequency,
OUT = 2.5 V, VIN = 3.5 V
Figure 19. Noise Spectral Density vs. Output Voltage, ILOAD = 10 mA
V
Rev. 0 | Page 9 of 20
ADP1752/ADP1753
0
1.5V/800mA
2.5V/800mA
1.5V/10mA
2.5V/10mA
0.75V/10mA
–10
0.75V/800mA
–20
–30
–40
–50
–60
–70
–80
–90
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 23. Power Supply Rejection Ratio vs. Frequency and Output Voltage
Rev. 0 | Page 10 of 20
ADP1752/ADP1753
THEORY OF OPERATION
The ADP1752 is available in seven fixed output voltage options
between 0.75 V and 2.5 V. The ADP1752 allows for connection
of an external soft start capacitor that controls the output voltage
ramp during startup. The ADP1753 is the adjustable version
with an output voltage that can be set to a value between 0.75 V
and 3.0 V by an external voltage divider. Both devices are con-
trolled by an enable pin (EN).
The ADP1752/ADP1753 are low dropout linear regulators that
use an advanced, proprietary architecture to provide high power
supply rejection ratio (PSRR) and excellent line and load transient
response with only a small 4.7 µF ceramic output capacitor.
Both devices operate from a 1.6 V to 3.6 V input rail and
provide up to 0.8 A of output current. Supply current in
shutdown mode is typically 2 µA.
SOFT START FUNCTION (ADP1752/ADP1753)
REVERSE POLARITY
ADP1752
PROTECTION
For applications that require a controlled startup, the ADP1752/
ADP1753 provide a programmable soft start function. The
programmable soft start is useful for reducing inrush current
upon startup and for providing voltage sequencing. To implement
soft start, connect a small ceramic capacitor from SS to GND.
Upon startup, a 0.9 µA current source charges this capacitor.
The ADP1752/ADP1753 start-up output voltage is limited by
the voltage at SS, providing a smooth ramp-up to the nominal
output voltage. The soft start time is calculated as follows:
VIN
VOUT
UVLO
GND
SHORT-CIRCUIT
AND THERMAL
PROTECTION
SENSE
R1
R2
0.5V
REF
PG
EN
t
SS = VREF × (CSS/ISS)
where:
SS is the soft start period.
REF is the 0.5 V reference voltage.
SS is the soft start capacitance from SS to GND.
SS is the current sourced from SS (0.9 µA).
(1)
PG
DETECT
0.9µA
SS
SHUTDOWN
t
V
C
I
Figure 24. ADP1752 Internal Block Diagram
REVERSE POLARITY
ADP1753
When the ADP1752/ADP1753 are disabled (using EN), the soft
PROTECTION
start capacitor is discharged to GND through an internal 100 Ω
VIN
VOUT
resistor.
UVLO
2.50
2.25
GND
EN
SHORT-CIRCUIT
AND THERMAL
PROTECTION
2.00
1.75
1nF
1.50
ADJ
SS
0.5V
REF
PG
EN
1.25
4.7nF
PG
DETECT
1.00
0.9µA
10nF
0.75
SHUTDOWN
0.50
0.25
0
Figure 25. ADP1753 Internal Block Diagram
Internally, the ADP1752/ADP1753 consist of a reference, an error
amplifier, a feedback voltage divider, and a PMOS pass transistor.
Output current is delivered via the PMOS pass transistor, which is
controlled by the error amplifier. The error amplifier compares the
reference voltage with the feedback voltage from the output and
amplifies the difference. If the feedback voltage is lower than the
reference voltage, the gate of the PMOS device is pulled lower,
allowing more current to pass and increasing the output voltage.
If the feedback voltage is higher than the reference voltage, the
gate of the PMOS device is pulled higher, allowing less current
to pass and decreasing the output voltage.
0
2
4
6
8
10
TIME (ms)
Figure 26. VOUT Ramp-Up with External Soft Start Capacitor
Rev. 0 | Page 11 of 20
ADP1752/ADP1753
T
The EN pin active/inactive thresholds are derived from the VIN
voltage. Therefore, these thresholds vary with changing input
voltage. Figure 29 shows typical EN active/inactive thresholds
when the input voltage varies from 1.6 V to 3.6 V.
1.1
EN
1
1.0
V
OUT
0.9
EN ACTIVE
2
0.8
V
C
= 1.5V
OUT
= C
500mV/DIV
B
= 4.7µF
IN
OUT
EN INACTIVE
B
CH1 2.0V
CH2 500mV
M40µs
W
A CH1
920mV
0.7
W
T
9.8%
Figure 27. VOUT Ramp-Up with Internal Soft Start
0.6
ADJUSTABLE OUTPUT VOLTAGE (ADP1753)
0.5
The output voltage of the ADP1753 can be set over a 0.75 V to
3.0 V range. The output voltage is set by connecting a resistive
voltage divider from VOUT to ADJ. The output voltage is calcu-
lated using the following equation:
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
INPUT VOLTAGE (V)
Figure 29. Typical EN Pin Thresholds vs. Input Voltage
POWER-GOOD FEATURE
VOUT = 0.5 V × (1 + R1/R2)
(2)
The ADP1752/ADP1753 provide a power-good pin, PG, to
indicate the status of the output. This open-drain output
requires an external pull-up resistor to VIN. If the part is in
shutdown, in current limit mode, in thermal shutdown, or if it
falls below 90% of the nominal output voltage, PG immediately
transitions low. During soft start, the rising threshold of the
power-good signal is 93.5% of the nominal output voltage.
where:
R1 is the resistor from VOUT to ADJ.
R2 is the resistor from ADJ to GND.
The maximum bias current into ADJ is 150 nA. Therefore, to
achieve less than 0.5% error due to the bias current, use values
less than 60 kΩ for R2.
The open-drain output is held low when the ADP1752/ADP1753
have sufficient input voltage to turn on the internal PG transistor.
An optional soft start delay can be detected. The PG transistor
is terminated via a pull-up resistor to VOUT or VIN.
ENABLE FEATURE
The ADP1752/ADP1753 use the EN pin to enable and disable
the VOUT pin under normal operating conditions. As shown in
Figure 28, when a rising voltage on EN crosses the active
threshold, VOUT turns on. When a falling voltage on EN
crosses the inactive threshold, VOUT turns off.
Power-good accuracy is 93.5% of the nominal regulator output
voltage when this voltage is rising, with a 90% trip point when
this voltage is falling.
T
Regulator input voltage brownouts or glitches trigger a power
no-good if VOUT falls below 90%.
EN
A normal power-down triggers a power no-good when VOUT
drops below 90%.
V
OUT
1
V
C
= 1.5V
OUT
= C
500mV/DIV
B
= 4.7µF
IN
OUT
B
CH1 500mV
CH2 500mV
M2.0ms
W
A CH1
1.05V
W
T
29.6%
Figure 28. Typical EN Pin Operation
As shown in Figure 28, the EN pin has hysteresis built in. This
hysteresis prevents on/off oscillations that can occur due to
noise on the EN pin as it passes through the threshold points.
Rev. 0 | Page 12 of 20
ADP1752/ADP1753
T
REVERSE CURRENT PROTECTION FEATURE
V
IN
1V/DIV
The ADP1752/ADP1753 have additional circuitry to protect
against reverse current flow from VOUT to VIN. For a typical
LDO with a PMOS pass device, there is an intrinsic body diode
between VIN and VOUT. When VIN is greater than VOUT, this
diode is reverse-biased. If VOUT is greater than VIN, the intrinsic
diode becomes forward-biased and conducts current from VOUT
to VIN, potentially causing destructive power dissipation. The
reverse current protection circuitry detects when VOUT is greater
than VIN and reverses the direction of the intrinsic diode connec-
tion, reverse-biasing the diode. The gate of the PMOS pass
device is also connected to VOUT, keeping the device off.
1
V
OUT
500mV/DIV
PG
1V/DIV
2
V
C
= 1.5V
OUT
= C
= 4.7µF
IN
OUT
B
B
CH1 1.0V
CH3 1.0V
CH2 500mV
M40.0µs A CH3
W
900mV
W
W
B
T
50.40%
Figure 32 shows a plot of the reverse current vs. the VOUT to VIN
Figure 30. Typical PG Behavior vs. VOUT, VIN Rising (VOUT = 1.5 V)
differential.
4000
3500
3000
2500
2000
1500
1000
500
T
V
IN
1V/DIV
1
V
OUT
500mV/DIV
PG
1V/DIV
2
V
C
= 1.5V
OUT
= C
0
= 4.7µF
IN
OUT
0
0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 3.3 3.6
– V (V)
V
OUT
IN
B
B
CH1 1.0V
CH3 1.0V
CH2 500mV
M40.0µs A CH3
W
900mV
W
W
B
T
50.40%
Figure 32. Reverse Current vs. VOUT − VIN
Figure 31. Typical PG Behavior vs. VOUT, VIN Falling (VOUT = 1.5 V)
Rev. 0 | Page 13 of 20
ADP1752/ADP1753
APPLICATIONS INFORMATION
CAPACITOR SELECTION
Input Bypass Capacitor
Connecting a 4.7 µF capacitor from the VIN pin to GND reduces
the circuit sensitivity to printed circuit board (PCB) layout,
especially when long input traces or high source impedance
are encountered. If output capacitance greater than 4.7 µF is
required, it is recommended that the input capacitor be increased
to match it.
Output Capacitor
The ADP1752/ADP1753 are designed for operation with small,
space-saving ceramic capacitors, but they can function with most
commonly used capacitors as long as care is taken with the
effective series resistance (ESR) value. The ESR of the output
capacitor affects the stability of the LDO control loop. A mini-
mum of 3.3 µF capacitance with an ESR of 500 mΩ or less is
recommended to ensure the stability of the ADP1752/ADP1753.
Transient response to changes in load current is also affected by
output capacitance. Using a larger value of output capacitance
improves the transient response of the ADP1752/ADP1753 to
large changes in load current. Figure 33 and Figure 34 show the
transient responses for output capacitance values of 4.7 µF and
22 µF, respectively.
Input and Output Capacitor Properties
Any good quality ceramic capacitors can be used with the
ADP1752/ADP1753, as long as they meet the minimum
capacitance and maximum ESR requirements. Ceramic
capacitors are manufactured with a variety of dielectrics,
each with different behavior over temperature and applied
voltage. Capacitors must have a dielectric adequate to ensure
the minimum capacitance over the necessary temperature
range and dc bias conditions. X5R or X7R dielectrics with a
voltage rating of 6.3 V or 10 V are recommended. Y5V and
Z5U dielectrics are not recommended, due to their poor tempera-
ture and dc bias characteristics.
T
I
LOAD
1mA TO 800mA LOAD STEP, 2V/µs, 500mA/DIV
1
2
Figure 35 shows the capacitance vs. voltage bias characteristics
of an 0805 case, 4.7 µF, 10 V, X5R capacitor. The voltage stability
of a capacitor is strongly influenced by the capacitor size and
voltage rating. In general, a capacitor in a larger package or with
a higher voltage rating exhibits better stability. The temperature
variation of the X5R dielectric is about 15% over the −40°C to
+85°C temperature range and is not a function of package size
or voltage rating.
V
OUT
50mV/DIV
V
C
= 3.6V, V
= C
OUT
= 1.5V
= 4.7µF
IN
OUT
IN
B
B
W
CH1 500mA Ω
CH2 50mV
M1µs
A CH1
380mA
W
5
T
11.6%
MURATA P/N GRM219R61A475KE34
Figure 33. Output Transient Response, COUT = 4.7 µF
4
3
2
1
0
T
I
LOAD
1mA TO 800mA LOAD STEP, 2V/µs, 500mA/DIV
1
2
V
OUT
0
2
4
6
8
10
VOLTAGE BIAS (V)
20mV/DIV
Figure 35. Capacitance vs. Voltage Bias Characteristics
V
C
= 3.6V, V
= C
OUT
= 1.5V
= 22µF
IN
OUT
IN
Equation 3 can be used to determine the worst-case capacitance
accounting for capacitor variation over temperature, component
tolerance, and voltage.
B
B
W
CH1 500mA Ω
CH2 20mV
M1µs
A CH1
530mA
W
T
12.2%
Figure 34. Output Transient Response, COUT = 22 µF
CEFF = COUT × (1 − TEMPCO) × (1 − TOL)
(3)
where:
C
EFF is the effective capacitance at the operating voltage.
TEMPCO is the worst-case capacitor temperature coefficient.
TOL is the worst-case component tolerance.
Rev. 0 | Page 14 of 20
ADP1752/ADP1753
In this example, the worst-case temperature coefficient
THERMAL CONSIDERATIONS
(TEMPCO) over −40°C to +85°C is assumed to be 15% for an
X5R dielectric. The tolerance of the capacitor (TOL) is assumed
to be 10%, and COUT = 4.46 μF at 1.8 V, as shown in Figure 35.
To guarantee reliable operation, the junction temperature of the
ADP1752/ADP1753 must not exceed 125°C. To ensure that the
junction temperature stays below this maximum value, the user
needs to be aware of the parameters that contribute to junction
temperature changes. These parameters include ambient tempera-
ture, power dissipation in the power device, and thermal resistance
between the junction and ambient air (θJA). The θJA value is depen-
dent on the package assembly compounds used and the amount
of copper to which the GND pin and the exposed pad (EPAD)
of the package are soldered on the PCB. Table 6 shows typical
θJA values for the 16-lead LFCSP for various PCB copper sizes.
Table 7 shows typical ΨJB values for the 16-lead LFCSP.
Substituting these values in Equation 3 yields
CEFF = 4.46 μF × (1 − 0.15) × (1 − 0.1) = 3.41 μF
Therefore, the capacitor chosen in this example meets the
minimum capacitance requirement of the LDO over temper-
ature and tolerance at the chosen output voltage.
To guarantee the performance of the ADP1752/ADP1753, it is
imperative that the effects of dc bias, temperature, and toler-
ances on the behavior of the capacitors be evaluated for each
application.
Table 6. Typical θJA Values
UNDERVOLTAGE LOCKOUT
Copper Size (mm2)
θJA (°C/W), LFCSP
01
130
80
69
54
42
The ADP1752/ADP1753 have an internal undervoltage lockout
circuit that disables all inputs and the output when the input
voltage is less than approximately 1.58 V. This ensures that the
ADP1753/ADP1753 inputs and the output behave in a predicta-
ble manner during power-up.
100
500
1000
6400
CURRENT-LIMIT AND THERMAL OVERLOAD
PROTECTION
1 Device soldered to minimum size pin traces.
Table 7. Typical ΨJB Values
The ADP1752/ADP1753 are protected against damage due to
excessive power dissipation by current-limit and thermal
overload protection circuits. The ADP1752/ADP1753 are
designed to reach current limit when the output load reaches
1.4 A (typical). When the output load exceeds 1.4 A, the output
voltage is reduced to maintain a constant current limit.
Copper Size (mm2)
ΨJB (°C/W) @ 1 W
100
500
1000
32.7
31.5
25.5
The junction temperature of the ADP1752/ADP1753 can be
calculated from the following equation:
Thermal overload protection is included, which limits the
junction temperature to a maximum of 150°C (typical). Under
extreme conditions (that is, high ambient temperature and
power dissipation) when the junction temperature begins to
rise above 150°C, the output is turned off, reducing the output
current to zero. When the junction temperature drops below
135°C (typical), the output is turned on again and the output
current is restored to its nominal value.
TJ = TA + (PD × θJA)
(4)
(5)
where:
TA is the ambient temperature.
PD is the power dissipation in the die, given by
PD = [(VIN − VOUT) × ILOAD] + (VIN × IGND
where:
VIN and VOUT are the input and output voltages, respectively.
)
Consider the case where a hard short from VOUT to ground
occurs. At first, the ADP1752/ADP1753 reach current limit so
that only 1.4 A is conducted into the short. If self-heating of
the junction becomes great enough to cause its temperature to
rise above 150°C, thermal shutdown activates, turning off the
output and reducing the output current to zero. As the junction
temperature cools and drops below 135°C, the output turns on
and conducts 1.4 A into the short, again causing the junction
temperature to rise above 150°C. This thermal oscillation between
135°C and 150°C causes a current oscillation between 1.4 A and
0 A that continues as long as the short remains at the output.
I
LOAD is the load current.
I
GND is the ground current.
Power dissipation due to ground current is quite small and can
be ignored. Therefore, the junction temperature equation can
be simplified as follows:
TJ = TA + {[(VIN − VOUT) × ILOAD] × θJA}
(6)
As shown in Equation 6, for a given ambient temperature, input-
to-output voltage differential, and continuous load current, a
minimum copper size requirement exists for the PCB to ensure
that the junction temperature does not rise above 125°C. Figure 36
through Figure 41 show junction temperature calculations for
different ambient temperatures, load currents, VIN to VOUT
differentials, and areas of PCB copper.
Current-limit and thermal overload protections are intended to
protect the device against accidental overload conditions. For
reliable operation, device power dissipation should be externally
limited so that junction temperatures do not exceed 125°C.
Rev. 0 | Page 15 of 20
ADP1752/ADP1753
140
140
120
100
80
MAX JUNCTION
MAX JUNCTION
TEMPERATURE
TEMPERATURE
120
100
80
60
40
20
0
LOAD = 800mA
LOAD = 800mA
LOAD = 400mA
LOAD = 200mA
LOAD = 400mA
60
LOAD = 200mA
LOAD = 100mA
LOAD = 50mA
LOAD = 10mA
40
20
LOAD = 100mA
LOAD = 50mA
LOAD = 10mA
0
0.25
0.75
1.25
1.75
2.25
2.75
0.25
0.75
1.25
1.75
(V)
2.25
2.75
V
– V
OUT
(V)
V
– V
IN
IN OUT
Figure 36. 6400 mm2 of PCB Copper, TA = 25°C, LFCSP
Figure 39. 6400 mm2 of PCB Copper, TA = 50°C, LFCSP
140
120
100
80
140
120
100
80
MAX JUNCTION
TEMPERATURE
MAX JUNCTION
TEMPERATURE
LOAD = 800mA
LOAD = 400mA
LOAD = 800mA
LOAD = 400mA
LOAD = 200mA
LOAD = 200mA
60
60
LOAD = 100mA
LOAD = 50mA
LOAD = 10mA
40
40
20
20
LOAD = 100mA
LOAD = 50mA
LOAD = 10mA
0
0
0.25
0.75
1.25
1.75
2.25
2.75
0.25
0.75
1.25
1.75
(V)
2.25
2.75
V
– V
OUT
(V)
V
– V
IN
IN OUT
Figure 37. 500 mm2 of PCB Copper, TA = 25°C, LFCSP
Figure 40. 500 mm2 of PCB Copper, TA = 50°C, LFCSP
140
120
100
80
140
120
100
80
MAX JUNCTION
TEMPERATURE
MAX JUNCTION
TEMPERATURE
LOAD = 400mA
LOAD =
800mA
LOAD = 800mA
LOAD = 400mA
LOAD = 200mA
LOAD = 200mA
LOAD = 100mA
60
60
LOAD = 100mA
LOAD = 50mA
LOAD = 10mA
40
40
20
20
LOAD = 50mA
LOAD = 10mA
1.75
0
0
0.25
0.75
1.25
2.25
2.75
0.25
0.75
1.25
1.75
(V)
2.25
2.75
V
– V
OUT
(V)
V
– V
IN
IN OUT
Figure 38. 0 mm2 of PCB Copper, TA = 25°C, LFCSP
Figure 41. 0 mm2 of PCB Copper, TA = 50°C, LFCSP
Rev. 0 | Page 16 of 20
ADP1752/ADP1753
140
120
100
80
In cases where the board temperature is known, the thermal
MAX JUNCTION
TEMPERATURE
characterization parameter, Ψ , can be used to estimate the
JB
junction temperature rise. Maximum junction temperature (TJ)
is calculated from the board temperature (TB) and power
dissipation (PD) using the following formula:
LOAD = 800mA
LOAD = 200mA
TJ = TB + (PD × ΨJB)
(7)
LOAD = 400mA
60
Figure 42 through Figure 45 show junction temperature calcula-
tions for different board temperatures, load currents, VIN to
40
V
OUT differentials, and areas of PCB copper.
140
20
LOAD = 100mA
LOAD = 50mA
LOAD = 10mA
MAX JUNCTION
TEMPERATURE
120
0
0.25
0.75
1.25
1.75
(V)
2.25
2.75
V
– V
OUT
IN
100
Figure 44. 1000 mm2 of PCB Copper, TB = 25°C, LFCSP
LOAD = 800mA
80
60
40
20
0
140
120
100
80
MAX JUNCTION
TEMPERATURE
LOAD = 400mA
LOAD = 200mA
LOAD = 800mA
LOAD = 100mA
LOAD = 50mA
LOAD = 10mA
LOAD = 400mA
LOAD = 200mA
60
0.25
0.75
1.25
1.75
(V)
2.25
2.75
V
– V
OUT
IN
LOAD = 100mA
LOAD = 50mA
LOAD = 10mA
40
Figure 42. 500 mm2 of PCB Copper, TB = 25°C, LFCSP
140
120
100
80
20
MAX JUNCTION
TEMPERATURE
0
0.25
0.75
1.25
1.75
(V)
2.25
2.75
LOAD = 800mA
LOAD = 400mA
V
– V
OUT
IN
Figure 45. 1000 mm2 of PCB Copper, TB = 50°C, LFCSP
LOAD = 200mA
60
LOAD = 100mA
LOAD = 50mA
LOAD = 10mA
40
20
0
0.25
0.75
1.25
1.75
(V)
2.25
2.75
V
– V
OUT
IN
Figure 43. 500 mm2 of PCB Copper, TB = 50°C, LFCSP
Rev. 0 | Page 17 of 20
ADP1752/ADP1753
PCB LAYOUT CONSIDERATIONS
Heat dissipation from the package can be improved by increas-
ing the amount of copper attached to the pins of the ADP1752/
ADP1753. However, as shown in Table 6, a point of diminishing
returns is eventually reached, beyond which an increase in the
copper size does not yield significant heat dissipation benefits.
Here are a few general tips when designing PCBs:
•
Place the input capacitor as close as possible to the VIN
and GND pins.
•
Place the output capacitor as close as possible to the VOUT
and GND pins.
•
•
Place the soft start capacitor as close as possible to the SS pin.
Connect the load as close as possible to the VOUT and
SENSE pins (ADP1754) or to the VOUT and ADJ pins
(ADP1755).
Use of 0603 or 0805 size capacitors and resistors achieves the
smallest possible footprint solution on boards where area is
limited.
Figure 47. Typical Board Layout—Top Side
Figure 48. Typical Board Layout—Bottom Side
Figure 46. Evaluation Board
Rev. 0 | Page 18 of 20
ADP1752/ADP1753
OUTLINE DIMENSIONS
4.00
0.60 MAX
(BOTTOM VIEW)
BSC SQ
0.60 MAX
0.65 BSC
PIN 1
INDICATOR
13
16
1
4
12
PIN 1
INDICATOR
2.25
2.10 SQ
1.95
TOP
VIEW
3.75
BSC SQ
0.75
0.60
0.50
9
8
5
0.25 MIN
0.80 MAX
0.65 TYP
12° MAX
1.95 BSC
0.05 MAX
0.02 NOM
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
1.00
0.85
0.80
0.35
0.30
0.25
0.20 REF
COPLANARITY
0.08
SECTION OF THIS DATA SHEET.
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-220-VGGC
Figure 49. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
4 mm × 4 mm Body, Very Thin Quad
(CP-16-4)
Dimensions shown in millimeters
ORDERING GUIDE
Model
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Output Voltage (V)
Package Description
Package Option
CP-16-4
CP-16-4
CP-16-4
CP-16-4
CP-16-4
CP-16-4
CP-16-4
ADP1752ACPZ-0.75R71
ADP1752ACPZ-1.0-R71
ADP1752ACPZ-1.1-R71
ADP1752ACPZ-1.2-R71
ADP1752ACPZ-1.5-R71
ADP1752ACPZ-1.8-R71
ADP1752ACPZ-2.5-R71
ADP1753ACPZ-R71
ADP1753ACPZ1
0.75
1.0
1.1
1.2
1.5
1.8
2.5
16-Lead LFCSP_VQ
16-Lead LFCSP_VQ
16-Lead LFCSP_VQ
16-Lead LFCSP_VQ
16-Lead LFCSP_VQ
16-Lead LFCSP_VQ
16-Lead LFCSP_VQ
16-Lead LFCSP_VQ
16-Lead LFCSP_VQ
Evaluation Board
Evaluation Board
Adjustable from 0.75 to 3.0
Adjustable from 0.75 to 3.0
1.5
CP-16-4
CP-16-4
ADP1752-1.5-EVALZ1
ADP1753-EVALZ1
Adjustable
1 Z = RoHS Compliant Part.
Rev. 0 | Page 19 of 20
ADP1752/ADP1753
NOTES
©2008 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07718-0-10/08(0)
Rev. 0 | Page 20 of 20
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