ADP1755 [ADI]
CMOS Linear Regulator;
| 型号： | ADP1755 |
| 厂家： | 
ADI |
| 描述： | CMOS Linear Regulator |
| 文件： | 总19页 (文件大小：935K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
3 A, Low VIN, Low Noise,
CMOS Linear Regulator
ADP1763
Data Sheet
FEATURES
TYPICAL APPLICATION CIRCUITS
3 A maximum output current
Low input voltage supply range
ADP1763
V
= 1.5V
V
= 1.8V
OUT
IN
VIN
VOUT
SENSE
EN
C
10µF
C
OUT
10µF
IN
VIN = 1.10 V to 1.98 V, no external bias supply required
R
ON
PULL-UP
Fixed output voltage range: VOUT_FIXED = 0.9 V to 1.5 V
Adjustable output voltage range: VOUT_ADJ = 0.5 V to 1.5 V
Ultralow noise: 2 μV rms, 100 Hz to 100 kHz
Noise spectral density
100kΩ
OFF
PG
PG
SS
VADJ
C
SS
VREG
REFCAP
10nF
C
C
1µF
REF
1µF
GND
REG
4 nV/√Hz at 10 kHz
3 nV/√Hz at 100 kHz
Figure 1. Fixed Output Operation
Low dropout voltage: 95 mV typical at 3 A load
Operating supply current: 4.5 mA typical at no load
1.5ꢀ fixed output voltage accuracy over line, load, and
temperature
Excellent power supply rejection ratio (PSRR) performance
59 dB typical at 10 kHz at 3 A load
43 dB typical at 100 kHz at 3 A load
Excellent load/line transient response
Soft start to reduce inrush current
Optimized for small 10 μF ceramic capacitors
Current-limit and thermal overload protection
Power-good indicator
ADP1763
V
= 1.8V
R
V
= 1.5V
C
OUT
IN
OUT
VIN
VOUT
C
10µF
IN
10µF
SENSE
ON
PULL-UP
100kΩ
EN
OFF
PG
PG
SS
VADJ
C
R
VREG
REFCAP
SS
ADJ
10nF
10kΩ
C
C
REF
REG
1µF
GND
1µF
Figure 2. Adjustable Output Operation
Precision enable
16-lead, 3 mm × 3 mm LFCSP package
APPLICATIONS
Table 1. Related Devices
Input
Voltage Current
Maximum Fixed/
Regulation to noise sensitive applications such as radio
frequency (RF) transceivers, analog-to-digital converter
(ADC) and digital-to-analog converter (DAC) circuits,
phase-locked loops (PLLs), voltage controlled oscillators
(VCOs) and clocking integrated circuits
Field-programmable gate array (FPGA) and digital signal
processor (DSP) supplies
Medical and healthcare
Device
Adjustable
Package
ADP1761 1.10 V to 1 A
1.98 V
ADP1762 1.10 V to 2 A
1.98 V
ADP1740/ 1.6 V to
ADP1741 3.6 V
ADP1752/ 1.6 V to
ADP1753 3.6 V
Fixed/adjustable 16-lead
LFCSP
Fixed/adjustable 16-lead
LFCSP
2 A
Fixed/adjustable 16-lead
LFCSP
0.8 A
1.2 A
Fixed/adjustable 16-lead
LFCSP
Fixed/adjustable 16-lead
LFCSP
Industrial and instrumentation
ADP1754/ 1.6 V to
ADP1755 3.6 V
GENERAL DESCRIPTION
The ADP1763 is a low noise, low dropout (LDO) linear regulator. It
is designed to operate from a single input supply with an input
voltage as low as 1.10 V without the requirement of an external bias
supply to increase efficiency and provide up to 3 A of output current.
The ADP1763 is available in fixed output voltages ranging from
0.9 V to 1.5 V. The output of the adjustable output model can be
set from 0.5 V to 1.5 V through an external resistor connected
between VADJ and ground.
The low 95 mV typical dropout voltage at a 3 A load allows the
ADP1763 to operate with a small headroom while maintaining
regulation and providing better efficiency.
The ADP1763 has an externally programmable soft start time by
connecting a capacitor to the SS pin. Short-circuit and thermal
overload protection circuits prevent damage in adverse conditions.
The ADP1763 is available in a small 16-lead LFCSP package for the
smallest footprint solution to meet a variety of applications.
The ADP1763 is optimized for stable operation with small 10 μF
ceramic output capacitors. The ADP1763 delivers optimal
transient performance with minimal board area.
Rev. 0
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Technical Support
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ADP1763* Product Page Quick Links
Last Content Update: 11/01/2016
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ADP1763
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Soft Start Function ..................................................................... 11
Adjustable Output Voltage........................................................ 12
Enable Feature ............................................................................ 12
Power-Good (PG) Feature ........................................................ 12
Applications Information.............................................................. 13
Capacitor Selection .................................................................... 13
Undervoltage Lockout ............................................................... 14
Current-Limit and Thermal Overload Protection................. 14
Paralleling ADP1763 for High Current Applications ............ 14
Thermal Considerations............................................................ 15
PCB Layout Considerations...................................................... 17
Outline Dimensions....................................................................... 18
Ordering Guide .......................................................................... 18
Applications....................................................................................... 1
General Description......................................................................... 1
Typical Application Circuits............................................................ 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Input and Output Capacitor: Recommended Specifications.. 4
Absolute Maximum Ratings............................................................ 5
Thermal Data................................................................................ 5
Thermal Resistance ...................................................................... 5
ESD Caution.................................................................................. 5
Pin Configuration and Function Descriptions............................. 6
Typical Performance Characteristics ............................................. 7
Theory of Operation ...................................................................... 11
REVISION HISTORY
4/16—Revision 0: Initial Version
Rev. 0 | Page 2 of 18
Data Sheet
ADP1763
SPECIFICATIONS
VIN = VOUT + 0.2 V or VIN = 1.1 V, whichever is greater, ILOAD = 10 mA, CIN = 10 μF, COUT = 10 μF, CREF = 1 μF, CREG = 1 μF, TA = 25°C,
Minimum and maximum limits at TJ = −40°C to +125°C, unless otherwise noted.
Table 2.
Parameter
Symbol
Test Conditions/Comments
Min
Typ Max
Unit
INPUT VOLTAGE SUPPLY RANGE
CURRENT
VIN
TJ = −40°C to +125°C
1.10
1.98
V
Operating Supply Current
IGND
ILOAD = 0 μA
ILOAD = 10 mA
ILOAD = 100 mA
ILOAD = 3 A
EN = GND
TJ = −40°C to +85°C,
VIN = (VOUT + 0.2 V) to 1.98 V
TJ = 85°C to 125°C,
VIN = (VOUT + 0.2 V) to 1.98 V
4.5
4.9
5.5
12
2
8
8
8.5
16
mA
mA
mA
mA
μA
Shutdown Current
OUTPUT NOISE1
IGND-SD
180
800
μA
μA
OUTNOISE
10 Hz to 100 kHz, VIN = 1.1 V, VOUT = 0.9 V
100 Hz to 100 kHz, VIN = 1.1 V, VOUT = 0.9 V
10 Hz to 100 kHz, VIN = 1.5 V, VOUT = 1.3 V
100 Hz to 100 kHz, VIN = 1.5 V, VOUT = 1.3 V
10 Hz to 100 kHz, VIN = 1.7 V, VOUT = 1.5 V
100 Hz to 100 kHz, VIN = 1.7 V, VOUT = 1.5 V
VOUT = 0.9 V to 1.5 V, ILOAD = 100 mA
At 10 kHz
12
2
15
2
21
2
μV rms
μV rms
μV rms
μV rms
μV rms
μV rms
Noise Spectral Density
OUTNSD
PSRR
4
3
nV/√Hz
nV/√Hz
At 100 kHz
POWER SUPPLY REJECTION RATIO1
ILOAD = 3 A, modulated VIN
10 kHz, VOUT = 1.3 V, VIN = 1.7 V
100 kHz, VOUT = 1.3 V, VIN = 1.7 V
1 MHz, VOUT = 1.3 V, VIN = 1.7 V
10 kHz, VOUT = 0.9 V, VIN = 1.3 V
100 kHz, VOUT = 0.9 V, VIN = 1.3 V
1 MHz, VOUT = 0.9 V, VIN = 1.3 V
59
43
37
62
45
33
dB
dB
dB
dB
dB
dB
OUTPUT VOLTAGE
Output Voltage Range
TA = 25°C
VOUT_FIXED
VOUT_ADJ
VOUT
0.9
0.5
−0.5
−1
1.5
1.5
+0.5
+1.5
V
V
%
%
Fixed Output Voltage Accuracy
ILOAD = 100 mA, TA = 25°C
10 mA < ILOAD < 3 A, VIN = (VOUT + 0.2 V) to
1.98 V, TJ = 0°C to 85°C
10 mA < ILOAD < 3 A, VIN = (VOUT + 0.2 V) to
1.98 V
−1.5
+1.5
%
ADJUSTABLE PIN CURRENT
IADJ
AD
TA = 25°C
VIN = (VOUT + 0.2 V) to 1.98 V
TA = 25°C
49.5
48.8
50.0 50.5
50.0 51.0
3.0
μA
μA
ADJUSTABLE OUTPUT VOLTAGE GAIN FACTOR
VIN = (VOUT + 0.2 V) to 1.98 V
2.95
3.055
REGULATION
Line Regulation
Load Regulation2
DROPOUT VOLTAGE3
∆VOUT/∆VIN
∆VOUT/∆IOUT ILOAD = 10 mA to 3 A
VIN = (VOUT + 0.2 V) to 1.98 V
−0.15
+0.15 %/V
0.12 0.45
%/A
mV
mV
ms
μA
A
VDROPOUT
ILOAD = 100 mA, VOUT ≥ 1.2 V
12
95
0.6
10
4
23
ILOAD = 3 A, VOUT ≥ 1.2 V
CSS = 10 nF, VOUT = 1.3 V
1.1 V ≤ VIN ≤ 1.98 V
145
START-UP TIME1, 4
tSTART-UP
ISS
SOFT START CURRENT
CURRENT-LIMIT THRESHOLD5
8
12
5
ILIMIT
3.3
Rev. 0 | Page 3 of 18
ADP1763
Data Sheet
Parameter
Symbol
Test Conditions/Comments
Min
Typ Max
Unit
THERMAL SHUTDOWN
Threshold
Hysteresis
TSSD
TSSD-HYS
TJ rising
150
15
°C
°C
POWER-GOOD (PG) OUTPUT THRESHOLD
Output Voltage
Falling
PGFALL
PGRISE
1.1 V ≤ VIN ≤ 1.98 V
1.1 V ≤ VIN ≤ 1.98 V
−7.5
−5
%
%
Rising
PG OUTPUT
Output Voltage Low
Leakage Current
Delay1
PGLOW
IPG-LKG
PGDELAY
1.1 V ≤ VIN ≤ 1.98 V, IPG ≤ 1 mA
1.1 V ≤ VIN ≤ 1.98 V
ENRISING to PGRISING
0.35
1
V
μA
ms
0.01
0.75
PRECISION EN INPUT
Logic Input
1.1 V ≤ VIN ≤ 1.98 V
High
Low
ENHIGH
ENLOW
ENHYS
IEN-LKG
tIEN-DLY
UVLO
595
550
625
580
45
0.01
100
690
630
mV
mV
mV
μA
μs
Input Logic Hysteresis
Input Leakage Current
Input Delay Time
UNDERVOLTAGE LOCKOUT
Input Voltage
Rising
EN = VIN or GND
From EN rising from 0 V to VIN to 0.1 × VOUT
1
UVLORISE
UVLOFALL
UVLOHYS
TJ = −40°C to +125°C
TJ = −40°C to +125°C
1.01 1.06
0.93
80
V
V
mV
Falling
Hysteresis
0.87
1 Guaranteed by design and characterization; not production tested.
2 Based on an endpoint calculation using 10 mA and 3 A loads.
3 Dropout voltage is defined as the input to output voltage differential when the input voltage is set to the nominal output voltage, which applies only for output
voltages above 1.1 V.
4 Start-up time is defined as the time from the rising edge of EN to VOUT being at 90% of its nominal value.
5 Current-limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 1.0 V
output voltage is defined as the current that causes the output voltage to drop to 90% of 1.0 V, or 0.9 V.
INPUT AND OUTPUT CAPACITOR: RECOMMENDED SPECIFICATIONS
Table 3.
Parameter
CAPACITANCE1
Symbol
Test Conditions/Comments
Min
Typ
Max
Unit
TA = −40°C to +125°C
Input
Output
Regulator
Reference
CIN
7.0
7.0
0.7
0.7
10
10
1
μF
μF
μF
μF
COUT
CREG
CREF
RESR
1
CAPACITOR EQUIVALENT SERIES RESISTANCE (ESR)
TA = −40°C to +125°C
CIN, COUT
CREG, CREF
0.001
0.001
0.5
0.2
Ω
Ω
1 The minimum input and output capacitance must be >7.0 μF over the full range of the operating conditions. Consider the full range of the operating conditions in the
application during device selection to ensure that the minimum capacitance specification is met. X7R and X5R type capacitors are recommended. Y5V and Z5U
capacitors are not recommended for use with any LDO.
Rev. 0 | Page 4 of 18
Data Sheet
ADP1763
ABSOLUTE MAXIMUM RATINGS
The junction to ambient thermal resistance is highly dependent
on the application and board layout. In applications where high
maximum power dissipation exists, close attention to thermal
board design is required. The value of θJA may vary, depending on
PCB material, layout, and environmental conditions. The specified
values of θJA are based on a 4-layer, 4 in × 3 in circuit board. For
details about board construction, refer to JEDEC JESD51-7.
Table 4.
Parameter
Rating
VIN to GND
EN to GND
VOUT to GND
SENSE to GND
VREG to GND
REFCAP to GND
VADJ to GND
SS to GND
−0.3 V to +2.16 V
−0.3 V to +3.96 V
−0.3 V to VIN
−0.3 V to VIN
−0.3 V to VIN
−0.3 V to VIN
−0.3 V to VIN
−0.3 V to VIN
−0.3 V to +3.96 V
−65°C to +150°C
−40°C to +125°C
125°C
ΨJB is the junction to board thermal characterization parameter
with units of °C/W. ΨJB of the package is based on modeling and
a calculation using a 4-layer board. The JEDEC JESD51-12
document, Guidelines for Reporting and Using Package Thermal
Information, states that thermal characterization parameters are
not the same as thermal resistances. ΨJB measures the component
power flowing through multiple thermal paths rather than a single
path, as in thermal resistance (θJB). Therefore, ΨJB thermal paths
include convection from the top of the package as well as radiation
from the package, factors that make ΨJB more useful in real-world
applications. The maximum junction temperature (TJ) is calculated
from the board temperature (TB) and power dissipation (PD), using
the following formula:
PG to GND
Storage Temperature Range
Operating Temperature Range
Operating Junction Temperature
Lead Temperature (Soldering, 10 sec)
300°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
TJ = TB + (PD × ΨJB)
Refer to the JEDEC JESD51-8 and JESD51-12 documents for
more detailed information about ΨJB.
THERMAL DATA
THERMAL RESISTANCE
Absolute maximum ratings apply only individually, not in
combination. The ADP1763 may be damaged when junction
temperature limits are exceeded. Monitoring ambient temperature
does not guarantee that the junction temperature is within the
specified temperature limits. In applications with high power
dissipation and poor thermal resistance, the maximum ambient
temperature may need to be derated.
θJA and ΨJB are specified for the worst case conditions, that is, a
device soldered in a circuit board for surface-mount packages.
Table 5. Thermal Resistance for a 4-Layer 6400 mm2 Copper Size
Package Type
θJA
ΨJB
Unit
16-Lead LFCSP
56
28.4
°C/W
In applications with moderate power dissipation and low printed
circuit board (PCB) thermal resistance, the maximum ambient
temperature can exceed the maximum limit as long as the junction
temperature is within specification limits. The junction temperature
(TJ) of the device is dependent on the ambient temperature (TA),
the power dissipation of the device (PD), and the junction to
ambient thermal resistance of the package (θJA). TJ is calculated
using the following formula:
ESD CAUTION
TJ = TA + (PD × θJA)
The junction to ambient thermal resistance (θJA) of the package
is based on modeling and a calculation using a 4-layer board.
Rev. 0 | Page 5 of 18
ADP1763
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
VIN 1
VIN 2
VIN 3
12 VOUT
11 VOUT
ADP1763
TOP VIEW
10
9
VOUT
VOUT
(Not to Scale)
4
VIN
NOTES
1. THE EXPOSED PAD IS ELECTRICALLY
CONNECTED TO GND. IT IS RECOMMENDED
THAT THIS PAD BE CONNECTED TO A GROUND
PLANE ON THE PCB. THE EXPOSED PAD IS
ON THE BOTTOM OF THE PACKAGE.
Figure 3. Pin Configuration
Table 6. Pin Function Descriptions
Pin No. Mnemonic Description
1 to 4
VIN
Regulator Input Supply. Bypass VIN to GND with a 10 μF or greater capacitor. Note that all four VIN pins must be
connected to the source supply.
5
6
REFCAP
VREG
Reference Filter Capacitor. Connect a 1 μF capacitor from the REFCAP pin to ground. Do not connect a load to
ground.
Regulated Input Supply to LDO Amplifier. Bypass VREG to GND with a 1 μF or greater capacitor. Do not connect
a load to ground.
7
8
GND
VADJ
Ground.
Adjustable Voltage Pin for the Adjustable Output Option. Connect a 10 kΩ external resistor between the VADJ
pin and ground to set the output voltage to 1.5 V. For the fixed output option, leave this pin floating.
9 to 12
13
VOUT
Regulated Output Voltage. Bypass VOUT to GND with a 10 μF or greater capacitor. Note that all four VOUT pins
must be connected to the load.
Sense Input. The SENSE pin measures the actual output voltage at the load and feeds it to the error amplifier.
Connect VSENSE as close to the load as possible to minimize the effect of IR voltage drop between VOUT and the load.
SENSE
14
15
SS
PG
Soft Start Pin. A 10 nF capacitor connected to the SS pin and ground sets the start-up time to 0.6 ms.
Power-Good Output. This open-drain output requires an external pull-up resistor. If the device is in shutdown
mode, current-limit mode, or thermal shutdown mode, or if VOUT falls below 90% of the nominal output
voltage, the PG pin immediately transitions low.
16
EN
EP
Enable Input. Drive the EN pin high to turn on the regulator. Drive the EN pin low to turn off the regulator. For
automatic startup, connect the EN pin to the VIN pin.
Exposed Pad. The exposed pad is electrically connected to GND. It is recommended that this pad be connected
to a ground plane on the PCB. The exposed pad is on the bottom of the package.
Rev. 0 | Page 6 of 18
Data Sheet
ADP1763
TYPICAL PERFORMANCE CHARACTERISTICS
VIN = 1.5 V, VOUT = 1.3 V, TA = 25°C, unless otherwise noted.
1.305
16
14
12
10
8
NO LOAD
I
I
I
I
I
= 10mA
= 100mA
= 1A
LOAD
LOAD
LOAD
LOAD
LOAD
1.303
1.301
1.299
1.297
1.295
= 2A
= 3A
6
4
I
I
I
= 10mA
= 500mA
= 2A
LOAD
LOAD
LOAD
2
= 100mA
= 1A
0
–50
–50
–25
0
25
50
75
100
125
150
–25
0
25
50
75
100
125
150
JUNCTION TEMPERATURE (°C)
JUNCTION TEMPERATURE (°C)
Figure 4. Output Voltage (VOUT) vs. Junction Temperature
Figure 7. Ground Current vs. Junction Temperature
1.303
14
12
10
8
1.303
1.302
1.302
1.301
6
4
2
0
0.01
0.01
0.1
1
10
0.1
1
10
LOAD CURRENT (A)
LOAD CURRENT (A)
Figure 5. Output Voltage (VOUT) vs. Load Current
Figure 8. Ground Current vs. Load Current
1.310
1.308
1.306
1.304
1.302
1.300
1.298
14
12
10
8
I
I
I
I
= 100mA
= 1A
LOAD
LOAD
LOAD
LOAD
= 2A
= 3A
6
NO LOAD
4
I
I
I
I
I
I
= 10mA
= 100mA
= 500mA
= 1A
LOAD
LOAD
LOAD
LOAD
LOAD
LOAD
2
= 2A
= 3A
0
1.5
1.5
1.6
1.7
1.8
1.9
2.0
1.6
1.7
1.8
1.9
2.0
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
Figure 6. Output Voltage vs. Input Voltage
Figure 9. Ground Current vs. Input Voltage
Rev. 0 | Page 7 of 18
ADP1763
Data Sheet
14
12
10
8
200
V
V
V
V
V
V
= 1.5V
= 1.7V
= 1.9V
= 1.6V
= 1.8V
= 1.98V
IN
IN
IN
IN
IN
IN
180
160
140
120
100
80
6
60
NO LOAD
4
40
I
I
I
I
I
I
= 10mA
= 100mA
= 500mA
= 1A
LOAD
LOAD
LOAD
LOAD
LOAD
LOAD
20
2
0
= 2A
= 3A
0
1.1
–20
–50
1.2
1.3
1.4
1.5
1.6
–25
0
25
50
75
100
125
150
INPUT VOLTAGE (V)
JUNCTION TEMPERATURE (°C)
Figure 10. Shutdown Current vs. Junction Temperature at
Figure 13. Ground Current vs. Input Voltage (in Dropout), VOUT = 1.3 V
Various Input Voltages (VIN
)
100
90
80
70
60
50
40
30
20
10
0
3A/µs SLEW RATE
LOAD
2
V
OUT
1
B
CH1 50.0mV
CH2 2.00A M4.00µs
18.70%
A CH2
640mA
W
0.1
1
10
T
LOAD CURRENT (A)
Figure 11. Dropout Voltage vs. Load Current, VOUT = 1.3 V
Figure 14. Load Transient Response, COUT = 10 μF, VIN = 1.8 V, VOUT = 1.3 V
1.35
1.30
1.25
1.20
1.15
1.10
I
I
I
I
= 100mA
= 1A
LOAD
LOAD
LOAD
LOAD
= 2A
3A/µs SLEW RATE
= 3A
LOAD
2
V
OUT
1
B
CH1 50.0mV
CH2 2.00A M4.00µs
18.70%
A CH2
640mA
W
1.2
1.3
1.4
1.5
T
INPUT VOLTAGE (V)
Figure 12. Output Voltage vs. Input Voltage (in Dropout), VOUT = 1.3 V
Figure 15. Load Transient Response, COUT = 47 μF, VIN = 1.8 V, VOUT = 1.3 V
Rev. 0 | Page 8 of 18
Data Sheet
ADP1763
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
V
V
V
V
V
V
= 1.1V
= 1.2V
= 1.3V
= 1.4V
= 1.5V
= 1.6V
IN
IN
IN
IN
IN
IN
1V/µs SLEW RATE
V
IN
2
1
V
OUT
CH1 5.00mV
CH2 500mV
M2.00µs
17.50%
A CH2
1.68V
1
10
100
1k
10k
100k
1M
10M
T
FREQUENCY (Hz)
Figure 19. Power Supply Rejection Ratio (PSRR) vs. Frequency for
Various Loads, VOUT = 0.9 V, Load Current = 3 A
Figure 16. Line Transient Response, Load Current = 3 A,
VIN = 1.5 V to 1.98 V Step, VOUT = 1.3 V
–10
–20
–30
–40
–50
–60
–70
–80
16
14
12
10
8
V
V
= 1.3V (100Hz TO 100kHz)
= 1.3V (10Hz TO 100kHz)
OUT
OUT
6
V
V
V
V
V
V
= 1.5V
= 1.6V
= 1.7V
= 1.8V
= 1.9V
= 1.98V
4
IN
IN
IN
IN
IN
IN
–90
–100
–110
2
0
0.1
1
10
100
1k
10k
100k
1M
10M
1
10
FREQUENCY (Hz)
LOAD CURRENT (A)
Figure 17. Noise vs. Load Current for Various Output Voltages
Figure 20. Power Supply Rejection Ratio (PSRR) vs. Frequency for
Various Loads, VOUT = 1.3 V, Load Current = 3 A
10k
–10
V
V
V
V
= 1.7V
= 1.8V
= 1.9V
= 1.98V
IN
IN
IN
IN
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
1k
100
10
1
V
V
V
= 0.9V
= 1.3V
= 1.5V
OUT
OUT
OUT
0.1
10
100
1k
10k
100k
1
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 21. Power Supply Rejection Ratio (PSRR) vs. Frequency for
Various Loads, VOUT = 1.5 V, Load Current = 3 A
Figure 18. Noise Spectral Density vs. Frequency for Various Output Voltages,
LOAD = 100 mA
I
Rev. 0 | Page 9 of 18
ADP1763
Data Sheet
–10
I
I
I
I
= 500mA
= 1A
LOAD
LOAD
LOAD
LOAD
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
= 2A
= 3A
1
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 22. Power Supply Rejection Ratio (PSRR) vs. Frequency for
Various Input Voltages, VOUT = 1.3 V, VIN = 1.7 V
Rev. 0 | Page 10 of 18
Data Sheet
ADP1763
THEORY OF OPERATION
The ADP1763 is an LDO, low noise linear regulator that uses an
advanced proprietary architecture to achieve high efficiency
regulation. It also provides high PSRR and excellent line and load
transient response using a small 10 F ceramic output capacitor.
The device operates from a 1.10 V to 1.98 V input rail to
provide up to 3 A of output current. Supply current in
shutdown mode is typically 2 μA.
operating conditions. When EN is high, VOUT turns on. When
EN is low, VOUT turns off. For automatic startup, tie EN to VIN.
SOFT START FUNCTION
For applications that require a controlled startup, the ADP1763
provides a programmable soft start function. The programmable
soft start is useful for reducing inrush current upon startup and
for providing voltage sequencing. To implement soft start, connect
a small ceramic capacitor from SS to GND. At startup, a 10 μA
current source charges this capacitor. The voltage at SS limits
the ADP1763 start-up output voltage, providing a smooth ramp-up
to the nominal output voltage. To calculate the start-up time for
the fixed output and adjustable output, use the following equations:
ADP1763
VIN
VOUT
INTERNAL
BIAS SUPPLY
SHORT-CIRCUIT,
THERMAL PROJECT
VREG
SENSE
t
START-UP_FIXED = tDELAY + VREF × (CSS/ISS)
(1)
t
START-UP_ADJ = tDELAY + VADJ × (CSS/ISS)
(2)
where:
DELAY is a fixed delay of 100 μs.
REF is a 0.5 V internal reference for the fixed output model option.
CSS is the soft start capacitance from SS to GND.
ISS is the current sourced from SS (10 μA).
PG
SS
REFERENCE,
BIAS
EN
t
V
GND
SS BLOCK
V
ADJ is the voltage at the VADJ pin equal to RADJ × IADJ.
REFCAP
1.7
Figure 23. Functional Block Diagram, Fixed Output
1.5
1.3
1.1
0.9
0.7
0.5
ADP1763
VIN
VOUT
INTERNAL
BIAS SUPPLY
SHORT-CIRCUIT,
THERMAL PROJECT
VREG
SENSE
I
ADJ
EN
VADJ
0.3
EN
PG
SS
C
C
C
= 0nF
SS
SS
SS
0.1
= 10nF
= 22nF
–0.1
–0.2
0.3
0.8
1.3
1.8
TIME (ms)
GND
SS BLOCK
Figure 25. Fixed VOUT Ramp-Up with External Soft Start Capacitor (VOUT, EN) vs. Time
2.0
REFCAP
Figure 24. Functional Block Diagram, Adjustable Output
1.5
1.0
0.5
Internally, the ADP1763 consists of a reference, an error amplifier,
and a pass device. The output current is delivered via the pass
device, which is controlled by the error amplifier, forming a
negative feedback system that ideally drives the feedback voltage
to equal the reference voltage. If the feedback voltage is lower
than the reference voltage, the negative feedback drives more
current, increasing the output voltage. If the feedback voltage is
higher than the reference voltage, the negative feedback drives
less current, decreasing the output voltage.
EN
0
V
V
V
V
= 0.5V; C = 10nF
SS
OUT
OUT
OUT
OUT
= 0.5V; C = 22nF
SS
= 1.5V; C = 10nF
SS
= 1.5V; C = 22nF
SS
The ADP1763 is available in output voltages ranging from 0.9 V to
1.5 V for a fixed output. Contact a local Analog Devices, Inc.,
sales representative for other fixed voltage options. The adjustable
output option can be set from 0.5 V to 1.5 V. The ADP1763 uses
the EN pin to enable and disable the VOUT pin under normal
–0.5
–0.2
0.3
0.8
1.3
1.8
TIME (ms)
Figure 26. Adjustable VOUT Ramp-Up with External Soft Start Capacitor
(VOUT, EN) vs. Time
Rev. 0 | Page 11 of 18
ADP1763
Data Sheet
ADJUSTABLE OUTPUT VOLTAGE
POWER-GOOD (PG) FEATURE
The output voltage of the ADP1763 can be set over a 0.5 V to
1.5 V range. Connect a resistor (RADJ) from the VADJ pin to
ground to set the output voltage. To calculate the output voltage,
use the following equation:
The ADP1763 provides a power-good pin (PG) to indicate the
status of the output. This open-drain output requires an external
pull-up resistor that can be connected to VIN or VOUT. If the
device is in shutdown mode, current-limit mode, or thermal
shutdown, or if it falls below 90% of the nominal output voltage,
PG immediately transitions low. During soft start, the rising
threshold of the power-good signal is 95% of the nominal
output voltage.
V
OUT = AD × (RADJ × IADJ
)
(3)
where:
AD is the gain factor with a typical value of 3.0 between the
VADJ pin and the VOUT pin.
The open-drain output is held low when the ADP1763 has
sufficient input voltage to turn on the internal PG transistor. An
optional soft start delay can be detected. The PG transistor is
terminated via a pull-up resistor to VOUT or VIN.
I
ADJ is the 50.0 μA constant current out of the VADJ pin.
ENABLE FEATURE
The ADP1763 uses the EN pin to enable and disable the VOUT
pins under normal operating conditions. As shown in Figure 27,
when a rising voltage on EN crosses the active threshold, VOUT
turns on. When a falling voltage on EN crosses the inactive
threshold, VOUT turns off.
Power-good accuracy is 92.5% of the nominal regulator output
voltage when this voltage is rising, with a 95% trip point when
this voltage is falling.
Regulator input voltage brownouts or glitches trigger a power
no good if VOUT falls below 92.5%.
EN
A normal power-down triggers a power good when VOUT is at 95%.
V
OUT
V
IN
1
2
4
V
OUT
1
B
B
W
CH1 200mV
CH2 200mV
M4.0ms
A CH1
768mV
W
PG
T
8.26ms
Figure 27. Typical EN Pin Operation
CH1 1.00V
CH2 1.00V
CH4 1.00V
M100µs
A CH4
420mV
As shown in Figure 28, the EN pin has hysteresis built in. This
hysteresis prevents on/off oscillations that can occur due to
noise on the EN pin as it passes through the threshold points.
T
228.0000µs
Figure 29. Typical PG Behavior vs. VOUT, VIN Rising (VOUT = 1.3 V)
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
V
IN
1
2
4
V
OUT
PG
0
0.55 0.56 0.57 0.58 0.59 0.60 0.61 0.62 0.63 0.64 0.65
CH1 1.00V
CH2 1.00V
CH4 1.00V
M200µs
0.000000s
A CH1
3.00V
EN VOLTAGE (V)
T
Figure 28. Output Voltage vs. Typical EN Pin Voltage, VOUT = 1.3 V
Figure 30. Typical PG Behavior vs. VOUT, VIN Falling (VOUT = 1.3 V)
Rev. 0 | Page 12 of 18
Data Sheet
ADP1763
APPLICATIONS INFORMATION
CAPACITOR SELECTION
Input and Output Capacitor Properties
Use any good quality ceramic capacitors with the ADP1763, as
long as they meet the minimum capacitance and maximum ESR
requirements. Ceramic capacitors are manufactured with a variety
of dielectrics, each with different behavior over temperature and
applied voltage. Capacitors must have a dielectric adequate to
ensure the minimum capacitance over the necessary temperature
range and dc bias conditions. X5R or X7R dielectrics with a
voltage rating of 6.3 V or 10 V are recommended. Y5V and Z5U
dielectrics are not recommended, due to their poor temperature
and dc bias characteristics.
Output Capacitor
The ADP1763 is designed for operation with small, space-saving
ceramic capacitors, but it can function with most commonly used
capacitors as long as care is taken with the effective series
resistance (ESR) value. The ESR of the output capacitor affects
the stability of the LDO control loop. A minimum of 10 μF
capacitance with an ESR of 500 mΩ or less is recommended to
ensure the stability of the ADP1763. Transient response to changes
in load current is also affected by output capacitance. Using a
larger value of output capacitance improves the transient response
of the ADP1763 to large changes in load current. Figure 31 and
Figure 32 show the transient responses for output capacitance
values of 10 μF and 47 μF, respectively.
Figure 33 shows the capacitance vs. bias voltage characteristics
of an 0805 case, 10 μF, 10 V, X5R capacitor. The voltage stability
of a capacitor is strongly influenced by the capacitor size and
voltage rating. In general, a capacitor in a larger package or with
a higher voltage rating exhibits better stability. The temperature
variation of the X5R dielectric is about 15% over the −40°C to
+85°C temperature range and is not a function of package size
or voltage rating.
I
LOAD
2
12
V
OUT
10
8
1
6
B
CH1 50.0mV
CH2 2.00A M1.00µs
18.70%
A CH2
640mA
W
4
T
Figure 31. Output Transient Response, COUT = 10 μF
2
0
0
1
2
3
4
5
6
DC BIAS VOLTAGE (V)
I
LOAD
Figure 33. Capacitance vs. DC Bias Voltage
2
1
Use Equation 4 to determine the worst case capacitance,
accounting for capacitor variation over temperature, component
tolerance, and voltage.
V
OUT
CEFF = COUT × (1 − tempco) × (1 − TOL)
(4)
where:
CEFF is the effective capacitance at the operating voltage.
C
OUT is the output capacitor.
CH1 50.0mV
CH2 2.00A M1.00µs
19.00%
A CH2
640mA
T
Tempco is the worst case capacitor temperature coefficient.
TOL is the worst case component tolerance.
Figure 32. Output Transient Response, COUT = 47 μF
Input Bypass Capacitor
In this example, the worst case temperature coefficient
(tempco) over −40°C to +85°C is assumed to be 15% for an X5R
dielectric. The tolerance of the capacitor (TOL) is assumed to
be 10%, and COUT = 10 μF at 1.0 V, as shown in Figure 33.
Connecting a 10 μF capacitor from the VIN pin to the GND pin
to ground reduces the circuit sensitivity to the PCB layout,
especially when long input traces or a high source impedance
is encountered. If output capacitance greater than 10 μF is
required, it is recommended that the input capacitor be increased
to match it.
Substituting these values in Equation 4 yields
CEFF = 10 ꢀF × (1 − 0.15) × (1 − 0.1) = 7.65 ꢀF
Rev. 0 | Page 13 of 18
ADP1763
Data Sheet
Therefore, the capacitor chosen in this example meets the
minimum capacitance requirement of the LDO over temperature
and tolerance at the chosen output voltage.
Consider the case where a hard short from VOUT to ground
occurs. At first, the ADP1763 reaches the current limit so that
only 4 A is conducted into the short circuit. If self heating of the
junction becomes great enough to cause its temperature to rise
above 150°C, thermal shutdown activates, turning off the output
and reducing the output current to zero. As the junction
temperature cools and drops below 135°C, the output turns on
and conducts 4 A into the short circuit, again causing the
junction temperature to rise above 150°C. This thermal oscillation
between 135°C and 150°C causes a current oscillation between
4 A and 0 A that continues as long as the short circuit remains
at the output.
To guarantee the performance of the ADP1763, it is imperative
that the effects of dc bias, temperature, and tolerances on the
behavior of the capacitors be evaluated for each application.
UNDERVOLTAGE LOCKOUT
The ADP1763 has an internal undervoltage lockout circuit that
disables all inputs and the output when the input voltage is less
than approximately 1.06 V. The UVLO ensures that the ADP1763
inputs and the output behave in a predictable manner during
power-up.
Current-limit and thermal overload protections are intended to
protect the device against accidental overload conditions. For
reliable operation, limit device power dissipation externally so that
junction temperatures do not exceed 125°C.
CURRENT-LIMIT AND THERMAL OVERLOAD
PROTECTION
The ADP1763 is protected against damage due to excessive power
dissipation by current-limit and thermal overload protection
circuits. The ADP1763 is designed to reach the current limit
when the output load reaches 4 A (typical). When the output
load exceeds 4 A, the output voltage is reduced to maintain a
constant current limit.
PARALLELING ADP1763 FOR HIGH CURRENT
APPLICATIONS
In applications where high output current is required while
maintaining low noise and high PSRR performance, connect two
ADP1763 devices in parallel to handle loads up to 5 A.
Thermal overload protection is included, which limits the
junction temperature to a maximum of 150°C (typical). Under
extreme conditions (that is, high ambient temperature and power
dissipation) when the junction temperature begins to rise above
150°C, the output is turned off, reducing the output current to
zero. When the junction temperature drops below 135°C (typical),
the output is turned on again, and the output current is restored
to its nominal value.
When paralleling the ADP1763, the two outputs must be of the
same voltage setting to maintain stable current sharing between
the two LDO regulators. To improve current sharing accuracy, add
identical ballast resistors (RBALLAST) at the output of each regulator,
as shown in Figure 34. Note that large ballast resistors improve
current sharing accuracy but degrade the load regulation perform-
ance and increase the losses along the power line; therefore, it is
recommended to keep the ballast resistors at a minimum. In
addition, tie the VADJ, SS, and REFCAP pins of the LDO regu-
lators together to minimize error between the two outputs.
ADP1763
R
= 5mΩ
V
= 1.5V
BALLAST
V
= 1.2V/5A
IN
OUT
VIN
VOUT
C
C
OUT
IN
10µF
10µF
SENSE
EN
R
PULLUP
ENABLE
100kΩ
PG
SS
VADJ
R
ADJ
C
1nF
4.02kΩ
SS
VREG
REFCAP
C
1µF
REF
C
1µF
GND
REG
ADP1763
R
= 5mΩ
BALLAST
VIN
VOUT
C
C
OUT
IN
10µF
10µF
SENSE
EN
PG
SS
VADJ
VREG
REFCAP
C
1µF
C
1µF
REF
GND
REG
Figure 34. Two ADP1763 Devices Connected in Parallel to Achieve Higher Current Output
Rev. 0 | Page 14 of 18
Data Sheet
ADP1763
Use Equation 5 to calculate the output of the two paralleled
ADP1763 LDOs.
Figure 35 through Figure 40 show junction temperature calculations
for different ambient temperatures, load currents, VIN to VOUT
differentials, and areas of PCB copper.
140
V
OUT = 2 × AD × (RADJ × IADJ
)
(5)
where:
T
MAX
J
AD is the gain factor with a typical value of 3.0 between the
VADJ pin and the VOUT pin.
120
100
80
60
40
20
0
3A
2A
I
ADJ is the 50.0 μA constant current out of the VADJ pin.
1A
THERMAL CONSIDERATIONS
500mA
To guarantee reliable operation, the junction temperature of the
ADP1763 must not exceed 125°C. To ensure that the junction
temperature stays below this maximum value, the user needs to be
aware of the parameters that contribute to junction temperature
changes. These parameters include ambient temperature, power
dissipation in the power device, and thermal resistance between
the junction and ambient air (θJA). The θJA value is dependent
on the package assembly compounds used and the amount of
copper to which the GND pin and the exposed pad (EPAD) of the
package are soldered on the PCB. Table 7 shows typical θJA values
for the 16-lead LFCSP for various PCB copper sizes. Table 8
shows typical ΨJB values for the 16-lead LFCSP.
100mA
10mA
0.2
0.4
0.6
0.8
– V
1.0
(V)
1.2
1.4
1.6
V
IN
OUT
Figure 35. 6400 mm2 of PCB Copper, TA = 25°C
140
120
100
80
T
MAX
J
2A
3A
1A
Table 7. Typical θJA Values
Copper Size (mm2)
θJA (°C/W), LFCSP
500mA
25
138.1
102.9
76.9
67.3
56
100
500
1000
6400
60
100mA
40
10mA
1.2
20
Table 8. Typical ΨJB Values
0
0.2
Copper Size (mm2)
ΨJB (°C/W) at 1 W
0.4
0.6
0.8
– V
1.0
(V)
1.4
1.6
V
IN
OUT
100
500
1000
33.3
28.9
28.5
Figure 36. 500 mm2 of PCB Copper, TA = 25°C
140
120
100
80
T
MAX
J
To calculate the junction temperature of the ADP1763, use the
following equation:
3A
1A
2A
TJ = TA + (PD × θJA)
where:
(6)
500mA
TA is the ambient temperature.
60
PD is the power dissipation in the die, given by
100mA
40
PD = ((VIN − VOUT) × ILOAD) + (VIN × IGND
where:
VIN and VOUT are the input and output voltages, respectively.
)
(7)
10mA
20
0
0.2
I
I
LOAD is the load current.
GND is the ground current.
0.4
0.6
0.8
– V
1.0
(V)
1.2
1.4
1.6
V
IN
OUT
Figure 37. 25 mm2 of PCB Copper, TA = 25°C
As shown in Equation 6, for a given ambient temperature, and
computed power dissipation, a minimum copper size
requirement exists for the PCB to ensure that the junction
temperature does not rise above 125°C.
Rev. 0 | Page 15 of 18
ADP1763
Data Sheet
140
Figure 41 through Figure 44 show junction temperature calculations
for different board temperatures, load currents, VIN to VOUT
differentials, and areas of PCB copper.
140
T
MAX
J
120
3A
1A
2A
100
80
60
40
20
500mA
T
MAX
J
120
100
80
60
40
20
0
3A
100mA
10mA
2A
1A
500mA
100mA
10mA
0
0.2
0.4
0.6
0.8
– V
1.0
(V)
1.2
1.4
1.6
V
IN
OUT
Figure 38. 6400 mm2 of PCB Copper, TA = 50°C
140
120
100
80
0.2
0.4
0.6
0.8
– V
1.0
(V)
1.2
1.4
1.6
T
MAX
J
V
IN
OUT
Figure 41. 500 mm2 of PCB Copper, TB = 25°C
3A
2A
1A
140
120
100
80
T
MAX
J
500mA
3A
2A
100mA
10mA
60
1A
40
500mA
100mA
10mA
60
20
40
0
0.2
0.4
0.6
0.8
– V
1.0
(V)
1.2
1.4
1.6
V
IN
OUT
20
Figure 39. 500 mm2 of PCB Copper, TA = 50°C
0
140
120
100
80
0.2
0.4
0.6
0.8
– V
1
1.2
1.4
1.6
3A
T
MAX
J
V
(V)
OUT
IN
Figure 42. 500 mm2 of PCB Copper, TB = 50°C
2A
1A
500mA
140
120
100
80
T
MAX
J
3A
100mA
60
2A
1A
10mA
40
60
20
500mA
100mA
10mA
40
0
0.2
0.4
0.6
0.8
– V
1.0
(V)
1.2
1.4
1.6
V
IN
OUT
20
Figure 40. 25 mm2 of PCB Copper, TA = 50°C
0
0.2
0.4
0.6
0.8
– V
1.0
(V)
1.2
1.4
1.6
In cases where the board temperature is known, the thermal
characterization parameter (ΨJB) can be used to estimate the
junction temperature rise. The maximum junction temperature
(TJ) is calculated from the board temperature (TB) and power
dissipation (PD) using the following formula:
V
IN
OUT
Figure 43. 1000 mm2 of PCB Copper, TB = 25°C
TJ = TB + (PD × ΨJB)
(8)
Rev. 0 | Page 16 of 18
Data Sheet
ADP1763
140
120
100
80
Use of 0603 or 0805 size capacitors and resistors achieves the
smallest possible footprint solution on boards where area is
limited.
T
MAX
J
2A
3A
1A
500mA
100mA
10mA
60
40
20
0
0.2
0.4
0.6
0.8
– V
1.0
(V)
1.2
1.4
1.6
V
IN
OUT
Figure 44. 1000 mm2 of PCB Copper, TB = 50°C, LFCSP
T
= 112°C
ADP1763
Figure 46. Evaluation Board
T
= 92°C
B
Figure 45. Thermal Image of the ADP1763 Evaluation Board at ILOAD = 3 A,
IN = 1.5 V, VOUT = 1.3 V, TB = 92°C
V
Figure 45 shows a thermal image of the ADP1763 evaluation
board operating at a 3 A current load. The total power dissipation
on the ADP1763 is 600 mW, which makes the temperature on
the surface of the device higher by 30°C than the temperature of
the evaluation board.
PCB LAYOUT CONSIDERATIONS
Heat dissipation from the package can be improved by increasing
the amount of copper attached to the pins of ADP1763. However,
as shown in Table 8, a point of diminishing returns is eventually
reached, beyond which an increase in the copper size does not
yield significant heat dissipation benefits.
Figure 47. Typical Board Layout, Top Side
Use the following recommendations when designing PCBs:
Place the input capacitor as close as possible to the VIN
and GND pins.
Place the output capacitor as close as possible to the VOUT
and GND pins.
Place the soft start capacitor (CSS) as close as possible to the
SS pin.
Place the reference capacitor (CREF) and regulator capacitor
(CREG) as close as possible to the REFCAP pin and VREG pin,
respectively.
Connect the load as close as possible to the VOUT and
SENSE pins.
Figure 48. Typical Board Layout, Bottom Side
Rev. 0 | Page 17 of 18
ADP1763
Data Sheet
OUTLINE DIMENSIONS
3.10
3.00 SQ
2.90
0.30
0.23
0.18
PIN 1
INDICATOR
PIN 1
INDICATOR
13
16
0.50
BSC
1
4
12
EXPOSED
PAD
1.75
1.60 SQ
1.45
9
8
5
0.50
0.40
0.30
0.25 MIN
TOP VIEW
BOTTOM VIEW
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.80
0.75
0.70
0.05 MAX
0.02 NOM
COPLANARITY
0.08
SECTION OF THIS DATA SHEET.
SEATING
PLANE
0.20 REF
COMPLIANT TO JEDEC STANDARDS MO-220-WEED-6.
Figure 49. 16-Lead Lead Frame Chip Scale Package [LFCSP]
3 mm × 3 mm Body and 0.75 mm Package Height
(CP-16-22)
Dimensions shown in millimeters
ORDERING GUIDE
Output
Package
Option
Model1
Temperature Range Voltage (V)2 Package Description
Branding
ADP1763ACPZ-R7
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Adjustable
0.9
0.95
1.0
1.1
1.2
1.25
1.3
1.5
1.3
1.1
16-Lead Lead Frame Chip Scale Package [LFCSP] CP-16-22 LS0
16-Lead Lead Frame Chip Scale Package [LFCSP] CP-16-22 LS1
16-Lead Lead Frame Chip Scale Package [LFCSP] CP-16-22 LUQ
16-Lead Lead Frame Chip Scale Package [LFCSP] CP-16-22 LS2
16-Lead Lead Frame Chip Scale Package [LFCSP] CP-16-22 LS3
16-Lead Lead Frame Chip Scale Package [LFCSP] CP-16-22 LS4
16-Lead Lead Frame Chip Scale Package [LFCSP] CP-16-22 LS5
16-Lead Lead Frame Chip Scale Package [LFCSP] CP-16-22 LS6
16-Lead Lead Frame Chip Scale Package [LFCSP] CP-16-22 LS7
Evaluation Board
ADP1763ACPZ-0.9-R7
ADP1763ACPZ0.95-R7
ADP1763ACPZ-1.0-R7
ADP1763ACPZ-1.1-R7
ADP1763ACPZ-1.2-R7
ADP1763ACPZ1.25-R7
ADP1763ACPZ-1.3-R7
ADP1763ACPZ-1.5-R7
ADP1763-1.3-EVALZ
ADP1763-ADJ-EVALZ
Evaluation Board
1 Z = RoHS Compliant Part.
2 For additional options, contact a local Analog Devices sales or distribution representative. Additional voltage output options available include the following: 0.5 V,
0.55 V, 0.6 V, 0.65 V, 0.7 V, 0.75 V, 0.8 V, 0.85 V, 1.05 V, 1.15 V, 1.35 V, 1.4 V, or 1.45 V.
©2016 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D12923-0-4/16(0)
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